storage device

Abstract

A storage device is provided. The storage device according to an embodiment of the present disclosure can include a string including a plurality of memory cells and a selection transistor connected between a conductive line and the plurality of memory cells, a peripheral circuit configured to perform an erase operation of the string, and a control logic configured to control the peripheral circuit during the erase operation such that a voltage level of an erase voltage applied to the conductive line is increased with a first voltage-time ramp in a first time period from a time one to a later time two, and the voltage level of the erase voltage is increased with a second voltage-time ramp in a second time period from the time two to a later time three, wherein the second voltage-time ramp is greater than the first voltage-time ramp.

Description

Technical Field

[0001] This disclosure relates to an electronic device, and more specifically, to a storage device and a method of operating the storage device. Background Technology

[0002] A storage device is a device that stores data under the control of a host device such as a computer or smartphone. A storage device may include a storage unit for storing data and a storage controller for controlling the storage unit. The storage device may be a volatile storage device or a non-volatile storage device.

[0003] Volatile memory devices are devices that store data only while powered on and lose the stored data when the power is turned off. Volatile memory devices can include static random access memory (SRAM), dynamic random access memory (DRAM), etc.

[0004] Non-volatile storage devices are devices that do not lose data even when the power supply is cut off. Non-volatile storage devices can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), flash memory, etc. Summary of the Invention

[0005] Embodiments of this disclosure provide a memory device capable of improving the performance degradation of selected transistors and memory cells, as well as a method of operating the memory device.

[0006] A storage device according to an embodiment of the present disclosure may include: a string including a plurality of memory cells and a select transistor connected between a conductive line and the plurality of memory cells; peripheral circuitry configured to perform an erase operation on the string; and control logic configured to control the peripheral circuitry during the erase operation such that, during a first time period including a time one to a later time two, the voltage level of an erase voltage applied to the conductive line is increased; during a second time period including a time two to a later time three, the voltage level of the applied erase voltage is maintained; during a third time period including a time three to a later time four, the voltage level of the applied erase voltage is increased; and during a fourth time period between a time one to a later time two or a fifth time period between a time three to a later time four, the select line connected to the select transistor is floated.

[0007] A storage device according to an embodiment of the present disclosure may include: a string including a plurality of memory cells and a selection transistor connected between a conductive line and the plurality of memory cells; peripheral circuitry configured to perform an erase operation on the string; and control logic configured to control the peripheral circuitry during the erase operation such that, during a first time period from time one to a later time two, the voltage level of an erase voltage applied to the conductive line is increased with a first voltage-time slope, and during a second time period from time two to a later time three, the voltage level of the erase voltage is increased with a second voltage-time slope, wherein the second voltage-time slope is greater than the first voltage-time slope.

[0008] A storage device according to an embodiment of the present disclosure may include: a string including a plurality of memory cells and a selection transistor connected between a conductive line and the plurality of memory cells; peripheral circuitry configured to perform an erase operation on the string; and control logic configured to control the peripheral circuitry during the erase operation such that, during a first time period from time one to a later time two, the voltage level of an erase voltage applied to the conductive line is increased with a first voltage-time slope, during a second time period from time two to a later time three, the voltage level of the erase voltage is increased with a second voltage-time slope, and during a later time period from time three to a later time four, the voltage level of the erase voltage is increased with a third voltage-time slope, wherein each of the first voltage-time slope and the third voltage-time slope is greater than the second voltage-time slope.

[0009] An operation method of a storage device according to an embodiment of the present disclosure may include: increasing the voltage level of an erase voltage applied to a conductive line from a first time point to a second time point later than the first time point; maintaining the voltage level of the erase voltage applied to the conductive line from the second time point to a third time point later than the second time point; increasing the voltage level of the erase voltage applied to the conductive line from the third time point to a fourth time point later than the third time point; and floating the select line connected to the select transistor at a fifth time point later than the first time point but earlier than the second time point or a sixth time point later than the third time point but earlier than the fourth time point.

[0010] An operation method of a storage device according to an embodiment of the present disclosure may include: increasing the voltage level of an erase voltage applied to a conductive line at a first slope from a first time point to a second time point later than the first time point; and increasing the voltage level of an erase voltage applied to a conductive line at a second slope from the second time point to a third time point later than the second time point, wherein the second slope may be greater than the first slope.

[0011] An operation method of a storage device according to an embodiment of the present disclosure may include: increasing the voltage level of an erase voltage applied to a conductive line at a first slope from a first time point to a second time point later than the first time point; increasing the voltage level of an erase voltage applied to a conductive line at a second slope from the second time point to a third time point later than the second time point; and increasing the voltage level of an erase voltage applied to a conductive line at a third slope from the third time point to a fourth time point later than the third time point, wherein each of the first slope and the third slope may be greater than the second slope.

[0012] This technology provides a memory device that can improve the performance reduction of selected transistors and memory cells. Attached Figure Description

[0013] Figure 1 This is a block diagram illustrating the configuration of a storage device according to an embodiment of the present disclosure.

[0014] Figure 2 It is shown Figure 1 A block diagram of the structure of the storage device.

[0015] Figure 3 It is shown Figure 2 A block diagram of the control logic structure.

[0016] Figure 4 It is shown Figure 2 A diagram of the structure of any of the storage blocks.

[0017] Figure 5 This is a set of diagrams illustrating the erase operation of a storage device according to an embodiment of the present disclosure.

[0018] Figure 6 This is a set of diagrams illustrating the erase operation of a storage device according to an embodiment of the present disclosure.

[0019] Figure 7 This is a set of diagrams illustrating the erase operation of a storage device according to an embodiment of the present disclosure.

[0020] Figure 8 This is a set of diagrams illustrating the erase operation of a storage device according to an embodiment of the present disclosure.

[0021] Figure 9 This is a set of diagrams illustrating the erase operation of a storage device according to an embodiment of the present disclosure.

[0022] Figure 10 This is a set of diagrams illustrating the erase operation of a storage device according to an embodiment of the present disclosure.

[0023] Figure 11This is a block diagram illustrating a memory card system for which an embodiment of a storage device according to the present disclosure can be applied.

[0024] Figure 12 This is a block diagram illustrating a solid-state drive (SSD) system for which embodiments of the storage device according to the present disclosure can be applied.

[0025] Figure 13 This is a block diagram illustrating a user system to which an embodiment of the storage device according to the present disclosure can be applied. Detailed Implementation

[0026] The specific structural or functional descriptions of embodiments based on the concepts disclosed in this specification or application are for the purpose of describing embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be implemented in various forms, and the descriptions are not limited to those described in this specification or application.

[0027] In the following description, embodiments of the present disclosure will be illustrated with reference to the accompanying drawings so that those skilled in the art can readily implement the technical spirit of the present disclosure.

[0028] Figure 1 This is a block diagram illustrating the configuration of a storage device according to an embodiment of the present disclosure.

[0029] refer to Figure 1 The storage device 50 may include a storage device 100 and a storage controller 200. The storage device 50 may be a device that stores data under the control of a host 300, such as a mobile phone, smartphone, MP3 player, laptop, desktop computer, game console, television, tablet computer, or in-vehicle infotainment system.

[0030] Storage device 50 can be manufactured as one of various types of storage devices depending on the host interface, which serves as the communication method with host 300. For example, storage device 50 can be configured as any of various types of storage devices, such as: SSD; multimedia cards in the form of MMC, eMMC, RS-MMC, and micro-MMC; secure digital cards in the form of SD, mini-SD, and micro-SD; Universal Serial Bus (USB) storage devices; Universal Flash Memory (UFS) devices; PCMCIA card storage devices; Peripheral Component Interconnect (PCI) card storage devices; PCI Express (PCI-E) card storage devices; Compact Flash (CF) cards; smart media cards; and Memory Stick.

[0031] Storage device 50 can be manufactured in any of the various types of packages. For example, storage device 50 can be manufactured in any of the various package types, such as point-of-purchase (POP), system-in-package (SIP), system-on-chip (SOC), multi-chip package (MCP), chip-on-board (COB), wafer-level fabrication package (WFP), and wafer-level stacked package (WSP).

[0032] Storage device 100 can store data. Storage device 100 operates under the control of storage controller 200. Storage device 100 may include multiple planes. A plane can be an independently operable area. Each plane can independently perform any of the following operations: programming, reading, and erasing.

[0033] Storage device 100 may include a storage cell array comprising multiple storage cells for storing data. The storage cell array may include multiple storage blocks. Each storage block may include multiple storage cells. A storage block can be a unit for performing an erase operation to erase data stored in storage device 100. That is, data stored in the same storage block can be erased simultaneously. In an embodiment, a storage block may include multiple pages. A page can be a unit for storing data in storage device 100 or retrieving data stored in storage device 100. That is, the physical address provided to storage device 100 from storage controller 200 during programming or reading operations can be an address used to identify a specific page.

[0034] In this embodiment, the storage device 100 may be a dual data rate synchronous dynamic random access memory (DDR SDRAM), a fourth-generation low-power dual data rate (LPDDR4) SDRAM, a graphics dual data rate (GDDR) SDRAM, low-power DDR (LPDDR), Rambus dynamic random access memory (RDRAM), NAND flash memory, vertical NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin-transfer torque random access memory (STT-RAM), etc. For ease of description, this specification assumes that the storage device 100 is a NAND flash memory.

[0035] In one embodiment, the storage device 100 may be implemented in a three-dimensional array structure. This disclosure is applicable not only to flash memory devices in which the charge storage layer is composed of conductive floating gates (FGs), but also to charge-trapped flash memory (CTF) in which the charge storage layer is composed of an insulating film.

[0036] In an implementation, each storage cell included in the storage device 100 can be programmed to be one of a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits.

[0037] Storage controller 200 can control the overall operation of storage device 50. When power is applied to storage device 50, storage controller 200 can execute firmware (FW). When storage device 100 is a flash memory storage device, storage controller 200 can execute firmware such as flash translation layer (FTL) to control communication between host 300 and storage device 100.

[0038] When a write request is received from host 300, storage controller 200 can receive write data to be stored in storage device 100 and a logical address (LA) for identifying the corresponding write data. Storage controller 200 can translate the input LA into a physical address (PA), which indicates the physical address of the storage cell in storage device 100 where the write data is stored. In an embodiment, one PA may correspond to one physical page. Storage controller 200 can provide storage device 100 with programming commands for storing data, the physical address, and the write data.

[0039] In this implementation, when a read request is input from the host 300, the storage controller 200 can receive the logical address corresponding to the read request from the host 300. Here, the LA corresponding to the read request can be the LA that identifies the read request data.

[0040] The storage controller 200 can obtain the PA mapped to the LA corresponding to the read request from the mapping data indicating the correspondence between the LA provided by the host 300 and the PA of the storage device 100.

[0041] In this implementation, the storage controller 200 can control the storage device 100 to independently perform programming, reading, or erasing operations, regardless of requests from the host 300. For example, the storage controller 200 can control the storage device 100 to perform background operations such as wear leveling, garbage collection, or read recycling.

[0042] The host 300 can communicate with the storage device 50 using at least one of the following communication methods: Universal Serial Bus (USB), Serial AT Interface (SATA), Serial Attached SCSI (SAS), High Speed ​​Inter-Chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Memory (UFS), Security Digital Card (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Module (DIMM), Registered DIMM (RDIMM), and Low Load DIMM (LRDIMM).

[0043] Figure 2 It is shown Figure 1 A block diagram illustrating an embodiment of the storage device 100.

[0044] Reference Figure 2 The storage device 100 may include a storage cell array 110, peripheral circuitry 120, and control logic 130.

[0045] The memory cell array 110 includes multiple memory blocks BLK1 to BLKz. These memory blocks BLK1 to BLKz are connected to the address decoder 121 via row lines RL and to the read / write circuitry 123 via bit lines BL1 to BLm. All memory blocks BLK1 to BLKz are connected together to the first bit line BL1 to the m-th bit line BLm. Each memory block BLK1 to BLKz may include multiple memory cells.

[0046] In this implementation, the multiple memory cells can be non-volatile memory cells. A row line RL can include at least one source select line, multiple word lines, and at least one drain select line. Memory cells connected to the same word line can be defined as a page. Therefore, a memory block can include multiple pages.

[0047] Each storage cell included in the storage cell array 110 can be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits.

[0048] The peripheral circuit 120 can be configured to perform programming, reading, or erasing operations on selected areas of the memory cell array 110 under the control of the control logic 130. The peripheral circuit 120 can drive the memory cell array 110. For example, under the control of the control logic 130, the peripheral circuit 120 can apply various operating voltages to the row lines RL and the first bit lines BL1 to m bit lines BLm, or discharge the applied voltages.

[0049] The peripheral circuit 120 may include an address decoder 121, a voltage generator 122, a read / write circuit 123, and a data input / output circuit 124.

[0050] Address decoder 121 can be connected to memory cell array 110 via row line RL. Control logic 130 can operate address decoder 121. Address decoder 121 can receive addresses from control logic 130. In one embodiment, address decoder 121 can decode block addresses from received addresses and select any one of multiple memory blocks BLK1 to BLKz based on the decoded address. In another embodiment, address decoder 121 can decode row addresses from received addresses and select any word line within the selected memory block. Address decoder 121 can select the row line RL corresponding to the selected memory block and transmit the operating voltage generated by voltage generator 122 to the selected row line RL.

[0051] Specifically, during programming operations, address decoder 121 can apply a programming voltage to the selected word line and a programming pass voltage to the unselected word line, the programming pass voltage being lower than the programming voltage. During programming verification operations, address decoder 121 can apply a verification voltage to the selected word line and a verification pass voltage higher than the verification voltage to the unselected word line. During reading operations, address decoder 121 can apply a read voltage to the selected word line and a read pass voltage higher than the read voltage to the unselected word line.

[0052] In this embodiment, the erase operation of the storage device 100 can be performed within a storage block cell. During the erase operation, the address decoder 121 can select a storage block based on the decoded address. During the erase operation, the address decoder 121 can apply a ground voltage to the word line connected to the selected storage block.

[0053] In an implementation, the address decoder 121 may also include an address buffer, a block decoder, a line decoder, etc.

[0054] Voltage generator 122 can generate multiple voltages using the external power supply voltage supplied to storage device 100. Voltage generator 122 can operate in response to control of control logic 130. For example, voltage generator 122 can adjust the external power supply voltage to generate an internal power supply voltage. The internal power supply voltage generated by voltage generator 122 can be supplied to address decoder 121, read / write circuit 123, data input / output circuit 124, and control logic 130, and can be used as the operating voltage of storage device 100.

[0055] For example, under the control of control logic 130, voltage generator 122 can generate programming voltage, verification voltage, programming pass voltage, verification pass voltage, reading voltage, and erasing voltage.

[0056] In one implementation, voltage generator 122 may include a plurality of pumping capacitors to generate a plurality of operating voltages with different voltage levels. Voltage generator 122 can generate the plurality of operating voltages by selectively activating the plurality of pumping capacitors in response to control of control logic 130. The generated plurality of operating voltages can be provided to memory cell array 110 by address decoder 121.

[0057] The read / write circuit 123 may include first page buffers PB1 through m-th page buffers PBm. First page buffers PB1 through m-th page buffers PBm may be connected to the memory cell array 110 via first bit lines BL1 through m-th bit lines BLm, respectively. First page buffers PB1 through m-th page buffers PBm may operate in response to control logic 130. For example, first page buffers PB1 through m-th page buffers PBm may operate in response to a page buffer control signal (not shown).

[0058] In this implementation, the first page buffer PB1 to the m-th page buffer PBm can sense the data stored in the memory cell array 110 by sensing the voltage or current of the first bit line BL1 to the m-th bit line BLm. The first page buffer PB1 to the m-th page buffer PBm can temporarily store the sensed data. The first page buffer PB1 to the m-th page buffer PBm can provide the sensed data to the data input / output circuit 124 via the data line DL.

[0059] In this implementation, the first page buffer PB1 to the m-th page buffer PBm can receive data to be stored in the memory cell array 110 via the data input / output circuit 124. The data received by the first page buffer PB1 to the m-th page buffer PBm through the execution of a programming operation can be stored in the memory cell array 110.

[0060] The programming operation of storing data in a memory cell may include a programming voltage application step and a verification step. In the programming voltage application step, when a programming voltage is applied to the selected word line, the first page buffer PB1 to the m-th page buffer PBm can transfer the data to be stored to the selected memory cell. The threshold voltage of the memory cell connected to the bit line to which the programming permission voltage (e.g., ground voltage) is applied can be increased. The threshold voltage of the memory cell connected to the bit line to which the programming inhibition voltage (e.g., power supply voltage) is applied can be maintained. In the verification step of verifying the programming operation, the first page buffer PB1 to the m-th page buffer PBm can sense the data stored in the memory cell from the selected memory cell via the first bit line BL1 to the m-th bit line BLm.

[0061] The data input / output circuit 124 can be connected to the first page buffer PB1 to the m-th page buffer PBm via the data line DL. The data input / output circuit 124 can operate in response to the control logic 130.

[0062] Data input / output circuit 124 can transfer data from... Figure 1 The data DATA received by the storage controller 200 is provided to the read / write circuit 123.

[0063] In one implementation, the data input / output circuit 124 may include multiple input / output buffers (not shown) for receiving data DATA. During programming operations, the data input / output circuit 124 receives the data DATA to be stored from the memory controller 200. During read operations, the data input / output circuit 124 may output data transferred from the first page buffer PB1 to the m-th page buffer PBm included in the read / write circuit 123 to the memory controller 200.

[0064] Control logic 130 is configured to control the overall operation of storage device 100. Control logic 130 can receive commands CMD and addresses ADDR.

[0065] Figure 3 It is shown Figure 2 A block diagram illustrating the implementation of the control logic.

[0066] refer to Figure 3 The control logic 130 may include a conductive line voltage controller 131, a selection line voltage controller 132, and a word line voltage controller 133.

[0067] The conductor voltage controller 131 can generate a control signal for controlling the voltage applied to the conductor during an erasure operation, and can provide this control signal to the peripheral circuitry 120. The conductor can be a source line or a bit line.

[0068] The select line voltage controller 132 can generate a control signal for controlling the voltage applied to the select line during an erase operation, and can provide this control signal to the peripheral circuitry 120. The select line can be a source select line or a drain select line.

[0069] The word line voltage controller 133 can generate a control signal for controlling the voltage applied to the word line during an erase operation, and can provide the control signal to the peripheral circuitry 120.

[0070] Figure 4 It is shown Figure 2 A diagram illustrating an implementation of any of the storage blocks.

[0071] refer to Figure 4 The storage block BLK1 may include multiple storage cells connected to multiple word lines WL1 to WL16, which are arranged parallel to each other between the source select line SSL and the drain select line DSL. More specifically, the storage block BLK1 may include multiple strings ST1 to STk connected between the bit lines BL1 to BLn and the source line SL. Figure 4 Bit lines BL1 to BLn can be Figure 2 The first line BL1 to the m-th line BLm.

[0072] In one implementation, as shown, one of the strings ST1 to STk can be connected to one of the bit lines BL1 to BLn. In another implementation, different from the one shown, multiple strings ST1 to STk can be connected to one of the bit lines BL1 to BLn.

[0073] The source line SL can be connected together to strings ST1 through STk. Since strings ST1 through STk can be configured similarly to each other, string ST1 connected to the first bit line BL1 will be specifically described as an example.

[0074] String ST1 may include: a source select transistor SST; multiple memory cells MC1 to MC16; and a drain select transistor DST connected in series between the source line SL and the first bit line BL1. A string ST1 may include at least one or more of the source select transistor SST and the drain select transistor DST, and may include memory cells MC1 to MC16. The total number of memory cells may be greater than the number of memory cells MC1 to MC16 shown in the figure.

[0075] The source of the source select transistor SST can be connected to the source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. Memory cells MC1 to MC16 can be connected in series between the source select transistor SST and the drain select transistor DST.

[0076] The gate of the source select transistor SST, which is included in different strings ST1 to STk, can be connected to the source select line SSL. The gate of the drain select transistor DST, which is included in different strings ST1 to STk, can be connected to the drain select line DSL.

[0077] The gates of memory cells MC1 to MC16, included in different strings ST1 to STk, can be connected to multiple word lines WL1 to WL16. A group of memory cells connected to the same word line in different strings ST1 to STk can be referred to as a physical page PG. Therefore, memory block BLK1 can include as many physical pages PG as word lines WL1 to WL16. Figure 4In this context, the source line SL, source select line SSL, word lines WL1 to WL16, and drain select line DSL can be included. Figure 2 In the line RL.

[0078] When a storage cell is a single-level cell (SLC) that stores one bit of data, a physical page (PG) can store one logical page (LPG) of data. Alternatively, a storage cell can store two or more bits of data. In this case, a physical page (PG) can store two or more logical pages (LPGs) of data.

[0079] Figure 5 This is a set of diagrams illustrating the erase operation of a storage device according to an embodiment of the present disclosure.

[0080] exist Figure 5 The image shows the voltage applied to conductor line A1, select line A2, and word line A3 during the erase operation.

[0081] refer to Figure 5 The erasure operation may include first to fifth time points T1a, T2a, T3a, T4a, and T5a. These first to fifth time points T1a, T2a, T3a, T4a, and T5a can be time points that occur sequentially during the erasure operation. The second time point T2a can be a time point later than the first time point T1a, the third time point T3a can be a time point later than the second time point T2a, the fourth time point T4a can be a time point later than the third time point T3a, and the fifth time point T5a can be a time point later than the fourth time point T4a.

[0082] During the erase operation, from the first time point T1a to the fifth time point T5a, an erase voltage VEa can be applied to the conductive line. The conductive line can be a bit line or a source line. The time point at which the erase voltage VEa is first applied to the conductive line can be defined as the first time point T1a. The erase voltage VEa can be a positive voltage higher than 0V. Figure 5 As shown in (A1), a first initial voltage Vi1a can be applied to the conductive line before applying the erasure voltage VEa. For example, the first initial voltage Vi1a can be 0V.

[0083] From the first time point T1a to the second time point T2a, the voltage level of the erase voltage VEa applied to the conductive line can be increased. From the first time point T1a to the second time point T2a, the erase voltage VEa can be increased from the first initial voltage Vi1a to the first voltage level V1a.

[0084] From the second time point T2a to the third time point T3a, the erase voltage level VEa applied to the conductive line can be maintained. From the second time point T2a to the third time point T3a, the erase voltage level VEa can be maintained at the first voltage level V1a. The time point at which the erase voltage level VEa applied to the conductive line increases and then begins to be maintained can be defined as the second time point T2a.

[0085] From the third time point T3a to the fifth time point T5a, the voltage level of the erase voltage VEa applied to the conductive line can be increased. From the third time point T3a to the fifth time point T5a, the voltage level of the erase voltage VEa can be increased from the first voltage level V1a to the second voltage level V2a. The time point at which the voltage level of the erase voltage VEa applied to the conductive line is maintained and then begins to increase can be defined as the third time point T3a.

[0086] The erase voltage level VEa applied to the conductor can be maintained from the fifth time point T5a. The erase voltage level VEa can be maintained at a second voltage level V2a from the fifth time point T5a. The second voltage level V2a can be the maximum erase voltage level. The time point at which the erase voltage level VEa applied to the conductor increases and then begins to be maintained can be defined as the fifth time point T5a.

[0087] like Figure 5 As shown in (A2), during the erase operation, a second initial voltage Vi2a can be applied to the select line from before the first time point T1a to the fourth time point T4a. This select line can be either a drain select line or a source select line. For example, the second initial voltage Vi2a can be 0V.

[0088] Starting from the fourth time point T4a, the select line can be floated. The time point at which the select line begins to float can be defined as the fourth time point T4a. As the select line is floated, its voltage level can be increased through coupling. Since the erase voltage VEa applied to the conductor increases to the fifth time point T5a, the voltage level of the select line can also increase to the fifth time point T5a.

[0089] At the fourth time point T4a, the erase voltage VEa can be at the third voltage level V3a. From the fifth time point T5a onwards, the voltage level of the select line can be maintained at the fourth voltage level V4a. The difference between the second voltage level V2a and the third voltage level V3a can be the same as that between the fourth voltage level V4a.

[0090] like Figure 5 As shown in (A3), during the erase operation, a voltage of 0V can be applied to the word line from before the first time point T1a to after the fifth time point T5a.

[0091] Due to the difference between the voltage level of the erase voltage VEa from the first time point T1a to the fourth time point T4a of the erase operation and the voltage level of the second initial voltage Vi2a, gate-induced drain leakage current (GIDL) may be generated in the string, and holes generated by GIDL may be injected into the channel of the string.

[0092] When the erase voltage VEa is maintained at the maximum erase voltage level from the fifth time point T5a of the erase operation, the holes injected into the channel of the string will be tunneled through, thus erasing the memory cells of the string.

[0093] refer to Figure 2 , Figure 3 and Figure 5 During the erase operation, the control logic 130 can control the peripheral circuit 120 to increase the erase voltage VEa applied to the conductive line from the first time point T1a to the second time point T2a, which is later than the first time point T1a; maintain the erase voltage VEa applied to the conductive line from the second time point T2a to the third time point T3a, which is later than the second time point T2a; increase the erase voltage VEa applied to the conductive line from the third time point T3a to the fifth time point T5a, which is later than the third time point T3a; and float the select line at the fourth time point T4a, which is later than the third time point T3a but earlier than the fifth time point T5a.

[0094] During the erase operation, a significant potential difference may arise between adjacent portions of the channel's conductive lines and the select line when the erase voltage increases rapidly. This potential difference generates a hot-carrying current between these portions, potentially producing electron-hole pairs. Electrons from these hot-carrying pairs can be injected into the charge storage layer adjacent to the select line, altering the threshold voltage of the select transistor and reducing its on / off characteristics.

[0095] In the memory device according to this disclosure, since the erase voltage VEa is maintained at a voltage level from the second time point T2a to the third time point T3a during the erase operation, the time for holes in the electron-hole pairs formed by the GIDL to move to the adjacent portions of the select line and word line of the channel can be ensured. As holes move to the adjacent portions of the select line and word line of the channel, the potential difference between the adjacent portions of the conductive lines and the adjacent portions of the select line can be relatively reduced, thereby improving the phenomenon of reduced on / off characteristics of the select transistor due to hot current.

[0096] In the memory device according to this disclosure, since the select line is floated from the fourth time point T4a between the third time point T3a and the fifth time point T5a, the fourth voltage level V4a of the select line can be sufficiently small after the fifth time point T5a. Therefore, after the fifth time point T5a, the difference between the voltage level of the select line and the voltage level of the word line may be small, and the potential difference between the adjacent portions of the select line and the adjacent portions of the word line in the channel can be relatively small. Therefore, the phenomenon of hot carrier currents generated in the adjacent portions of the select line and the adjacent portions of the word line in the channel after the fifth time point T5a, resulting in a degraded characteristic of the select transistor and the memory cell, can be improved.

[0097] Figure 6 This is a set of diagrams illustrating the erase operation of a storage device according to an embodiment of the present disclosure.

[0098] exist Figure 6 The image shows the voltage applied to conductor B1, select line B2, and word line B3 during the erase operation.

[0099] refer to Figure 6 The erasure operation may include first to fifth time points T1b, T2b, T3b, T4b, and T5b. These first to fifth time points T1b, T2b, T3b, T4b, and T5b can be time points that occur sequentially during the erasure operation. The second time point T2b can be a time point later than the first time point T1b, the third time point T3b can be a time point later than the second time point T2b, the fourth time point T4b can be a time point later than the third time point T3b, and the fifth time point T5b can be a time point later than the fourth time point T4b.

[0100] During the erase operation, an erase voltage VEb can be applied to the conductive line from a first time point T1b to a fifth time point T5b. The conductive line can be a bit line or a source line. The time point at which the erase voltage VEb begins to be applied to the conductive line can be defined as the first time point T1b. The erase voltage VEb can be a positive voltage higher than 0V. Figure 6 As shown in (B1), a first initial voltage Vi1b can be applied to the conductor before applying the erasure voltage VEb. For example, the first initial voltage Vi1b can be 0V.

[0101] From the first time point T1b to the third time point T3b, the voltage level of the erase voltage VEb applied to the conductive line can be increased. From the first time point T1b to the third time point T3b, the erase voltage VEb can be increased from the first initial voltage Vi1b to the first voltage level V1b.

[0102] From the third time point T3b to the fourth time point T4b, the erase voltage level VEb applied to the conductive line can be maintained. From the third time point T3b to the fourth time point T4b, the erase voltage level VEb can be maintained at the first voltage level V1b. The time point at which the erase voltage level VEb applied to the conductive line increases and then begins to be maintained can be defined as the third time point T3b.

[0103] From time point T4b to time point T5b, the voltage level of the erase voltage VEb applied to the conductive line can be increased. From time point T4b to time point T5b, the voltage level of the erase voltage VEb can increase from a first voltage level V1b to a second voltage level V2b. The time point at which the voltage level of the erase voltage VEb applied to the conductive line is maintained and then begins to increase can be defined as time point T4b.

[0104] The erase voltage level VEb applied to the conductor is maintained from the fifth time point T5b. From the fifth time point T5b, the erase voltage level VEb can be maintained at a second voltage level V2b. The second voltage level V2b can be the maximum erase voltage level. The time point at which the erase voltage level VEb applied to the conductor increases and then begins to be maintained can be defined as the fifth time point T5b.

[0105] like Figure 6 As shown in (B2), during the erase operation, a second initial voltage Vi2b can be applied to the select line from before the first time point T1b to the second time point T2b. The select line can be a drain select line or a source select line. For example, the second initial voltage Vi2b can be 0V.

[0106] Starting from the second time point T2b, the select line can be floated. The time point at which the select line begins to float can be defined as the second time point T2b. As the select line is floated, its voltage level can be increased through coupling. Since the voltage level of the erase voltage VEb applied to the conductor increases from the second time point T2b to the third time point T3b, is maintained from the third time point T3b to the fourth time point T4b, and increases from the fourth time point T4b to the fifth time point T5b, the voltage level of the select line can increase from the second time point T2b to the third time point T3b, be maintained from the third time point T3b to the fourth time point T4b, and increase from the fourth time point T4b to the fifth time point T5b.

[0107] At the second time point T2b, the voltage level of the erase voltage VEb can be the third voltage level V3b. From the fifth time point T5b onwards, the voltage level of the select line can be maintained at the fourth voltage level V4b. The difference between the second voltage level V2b and the third voltage level V3b can be the same as that between the fourth voltage level V4b.

[0108] like Figure 6 As shown in (B3), during the erase operation, a voltage of 0V can be applied to the word line from before the first time point T1b to after the fifth time point T5b.

[0109] From the first time point T1b to the second time point T2b of the erase operation, due to the difference between the voltage level of the erase voltage VEb and the voltage level of the second initial voltage Vi2b, GIDL may be generated in the string, and the holes generated by GIDL may be injected into the channel of the string.

[0110] As the erase voltage VEb is maintained at the maximum erase voltage level from the fifth time point T5b of the erase operation, the holes injected into the channel of the string will be tunneled through, thus erasing the memory cells of the string.

[0111] refer to Figure 2 , Figure 3 and Figure 6 During the erase operation, control logic 130 can control peripheral circuit 120 to increase the erase voltage VEb applied to the conductive line from a first time point T1b to a third time point T3b later than the first time point T1b, maintain the erase voltage VEb applied to the conductive line from the third time point T3b to a fourth time point T4b later than the third time point T3b, increase the erase voltage VEb applied to the conductive line from the fourth time point T4b to a fifth time point T5b later than the fourth time point T4b, and float the select line at a second time point T2b later than the first time point T1b and earlier than the third time point T3b.

[0112] In the memory device according to this disclosure, since the erase voltage VEb is maintained at a voltage level from a third time point T3b to a fourth time point T4b during the erase operation, the time for holes in the electron-hole pairs formed by the GIDL to move to the adjacent portions of the select line and word line of the channel can be ensured. As holes move to the adjacent portions of the select line and word line of the channel, the potential difference between the adjacent portions of the conductive lines and the adjacent portions of the select line can be relatively reduced, thus improving the phenomenon of reduced on / off characteristics of the select transistor due to hot current.

[0113] In the storage device according to this disclosure, since the select line is floated from a second time point T2b between the first time point T1b and the third time point T3b, the fourth voltage level V4b of the select line may have sufficiently increased after the fifth time point T5b. Therefore, after the fifth time point T5b, the difference between the voltage level of the select line and the voltage level of the conductive line can be sufficiently reduced, and the potential difference between the adjacent portions of the conductive line and the adjacent portions of the select line in the channel can be relatively small. Therefore, the phenomenon that hot currents may be generated in the adjacent portions of the conductive line and the adjacent portions of the select line in the channel after the fifth time point T5b, thereby potentially reducing the characteristics of the select transistor, can be mitigated.

[0114] Figure 7 This is a set of diagrams illustrating the erase operation of a storage device according to an embodiment of the present disclosure.

[0115] exist Figure 7 The image shows the voltage applied to the conductor line C1, select line C2, and word line C3 during the erase operation.

[0116] refer to Figure 7 The erasure operation may include first to fourth time points T1c, T2c, T3c, and T4c. These first to fourth time points T1c, T2c, T3c, and T4c can be time points that occur sequentially during the erasure operation. The second time point T2c can be a time point later than the first time point T1c, the third time point T3c can be a time point later than the second time point T2c, and the fourth time point T4c can be a time point later than the third time point T3c.

[0117] During the erase operation, an erase voltage VEc can be applied to the conductive line from a first time point T1c to a fourth time point T4c. The conductive line can be a bit line or a source line. The time point at which the erase voltage VEc is applied to the conductive line can be defined as the first time point T1c. The erase voltage VEc can be a positive voltage higher than 0V. Before applying the erase voltage VEc, a first initial voltage Vi1c can be applied to the conductive line. For example, the first initial voltage Vi1c can be 0V.

[0118] From the first time point T1c to the second time point T2c, the voltage level of the erasure voltage VEc applied to the conductive line can increase with a first slope L1c. For example... Figure 7 As shown in (C1), from the first time point T1c to the second time point T2c, the erase voltage VEc can be increased from the first initial voltage Vi1c to the first voltage level V1c.

[0119] From the second time point T2c to the fourth time point T4c, the voltage level of the erase voltage VEc applied to the conductive wire can increase with a second slope L2c. The second slope L2c can be greater than the first slope L1c. The first slope L1c can be gentler than the second slope L2c. The time point at which the slope of the increase in the erase voltage VEc changes can be defined as the second time point T2c. From the second time point T2c to the fourth time point T4c, the erase voltage VEc can increase from the first voltage level V1c to the second voltage level V2c.

[0120] The erase voltage VEc applied to the conductor can be maintained from the fourth time point T4c. From the fourth time point T4c, the erase voltage VEc can be maintained at the second voltage level V2c. The second voltage level V2c can be the maximum erase voltage level. The time point at which the erase voltage VEc applied to the conductor increases and then begins to be maintained can be defined as the fourth time point T4c.

[0121] like Figure 7 As shown in (C2), during the erase operation, a second initial voltage Vi2c can be applied to the select line from before the first time point T1c to the third time point T3c. The select line can be a drain select line or a source select line. For example, the second initial voltage Vi2c can be 0V.

[0122] Starting from the third time point T3c, the select line can be floated. The time point at which the select line begins to float can be defined as the third time point T3c. As the select line is floated, its voltage level can be increased through coupling. Since the erase voltage VEc applied to the conductor increases with a second slope L2c from the third time point T3c to the fourth time point T4c, the voltage level of the select line can also increase with a second slope L2c from the third time point T3c to the fourth time point T4c.

[0123] At the third time point T3c, the erase voltage VEc can be at the third voltage level V3c. From the fourth time point T4c onwards, the voltage level of the select line can be maintained at the fourth voltage level V4c. The difference between the second voltage level V2c and the third voltage level V3c can be the same as the difference between the fourth voltage level V4c.

[0124] like Figure 7 As shown in (C3), during the erase operation, a voltage of 0V can be applied to the word line from before the first time point T1c to after the fourth time point T4c.

[0125] From the first time point T1c to the third time point T3c of the erase operation, due to the difference between the voltage level of the erase voltage VEc and the voltage level of the second initial voltage Vi2c, GIDL may be generated in the string, and the holes generated by GIDL may be injected into the channel of the string.

[0126] As the erase voltage VEc remains at its maximum level from the fourth time point T4c of the erase operation, the holes injected into the channel of the string are tunneled through, thus erasing the memory cells of the string.

[0127] refer to Figure 2 , Figure 3 and Figure 7 During the erase operation, control logic 130 can control peripheral circuit 120 to increase the erase voltage VEc applied to the conductive line with a first slope L1c from a first time point T1c to a second time point T2c later than the first time point T1c, increase the erase voltage VEc applied to the conductive line with a second slope L2c greater than the first slope L1c from the second time point T2c to a fourth time point T4c later than the second time point T2c, and float the select line at a third time point T3c later than the second time point T2c and earlier than the fourth time point T4c.

[0128] In the memory device according to this disclosure, during the erase operation, the voltage level of the erase voltage VEc increases relatively smoothly from a first time point T1c to a second time point T2c. Therefore, the time it takes for the holes of the electron-hole pairs formed by the GIDL to move to the adjacent portions of the select line and word line of the channel can be ensured. As the holes move to the adjacent portions of the select line and word line of the channel, the potential difference between the adjacent portions of the conductive lines and the adjacent portions of the select line can be relatively reduced, thereby improving the phenomenon of reduced on / off characteristics of the select transistor due to hot current.

[0129] In the memory device according to this disclosure, since the select line is floated from the third time point T3c between the second time point T2c and the fourth time point T4c, the fourth voltage level V4c of the select line can be sufficiently small after the fourth time point T4c. Therefore, after the fourth time point T4c, the difference between the voltage level of the select line and the voltage level of the word line may be small, and the potential difference between the adjacent portions of the select line and the adjacent portions of the word line in the channel can be relatively small. Therefore, the phenomenon that hot carrier currents are generated in the adjacent portions of the select line and the adjacent portions of the word line in the channel after the fourth time point T4c, which may degrade the characteristics of the select transistor and the memory cell, can be mitigated.

[0130] Figure 8 This is a diagram illustrating the erase operation of a storage device according to an embodiment of the present disclosure.

[0131] exist Figure 8 The diagram shows the voltage applied to conductor line D1, select line D2, and word line D3 during the erase operation.

[0132] refer to Figure 8 The erasure operation may include first to fourth time points T1d, T2d, T3d, and T4d. These first to fourth time points T1d, T2d, T3d, and T4d can be time points that occur sequentially during the erasure operation. The second time point T2d can be a time point later than the first time point T1d, the third time point T3d can be a time point later than the second time point T2d, and the fourth time point T4d can be a time point later than the third time point T3d.

[0133] During the erase operation, an erase voltage VEd can be applied to the conductive line from a first time point T1d to a fourth time point T4d. The conductive line can be a bit line or a source line. The time point at which the erase voltage VEd is applied to the conductive line can be defined as the first time point T1d. The erase voltage VEd can be a positive voltage higher than 0V. Figure 8 As shown in (D1), a first initial voltage Vi1d can be applied to the conductor before applying the erasure voltage VEd. For example, the first initial voltage Vi1d can be 0V.

[0134] From the first time point T1d to the third time point T3d, the erase voltage VEd applied to the conductive line can increase with a first slope L1d. From the first time point T1d to the third time point T3d, the erase voltage VEd can increase from a first initial voltage Vi1d to a first voltage level V1d.

[0135] From the third time point T3d to the fourth time point T4d, the erase voltage VEd applied to the conductor can increase with a second slope L2d. The second slope L2d can be greater than the first slope L1d. The first slope L1d can be gentler than the second slope L2d. The point in time when the slope of the increase in the erase voltage VEd changes can be defined as the third time point T3d. From the third time point T3d to the fourth time point T4d, the erase voltage VEd can increase from the first voltage level V1d to the second voltage level V2d.

[0136] The erase voltage level VEd applied to the conductor is maintained from the fourth time point T4d. From the fourth time point T4d, the erase voltage level VEd can be maintained at a second voltage level V2d. The second voltage level V2d can be the maximum erase voltage level. The time point at which the erase voltage level VEd applied to the conductor increases and then begins to be maintained can be defined as the fourth time point T4d.

[0137] like Figure 8As shown in (D2), during the erase operation, a second initial voltage Vi2d can be applied to the select line from before the first time point T1d to the second time point T2d. The select line can be a drain select line or a source select line. For example, the second initial voltage Vi2d can be 0V.

[0138] Starting from the second time point T2d, the select line can be floated. The time point at which the select line begins to float can be defined as the second time point T2d. As the select line is floated, its voltage level can be increased through coupling. Since the erase voltage VEd applied to the conductor increases with a first slope L1d from the second time point T2d to the third time point T3d, and with a second slope L2d from the third time point T3d to the fourth time point T4d, the voltage level of the select line can increase with a first slope L1d from the second time point T2d to the third time point T3d, and with a second slope L2d from the third time point T3d to the fourth time point T4d.

[0139] At the second time point T2d, the voltage level of the erase voltage VEd can be the third voltage level V3d. From the fourth time point T4d onwards, the voltage level of the select line can be maintained at the fourth voltage level V4d. The difference between the second voltage level V2d and the third voltage level V3d can be the same as the fourth voltage level V4d.

[0140] like Figure 8 As shown in (D3), during the erase operation, a voltage of 0V can be applied to the word line from before the first time point T1d to after the fourth time point T4d.

[0141] From the first time point T1d to the second time point T2d of the erase operation, due to the difference between the voltage level of the erase voltage VEd and the voltage level of the second initial voltage Vi2d, GIDL may be generated in the string, and the holes generated by GIDL may be injected into the channel of the string.

[0142] When the erase voltage VEc is maintained at the maximum erase voltage level from the fourth time point T4d of the erase operation, the holes injected into the channel of the string will be tunneled through, thus erasing the memory cells of the string.

[0143] refer to Figure 2 , Figure 3 and Figure 8During the erase operation, control logic 130 can control peripheral circuit 120 to increase the erase voltage VEd applied to the conductive line at a first slope L1d from a first time point T1d to a third time point T3d later than the first time point T1d, and to increase the erase voltage VEd applied to the conductive line at a second slope L2d greater than the first slope L1d from the third time point T3d to a fourth time point T4d later than the third time point T3d, and to float the select line at a second time point T2d later than the first time point T1d and earlier than the third time point T3d.

[0144] In the storage device according to this disclosure, during the erase operation, the voltage level of the erase voltage VEd increases relatively gradually from a first time point T1d to a third time point T3d. Therefore, the time it takes for the holes of the electron-hole pairs formed by the GIDL to move to the adjacent portions of the select line and word line of the channel can be ensured. As the holes move to the adjacent portions of the select line and word line of the channel, the potential difference between the adjacent portions of the conductive lines and the adjacent portions of the select line can be relatively reduced, thereby improving the phenomenon of reduced on / off characteristics of the select transistor due to hot current.

[0145] In the storage device according to this disclosure, since the select line is floated from a second time point T2d between the first time point T1d and the third time point T3d, the fourth voltage level V4d of the select line can be sufficiently increased after the fourth time point T4d. Therefore, after the fourth time point T4d, the difference between the voltage level of the select line and the voltage level of the conductive line can be reduced, and the potential difference between the adjacent portions of the conductive line and the adjacent portions of the select line in the channel can be relatively small. Therefore, the phenomenon of hot current generation in the adjacent portions of the conductive line and the adjacent portions of the select line in the channel after the fourth time point T4d, resulting in a decrease in the characteristics of the select transistor, can be improved.

[0146] Figure 9 This is a set of diagrams illustrating the erase operation of a storage device according to an embodiment of the present disclosure.

[0147] exist Figure 9 The diagram shows the voltage applied to the conductor line E1, select line E2, and word line E3 during the erase operation.

[0148] refer to Figure 9The erasure operation may include first to fifth time points T1e, T2e, T3e, T4e, and T5e. These first to fifth time points T1e, T2e, T3e, T4e, and T5e can be time points that occur sequentially during the erasure operation. The second time point T2e can be a time point later than the first time point T1e, the third time point T3e can be a time point later than the second time point T2e, the fourth time point T4e can be a time point later than the third time point T3e, and the fifth time point T5e can be a time point later than the fourth time point T4e.

[0149] During the erase operation, an erase voltage VEe can be applied to the conductive line from the first time point T1e to the fifth time point T5e. The conductive line can be a bit line or a source line. The time point at which the erase voltage VEe is applied to the conductive line can be defined as the first time point T1e. The erase voltage VEe can be a positive voltage higher than 0V. As shown in Figure 9(E1), a first initial voltage Vi1e can be applied to the conductive line before applying the erase voltage VEe. For example, the first initial voltage Vi1e can be 0V.

[0150] From the first time point T1e to the second time point T2e, the voltage level of the erasure voltage VEe applied to the conductive line can increase with a first slope L1e. For example... Figure 9 As shown in (E1), from the first time point T1e to the second time point T2e, the erase voltage VEe can be increased from the first initial voltage Vi1e to the first voltage level V1e.

[0151] From the second time point T2e to the third time point T3e, the voltage level of the erase voltage VEe applied to the conductive line can increase with a second slope L2e. The second slope L2e can be less than the first slope L1e. The second slope L2e can be gentler than the first slope L1e. From the second time point T2e to the third time point T3e, the voltage level of the erase voltage VEe can increase from the first voltage level V1e to the second voltage level V2e. The time point at which the slope of the increase in the voltage level of the erase voltage VEe applied to the conductive line changes from the first slope L1e to the second slope L2e can be defined as the second time point T2e.

[0152] From the third time point T3e to the fifth time point T5e, the voltage level of the erase voltage VEE applied to the conductive line can increase with a third slope L3e. The third slope L3e can be greater than the second slope L2e. The second slope L2e can be gentler than the third slope L3e. The third slope L3e can be the same as or greater than the first slope L1e. From the third time point T3e to the fifth time point T5e, the voltage level of the erase voltage VEE can increase from the second voltage level V2e to the third voltage level V3e. The time point at which the slope of the increase in the voltage level of the erase voltage VEE applied to the conductive line changes from the second slope L2e to the third slope L3e can be defined as the third time point T3e.

[0153] The erase voltage VEe applied to the conductor is maintained from the fifth time point T5e. From the fifth time point T5e, the erase voltage VEe can be maintained at the third voltage level V3e. The third voltage level V3e can be the maximum erase voltage level. The time point at which the erase voltage VEe applied to the conductor increases with a third slope L3e and then begins to be maintained can be defined as the fifth time point T5e.

[0154] like Figure 9 As shown in (E2), during the erase operation, a second initial voltage Vi2e can be applied to the select line from before the first time point T1e to the fourth time point T4e. The select line can be a drain select line or a source select line. For example, the second initial voltage Vi2e can be 0V.

[0155] Starting from the fourth time point T4e, the select line can be floated. The time point at which the select line begins to float can be defined as the fourth time point T4e. As the select line is floated, its voltage level can be increased through coupling. Since the erase voltage VEe applied to the conductor increases with a third slope L3e from the fourth time point T4e to the fifth time point T5e, the voltage level of the select line can also increase with a third slope L3e from the fourth time point T4e to the fifth time point T5e.

[0156] At the fourth time point T4e, the voltage level of the erase voltage VEe can be the fourth voltage level V4e. From the fifth time point T5e onwards, the voltage level of the select line can be maintained at the fifth voltage level V5e. The difference between the third voltage level V3e and the fourth voltage level V4e can be the same as that between the fifth voltage level V5e.

[0157] like Figure 9 As shown in (E3), during the erase operation, a voltage of 0V can be applied to the word line from before the first time point T1e to after the fifth time point T5e.

[0158] From the first time point T1e to the fourth time point T4e of the erase operation, due to the difference between the voltage level of the erase voltage VEe and the voltage level of the second initial voltage Vi2e, GIDL may be generated in the string, and the holes generated by GIDL may be injected into the channel of the string.

[0159] When the erase voltage VEe is maintained at the maximum erase voltage level from the fifth time point T5e of the erase operation, the holes injected into the channel of the string will be tunneled, thereby erasing the memory cells of the string.

[0160] refer to Figure 2 , Figure 3 and Figure 9 During the erase operation, control logic 130 can control peripheral circuit 120 to increase the erase voltage VEe applied to the conductive line at a first slope L1e from a first time point T1e to a second time point T2e later than the first time point T1e, increase the erase voltage VEe applied to the conductive line at a second slope L2e less than the first slope L1e from the second time point T2e to a third time point T3e later than the second time point T2e, increase the erase voltage VEe applied to the conductive line at a third slope L3e greater than the second slope L2e from the third time point T3e to a fifth time point T5e later than the third time point T3e, and float the select line at a fourth time point T4e later than the third time point T3e but earlier than the fifth time point T5e.

[0161] In the memory device according to this disclosure, during the erase operation, the voltage level of the erase voltage VEe can increase relatively gradually from the second time point T2e to the third time point T3e. Therefore, the time it takes for the holes of the electron-hole pairs formed by the GIDL to move to the adjacent portions of the select line and word line of the channel can be ensured. As the holes move to the adjacent portions of the select line and word line of the channel, the potential difference between the adjacent portions of the conductive lines and the adjacent portions of the select line can be relatively reduced, thus improving the phenomenon of reduced on / off characteristics of the select transistor due to hot current.

[0162] In the memory device according to this disclosure, since the select line is floated from the fourth time point T4e between the third time point T3e and the fifth time point T5e, the fifth voltage level V5e of the select line can be sufficiently reduced after the fifth time point T5e. Therefore, after the fifth time point T5e, the difference between the voltage level of the select line and the voltage level of the word line can be reduced, and the potential difference between the adjacent portions of the select line and the adjacent portions of the word line in the channel can be relatively small. Therefore, the phenomenon of hot currents generated in the adjacent portions of the select line and the adjacent portions of the word line in the channel after the fifth time point T5e, resulting in a degraded characteristic of the select transistor and the memory cell, can be improved.

[0163] Figure 10 This is a set of diagrams illustrating the erase operation of a storage device according to an embodiment of the present disclosure.

[0164] exist Figure 10 The diagram shows the voltage applied to the conductor line F1, select line F2, and word line F3 during the erase operation.

[0165] refer to Figure 10 The erasure operation may include first to fifth time points T1f, T2f, T3f, T4f, and T5f. These first to fifth time points T1f, T2f, T3f, T4f, and T5f can be time points that occur sequentially during the erasure operation. The second time point T2f can be a time point later than the first time point T1f, the third time point T3f can be a time point later than the second time point T2f, the fourth time point T4f can be a time point later than the third time point T3f, and the fifth time point T5f can be a time point later than the fourth time point T4f.

[0166] During the erase operation, an erase voltage VEf can be applied to the conductive line from the first time point T1f to the fifth time point T5f. The conductive line can be a bit line or a source line. The time point at which the erase voltage VEf is applied to the conductive line can be defined as the first time point T1f. The erase voltage VEf can be a positive voltage higher than 0V. Figure 10 As shown in (F1), a first initial voltage Vi1f can be applied to the conductor before applying the erasure voltage VEf. For example, the first initial voltage Vi1f can be 0V.

[0167] From the first time point T1f to the third time point T3f, the voltage level of the erase voltage VEf applied to the conductive line can be increased with a first slope L1f. From the first time point T1f to the third time point T3f, the erase voltage VEf can be increased from a first initial voltage Vi1f to a first voltage level V1f.

[0168] From the third time point T3f to the fourth time point T4f, the voltage level of the erase voltage VEf applied to the conductor can increase with a second slope L2f. The second slope L2f can be less than the first slope L1f. The second slope L2f can be gentler than the first slope L1f. From the third time point T3f to the fourth time point T4f, the voltage level of the erase voltage VEf can increase from the first voltage level V1f to the second voltage level V2f. The time point at which the slope of the increase in the voltage level of the erase voltage VEf applied to the conductor changes from the first slope L1f to the second slope L2f can be defined as the third time point T3f.

[0169] From time point T4f to time point T5f, the voltage level of the erase voltage VEf applied to the conductor can increase with a third slope L3f. The third slope L3f can be greater than the second slope L2f. The second slope L2f can be gentler than the third slope L3f. The third slope L3f can be the same as or greater than the first slope L1f. From time point T4f to time point T5f, the voltage level of the erase voltage VEf can increase from the second voltage level V2f to the third voltage level V3f. The time point at which the slope of the increase in the erase voltage VEf applied to the conductor changes from the second slope L2f to the third slope L3f can be defined as time point T4f.

[0170] The erase voltage level VEf applied to the conductor can be maintained from the fifth time point T5f. From the fifth time point T5f, the erase voltage level VEf can be maintained at the third voltage level V3f. The third voltage level V3f can be the maximum erase voltage level. The time point at which the erase voltage level VEf applied to the conductor increases with the third slope L3f and then begins to be maintained can be defined as the fifth time point T5f.

[0171] like Figure 10 As shown in (F2), during the erase operation, a second initial voltage Vi2f can be applied to the select line from before the first time point T1f to the second time point T2f. The select line can be a drain select line or a source select line. For example, the second initial voltage Vi2f can be 0V.

[0172] Starting from the second time point T2f, the select line can be floated. The time point at which the select line begins to float can be defined as the second time point T2f. As the select line is floated, its voltage level can be increased through coupling. Since the erase voltage VEf applied to the conductor increases with a first slope L1f from the second time point T2f to the third time point T3f, increases with a second slope L2f from the third time point T3f to the fourth time point T4f, and increases with a third slope L3f from the fourth time point T4f to the fifth time point T5f, the voltage level of the select line can also increase with a first slope L1f from the second time point T2f to the third time point T3f, a second slope L2f from the third time point T3f to the fourth time point T4f, and a third slope L3f from the fourth time point T4f to the fifth time point T5f.

[0173] At the second time point T2f, the voltage level of the erase voltage VEf can be the fourth voltage level V4f. From the fifth time point T5f onwards, the voltage level of the select line can be maintained at the fifth voltage level V5f. The difference between the third voltage level V3f and the fourth voltage level V4f can be the same as that between the fifth voltage level V5f.

[0174] like Figure 10 As shown in (F3), during the erase operation, a voltage of 0V can be applied to the word line from before the first time point T1f to after the fifth time point T5f.

[0175] From the first time point T1f to the second time point T2f of the erase operation, due to the difference between the voltage level of the erase voltage VEf and the voltage level of the second initial voltage Vi2f, GIDL may be generated in the string, and the holes generated by GIDL may be injected into the channel of the string.

[0176] When the erase voltage VEf is maintained at the maximum erase voltage level from the fifth time point T5f of the erase operation, the holes injected into the channel of the string will be tunneled through, thereby erasing the memory cells of the string.

[0177] refer to Figure 2 , Figure 3 and Figure 10 During the erase operation, control logic 130 can control peripheral circuit 120 to increase the erase voltage VEf applied to the conductive line at a first slope L1f from a first time point T1f to a third time point T3f later than the first time point T1f, increase the erase voltage VEf applied to the conductive line at a second slope L2f less than the first slope L1f from the third time point T3f to a fourth time point T4f later than the third time point T3f, increase the erase voltage VEf applied to the conductive line at a third slope L3f greater than the second slope L2f from the fourth time point T4f to a fifth time point T5f later than the fourth time point T4f, and float the select line at a second time point T2f later than the first time point T1f and earlier than the third time point T3f.

[0178] In the memory device according to this disclosure, during the erase operation, the voltage level of the erase voltage VEf can increase relatively gradually from the third time point T3f to the fourth time point T4f. Therefore, the time it takes for the holes of the electron-hole pairs formed by the GIDL to move to the adjacent portions of the select line and word line of the channel can be ensured. As the holes move to the adjacent portions of the select line and word line of the channel, the potential difference between the adjacent portions of the conductive lines and the adjacent portions of the select line can be relatively reduced, thus improving the phenomenon of reduced on / off characteristics of the select transistor due to hot current.

[0179] In the storage device according to this disclosure, since the select line is floated from the second time point T2f between the first time point T1f and the third time point T3f, the fifth voltage level V5f of the select line can be sufficiently increased after the fifth time point T5f. Therefore, after the fifth time point T5f, the difference between the voltage level of the select line and the voltage level of the conductive line can be reduced, and the potential difference between the adjacent portions of the conductive line and the adjacent portions of the select line in the channel can be relatively small. Therefore, the phenomenon of hot current generation in the adjacent portions of the conductive line and the adjacent portions of the select line in the channel after the fifth time point T5f, resulting in a decrease in the on / off characteristics of the select transistor, can be improved.

[0180] Figure 11 This is a block diagram illustrating a memory card system using a storage device according to an embodiment of the present disclosure.

[0181] Reference Figure 11 The memory card system 2000 includes a memory controller 2100, a memory device 2200, and a connector 2300.

[0182] Storage controller 2100 can be connected to storage device 2200. Storage controller 2100 can be configured to access storage device 2200. For example, storage controller 2100 can be configured to perform read operations, programming operations, and erase operations, or control background operations of storage device 2200. Storage controller 2100 is configured to provide an interface between storage device 2200 and a host. Storage controller 2100 is configured to drive firmware for controlling storage device 2200. Storage controller 2100 can be used in conjunction with reference to... Figure 1 The storage controller 200 described is implemented in the same manner.

[0183] For example, the storage controller 2100 may include components such as random access memory (RAM), a processor, a host interface, a memory interface, and an error corrector.

[0184] Storage controller 2100 can communicate with external devices via connector 2300. Storage controller 2100 can communicate with external devices (e.g., a host) according to specific communication standards. For example, storage controller 2100 can be configured to communicate with external devices using at least one of various communication standards, such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe. For example, connector 2300 can be defined by at least one of the aforementioned communication standards.

[0185] For example, the storage device 2200 can be implemented with various non-volatile memory elements, such as electrically erasable and programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-transfer torque magnetic RAM (STT-MRAM).

[0186] For example, the memory controller 2100 or memory device 2200 can be packaged and provided as a semiconductor package, such as a stacked package (PoP), ball grid array (BGA), chip-scale package (CSP), plastic leaded chip carrier (PLCC), PDIP, waffle wafer, wafer in wafer form, chip-on-board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), thin quad flat package (TQFP), small outline integrated circuit package (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system-in-package (SIP), multi-chip package (MCP), wafer-level fabrication package (WFP), or wafer-level fabrication stacked package (WSP). Alternatively, the memory device 2200 may include multiple non-volatile memory chips, and the multiple non-volatile memory chips may be packaged and provided as a single semiconductor package based on the above-described packaging methods.

[0187] For example, the storage controller 2100 and the storage device 2200 can be integrated into a single semiconductor device. For example, the storage controller 2100 and the storage device 2200 can be integrated into a single semiconductor device to configure a solid-state drive (SSD). The storage controller 2100 and the storage device 2200 can be integrated into a single semiconductor device to configure a memory card. For example, the storage controller 2100 and the storage device 2200 can be integrated into a single semiconductor device to configure memory cards such as PC cards (Personal Computer Memory Card International Association (PCMCIA)), compact flash memory cards (CF), smart media cards (SM or SMC), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro, or eMMC), SD cards (SD, miniSD, microSD, or SDHC), and universal flash memory (UFS).

[0188] For example, storage device 2200 can be a reference Figure 1 The storage device 100 is described.

[0189] Figure 12 This is a block diagram illustrating a solid-state drive (SSD) system for use with a storage device according to an embodiment of the present disclosure.

[0190] refer to Figure 12 The SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 can exchange signals SIG with the host 3100 via a signal connector 3001 and can receive power PWR via a power connector 3002. The SSD 3200 may include an SSD controller 3210, multiple flash memory units 3221 to 322n, an auxiliary power supply 3230, and a cache memory 3240.

[0191] In this implementation, the SSD controller 3210 can execute the reference... Figure 1 The functions of the storage controller 200.

[0192] SSD controller 3210 can control multiple flash memory devices 3221 to 322n in response to a signal SIG received from host 3100. For example, the signal SIG can be a signal based on the interface between host 3100 and SSD 3200. For example, the signal SIG can be a signal defined by at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe.

[0193] The auxiliary power supply 3230 can be connected to the host 3100 via power connector 3002. The auxiliary power supply 3230 can receive power from and charge the host 3100. When the power supply from the host 3100 is uneven, the auxiliary power supply 3230 can provide power to the SSD 3200. For example, the auxiliary power supply 3230 can be located inside the SSD 3200, or it can be located outside the SSD 3200. For example, the auxiliary power supply 3230 can be located on the motherboard and can provide auxiliary power to the SSD 3200.

[0194] Buffer memory 3240 operates as a buffer memory for SSD 3200. For example, buffer memory 3240 may temporarily store data received from host 3100 or data received from multiple flash memories 3221 to 322n, or it may temporarily store metadata (e.g., a mapping table) of flash memories 3221 to 322n. Buffer memory 3240 may include volatile memory (e.g., DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM) or non-volatile memory (e.g., FRAM, ReRAM, STT-MRAM, and PRAM).

[0195] For example, non-volatile memories 3321 to 322n can be references Figure 1 The storage device 100 is described.

[0196] Figure 13 This is a block diagram illustrating a user system for using a storage device according to an embodiment of the present disclosure.

[0197] Reference Figure 13 The user system 4000 may include an application processor 4100, a storage module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0198] Application processor 4100 can drive components, operating system (OS), user programs, etc., included in user system 4000. For example, application processor 4100 may include controllers, interfaces, graphics engines, etc., that control components included in user system 4000. Application processor 4100 can be provided as a system-on-a-chip (SoC).

[0199] Storage module 4200 can operate as main memory, operational memory, buffer memory, or cache memory of user system 4000. Storage module 4200 may include volatile random access memory (e.g., DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM) or non-volatile random access memory (e.g., PRAM, ReRAM, MRAM, and FRAM). For example, application processor 4100 and storage module 4200 may be packaged and provided as a single semiconductor package based on a stacked package (POP).

[0200] Network module 4300 can communicate with external devices. For example, network module 4300 can support wireless communications such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), LTE, WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi. For example, network module 4300 may be included in application processor 4100.

[0201] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Alternatively, storage module 4400 can transfer data stored in storage module 4400 to application processor 4100. For example, storage module 4400 can be implemented using non-volatile semiconductor memory elements such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, and 3D NAND flash memory. For example, storage module 4400 can be provided as a removable storage device (removable drive) such as a memory card and as an external drive for user system 4000.

[0202] For example, storage module 4400 may include multiple non-volatile storage devices, and the multiple non-volatile storage devices may be referenced. Figure 1 The storage device 100.

[0203] User interface 4500 may include interfaces for inputting data or instructions to application processor 4100 or outputting data to external devices. For example, user interface 4500 may include user input interfaces such as keyboards, keys, buttons, touch panels, touchscreens, touchpads, touch balls, cameras, microphones, gyroscope sensors, vibration sensors, and piezoelectric elements. User interface 4500 may include user output interfaces such as liquid crystal displays (LCDs), organic light-emitting diode (OLED) display devices, active-matrix OLED (AMOLED) display devices, LEDs, speakers, and monitors.

[0204] Cross-references to related applications

[0205] This application claims priority to Korean Patent Application 10-2020-0115683, filed on September 9, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device comprising: a string including a plurality of memory cells and a select transistor connected between a conductive line and the plurality of memory cells; peripheral circuitry to perform an erase operation of the string; and control logic to control the peripheral circuitry during the erase operation such that a voltage level of an erase voltage applied to the conductive line is increased for a first time period including a time one to a time two later, the voltage level applied as the erase voltage is maintained for a second time period including the time two to a time three later, the voltage level of the erase voltage applied is increased for a third time period including the time three to a time four later, and a select line connected to the select transistor is floated at a first time point between the time one to the time two later or a second time point between the time three to the time four later.

2. The memory device of claim 1, wherein, the select line is floated from the first time point.

3. The memory device of claim 2, wherein, the control logic controls the peripheral circuitry to apply an initial voltage to the select line from the time one to the first time point.

4. The memory device of claim 3, wherein, the initial voltage is 0V.

5. The memory device of claim 1, wherein, the select line is floated from the second time point.

6. The memory device of claim 1, wherein, the control logic controls the peripheral circuitry such that a 0V voltage is applied to a word line connected to the memory cells from the time one to the time four.

7. The memory device of claim 1, wherein, the conductive line is a source line, and the select line is a source select line.

8. A memory device comprising: a string including a plurality of memory cells and a select transistor connected between a conductive line and the plurality of memory cells; peripheral circuitry to perform an erase operation of the string; and control logic to control the peripheral circuitry during the erase operation such that a voltage level of an erase voltage applied to the conductive line is increased at a first voltage-time slope for a first time period from a time one to a time two later, and the voltage level of the erase voltage is increased at a second voltage-time slope for a second time period from the time two to a time three later, wherein the second voltage-time slope is greater than the first voltage-time slope, wherein the control logic controls the peripheral circuitry to float a select line connected to the select transistor at a time four later than the time one and earlier than the time two or at a time five later than the time two and earlier than the time three.

9. The memory device of claim 8, wherein, the control logic controls the peripheral circuitry to apply an initial voltage to the select line from the time one to the time four.

10. The memory device of claim 8, wherein, the control logic controls the peripheral circuitry to apply an initial voltage to the select line from the time one to the time five.

11. The memory device of claim 8, wherein, the conductive line is a source line.

12. The memory device of claim 8, wherein, the conductive line is a bit line.

13. A memory device comprising: a string including a plurality of memory cells and a select transistor connected between a conductive line and the plurality of memory cells; peripheral circuitry to perform an erase operation of the string; and control logic that controls the peripheral circuit during the erase operation such that a voltage level of an erase voltage applied to the conductive line is increased at a first voltage-time ramp during a first time period from a time one to a later time two, the voltage level of the erase voltage is increased at a second voltage-time ramp during a second time period from the time two to a later time three, and the voltage level of the erase voltage is increased at a third voltage-time ramp from the time three to a later time four, wherein each of the first voltage-time ramp and the third voltage-time ramp is greater than the second voltage-time ramp, wherein the control logic controls the peripheral circuit to float a select line connected to the select transistor at a time five later than the time one and earlier than the time two or at a time six later than the time three and earlier than the time four.

14. The memory device of claim 13, wherein, a voltage level of the select line is increased at the first voltage-time ramp from the time five to the time two, is increased at the second voltage-time ramp from the time two to the time three, and is increased at the third voltage-time ramp from the time three to the time four.

15. The memory device of claim 13, wherein, the third voltage-time ramp is greater than the first voltage-time ramp.

16. The memory device of claim 13, wherein, the third voltage-time ramp is the same as the first voltage-time ramp.

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