A method for manufacturing a rectifier circuit, a rectifier circuit, a voltage conversion circuit and a power supply

Abstract

The present invention belongs to the field of microelectronic technology, and discloses a rectifier circuit manufacturing method and a corresponding rectifier, voltage conversion circuit and power supply; based on the performance optimization of the rectifier unit in the DC-DC converter circuit, a process technology of a MOSFET rectifier unit is improved, and good electrical characteristics are obtained. The Schottky rectifier region is integrated in parallel with the MOSFET parasitic body diode on the existing structure, which can replace the MOSFET and the freewheeling diode parallel structure and obtain lower reverse recovery characteristics, thereby reducing the conduction power consumption under high frequency. In addition, the present invention does not require additional photomasks during the process implementation, does not increase the cost of such a process, and makes the process improvement highly sustainable, which is conducive to improving the efficiency of process improvement.

Description

Technical Field

[0001] The present invention belongs to the field of microelectronic technology, and in particular relates to a rectifier circuit manufacturing method, a rectifier circuit, a voltage conversion circuit and a power supply. Background Art

[0002] The rectifier circuit is one of the important circuit structures of the electronic circuit. With the deepening of the application of electronic circuits, more and more detailed technical requirements are put forward for the rectifier circuit, which not only requires the circuit to have superior performance, but also hopes to have high technical and economic value. Summary of the invention

[0003] The present invention is based on the performance optimization of the rectifying unit in the DC-DC converter circuit, improves the process technology of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) rectifying unit, and obtains good electrical characteristics. A Schottky rectifying region is integrated in parallel with the MOSFET parasitic body diode on the existing structure, which can replace the parallel structure of the MOSFET and the freewheeling diode and obtain lower reverse recovery characteristics, thereby reducing the conduction power consumption under high frequency.

[0004] In addition, the present invention does not require additional masks during the process implementation, does not increase the cost of such processes, and makes the process improvement highly sustainable, which is conducive to improving the efficiency of process improvement.

[0005] Through the mask preset steps, the first mask, the second mask, and the Nth mask are prepared, wherein N is a positive integer greater than 10; the N+1th mask, the N+2th mask, and the Mth mask are prepared, wherein M is a positive integer greater than 12.

[0006] And through the mask optimization step: sequentially using the first mask, the second mask until the Nth mask, and the N+1th mask until the Mth mask; wherein M>N; converting the preset circuit pattern to the preset target position.

[0007] The preparation of the shielding gate structure is achieved by setting the gate structure preparation steps; wherein, a total of M masks are used for the preparation of the shielding gate; the first characteristic pattern of the Schottky rectifier circuit is prepared on the Rth mask, and the second characteristic pattern of the Schottky rectifier circuit is prepared on the R+1th mask; wherein, N≤R≤M, M≠N; the last characteristic pattern required for the Schottky rectifier circuit is prepared on the Sth mask; wherein, N≤R≤S≤M, M≠N, and R and S are both positive integers; the above steps are integrated with the existing process of the shielding gate and optimized, without adding other masks to process the characteristic patterns.

[0008] Furthermore, through the structural association step, the process parameters in the gate structure preparation step are adjusted so that the Schottky rectifier circuit is connected in parallel with the parasitic body diode of the shielding gate; wherein the shielding gate is a trench structure, and an ILD interlayer dielectric and a polysilicon gate are introduced into the trench structure; the interlayer dielectric is used to isolate the polysilicon gate filled in the trench; and then the source, gate, and drain of the rectifier circuit are connected to the pins of the rectifier circuit, and the source and gate are connected to the metal layer through contact holes to realize the deviceization of the circuit topology.

[0009] In order to improve the performance, the freewheeling part generation step connects the source and the gate through contact holes, and the contact holes pass through the ILD interlayer dielectric and are connected to the source, gate and drain.

[0010] The source of its Schottky rectifier circuit is directly electrically connected to the metal layer, and the end of the source of the rectifier circuit away from the metal layer is electrically connected to the drain through a groove structure. The groove structure obtains the characteristic pattern between the Rth mask and the Sth mask. All of the above masks have improved characteristic patterns based on the original process, but there is no need to introduce a new mask process; the cost of such process is not increased, so that the process improvement is highly sustainable, which is conducive to improving the efficiency of process improvement.

[0011] In order to further improve the relationship between the gate structure and the rectifying structure, the present invention also discloses a functional area optimization step, by preparing a functional area optimization layer, the film structure obtained by deposition, electroplating and / or other film processes, and the MOSFET functional area pattern and the Schottky rectifying area pattern of the functional area optimization layer are transferred to the target position under the action of the same mask or the same series of masks.

[0012] After the Schottky rectifying region is transferred through the Nth mask, characteristic patterns of at least two contact holes are transferred on the drain of the rectifying region to improve circuit characteristics.

[0013] Furthermore, the gate oxide working window of the MOSFET and the rectifier unit is defined or etched by removing the oxygen-nitrogen sandwich mask, and the working window is used to obtain the gate oxide layer through an oxidation process; the gate oxide layer is used to isolate the gate polysilicon layer and other related layers and obtain related circuit units.

[0014] The oxygen-nitrogen interlayer includes a first mask, a second mask and a third mask; the first mask is a first oxide layer or a thermal oxide layer, the second mask is a nitride layer, and the third mask is a second oxide layer.

[0015] Furthermore, the process of the oxygen-nitrogen sandwich mask before the shield gate area is removed also includes trench group etching, thick oxygen deposition, polysilicon source deposition, polysilicon source back etching, polysilicon groove back etching, HDP (High-Density Plasma) chemical vapor deposition and oxide CPM (Chemical Mechanical Polishing). Specifically:

[0016] The trench group etching step obtains a first type base layer by epitaxy, and etches a gate trench group in the first type base layer. The gate trench group includes at least three trenches, and the depth of each trench in the gate trench group should not be less than the depth of the preset source first trench.

[0017] A third silicon oxide layer is deposited on the bottom and side surfaces of the gate trench group through a thick oxygen deposition step. The third oxide layer and the second oxide layer may have the same or different oxide materials.

[0018] Through the polysilicon source deposition step, polysilicon is deposited on the third oxide layer until the gate trench and the surface layer of the workpiece are filled, thereby forming source polysilicon, namely, the first polysilicon layer.

[0019] The first polysilicon layer where the polysilicon source is located is etched back through the polysilicon source back etching step, and the thick oxygen layer sidewalls of the gate trench group are retained to obtain a second trench group covered by the thick oxygen sidewalls; wherein the depth of the second trench group is greater than the thickness of the oxygen-nitrogen sandwich mask.

[0020] At least two third groove groups close to the Schottky rectifier circuit are obtained by etching the polysilicon groove with photoresist in combination with the photoresist.

[0021] Furthermore, a fourth oxide layer is obtained by high density plasma CVD (Chemical Vapor Deposition) through an oxide HDP step to seal the first polysilicon layer.

[0022] Through the oxide CMP step, the second mask is used as a stop layer, and a chemical mechanical polishing process is used to obtain a flush workpiece surface.

[0023] Furthermore, the method of the present invention also discloses an improvement for obtaining an SBR (Super Barrier Rectifier) ​​circuit.

[0024] Among them: the process after the oxygen-nitrogen sandwich mask is removed in the shielding gate area also includes gate oxidation, gate polysilicon deposition, gate polysilicon CMP and etching, nitrogen oxide removal, P-well lithography implantation and functional area isolation steps.

[0025] Through the gate oxidation step, after removing the oxygen-nitrogen sandwich mask and etching to obtain the gate trench, oxidation is performed to generate an oxide layer covering the MOSFET area and a gate oxide layer connecting the first oxide layer in the gate trench and filling the SBR area trench; the gate oxide layer is combined with the original oxide layer to form a fifth oxide layer.

[0026] The gate polysilicon deposition step deposits polysilicon into the gate trench and further covers the entire device surface to a preset thickness.

[0027] Through the gate polysilicon CMP and etching steps, with the fifth oxide layer as the termination layer, the CMP method is adopted to obtain an exposed oxide layer in the MOSFET area and retain polysilicon in the source area. Among them, the polysilicon in the MOSFET area must be lower than the exposed oxide layer surface after the etching process, so that the polysilicon layer in the SBR area is flush with other materials.

[0028] The oxynitride in the SBR region is removed by the oxynitride removal step, thereby obtaining a polysilicon workpiece located in the source trench and protruding from the oxide layer.

[0029] Through the P-well lithography and implantation steps, the P-well is constructed and the electrode contacts are implanted into the MOSFET region.

[0030] Through the functional area isolation step, an interlayer dielectric is used to fill each groove on the surface of the workpiece and cover the entire workpiece.

[0031] Furthermore, through improved metal layer preparation steps and contact hole connection steps, a metal film is constructed outside the interlayer dielectric body, so that the metal film is connected with the MOSFET area and the SBR area through the contact hole.

[0032] One improvement method is to make the thickness of the first mask no greater than 50Å and the thickness of the second oxide layer no greater than 1000Å.

[0033] Still further, a rectifier circuit can be used to obtain corresponding rectifier circuits, voltage converters, power supplies and other circuits or devices by using the method of the present invention.

[0034] Through the structurally associated gate structure unit and Schottky rectifier unit, the parasitic body diode of the Schottky rectifier unit is connected in parallel with the gate structure unit; the characteristic patterns of the gate structure unit and the Schottky rectifier unit are transferred to the workpiece by the same or same series of masks; the circuit preparation process includes M masks, wherein the Nth mask is a step mark mask, and the Rth to Sth masks are used to synchronize with the transfer process of the shielding gate characteristic pattern and form the characteristic pattern of the Schottky rectifier circuit; N≤R≤S≤M, M≠N, and M, N, R and S are all positive integers.

[0035] Furthermore, a voltage converter adopts the method of the present invention to prepare a core rectifier unit, and its rectifier and / or freewheeling unit is implemented by the method of the present invention or adopts the rectifier circuit disclosed in the present invention to perform chopping processing.

[0036] Furthermore, the rectifier circuits arranged in the low-side MOSFET of the converter can be replaced by the circuit disclosed in the present invention to obtain optimized performance; wherein, an external auxiliary circuit is also included to complete the boost or buck conversion, and the rectifier circuit includes a Schottky rectifier circuit integrated in the converter and a MOSFET parasitic body diode manufactured by synchronous integration, and the Schottky rectifier circuit is connected in parallel with the parasitic body diode.

[0037] The present invention integrates a Schottky rectifier region in parallel with a MOSFET parasitic body diode on the existing structure, which can replace the parallel structure of a MOSFET and a freewheeling diode and obtain a lower reverse recovery characteristic, thereby reducing the conduction power consumption at high frequencies.

[0038] It should be noted that the terms "first", "second" and similar terms used in this article are only for describing the various components in the technical solution, and do not constitute a limitation of the technical solution, nor can they be understood as an indication or suggestion of the importance of the corresponding elements; elements with "first", "second" and similar terms indicate that the corresponding technical solution contains at least one of the element. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solution of the present invention and facilitate further understanding of the technical effects, technical features and purposes of the present invention, the present invention is described in detail below in conjunction with the accompanying drawings. The accompanying drawings constitute an essential part of the specification and are used together with the embodiments of the present invention to illustrate the technical solution of the present invention, but do not constitute a limitation to the present invention.

[0040] The same reference numerals in the accompanying drawings represent the same components, specifically:

[0041] Figure 1 A schematic diagram of trench etching according to an embodiment of the present invention;

[0042] Figure 2 This is a schematic diagram of thick oxygen layer deposition according to an embodiment of the present invention;

[0043] Figure 3 This is a schematic diagram of the deposition of the first (source) polysilicon (layer) according to an embodiment of the present invention;

[0044] Figure 4 This is a schematic diagram of etching back the first (source) polysilicon (layer) according to an embodiment of the present invention;

[0045] Figure 5 A schematic diagram of etching a source polysilicon groove with photoresist added according to an embodiment of the present invention;

[0046] Figure 6 This is a schematic diagram of high-density plasma vapor deposition of an oxide (layer) in an embodiment (third) of the present invention;

[0047] Figure 7 This is a schematic diagram of chemical mechanical polishing of the oxide (layer) in the third embodiment of the present invention;

[0048] Figure 8 A schematic diagram of the division of the gate channel and the rectification area according to an embodiment of the present invention;

[0049] Fig. 9 This is a schematic diagram of removing the oxygen-nitrogen sandwich mask according to an embodiment of the present invention;

[0050] Fig.10 This is a schematic diagram of gate oxidation according to an embodiment of the present invention;

[0051] Fig.11 This is a schematic diagram of the deposition of the second (gate) polysilicon (layer) according to an embodiment of the present invention;

[0052] Fig.12 This is a schematic diagram of chemical mechanical polishing and etching of the second (gate) polysilicon (layer) according to an embodiment of the present invention;

[0053] Fig.13 It is a schematic diagram of removing the second mask (nitride layer) according to an embodiment of the present invention;

[0054] Fig.14 Schematic diagram of P-well photolithography and ion implantation according to an embodiment of the present invention;

[0055] Fig.15 It is a schematic diagram of source photolithography / ion implantation and interlayer dielectric deposition in an embodiment of the present invention;

[0056] Fig.16 This is a schematic diagram of the parallel structure of MOS and SBR according to an embodiment of the present invention;

[0057] Fig.17 This is a schematic diagram of a voltage conversion circuit according to an embodiment of the present invention;

[0058] Fig.18 This is a schematic diagram of a process flow of an embodiment of the method of the present invention;

[0059] Fig.19 It is a schematic diagram of the process of improving the method of the present invention;

[0060] Fig. 20 This is a schematic diagram of the process of Improvement 2 of the method of the present invention;

[0061] in:

[0062] 10- shielding grid, 20- Schottky rectifier circuit;

[0063] 100-drain (layer), 101-(deep) gate trench group,

[0064] 102- first mask (first oxide layer) or thermal oxide layer,

[0065] 104-third mask (second oxide layer),

[0066] 105-thick oxide layer (third oxide layer),

[0067] 106 - second mask (nitride layer),

[0068] 108- source polysilicon (first polysilicon layer),

[0069] 109-second groove group,

[0070] 110-first photoresist (layer),

[0071] 111- the third groove group,

[0072] 112- fourth oxide layer,

[0073] 114- Functional area division mask (layer),

[0074] 115-fifth oxide layer,

[0075] 116- second (gate) polysilicon (layer),

[0076] 118- second photoresist (layer),

[0077] 120-P well (implantation) (layer),

[0078] 122- ILD interlayer dielectric,

[0079] 124-electrode contact body,

[0080] 1000-Low-side MOSFET and accessory circuits,

[0081] 2000-voltage conversion output terminal,

[0082] 3000-Inductor Unit,

[0083] 3200-intersection point of high side and low side,

[0084] 4000-High-side MOSFET and accessory circuits,

[0085] 5000-voltage conversion input terminal,

[0086] 6000-Control circuit power supply terminal,

[0087] 7000-Power supply control circuit. DETAILED DESCRIPTION

[0088] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. Of course, the specific embodiments described below are only for explaining the technical solutions of the present invention, rather than for limiting the present invention. In addition, the parts described in the embodiments or the accompanying drawings are only examples of the relevant parts of the present invention, rather than the whole of the present invention.

[0089] like Fig.18 The figure shows a flow chart of an embodiment of a method for manufacturing a MOSFET rectifier circuit of the present invention; between the preceding process 200 and the succeeding process 600 are the steps of preparing the gate structure 300, associating the structure 400 and generating the freewheeling part 500 of the present invention.

[0090] Among them, it includes a mask preset step: by preparing a first mask, a second mask to an Nth mask, wherein N is a positive integer greater than 10; preparing an N+1th mask, an N+2th mask to an Mth mask, wherein M is a positive integer greater than 12.

[0091] It also includes a mask optimization step: by using the first mask, the second mask to the Nth mask, the N+1th mask to the Mth mask in sequence; wherein M>N; by using the first to Mth masks, the preset circuit pattern is converted to a preset target position.

[0092] like Fig.18 and Fig.16 As shown, the gate structure preparation step 300 completes the preparation of the device switch circuit core by preparing the shielding gate 10: wherein, the preparation of the shielding gate 10 uses a total of M masks; the first characteristic pattern of the Schottky rectifier circuit 20 is prepared on the R-th mask, and the second characteristic pattern of the Schottky rectifier circuit 20 is prepared on the R+1-th mask; wherein, N≤R≤M, M≠N; the last characteristic pattern required for the Schottky rectifier circuit 20 is prepared on the S-th mask; wherein, N≤R≤S≤M, M≠N, and R and S are both positive integers.

[0093] like Fig.16 In the structural association step, the process parameters in the gate structure preparation step are adjusted so that the Schottky rectifier circuit 20 is connected in parallel with the parasitic body diode of the shielding gate 10; the shielding gate 10 is a trench structure, including an ILD interlayer dielectric 122 and a polysilicon gate 116, and the interlayer dielectric 122 is used to isolate the polysilicon gate 116 filled in the trench; the source 108, the gate 116, and the drain 100 of the rectifier circuit are connected to the pins of the rectifier circuit, wherein the source 108 and the gate 116 are connected to the metal layer 128 through the contact hole 126.

[0094] like Fig.16 and Fig.17The freewheeling portion generation steps shown in the figure connect the source 108 and the gate 116 through the contact hole 126, and the contact hole 126 passes through the ILD interlayer dielectric 122 and is connected to the source 108, the gate 116 and the drain 100; wherein, the source 108 of the Schottky rectifier circuit 20 is directly electrically connected to the metal layer 128, and the end of the source 108 of the rectifier circuit 20 away from the metal layer 128 is electrically connected to the drain 100 through a groove structure, and its groove structure obtains a characteristic pattern between the R mask and the S mask.

[0095] Furthermore, if Fig.16 and 17 As shown, in the functional area optimization step, a functional area optimization layer is prepared, and the functional area optimization layer is a membrane structure, which is prepared by deposition, electroplating and / or other membrane processes; the characteristic pattern of the functional area optimization layer includes a MOSFET functional area pattern and a Schottky rectifying area pattern; the MOSFET functional area pattern and the Schottky rectifying area pattern are transferred to the target position under the action of the same mask or the same series of masks.

[0096] After the Schottky rectifying region 20 is transferred through the Nth mask, characteristic patterns of at least two contact holes are transferred on the drain of the rectifying region.

[0097] Through Figure 1 The removal process of the oxygen-nitrogen sandwich mask shown is used to define or etch the gate oxide working window of the MOSFET and the rectifier unit, and the working window is used to obtain the gate oxide layer through an oxidation process; the gate oxide layer is used to isolate the gate polysilicon layer and other related layers and obtain related circuit units.

[0098] like Figure 1 The oxygen-nitrogen sandwich shown includes a first mask 102 , a second mask 106 and a third mask 104 ; the first mask 102 is a first oxide layer or a thermal oxide layer, the second mask 106 is a nitride layer, and the third mask is the second oxide layer 104 .

[0099] Furthermore, if Figures 1 to 7 and Fig.19 As shown, the optimization steps of the MOSFET circuit of this embodiment; wherein, the process of removing the oxygen-nitrogen sandwich mask before the shielding gate 10 region is also included:

[0100] Groove group etching step 302: Figure 1 A first type substrate 100 is obtained by an epitaxial process, and a gate trench group 101 is obtained by etching in the first type substrate layer 100. The gate trench group 101 includes at least three trenches, and the depth of each trench is not less than the depth of the preset source first trench.

[0101] like Figure 2 and Fig.19The thick oxide deposition step 304 is performed by depositing a third silicon oxide layer 105 on the bottom surface and side surfaces of the gate trench set 101 ; wherein the third oxide layer 105 and the second oxide layer 104 may have the same or different oxide materials.

[0102] like Figure 3 and Fig.19 The polysilicon source deposition step 306 is shown to form source polysilicon, ie, the first polysilicon layer 108 , by depositing polysilicon on the third oxide layer 105 until the gate trench and the surface of the workpiece are filled.

[0103] like Figure 4 and Fig.19 The polysilicon source etching back step 308 is shown, by etching back the first polysilicon layer 108 where the polysilicon source is located, retaining the thick oxygen layer sidewalls of the gate trench group 101, and obtaining the second trench group 109 covered by the thick oxygen sidewalls, wherein the depth of the second trench group 109 is greater than the thickness of the oxygen-nitrogen sandwich mask.

[0104] like Figure 5 and Fig.19 The polysilicon groove etching step 310 with photoresist is shown, and at least two third trench groups 111 that are close to the Schottky rectifier circuit 20 are obtained in combination with the photoresist.

[0105] like Figure 6 and Fig.19 In the oxide HDP step 312 , high density plasma CVD is used to deposit oxide to obtain a fourth oxide layer 112 to seal the first polysilicon layer 108 .

[0106] like Figure 7 and Fig.19 The oxide CMP step 314 is shown: using the second mask 106 as a stop layer, a chemical mechanical polishing process is used to obtain a flush workpiece surface.

[0107] Furthermore, if Figures 8 to 16 and Fig. 20 As shown, the preparation of the SBR circuit of this embodiment includes the following steps; wherein: the process after the oxygen-nitrogen sandwich mask is removed in the shielding gate 10 region also includes:

[0108] like Figure 8-10 and Fig. 20 The gate oxidation step 402 shown is: after removing the oxygen-nitrogen sandwich mask and etching to obtain the gate trench, oxidation is performed to generate an oxide layer covering the MOSFET area and a gate oxide layer connecting the first oxide layer in the gate trench and filling the SBR area trench, and the gate oxide layer is combined with the original oxide layer to form a fifth oxide layer 115.

[0109] Usually, the SBR area needs a corresponding mask to define a specific area and match the relevant process to realize the corresponding device function; the embodiment of the present invention uses a self-alignment process to simplify the multi-step process to achieve the same effect; Figure 8 In the process, the SBR area can be defined while the gate trench is obtained by masking and etching.

[0110] like Fig.11 and Fig. 20 The gate polysilicon deposition step 404 is shown to deposit polysilicon into the gate trench and further cover the entire device surface to a predetermined thickness.

[0111] like Fig.12 and Fig. 20 The gate polysilicon CMP and etching step 406 is shown: using the fifth oxide layer 115 as the termination layer, the CMP method is used to obtain an exposed oxide layer in the MOSFET area and retain polysilicon in the source area, wherein the polysilicon in the MOSFET area must be lower than the exposed oxide layer surface after the etching process, and the polysilicon layer in the SBR area is made flush with other materials.

[0112] like Fig.13 and Fig. 20 The oxynitride removal step 408 is shown to remove the oxynitride in the SBR region to obtain the polysilicon workpiece film 116 in the source trench and protruding from the oxide layer.

[0113] like Fig.14 and Fig. 20 The P-well lithography and implantation step 410 is shown by constructing the P-well 120 and implanting the electrode contacts 124 into the MOSFET region.

[0114] like Fig.15 and Fig. 20 In the functional area isolation step 412, an interlayer dielectric 122 is used to fill each groove on the surface of the workpiece and cover the entire workpiece.

[0115] like Fig.16 As shown, in the metal layer preparation step, a metal film 128 is constructed outside the interlayer dielectric 122 ; the metal film 128 is connected to the MOSFET region and the SBR region through the contact hole 126 .

[0116] Through process optimization, the thickness of the first mask can be controlled to be no more than 50Å, and the thickness of the second oxide layer can be controlled to be no more than 1000Å.

[0117] like Fig.17 FIG. 1 is a circuit diagram of a rectifier circuit and a voltage conversion circuit of the present invention, wherein:

[0118] The gate structure unit and the Schottky rectifier unit are structurally related, and the Schottky rectifier unit is connected in parallel with the microscopic parasitic diode of the gate structure unit; the characteristic patterns of the gate structure unit and the Schottky rectifier unit are transferred to the workpiece by the same or same series of masks.

[0119] Furthermore, the circuit preparation process may include M masks, wherein the Nth mask is a step marking mask, and the Rth to Sth masks are used to synchronize with the transfer process of the shielding grid characteristic pattern and form the characteristic pattern of the Schottky rectifier circuit; N≤R≤S≤M, M≠N, M, N, R and S are all positive integers.

[0120] like Fig.17 The voltage conversion circuit shown in the figure adopts the rectifier circuit disclosed in the present invention to perform chopping processing; wherein the rectifier circuit arranged in the MOSFET of the converter low side 1000 or the rectifier circuit directly obtained according to the method of the present invention also includes the following Fig.17 The external auxiliary circuit shown is used to complete the step-up or step-down conversion, and its rectifier circuit includes a Schottky rectifier circuit integrated in the converter and a MOSFET parasitic body diode manufactured by synchronous integration, and the Schottky rectifier circuit is connected in parallel with the parasitic body diode; its auxiliary circuit includes a voltage conversion output terminal 2000, an inductor unit 3000, and its high-side and low-side junction 3200 is connected to the voltage conversion output terminal 2000 through the inductor 3200; one end of the high-side MOSFET 4000 is connected to the voltage conversion input terminal 5000, and the other end is connected to the high-side and low-side junction 3200; the control circuit power supply terminal, 6000 is the power control circuit 7000.

[0121] The power supply using the above circuit has similar switching characteristics and working performance based on the above principle, and its specific technical solution will not be described in detail.

[0122] It should be noted that the above embodiments are only for more clearly illustrating the technical solutions of the present invention. Those skilled in the art will understand that the implementation methods of the present invention are not limited to the above contents, and obvious changes, replacements or substitutions based on the above contents do not exceed the scope of the technical solutions of the present invention; other implementation methods will also fall within the scope of the present invention without departing from the concept of the present invention.

Claims

1. A method for manufacturing a MOSFET rectifier circuit, characterized in that: include: The mask presetting step includes: preparing a first mask, a second mask, and finally an N-th mask, wherein N is a positive integer greater than 10; preparing an N+1-th mask, an N+2-th mask, and finally an M-th mask, wherein M is a positive integer greater than 12; The mask optimization step: sequentially using the first mask, the second mask, the Nth mask, the N+1th mask, and the Mth mask; wherein M>N; by using the first to the Mth masks, converting a preset circuit pattern to a preset target position; The gate structure preparation steps include: preparing a shielding gate (10), wherein the preparation of the shielding gate (10) uses a total of M masks; preparing a first characteristic pattern of a Schottky rectifier circuit (20) on an R-th mask, and preparing a second characteristic pattern of the Schottky rectifier circuit (20) on an R+1-th mask; wherein N≤R≤M, and M≠N; preparing a last characteristic pattern required for the Schottky rectifier circuit (20) on an S-th mask; wherein N≤R≤S≤M, and M≠N, and R and S are both positive integers; Structural association step: adjusting the process parameters in the gate structure preparation step so that the Schottky rectifier circuit (20) is connected in parallel with the parasitic body diode of the shielding gate (10); the shielding gate (10) is a trench structure, the shielding gate (10) comprises an ILD interlayer dielectric (122) and a polysilicon gate (116), and the interlayer dielectric (122) is used to isolate the polysilicon gate (116) filled in the trench; connecting the source (108), gate (116), and drain (100) of the rectifier circuit to the pins of the rectifier circuit, wherein the source (108) and the gate (116) are connected to the metal layer (128) through contact holes (126); The step of generating a freewheeling portion includes: connecting the source (108) electrode and the gate (116) electrode through the contact hole (126), wherein the contact hole (126) passes through the ILD interlayer dielectric (122) and is connected to the source (108), the gate (116) and the drain (100); wherein the source (108) electrode of the Schottky rectifier circuit (20) is directly electrically connected to the metal layer (128), and an end of the source (108) electrode of the rectifier circuit (20) away from the metal layer (128) is electrically connected to the drain (100) electrode through a groove structure, and the groove structure obtains the characteristic pattern between the R mask and the S mask.

2. The method of claim 1, further comprising: Functional area optimization step: preparing a functional area optimization layer, wherein the functional area optimization layer is a membrane structure and is prepared by deposition, electroplating and / or other membrane processes; The characteristic pattern of the functional area optimization layer includes a MOSFET functional area pattern and a Schottky rectifying area pattern; the MOSFET functional area pattern and the Schottky rectifying area pattern are transferred to the target position under the same photomask or the same series of photomasks; Wherein, after the Schottky rectifying region is transferred through the Nth mask, at least two characteristic patterns of the contact holes are transferred on the drain of the rectifying region.

3. The method of claim 2, wherein: The gate oxide layer working window of the MOSFET and the rectifying unit is defined or etched by removing the oxygen-nitrogen sandwich mask, and the working window is used to obtain the gate oxide layer by oxidation process; the gate oxide layer is used to isolate the gate polysilicon layer and other related layers and obtain related circuit units; The oxygen-nitrogen interlayer comprises a first mask (102), a second mask (106) and a third mask (104); the first mask (102) is a first oxide layer or a thermal oxide layer, the second mask (106) is a nitride layer, and the third mask is a second oxide layer (104).

4. The method of claim 3 further comprising a MOSFET circuit optimization step, in, The manufacturing process of the oxygen-nitrogen sandwich mask before removing the shielding gate (10) region also includes: A groove group etching step (302): epitaxially obtaining a first type base layer, and etching in the first type base layer to obtain a gate groove group (101), wherein the gate groove group (101) comprises at least three grooves, and the depth of each groove in the gate groove group (101) should not be less than the depth of the preset source first groove; Thick oxygen deposition step (304): depositing a silicon third oxide layer (105) on the bottom surface and side elevations of the gate trench group (101), wherein the third oxide layer (105) and the second oxide layer (104) have the same or different oxide materials; A polysilicon source deposition step (306): depositing polysilicon on the third oxide layer (105) until the gate trench and the surface of the workpiece are filled to form source polysilicon, namely, a first polysilicon layer (108); A polysilicon source etching back step (308): etching back the first polysilicon layer (108) where the polysilicon source is located, retaining the thick oxygen layer sidewalls of the gate trench group (101), and obtaining a second trench group (109) covered by the thick oxygen sidewalls, wherein the depth of the second trench group (109) is greater than the thickness of the oxygen-nitrogen sandwich mask; A polysilicon groove etching step (310) with photoresist added: combining the photoresist to obtain at least two third groove groups (111) that are close to the Schottky rectifier circuit (20); Oxide HDP step (312): using high density plasma CVD to deposit oxide to obtain a fourth oxide layer (112) to seal the first polysilicon layer (108); Oxide CMP step (314): using the second mask (106) as a stop layer, a chemical mechanical polishing process is used to obtain a flush workpiece surface.

5. The method of claim 3, further comprising the step of acquiring an SBR circuit, in: The process after the oxygen-nitrogen sandwich mask is removed in the shielding gate (10) region further includes: Gate oxidation step (402): after removing the oxygen-nitrogen sandwich mask and etching to obtain a gate trench, oxidation is performed to generate an oxide layer covering the MOSFET region and a gate oxide layer in the gate trench that is connected to the first oxide layer and fills the SBR region trench, the gate oxide layer is combined with the original oxide layer to form a fifth oxide layer (115); Gate polysilicon deposition step (404): depositing polysilicon into the gate trench and further covering the entire device surface to a preset thickness; Gate polysilicon CMP and etching step (406): using the fifth oxide layer (115) as a stop layer, using a CMP method to obtain an exposed oxide layer in the MOSFET region and retaining polysilicon in the source region, wherein the polysilicon in the MOSFET region must be lower than the surface of the exposed oxide layer after the etching process, and the polysilicon layer in the SBR region is flush with other materials; Nitrogen oxide removal step (408): removing the nitrogen oxide in the SBR region to obtain a polysilicon workpiece (116) in the source trench and protruding from the oxide layer; P-well photolithography and implantation step (410): constructing a P-well (120) and implanting an electrode contact (124) into the MOSFET region; Functional area isolation step (412): using the interlayer dielectric (122) to fill each groove on the surface of the workpiece and cover the entire workpiece.

6. The method according to claim 4 or 5, further comprising: A metal layer preparation step and a contact hole connection step; The metal layer preparation step constructs a metal film (128) outside the interlayer dielectric (122); the metal film (128) is connected to the MOSFET region and the SBR region via a contact hole (126).

7. The method of claim 6, wherein: The thickness of the first mask is no greater than 50Å; The thickness of the second oxide layer is no more than 1000Å.

8. A rectifier circuit comprising: A gate structure unit and a Schottky rectifier unit having structural associations, wherein the Schottky rectifier unit is connected in parallel with a parasitic body diode of the gate structure unit; and characteristic patterns of the gate structure unit and the Schottky rectifier unit are transferred to a workpiece by using the same or same series of photomasks; The preparation process of the circuit includes M masks, wherein the Nth mask is a step marking mask, and the Rth to Sth masks are used to synchronize with the transfer process of the shielding grid characteristic pattern and form the characteristic pattern of the Schottky rectifier circuit; N≤R≤S≤M, M≠N, M, N, R and S are all positive integers.

9. A voltage converter, comprising: The rectifying and / or freewheeling unit thereof is prepared by any method as claimed in claims 1 to 7; Or adopt the rectifier circuit as claimed in claim 8 to perform chopping processing.

10. The converter according to claim 9, wherein: The rectifier circuit as claimed in claim 8 or the rectifier circuit obtained as claimed in any one of claims 1 to 7, arranged in the low-side MOSFET of the converter, also includes an external auxiliary circuit to complete the boost or buck conversion, and the rectifier circuit includes a Schottky rectifier circuit integrated in the converter and a MOSFET parasitic body diode manufactured by synchronous integration, and the Schottky rectifier circuit is connected in parallel with the parasitic body diode.

11. A power supply comprising: The rectifier circuit as claimed in claim 8 and / or the voltage converter as claimed in claim 9 or 10.

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