Fan-out chip packaging method and fan-out chip packaging structure

Abstract

Embodiments of the present invention provide a fan-out chip packaging method and a fan-out chip packaging structure, which relate to the technical field of semiconductor packaging. By mounting and forming a first film bump on the surface of a carrier, then encapsulating to form an encapsulant covering the first film bump, then removing the carrier and the first film bump, leaving the encapsulant with a first groove, then mounting a first chip in the first groove, forming a passivation layer on the surface of the encapsulant, and finally forming a wiring combination layer and completing ball implantation. Compared with the prior art, the present invention can avoid using the method of etching grooves on a silicon substrate to protect the chip, thus avoiding a series of problems caused by etching. And by using the method of reverse molding of the film bump, the process difficulty is reduced, and the size control of the first groove is more precise, which is beneficial to the installation of the chip. In addition, since the encapsulation action is completed on the carrier, the problem of encapsulation warping can be effectively prevented under the support of the carrier.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular, to a fan-out chip packaging method and a fan-out chip packaging structure. Background Art

[0002] With the rapid development of the semiconductor industry, fan-out wafer level package (FOWLP) packaging structures are widely used in the semiconductor industry. Generally, a single chip is cut from a wafer and then packaged onto a carrier wafer. The main advantages include high-density integration, small size of the packaged product, excellent product performance, fast signal transmission frequency, etc. The fan-out technology mainly realizes multi-pin output and the smaller the output pin pitch. Therefore, during the fan-out wafer chip packaging process, there are prone to problems such as plastic package warping, and as the number of wafer packages increases, the warping degree also increases.

[0003] The traditional process uses silicon material as a substrate. After etching and grooving the silicon material, the chip is mounted in the silicon material groove. However, due to the brittle nature of the silicon material, there is a risk of damage under external force. Once cracks occur, the product reliability is greatly affected. At the same time, when using the existing silicon material for packaging multiple different chip wafers, it is necessary to perform multiple etching operations separately to form grooves of different sizes for placing the chips. Therefore, the process is relatively complex and it is difficult to control the etching depth in the etching process. Once over-etching occurs, there will be exposure of the bottom material on the back of the chip. Summary of the Invention

[0004] The objectives of the present invention include, for example, providing a fan-out chip packaging method and a fan-out chip packaging structure that can avoid placing chips by etching grooves in a silicon substrate and can effectively solve the warping problem existing in the prior art.

[0005] Embodiments of the present invention can be implemented as follows:

[0006] In a first aspect, the present invention provides a fan-out chip packaging method, including:

[0007] Forming a first film adhesive protrusion on one side surface of a carrier;

[0008] Forming a plastic package body on one side surface of the carrier, covering the first film adhesive protrusion;

[0009] Removing the carrier and the first film adhesive protrusion to form a first groove corresponding to the first film adhesive protrusion on one side surface of the plastic package body;

[0010] Mounting a first chip in the first groove;

[0011] Forming a passivation layer on one side surface of the plastic package body;

[0012] Form a wiring combination layer on the passivation layer;

[0013] Mount balls on the wiring combination layer to form solder balls;

[0014] Wherein, the size of the first film bump is adapted to the size of the first chip, the passivation layer covers the first groove and the first chip, and the solder ball is electrically connected to the wiring combination layer, and the wiring combination layer is electrically connected to the first chip.

[0015] In an alternative embodiment, after the step of forming the first film bump on one surface of the carrier, the method further includes:

[0016] Mount a pre-mounted chip on the carrier.

[0017] In an alternative embodiment, the step of forming the first film bump on one surface of the carrier includes:

[0018] Dispose a first film layer on one surface of the carrier;

[0019] Dispose a second film layer on the first film layer;

[0020] Remove the second film layer in a first preset area and expose the first film layer to form a first film bump.

[0021] In an alternative embodiment, the step of forming the first film bump on one surface of the carrier includes:

[0022] Dispose a first film layer on one surface of the carrier;

[0023] Dispose a second film layer on the first film layer;

[0024] Remove the second film layer in a second preset area and expose the first film layer to form a first film bump and a second film bump;

[0025] Wherein, the second film bump is located between the first film bump and the pre-mounted chip.

[0026] In an alternative embodiment, the step of removing the carrier and the first film bump includes:

[0027] Cut the carrier;

[0028] Remove the first film bump and the carrier at its corresponding position to form the first groove;

[0029] Remove the carrier at the corresponding position of the pre-mounted chip to expose the pre-mounted chip.

[0030] In an alternative embodiment, the step of forming a passivation layer on one surface of the encapsulant includes:

[0031] Forming a first passivation layer on the surface of the encapsulant to cover the first chip and the pre-attached chip;

[0032] Removing the second adhesive film protrusion and the carrier at its corresponding position to form a second groove;

[0033] Mounting a second chip in the second groove;

[0034] Forming a second passivation layer on the surface of the encapsulant to cover the second chip.

[0035] In an alternative embodiment, there are multiple second adhesive film protrusions. The step of forming a passivation layer on one surface of the encapsulant includes:

[0036] Forming a first passivation layer on the surface of the encapsulant to cover the first chip and the pre-attached chip;

[0037] Removing the carrier at the position corresponding to the second adhesive film protrusion;

[0038] Removing a part of the second adhesive film protrusion to form a second groove;

[0039] Mounting a second chip in the second groove;

[0040] Forming a second passivation layer on the surface of the encapsulant to cover the second chip and the second adhesive film protrusion.

[0041] In an alternative embodiment, the step of forming a wiring combination layer on the passivation layer includes:

[0042] Providing a first metal layer on the passivation layer that penetrates through to the first chip;

[0043] Forming a first wiring layer on the passivation layer;

[0044] Providing a second metal layer on the first wiring layer that penetrates through to the first metal layer;

[0045] Forming a second wiring layer on the first wiring layer;

[0046] Providing a third metal layer on the second wiring layer that penetrates through to the second metal layer;

[0047] Wherein, the first metal layer is electrically connected to the first chip, the second metal layer is electrically connected to the first metal layer, the third metal layer is electrically connected to the second metal layer, and the third metal layer is used for electrical connection with the solder ball.

[0048] Second aspect, the present invention provides a fan-out chip packaging structure, which is prepared by using the fan-out chip packaging method described in any one of the foregoing embodiments. The fan-out chip packaging structure includes:

[0049] A plastic package body having a first groove provided on one surface;

[0050] A first chip mounted in the first groove;

[0051] A passivation layer provided on one surface of the plastic package body;

[0052] A wiring combination layer provided on the passivation layer;

[0053] And solder balls provided on the wiring combination layer;

[0054] Wherein, the passivation layer covers the first groove and the first chip, and the solder balls are electrically connected to the wiring combination layer, and the wiring combination layer is electrically connected to the first chip.

[0055] In an optional embodiment, the fan-out chip packaging structure further includes a second adhesive film protrusion, and the second adhesive film protrusion is embedded in the plastic package body and contacts the passivation layer.

[0056] The beneficial effects of the embodiments of the present invention include, for example:

[0057] The present invention provides a fan-out chip packaging method and a fan-out chip packaging structure. By mounting a first adhesive film protrusion on the surface of a carrier, then performing plastic packaging to form a plastic package body covering the first adhesive film protrusion, then removing the carrier and the first adhesive film protrusion, retaining the plastic package body with the first groove, then mounting a first chip in the first groove, and forming a passivation layer on the surface of the plastic package body, and finally forming a wiring combination layer and completing ball implantation. Compared with the prior art, the fan-out chip packaging method and structure provided by the present invention can form a groove by the way of reverse molding of the adhesive film protrusion, avoiding the formation of grooves by etching in the conventional technology. At the same time, the size of the first groove is determined by the first adhesive film protrusion, and the size of the first adhesive film protrusion is adapted to the size of the first chip, so that the first groove can be directly set according to the size of the first chip, which is convenient for placing the chip. In addition, since the plastic packaging action is completed on the carrier, with the support of the carrier, the problem of plastic packaging warping can be effectively prevented. Compared with the prior art, the fan-out chip packaging method and the fan-out chip packaging structure provided by the embodiments of the present invention can avoid using the method of etching grooves on a silicon substrate to prevent chips, thus avoiding a series of problems brought by etching. And by adopting the way of reverse molding of the adhesive film protrusion, the process difficulty is reduced, and the size control of the first groove is more accurate, which is beneficial to the installation of the chip. In addition, since the plastic packaging action is completed on the carrier, the problem of plastic packaging warping can be effectively prevented under the support of the carrier. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of the present invention, and thus should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0059] Figures 1 to 10 Process flow chart of the fan-out chip packaging method provided by the first embodiment of the present invention;

[0060] Figure 11 Schematic diagram of the fan-out chip packaging structure provided by the first embodiment of the present invention;

[0061] Figure 12 Process flow chart of the fan-out chip packaging method provided by the second embodiment of the present invention;

[0062] Figure 13 Schematic diagram of the fan-out chip packaging structure provided by the second embodiment of the present invention;

[0063] Figures 14 to 22 Process flow chart of the fan-out chip packaging method provided by the third embodiment of the present invention;

[0064] Figure 23 Schematic diagram of the fan-out chip packaging structure provided by the third embodiment of the present invention;

[0065] Figure 24 Process flow chart of the fan-out chip packaging method provided by the fourth embodiment of the present invention;

[0066] Figure 25 Schematic diagram of the fan-out chip packaging structure provided by the fourth embodiment of the present invention.

[0067] Reference Signs: 100 - fan-out chip packaging structure; 110 - plastic package; 111 - first groove; 113 - second groove; 120 - first chip; 130 - passivation layer; 131 - first passivation layer; 133 - second passivation layer; 140 - wiring combination layer; 141 - first wiring layer; 143 - second wiring layer; 145 - first metal layer; 147 - second metal layer; 149 - third metal layer; 150 - solder ball; 160 - pre-attached chip; 170 - second chip; 200 - carrier; 210 - first adhesive film layer; 230 - second adhesive film layer; 250 - first adhesive film protrusion; 270 - second adhesive film protrusion. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0068] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Usually, the components of the embodiments of the present invention described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0069] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed present invention, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0070] It should be noted that: similar reference numerals and letters indicate similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0071] In the description of the present invention, it should be noted that if terms such as "upper", "lower", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the invention is usually placed during use, it is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention.

[0072] In addition, terms such as "first" and "second" are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0073] As disclosed in the background art, in the existing fan out technology, silicon material is usually used as the substrate. After etching and grooving, the chip is mounted in the silicon material groove. However, due to the brittle characteristics of the silicon material and the risk of damage under external force, once cracks occur, the reliability of the product is greatly affected. At the same time, it is difficult to control the etching size and depth of the groove for the existing silicon material, and different chips require multiple etching to form grooves of different sizes and depths for chip placement, which undoubtedly makes the process more complex and difficult to control. Once over-etching occurs, there is a risk of exposing the bottom material on the back of the chip.

[0074] In addition, the existing fan-out wafer chip packaging method cannot control chip encapsulation and wiring in regions, and there is a problem of greater difficulty in design modification. Currently, design modification is carried out by adding an additional layer of circuit layer for wiring to connect the newly added chip regions, which undoubtedly makes the process more complex and reduces the product reliability due to incompatibility with the original structure.

[0075] To solve the above problems, the present invention provides a novel fan-out chip packaging method and a fan-out chip packaging structure. It should be noted that, without conflict, the features in the embodiments of the present invention can be combined with each other.

[0076] The first embodiment

[0077] This embodiment provides a fan-out chip packaging method, which can avoid placing chips by etching grooves in a silicon substrate and can effectively solve the warping problem existing in the prior art.

[0078] Referring to Figure 11 , the fan-out chip packaging method provided in this embodiment is used to prepare a fan-out chip packaging structure 100, where the fan-out chip packaging structure 100 includes a plastic package 110, a first chip 120, a passivation layer 130, a wiring combination layer 140, and solder balls 150. A first groove 111 is provided on one side surface of the plastic package 110, and the first chip 120 is mounted in the first groove 111. At the same time, the passivation layer 130 is provided on one side surface of the plastic package 110 and covers the first groove 111 and the first chip 120. The wiring combination layer 140 is provided on the passivation layer 130, and the solder balls 150 are provided on the wiring combination layer 140. The solder balls 150 are electrically connected to the wiring combination layer 140, and the wiring combination layer 140 is electrically connected to the first chip 120.

[0079] The fan-out chip packaging method provided in this embodiment specifically includes the following steps:

[0080] S1: Form a first adhesive film protrusion 250 on one side surface of the carrier 200.

[0081] Referring successively to Figure 1 and Figure 2 , specifically, when forming the first adhesive film protrusion 250, first provide a carrier 200, and provide a first adhesive film layer 210 on one side surface of the carrier 200, and then provide a second adhesive film layer 230 on the first adhesive film layer 210. Both the first adhesive film layer 210 and the second adhesive film layer 230 are UV adhesive layers, which facilitate subsequent peeling and removal operations. After the second adhesive film layer 230 is pasted, through a cutting process or a photomask process (exposure / development), the second adhesive film layer 230 in the first preset area is removed, and the first adhesive film layer 210 is exposed. The remaining second adhesive film layer 230 forms the first adhesive film protrusion 250. It should be noted that the shape of the first chip 120 can be used as the photomask shape here, and the excess second adhesive film layer 230 is removed. Among them, the thickness of the second adhesive film layer 230 is adapted to the thickness of the first chip 120 and determines the depth of the first groove 111.

[0082] It should be noted that the first film protrusion 250 here can also be formed of other materials, such as resin, encapsulation filler, metal, etc. There is no specific limitation here, as long as the subsequent peeling action can be satisfied.

[0083] S2: Form an encapsulant 110 on one side surface of the carrier 200 that covers the first film protrusion 250.

[0084] Combined with reference to Figure 3 , specifically, after forming the first film protrusion 250, using the encapsulation process, an encapsulant 110 is formed by encapsulation on the surface of the carrier 200, and the encapsulant 110 is used to protect the bottom film structure. Compared with the conventional technology that uses silicon material for protection, the anti-external force impact strength is greatly improved. And, by completing the preparation of the encapsulant 110 on the carrier 200 and using the supporting effect of the carrier 200, the encapsulation warping phenomenon can be effectively prevented, and the encapsulant 110 is prevented from warping and affecting the product quality.

[0085] S3: Remove the carrier 200 and the first film protrusion 250.

[0086] Combined with reference to Figure 4 , specifically, after removing the carrier 200 and the first film protrusion 250, a first groove 111 corresponding to the first film protrusion 250 is formed on one side surface of the encapsulant 110. Among them, both the first film protrusion 250 and the first film layer 210 are UV glue layers. By irradiating UV light or heating, the first film layer 210 and the first film protrusion 250 can be removed, and the carrier 200 can be peeled off, thus forming an encapsulant 110 with a first groove 111.

[0087] S4: Mount the first chip 120 in the first groove 111.

[0088] Combined with reference to Figure 5 , specifically, after removing the carrier 200 and the first film protrusion 250, the first chip 120 is mounted in the first groove 111. Among them, the first chip 120 is mounted upward, that is, the pads are upward, and an adhesive film is coated on the back of the first chip 120. The first chip 120 is adhesively fixed in the first groove 111 by using the adhesive film and cured by baking. Among them, the size of the first groove 111 needs to be adapted to the size of the first chip 120, so as to facilitate chip mounting. After completing the mounting of the first chip 120, it is also necessary to complete the dispensing work in the first groove 111 to fill the gap between the first chip 120 and the first groove 111 and bake and cure it. The dispensing layer can play a buffering role.

[0089] S5: Form a passivation layer 130 on one side surface of the encapsulant 110.

[0090] Combined with reference toFigure 6 Specifically, after the first chip 120 is mounted, a layer of dielectric material can be spin-coated on one side surface of the encapsulant 110, and after curing, the passivation layer 130 is formed. Among them, after the first chip 120 is mounted, a dispensing process can be performed to fill the gap between the first chip 120 and the first groove 111. At this time, one side surface of the encapsulant 110 is in a flat state, and the dielectric material can be directly coated. After the first chip 120 is mounted, the dispensing process can also be omitted and the dielectric material can be directly coated. The dielectric material will also fill the gap between the first chip 120 and the first groove 111, that is, the passivation layer 130 extends into the gap between the first chip 120 and the first groove 111 to complete the filling operation.

[0091] S6: Form a wiring combination layer 140 on the passivation layer 130.

[0092] Refer to Figure 7 Specifically, after the passivation layer 130 is formed, grooves are formed on the surface of the passivation layer 130 by plasma etching to expose the pads on the first chip 120, and then the first metal layer 145 is formed by processes such as electroplating. The first metal layer 145 is in contact with the pads on the first chip 120 and realizes electrical connection.

[0093] Refer to Figure 8 Then, a layer of dielectric material is spin-sprayed to form the first wiring layer 141. Then, a patterned conductive layer is formed on the first wiring layer 141 again. After exposure and development, a patterned opening is formed to expose the first metal layer 145. Then, electroplating is performed again to form the second metal layer 147. The second metal layer 147 penetrates through to the first metal layer 145 and is in electrical contact with the first metal layer 145. Among them, the second metal layer 147 serves as a circuit layer to realize the circuit connection of the product.

[0094] Refer to Figure 9 After the second metal layer 147 is formed, a layer of dielectric material is spin-coated on the first wiring layer 141 again to form the second wiring layer 143. Then, laser grooving is performed on the second wiring layer 143 again to expose the second metal layer 147, and the third metal layer 149 is formed by using the electroplating process. The third metal layer 149 is in electrical contact with the second metal layer 147 and is used for electrical connection with the solder ball 150. The third metal layer 149 can be a copper pillar, the bottom end is a copper pillar, and a UBM layer is formed on the surface of the copper pillar to improve the solderability of the solder ball 150.

[0095] Of course, in other preferred embodiments of the present invention, the ball mounting operation can also be directly completed on the first metal layer 145 of the passivation layer 130 without performing the wiring operation, and the signal output can be directly performed, thereby reducing the process cost.

[0096] It should be noted that the dielectric materials mentioned in this embodiment may be silicon nitride, silicon oxynitride, polyimide, benzocyclobutene, etc. At the same time, the first wiring layer 141 and the second wiring layer 143 can also be formed by processes such as physical vapor deposition (PVD) and chemical vapor deposition (CVD), which are not specifically limited here. At the same time, the first metal layer 145, the second metal layer 147, and the third metal layer 149 can all be copper materials, and the third metal layer 149 can be a copper pillar.

[0097] S7: Ball mounting is performed on the wiring combination layer 140 to form solder balls 150.

[0098] Referring to Figure 10 , specifically, after the third metal layer 149 is formed, solder balls 150 can be formed on the third metal layer 149 by means of stencil printing or ball mounting. The materials of the solder balls 150 can be SnAg, SnAgCu, etc. Finally, the cutting operation is completed to complete the preparation of the product.

[0099] Referring to Figure 11 , this embodiment also provides a fan-out chip package structure 100, which is prepared by using the above-mentioned fan-out chip packaging method. The fan-out chip package structure 100 includes a molding body 110, a first chip 120, a passivation layer 130, a wiring combination layer 140, and solder balls 150. A first groove 111 is provided on one side surface of the molding body 110, and the first chip 120 is mounted in the first groove 111. At the same time, the passivation layer 130 is provided on one side surface of the molding body 110 and covers the first groove 111 and the first chip 120. The wiring combination layer 140 is provided on the passivation layer 130, and the solder balls 150 are provided on the wiring combination layer 140. The solder balls 150 are electrically connected to the wiring combination layer 140, and the wiring combination layer 140 is electrically connected to the first chip 120.

[0100] In this embodiment, the wiring combination layer 140 includes a first wiring layer 141 and a second wiring layer 143. A first metal layer 145 is provided in the passivation layer 130, a second metal layer 147 is provided in the first wiring layer 141, a third metal layer 149 is provided in the second wiring layer 143, and the solder balls 150 are provided on the third metal layer 149. The third metal layer 149 is electrically connected to the second metal layer 147, the second metal layer 147 is electrically connected to the first metal layer 145, and the first metal layer 145 is electrically connected to the pads of the first chip 120, so that the first chip 120 is electrically connected to the solder balls 150 through the first metal layer 145, the second metal layer 147, and the third metal layer 149, thereby realizing signal output.

[0101] In summary, for the fan-out chip packaging method and the fan-out chip packaging structure 100 provided in this embodiment, a first film bump 250 is formed by surface mounting on a carrier 200, and then a molding compound is formed to form a molding compound body 110 covering the outside of the first film bump 250. Then, the carrier 200 and the first film bump 250 are removed, and the molding compound body 110 with a first groove 111 is retained. Then, a first chip 120 is mounted in the first groove 111, and a passivation layer 130 is formed on the surface of the molding compound body 110. Finally, a wiring combination layer 140 is formed and ball implantation is completed. For the fan-out chip packaging method and structure provided in this embodiment, a groove can be formed by means of inverse molding of the film bump, avoiding the formation of grooves by etching in the conventional technology. At the same time, the size of the first groove 111 is determined by the first film bump 250, and the size of the first film bump 250 is adapted to the size of the first chip 120, so that the first groove 111 can be directly set according to the size of the first chip 120, which is convenient for placing the chip. In addition, since the molding compound operation is completed on the carrier 200, with the supporting effect of the carrier 200, the problem of molding compound warping can be effectively prevented. The fan-out chip packaging method and the fan-out chip packaging structure 100 provided in this embodiment can avoid using the method of etching grooves in a silicon substrate to prevent chips, thus avoiding a series of problems brought by etching. And by adopting the method of inverse molding of the film bump, the process difficulty is reduced, and the size control of the first groove 111 is more accurate, which is beneficial to the installation of the chip. In addition, since the molding compound operation is completed on the carrier 200, the problem of molding compound warping can be effectively prevented under the support of the carrier 200.

[0102] Second Embodiment

[0103] This embodiment provides a fan-out chip packaging method. Its basic steps, principles, and the resulting technical effects are the same as those of the first embodiment. For a brief description, for the parts not mentioned in this embodiment, reference can be made to the corresponding content in the first embodiment.

[0104] Compared with the first embodiment, the difference in this embodiment is that after step S1, the method further includes the following steps:

[0105] S11: Mount a pre-mounted chip 160 on the carrier 200.

[0106] Combined with reference to Figure 12 , specifically, after forming the first film bump 250, the pre-mounted chip 160 is directly mounted on the first film layer 210. The type and size of the pre-mounted chip 160 can be the same as or different from those of the first chip 120 to be mounted subsequently. Among them, the pre-mounted chip 160 is mounted downward, that is, the pads of the pre-mounted chip 160 are mounted downward on the first film layer 210, so that the pre-mounted chip 160 can be exposed after the subsequent removal of the carrier 200.

[0107] The subsequent steps are the same as those in the first embodiment. Specifically, in step S2, the encapsulant 110 encapsulates the first film bump 250 and the pre-attached chip 160 simultaneously. In step S3, after removing the carrier 200 and the first film bump 250, the pre-attached chip 160 needs to be retained in the encapsulant 110. In step S5, the passivation layer 130 needs to cover the pre-attached chip 160 and the first chip 120 simultaneously. In step S6, the wiring combination layer 140 needs to be electrically connected to the pre-attached chip 160. Specifically, the first metal layer 145 makes electrical contact with the pads of the pre-attached chip 160.

[0108] The fan-out chip packaging method provided in this embodiment has the following specific preparation process: Take a carrier 200, and mount the first film layer 210 and the second film layer 230 on its surface. Here, the laser process or the photomask process is used to pattern the second film layer 230 in the first preset area to form the first film bump 250. Then, the pre-attached chip 160 is mounted on the first film layer 210 and is spaced apart from the first film bump 250. Then, the encapsulation process is performed again to form the encapsulant 110 to protect the mounted structure. Then, the first film layer 210 is separated from the encapsulant 110 by UV separation or thermal separation, so as to remove the carrier 200, the first film layer 210 and the first film bump 250, retain the pre-attached chip 160 in the encapsulant 110, and form a first groove 111 corresponding to the first film bump 250 on the encapsulant 110. Then, the first chip 120 is attached in the first groove 111. Its subsequent process is the same as that in the first embodiment.

[0109] It should be noted that there can be multiple pre-attached chips 160 here. In this embodiment, one is taken as an example for illustration. Here, the pre-attached chip 160 is mounted first, then the encapsulation is performed, and then the mounting and wiring processes of the first chip 120 are performed. Since the pre-attached chip 160 and the first chip 120 are respectively mounted, and only the pre-attached chip 160 is present during encapsulation, the warping problem caused by the simultaneous encapsulation of the pre-attached chip 160 and the first chip 120 in the traditional process is avoided. At the same time, for the pre-attached chip 160 and the first chip 120, there is no need to etch multiple times to form different grooves for chip placement, further simplifying the process flow and avoiding the etching process.

[0110] See Figure 13, this embodiment also provides a fan-out chip packaging structure 100, which is formed by using the aforementioned fan-out chip packaging method. Its basic structure, principle, technical effects are the same as those of the first embodiment. For the sake of brief description, for the parts not mentioned in this embodiment, reference can be made to the corresponding content in the first embodiment. The fan-out chip packaging structure 100 includes a plastic package 110, a first chip 120, a passivation layer 130, a wiring combination layer 140, solder balls 150, and a pre-attached chip 160. A first groove 111 is provided on one surface of the plastic package 110, and the first chip 120 is mounted in the first groove 111. The pre-attached chip 160 is embedded in the plastic package 110. At the same time, the passivation layer 130 is provided on one surface of the plastic package 110 and covers the pre-attached chip 160, the first groove 111, and the first chip 120. The wiring combination layer 140 is provided on the passivation layer 130, and the solder balls 150 are provided on the wiring combination layer 140. The solder balls 150 are electrically connected to the wiring combination layer 140, and the wiring combination layer 140 is simultaneously electrically connected to the first chip 120 and the pre-attached chip 160.

[0111] The third embodiment

[0112] This embodiment provides a fan-out chip packaging method. Its basic steps, principle, and technical effects are the same as those of the first embodiment or the second embodiment. For the sake of brief description, for the parts not mentioned in this embodiment, reference can be made to the corresponding content in the first embodiment or the second embodiment.

[0113] The fan-out chip packaging method provided by this embodiment includes the following steps:

[0114] S1: Form a first adhesive film protrusion 250 and a second adhesive film protrusion 270 on one surface of the carrier 200.

[0115] Combined with reference to Figure 14 , specifically, when forming the first adhesive film protrusion 250 and the second adhesive film protrusion 270, first provide a carrier 200, and provide a first adhesive film layer 210 on one surface of the carrier 200, and then provide a second adhesive film layer 230 on the first adhesive film layer 210. Both the first adhesive film layer 210 and the second adhesive film layer 230 are UV adhesive layers, which facilitate subsequent peeling and removal operations. After the second adhesive film layer 230 is pasted, through a cutting process or a photomask process (exposure / development), the second adhesive film layer 230 in the second preset area is removed, and the first adhesive film layer 210 is exposed. The remaining second adhesive film layer 230 forms the first adhesive film protrusion 250 and the second adhesive film protrusion 270. It should be noted that the shape of the first chip 120 and the second chip 170 can be used as the photomask shape here, and the redundant second adhesive film layer 230 is removed. Among them, the thickness of the second adhesive film layer 230 is adapted to the thickness of the first chip 120 and the second chip 170, and determines the depth of the subsequent first groove 111 and the second groove 113.

[0116] It should be noted that in a single product unit, the number of the second film protrusions 270 here is two, and the two second film protrusions 270 and the first film protrusion 250 are arranged in sequence, so as to jointly form three film protrusion structures.

[0117] After step S1, the method further includes step S11: mounting a pre-mounted chip 160 on the carrier 200.

[0118] Referring to Figure 15 , specifically, after forming the first film protrusion 250 and the second film protrusion 270, directly mount the pre-mounted chip 160 on the first film layer 210. The type and size of the pre-mounted chip 160 can be the same as or different from those of the first chip 120 to be mounted subsequently. Among them, the pre-mounted chip 160 is mounted downward, that is, the pads of the pre-mounted chip 160 are mounted downward on the first film layer 210, so that the pre-mounted chip 160 can be exposed after removing the carrier 200 subsequently. At the same time, the second film protrusion 270 is located between the first film protrusion 250 and the pre-mounted chip 160, that is, the two second film protrusions 270 are located between the first film protrusion 250 and the pre-mounted chip 160.

[0119] S2: Form a plastic package 110 covering the first film protrusion 250 on one side surface of the carrier 200.

[0120] Referring to Figure 16 , specifically, after completing the mounting of the pre-mounted chip 160, use the plastic packaging process to form a plastic package 110 on the surface of the carrier 200, and use the plastic package 110 to protect the bottom film structure. Compared with the conventional technology that uses silicon materials for protection, the anti-external force impact strength is greatly improved. And, by completing the preparation of the plastic package 110 on the carrier 200 and using the supporting effect of the carrier 200, the phenomenon of plastic package warping can be effectively prevented, and the quality of the product is prevented from being affected by the warping of the plastic package 110.

[0121] S3: Remove the carrier 200 and the first film protrusion 250.

[0122] Referring to Figure 17 , specifically, here the carrier 200 can be peeled off in a segmented removal manner. First, cut the carrier 200, and the cutting lines are located on both sides of the pre-mounted chip 160 and both sides of the first film protrusion 250. Then, block the carrier 200 at the corresponding position of the second film protrusion 270, and by irradiating UV light or heating, remove the first film protrusion 250 and the carrier 200 at its corresponding position to form a first groove 111. At the same time, remove the carrier 200 at the corresponding position of the pre-mounted chip 160 to expose the pads of the pre-mounted chip 160.

[0123] S4: Mount the first chip 120 in the first groove 111.

[0124] Refer to Figure 18 , specifically, after removing the first adhesive film protrusion 250 and the corresponding position of the carrier 200, mount the first chip 120 in the first groove 111. Among them, the first chip 120 is mounted upward, that is, the pads are upward, and an adhesive film is coated on the back of the first chip 120. The first chip 120 is bonded and fixed in the first groove 111 by using the adhesive film and cured by baking. Among them, the size of the first groove 111 needs to be adapted to the size of the first chip 120 to facilitate chip mounting.

[0125] S5: Form a first passivation layer 131 on the surface of the encapsulant 110 to cover the first chip 120 and the preset chip.

[0126] Refer to Figure 19 , specifically, after completing the mounting of the first chip 120, a layer of dielectric material can be spin-coated at the position corresponding to the first chip 120 and the preset chip on one side surface of the encapsulant 110, and after curing, the first passivation layer 131 is formed. Among them, after mounting the first chip 120, a dispensing process can be carried out to fill the gap between the first chip 120 and the first groove 111. At this time, one side surface of the encapsulant 110 is in a flat state, and the dielectric material can be directly coated. After mounting the first chip 120, the dispensing process can also not be carried out and the dielectric material can be directly coated. The dielectric material will also fill the gap between the first chip 120 and the first groove 111, that is, the passivation layer 130 extends to the gap between the first chip 120 and the first groove 111 to complete the filling operation.

[0127] It should be noted that after completing the preparation of the first passivation layer 131, the grooving operation can also be completed in advance on the first passivation layer 131 to expose the pads of the first chip 120 and the preset chip, facilitating the subsequent process.

[0128] S6: Remove the second adhesive film protrusion 270 and the corresponding position of the carrier 200.

[0129] Refer to Figure 20 , specifically, remove the second adhesive film protrusion 270 and the remaining carrier 200. The removal method is the same as that in step S3. After removal, a second groove 113 is formed on the encapsulant 110.

[0130] S7: Mount the second chip 170 in the second groove 113.

[0131] Refer to Figure 21, specifically, after removing the vehicle 200 and the second adhesive film protrusion 270, the second chip 170 is mounted in the second groove 113. Among them, the second chip 170 is mounted upward, that is, the pads are upward, and an adhesive film is coated on the back of the second chip 170. The second chip 170 is bonded and fixed in the second groove 113 by using the adhesive film and cured by baking. Among them, the size of the second groove 113 needs to be adapted to the size of the second chip 170 to facilitate chip mounting. After completing the mounting of the second chip 170, it is also necessary to complete the dispensing work in the second groove 113 to fill the gap between the second chip 170 and the second groove 113 and bake and cure it. The dispensing layer can play a buffering role.

[0132] S8: Form a second passivation layer 133 covering the second chip 170 on the surface of the encapsulation body 110.

[0133] Refer to Figure 22 , specifically, after completing the mounting of the second chip 170, a second passivation layer 133 is formed at the corresponding position of the second chip 170 by spin-coating a dielectric material again. The second passivation layer 133 is joined to the first passivation layer 131 to form a complete passivation layer 130 structure.

[0134] S9: Complete the wiring combination layer 140 on the first passivation layer 131 and the second passivation layer 133.

[0135] Specifically, after forming the first passivation layer 131 and the second passivation layer 133, grooves are formed on the surface of the second passivation layer 133 by plasma etching to expose the pads on the second chip 170. The grooves on the first passivation layer 131 can be formed in advance or formed here together, and the pads of the first chip 120, the pads of the second chip 170, and the pads of the pre-mounted chip 160 are all exposed.

[0136] Then, the preparation of the first metal layer 145, the first wiring layer 141, the second metal layer 147, the second wiring layer 143, and the third metal layer 149 is completed on the first passivation layer 131 and the second passivation layer 133. The preparation process is similar to that in the first embodiment and will not be described in detail here.

[0137] S10: Ball mounting is performed on the wiring combination layer 140 to form solder balls 150.

[0138] Specifically, after forming the third metal layer 149, solder balls 150 can be formed on the third metal layer 149 by using stencil printing or ball mounting methods. The material of the solder balls 150 can be SnAg, SnAgCu, etc. Finally, the cutting operation is completed to complete the preparation of the product.

[0139] Refer to Figure 23, this embodiment also provides a fan-out chip packaging structure 100, which is prepared by using the aforementioned fan-out chip packaging method. Its basic structure, principle, and the resulting technical effects are the same as those of the first embodiment or the second embodiment. For the sake of brief description, for the parts not mentioned in this embodiment, reference can be made to the corresponding content in the first embodiment or the second embodiment. The fan-out chip packaging structure 100 includes a molding compound 110, a first chip 120, a second chip 170, a passivation layer 130, a wiring combination layer 140, solder balls 150, and a pre-attached chip 160. A first groove 111 and a second groove 113 are provided on one surface of the molding compound 110. The first chip 120 is mounted in the first groove 111, the second chip 170 is mounted in the second groove 113, the pre-attached chip 160 is embedded in the molding compound 110. At the same time, the passivation layer 130 is provided on one surface of the molding compound 110 and covers the pre-attached chip 160, the first chip 120, and the second chip 170. The wiring combination layer 140 is provided on the passivation layer 130, and the solder balls 150 are provided on the wiring combination layer 140. The solder balls 150 are electrically connected to the wiring combination layer 140, and the wiring combination layer 140 is simultaneously electrically connected to the first chip 120, the second chip 170, and the pre-attached chip 160.

[0140] Among them, the passivation layer 130 includes a first passivation layer 131 and a second passivation layer 133. Among them, the first passivation layer 131 and the second passivation layer 133 are formed successively, and the first passivation layer 131 covers the first chip 120 and the pre-attached chip 160, and the second passivation layer 133 covers the second chip 170.

[0141] In summary, this embodiment provides a fan-out chip packaging method and a fan-out chip packaging structure 100. It adopts a method of partitioning and mounting chips. First, the carrier 200 in the area of the first film bump 250 and the pre-attached chip 160 is removed, the mounting of the first chip 120 and the coverage of the first passivation layer 131 are completed, and then the carrier 200 in the area of the second film bump 270 is removed to complete the mounting of the second chip 170 and the coverage of the second passivation layer 133. The advantage is that the coverage of the first passivation layer 131 at the left and right ends is carried out first to balance the warping of the molding compound 110, and then the coverage of the second passivation layer 133 in the middle area is carried out, which can effectively solve the warping problem caused by the molding of multiple chips in the traditional process.

[0142] Fourth Embodiment

[0143] This embodiment provides a fan-out chip packaging method. Its basic steps, principle, and the resulting technical effects are the same as those of the third embodiment. For the sake of brief description, for the parts not mentioned in this embodiment, reference can be made to the corresponding content in the third embodiment.

[0144] Compared with the fourth embodiment, the difference of the fan-out chip packaging method provided in this embodiment lies in that after step S5. In this embodiment, steps S1 - S4 are the same as those in the third embodiment and will not be described again here. The fan-out chip packaging method provided in this embodiment includes the following steps:

[0145] Steps S1 - S4 can refer to the third embodiment.

[0146] It should be noted that the separate mounting of the first adhesive film layer 210 and the second adhesive film layer 230 here is beneficial to the subsequent retention of the second adhesive film protrusion 270.

[0147] S5: Form a first passivation layer 131 covering the first chip 120 and the preset chip on the surface of the encapsulant 110.

[0148] Please continue to refer to Figure 19 , specifically, after the mounting of the first chip 120 is completed, a dielectric material can be spin-coated at the positions corresponding to the first chip 120 and the preset chip on one side surface of the encapsulant 110, and after curing, the first passivation layer 131 is formed.

[0149] S6: Remove the carrier 200 at the position corresponding to the second adhesive film protrusion 270, and remove part of the second adhesive film protrusion 270.

[0150] Combined with referring to Figure 24 , specifically, after removing the remaining carrier 200, one of the second adhesive film protrusions 270 can be removed, and the other second adhesive film protrusion 270 is retained, thereby forming a single second groove 113.

[0151] Step S7: Mount the second chip 170 in the second groove 113.

[0152] Specifically, after removing the carrier 200 and one of the second adhesive film protrusions 270, a single second groove 113 is formed, and then the second chip 170 is mounted in the second groove 113. Among them, the second chip 170 is mounted upward, that is, the pads are upward, and an adhesive film is coated on the back surface of the second chip 170. The second chip 170 is bonded and fixed in the second groove 113 by using the adhesive film and cured by baking.

[0153] S8: Form a second passivation layer 133 covering the second chip 170 and the second adhesive film protrusion 270 on the surface of the encapsulant 110.

[0154] Specifically, the second passivation layer 133 covers the second chip 170 and the second adhesive film protrusion 270, thereby covering both the second chip 170 and the second adhesive film protrusion 270, so that the second adhesive film protrusion 270 can be retained in the encapsulant 110.

[0155] Steps S9 and S10 are the same as those in the third embodiment, and for details, reference can be made to the third embodiment.

[0156] Participate Figure 25 , this embodiment also provides a fan-out chip packaging structure 100, which is prepared by using the aforementioned fan-out chip packaging method. Its basic structure, principle, and the resulting technical effects are the same as those in the third embodiment. For a brief description, for parts not mentioned in this embodiment, reference can be made to the corresponding content in the third embodiment. The fan-out chip packaging structure 100 includes a plastic package 110, a first chip 120, a second chip 170, a passivation layer 130, a wiring combination layer 140, solder balls 150, a pre-attached chip 160, and a second film bump 270. A first groove 111 and a second groove 113 are provided on one side surface of the plastic package 110. The first chip 120 is mounted in the first groove 111, the second chip 170 is mounted in the second groove 113, the pre-attached chip 160 and the second film bump 270 are embedded in the plastic package 110. At the same time, the passivation layer 130 is provided on one side surface of the plastic package 110 and covers the pre-attached chip 160, the first chip 120, and the second chip 170. The wiring combination layer 140 is provided on the passivation layer 130, and the solder balls 150 are provided on the wiring combination layer 140. The solder balls 150 are electrically connected to the wiring combination layer 140, and the wiring combination layer 140 is simultaneously electrically connected to the first chip 120, the second chip 170, and the pre-attached chip 160.

[0157] Among them, the passivation layer 130 includes a first passivation layer 131 and a second passivation layer 133. The first passivation layer 131 and the second passivation layer 133 are formed successively, and the first passivation layer 131 covers the first chip 120 and the pre-attached chip 160, and the second passivation layer 133 covers the second chip 170 and the second film bump 270.

[0158] It should be noted that in this embodiment, a second film bump 270 is reserved. The reserved second film bump 270 is not separated from the plastic package 110 for the first time, and can be separated by subsequent processes, which can be chemical or physical methods. The temperature characteristic of its characteristic material needs to be greater than the first separation condition.

[0159] In summary, for the fan-out chip packaging method and the fan-out chip packaging structure provided in this embodiment, by retaining at least one second film bump 270 in the plastic package 110, the problems of chip design modification and RDL line design modification required for product upgrade and version change in traditional processes can be solved. At the same time, the second film bump 270 in the reserved second groove 113 can act as an internal buffer layer of the product, further improving the warping problem.

[0160] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims described above.

Claims

1. A fan-out chip packaging method, characterized in that, it includes: forming a first film adhesive protrusion on one side surface of a carrier; forming a plastic package on one side surface of the carrier, covering the first film adhesive protrusion; removing the carrier and the first film adhesive protrusion to form a first groove corresponding to the first film adhesive protrusion on one side surface of the plastic package; mounting a first chip in the first groove; forming a passivation layer on one side surface of the plastic package; forming a wiring combination layer on the passivation layer; planting balls on the wiring combination layer to form solder balls; wherein, the size of the first film adhesive protrusion is adapted to the size of the first chip, the passivation layer covers the first groove and the first chip, and the solder balls are electrically connected to the wiring combination layer, and the wiring combination layer is electrically connected to the first chip.

2. The fan-out chip packaging method according to claim 1, characterized in that, after the step of forming a first film adhesive protrusion on one side surface of a carrier, the method further includes: mounting a pre-mounted chip on the carrier.

3. The fan-out chip packaging method according to claim 2, characterized in that, the step of forming a first film adhesive protrusion on one side surface of a carrier includes: providing a first film adhesive layer on one side surface of the carrier; providing a second film adhesive layer on the first film adhesive layer; removing the second film adhesive layer in a first preset area to expose the first film adhesive layer, so as to form a first film adhesive protrusion.

4. The fan-out chip packaging method according to claim 2, characterized in that, the step of forming a first film adhesive protrusion on one side surface of a carrier includes: providing a first film adhesive layer on one side surface of the carrier; providing a second film adhesive layer on the first film adhesive layer; removing the second film adhesive layer in a second preset area to expose the first film adhesive layer, so as to form a first film adhesive protrusion and a second film adhesive protrusion; wherein, the second film adhesive protrusion is located between the first film adhesive protrusion and the pre-mounted chip.

5. The fan-out chip packaging method according to claim 4, characterized in that, the step of removing the carrier and the first film adhesive protrusion includes: cutting the carrier; removing the first film adhesive protrusion and the carrier at its corresponding position to form the first groove; removing the carrier at the corresponding position of the pre-mounted chip to expose the pre-mounted chip.

6. The fan-out chip packaging method according to claim 5, characterized in that, the step of forming a passivation layer on one side surface of the plastic package includes: forming a first passivation layer covering the first chip and the pre-mounted chip on the surface of the plastic package; removing the second film adhesive protrusion and the carrier at its corresponding position to form a second groove; mounting a second chip in the second groove; forming a second passivation layer covering the second chip on the surface of the plastic package.

7. For the fan-out chip packaging method according to claim 5, the second film adhesive protrusion is multiple, characterized in that, the step of forming a passivation layer on one side surface of the plastic package includes: forming a first passivation layer covering the first chip and the pre-mounted chip on the surface of the plastic package; Remove the carrier at the position corresponding to the second film bump; Remove a part of the second film bump to form a second groove; Mount a second chip in the second groove; Form a second passivation layer covering the second chip and the second film bump on the surface of the plastic package.

8. The fan-out chip packaging method according to any one of claims 1-7, characterized in that the step of forming a wiring combination layer on the passivation layer includes: providing a first metal layer penetrating through to the first chip on the passivation layer; forming a first wiring layer on the passivation layer; providing a second metal layer penetrating through to the first metal layer on the first wiring layer; forming a second wiring layer on the first wiring layer; providing a third metal layer penetrating through to the second metal layer on the second wiring layer; wherein the first metal layer is electrically connected to the first chip, the second metal layer is electrically connected to the first metal layer, the third metal layer is electrically connected to the second metal layer, and the third metal layer is used for electrical connection with the solder ball.

9. A fan-out chip packaging structure, characterized in that it is prepared by using the fan-out chip packaging method according to any one of claims 1-8, and the fan-out chip packaging structure includes: a plastic package having a first groove provided on one side surface; a first chip mounted in the first groove; a passivation layer provided on one side surface of the plastic package; a wiring combination layer provided on the passivation layer; and, solder balls provided on the wiring combination layer; wherein the passivation layer covers the first groove and the first chip, and the solder balls are electrically connected to the wiring combination layer, and the wiring combination layer is electrically connected to the first chip.

10. The fan-out chip packaging structure according to claim 9, characterized in that the fan-out chip packaging structure further includes a second film bump, and the second film bump is embedded in the plastic package and contacts the passivation layer.

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