Solid-state imaging element, imaging device, and method for controlling solid-state imaging element

Abstract

In a solid-state imaging element that detects the presence or absence of an address event, pixel miniaturization is facilitated. The solid-state imaging element includes a plurality of detection pixels and a detection circuit. In the solid-state imaging element including the plurality of detection pixels and the detection circuit, each of the plurality of detection pixels generates a voltage signal based on the logarithmic value of the photocurrent. Furthermore, in the solid-state imaging element including the plurality of detection pixels and the detection circuit, the detection circuit detects whether a change in the voltage signal of a detection pixel indicated by an input selection signal among the plurality of detection pixels exceeds a predetermined threshold.

Description

Technical Field

[0001] The present technology relates to a solid-state imaging element, an imaging device, and a method for controlling the solid-state imaging element. Specifically, the present technology relates to a solid-state imaging element, an imaging device, and a method for controlling the solid-state imaging element that compares a change in brightness with a threshold value. Background Art

[0002] Typically, synchronous solid-state imaging elements that capture image data (frames) in synchronization with a synchronization signal such as a vertical synchronization signal have been used in imaging devices and the like. According to this conventional synchronous solid-state imaging element, image data can only be obtained in each cycle of the synchronization signal (for example, 1 / 60 second), making it difficult to cope with situations where faster processing is required in fields related to transportation, robots, etc. Therefore, an asynchronous solid-state imaging element has been proposed that detects the fact that the amount of change in pixel brightness for each pixel address exceeds a threshold as an address event (for example, see Patent Document 1). As described above, a solid-state imaging element that detects an address event for each pixel is called a dynamic vision sensor (DVS).

[0003] Reference List

[0004] Patent Document 1: Japanese Patent No. 5244587. Summary of the Invention

[0005] Problems to be solved by the present invention

[0006] In the aforementioned asynchronous solid-state imaging element, the presence or absence of an address event is detected to increase the speed of processing such as image recognition. However, a large number of circuits, such as a logarithmic response unit, a buffer, a differentiator, and a comparator, are required for each pixel to detect the presence or absence of an address event. This increases the circuit scale per pixel compared to synchronous solid-state imaging elements. This makes pixel miniaturization difficult.

[0007] The present technology has been conceived in view of such circumstances, and an object of the present technology is to facilitate miniaturization of pixels in a solid-state imaging element that detects the presence or absence of an address event.

[0008] Solution to the problem

[0009] The present technology was conceived to address the aforementioned issues, and its first aspect is a solid-state imaging element and a control method thereof. The solid-state imaging element includes a plurality of detection pixels, each of which generates a voltage signal corresponding to the logarithmic value of a photocurrent, and a detection circuit that detects whether the amount of change in the voltage signal of a detection pixel indicated by an input selection signal among the plurality of detection pixels exceeds a predetermined threshold value. This achieves the effect of reducing the circuit scale of the solid-state imaging element.

[0010] Furthermore, in the first aspect, the detection circuit may include a selection unit for selecting any voltage signal from each of the plurality of detection pixels; a differentiator for obtaining and outputting a variation in the selected voltage signal; and a comparison unit for comparing the output variation with a threshold value. This reduces the circuit size of the differentiator and subsequent components.

[0011] Furthermore, in the first aspect, the differentiator can hold the selected variation and output it to the comparison unit, which achieves the effect of detecting the address event of the selected detection pixel.

[0012] Furthermore, in the first aspect, the differentiator can hold the variation of each of the plurality of detection pixels and output the variation corresponding to the selected detection pixel to the comparison unit. This achieves an effect of suppressing omission of detection of address events.

[0013] Furthermore, in the first aspect, each of the plurality of detection pixels may include a logarithmic response unit that generates a voltage signal and a differentiator that obtains a variation in the generated voltage signal and outputs the variation to the detection circuit. This reduces the circuit size of the comparison unit and subsequent elements.

[0014] Furthermore, in the first aspect, the detection circuit may include a comparison unit that selects any change amount of each of the plurality of detection pixels and compares the selected change amount with a threshold value. This achieves the effect of detecting an address event of the selected detection pixel.

[0015] Furthermore, in the first aspect, the detection circuit may include a selection unit that selects an arbitrary change amount of each of the plurality of detection pixels, and a comparison unit that compares the selected change amount with a threshold value. This achieves the effect of detecting an address event of the selected detection pixel.

[0016] In addition, in the first aspect, the threshold value may include an upper threshold value and a lower threshold value that are different from each other, and the detection circuit may include an upper limit comparator that compares the upper threshold value with the change amount and a lower limit comparator that compares the lower threshold value with the change amount. This achieves the effect of detecting the on event and the off event.

[0017] In addition, in the first aspect, the threshold value may include an upper threshold value and a lower threshold value that are different from each other, and the detection circuit may include a selection switch that selects the upper threshold value or the lower threshold value and a comparator that compares the selected threshold value with the variation. This achieves an effect of reducing the circuit scale of the comparison unit.

[0018] Furthermore, in the first aspect, a plurality of grayscale pixels may be further included, each grayscale pixel generating a pixel signal corresponding to the exposure amount. This achieves an effect that an image with a larger amount of information can be obtained.

[0019] Furthermore, in the first aspect, the threshold value may include an upper threshold value and a lower threshold value that are different from each other, and the detection circuit may include: an upper limit selector that selects the amount of change of one of the two detection pixels; a lower limit selector that selects the amount of change of the other of the two detection pixels; an upper limit comparator that compares the amount of change of the selected one detection pixel with the upper threshold value; and a lower limit comparator that compares the amount of change of the other selected detection pixel with the upper threshold value. This achieves the effect of detecting both the on-event and the off-event simultaneously.

[0020] Furthermore, in the first aspect, the detection circuit may include a plurality of comparators that compare the amount of change in different detection pixels with a threshold value; a selection unit that selects the comparison result of any one of the comparators; and a buffer that outputs the selected comparison result. This achieves the effect of sharing the buffer among the plurality of detection pixels.

[0021] Furthermore, in the first aspect, a portion of the plurality of detection pixels and the detection circuit can be provided on a predetermined light receiving chip, and the remainder of the plurality of detection pixels and the detection circuit can be provided on a predetermined detection chip. This achieves the effect of reducing the circuit scale of the detection chip.

[0022] Furthermore, a second aspect of the present technology is an imaging device comprising a plurality of detection pixels, each of which generates a voltage signal corresponding to the logarithmic value of a photocurrent; a detection circuit that detects whether a change in the voltage signal of a detection pixel, indicated by an input selection signal, among the plurality of detection pixels exceeds a predetermined threshold; and a signal processing unit that processes a detection signal indicating the detection result of the detection circuit. This achieves the effect of reducing the circuit scale of the imaging device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a block diagram illustrating an exemplary configuration of an imaging device according to a first embodiment of the present technology.

[0024] Figure 2 It is a block diagram illustrating an exemplary stacked structure of the solid-state imaging element according to the first embodiment of the present technology.

[0025] Figure 3 is an exemplary plan view of a light receiving chip according to the first embodiment of the present technology.

[0026] Figure 4 is an exemplary plan view of a detection chip according to the first embodiment of the present technology.

[0027] Figure 5 is an exemplary plan view of an address event detection unit according to the first embodiment of the present technology.

[0028] Figure 6 is a circuit diagram illustrating an exemplary configuration of a logarithmic response unit according to the first embodiment of the present technology.

[0029] Figure 7 is a block diagram illustrating an exemplary configuration of a detection block according to the first embodiment of the present technology.

[0030] Figure 8 is a circuit diagram illustrating an exemplary configuration of a differentiator according to a first embodiment of the present technology.

[0031] Figure 9 is a circuit diagram illustrating an exemplary configuration of a comparison unit according to the first embodiment of the present technology.

[0032] Figure 10 is a circuit diagram illustrating an exemplary configuration of a differentiator, a selector, and a comparator according to the first embodiment of the present technology.

[0033] Figure 11 is a timing chart illustrating exemplary control of the row driving circuit according to the first embodiment of the present technology.

[0034] Figure 12 is a block diagram illustrating an exemplary configuration of a detection pixel and a detection circuit according to the first embodiment of the present technology.

[0035] Figure 13 is a flowchart illustrating an exemplary operation of the solid-state imaging element according to the first embodiment of the present technology.

[0036] Figure 14 is a block diagram illustrating an exemplary configuration of a detection pixel and a detection circuit according to a modification of the first embodiment of the present technology.

[0037] Figure 15 is a timing chart illustrating exemplary control of a row drive circuit according to a modification of the first embodiment of the present technology.

[0038] Figure 16 is a block diagram illustrating an exemplary configuration of a detection pixel and a detection circuit according to a second embodiment of the present technology.

[0039] Figure 17 is a circuit diagram illustrating an exemplary configuration of a differentiator according to a third embodiment of the present technology.

[0040] Figure 18 is a timing chart illustrating an exemplary operation of the solid-state imaging element according to the third embodiment of the present technology.

[0041] Figure 19 is a circuit diagram illustrating an exemplary configuration of a comparison unit according to a fourth embodiment of the present technology.

[0042] Figure 20 is a circuit diagram illustrating an exemplary configuration of a differentiator and a comparator according to a fifth embodiment of the present technology.

[0043] Figure 21 is an exemplary plan view of a light receiving chip according to a sixth embodiment of the present technology.

[0044] Figure 22 is an exemplary plan view of a detection chip according to a sixth embodiment of the present technology.

[0045] Figure 23 is a circuit diagram illustrating an exemplary configuration of a grayscale pixel according to a sixth embodiment of the present technology.

[0046] Figure 24 is a circuit diagram illustrating an exemplary configuration of a comparison unit according to a seventh embodiment of the present technology.

[0047] Figure 25 is a block diagram showing an exemplary schematic configuration of a vehicle control system.

[0048] Figure 26 is an exemplary block diagram illustrating exemplary locations for mounting a vehicle exterior information detection unit and an imaging unit. DETAILED DESCRIPTION

[0049] Hereinafter, a mode for carrying out the present technology (hereinafter referred to as an embodiment) will be described. The description will be made in the following order.

[0050] 1. First Embodiment (Example in which a plurality of detection pixels share a detection circuit)

[0051] 2. Second Embodiment (Example in which a plurality of detection pixels share a detection circuit including a differentiator)

[0052] 3. Third Embodiment (Example in which a plurality of detection pixels share a detection circuit and a differentiator holds a plurality of variation amounts)

[0053] 4. Fourth Embodiment (Example in which a plurality of detection pixels share a detection circuit and switch thresholds)

[0054] 5. Fifth Embodiment (Example in which a plurality of detection pixels share a detection circuit and a comparator performs switching)

[0055] 6. Sixth Embodiment (Example in which a plurality of detection pixels share a detection circuit and configure grayscale pixels)

[0056] 7. Seventh Embodiment (Example in which a plurality of detection pixels share a detection circuit and two-stage elements are arranged in the detection circuit)

[0057] 8. Application of mobile objects

[0058] <1. First embodiment>

[0059] [Exemplary Configuration of Imaging Device]

[0060] Figure 1 This is a block diagram illustrating an exemplary configuration of an imaging device 100 according to a first embodiment of the present technology. The imaging device 100 includes an optical unit 110, a solid-state imaging element 200, a recording unit 120, and a control unit 130. The imaging device 100 is assumed to be a camera mounted on an industrial robot, an in-vehicle camera, or the like.

[0061] The optical unit 110 collects incident light and guides it to the solid-state imaging element 200. The solid-state imaging element 200 photoelectrically converts the incident light to capture image data. The solid-state imaging element 200 performs predetermined signal processing, such as image recognition processing, on the captured image data and outputs the processed data to the recording unit 120 via the signal line 209.

[0062] The recording unit 120 records data from the solid-state imaging element 200. The control unit 130 controls the solid-state imaging element 200 to capture image data.

[0063] [Exemplary Configuration of Solid-State Imaging Element]

[0064] Figure 2 This figure illustrates an exemplary stacked structure of a solid-state imaging element 200 according to the first embodiment of the present technology. The solid-state imaging element 200 includes a detection chip 202 and a light receiving chip 201 stacked on the detection chip 202. These chips are electrically connected via a connection such as a through-hole. Note that connection can also be achieved using Cu-Cu bonding or bumps.

[0065] Figure 3 2 is an exemplary plan view of a light receiving chip 201 according to the first embodiment of the present technology. The light receiving chip 201 is provided with a light receiving unit 220 and through-hole arrangement parts 211 , 212 , and 213 .

[0066] Through holes connected to the detection chip 202 are arranged in the through hole arrangement parts 211, 212, and 213. Furthermore, a plurality of common blocks 221 are arranged in the light receiving unit 220 in a two-dimensional lattice pattern.

[0067] Multiple logarithmic response cells 310 are arranged in each shared block 221. For example, four logarithmic response cells 310 are arranged in a 2-row x 2-column arrangement in each shared block 221. These four logarithmic response cells 310 share the circuitry on the detection chip 202. The details of the shared circuitry will be described later. Note that the number of logarithmic response cells 310 in a shared block 221 is not limited to four.

[0068] The logarithmic response unit 310 generates a voltage signal corresponding to the logarithmic value of the photocurrent. A pixel address including a row address and a column address is assigned to each logarithmic response unit 310.

[0069] Figure 4 This is an exemplary plan view of a detection chip 202 according to the first embodiment of the present technology. Detection chip 202 includes via arrangement sections 231, 232, and 233, a signal processing circuit 240, a row driver circuit 251, a column driver circuit 252, and an address event detection unit 260. Vias connected to the light receiving chip 201 are arranged in via arrangement sections 231, 232, and 233.

[0070] The address event detection unit 260 detects the presence or absence of an address event for each logarithmic response unit 310 and generates a detection signal indicating the detection result.

[0071] The row driving circuit 251 selects a row address and causes the address event detection unit 260 to output a detection signal corresponding to the row address.

[0072] The column driving circuit 252 selects a column address and causes the address event detection unit 260 to output a detection signal corresponding to the column address.

[0073] The signal processing circuit 240 performs predetermined signal processing on the detection signal from the address event detection unit 260. The signal processing circuit 240 arranges the detection signal as a pixel signal in a two-dimensional grid pattern and obtains image data having 2 bits of information for each pixel. The signal processing circuit 240 then performs signal processing such as image recognition processing on the image data.

[0074] Figure 5 1 is an exemplary plan view of the address event detection unit 260 according to the first embodiment of the present technology. Multiple detection blocks 320 are arranged in the address event detection unit 260. A detection block 320 is provided for each common block 221 on the light receiving chip 201. When the number of common blocks 221 is N (N is an integer), N detection blocks 320 are arranged. Each detection block 320 is connected to a corresponding common block 221.

[0075] [Example configuration of a logarithmic response unit]

[0076] Figure 61 is a circuit diagram illustrating an exemplary configuration of a logarithmic response unit 310 according to the first embodiment of the present technology. The logarithmic response unit 310 includes a photoelectric conversion element 311, n-channel metal oxide semiconductor (nMOS) transistors 312 and 313, and a p-channel MOS (pMOS) transistor 314. For example, the photoelectric conversion element 311 and the nMOS transistors 312 and 313 are provided on the light receiving chip 201, and the pMOS transistor 314 is provided on the detection chip 202.

[0077] The source of nMOS transistor 312 is connected to the cathode of photoelectric conversion element 311, and the drain is connected to the power supply terminal. PMOS transistor 314 and nMOS transistor 313 are connected in series between the power supply terminal and the ground terminal. In addition, the connection point between pMOS transistor 314 and nMOS transistor 313 is connected to the gate of nMOS transistor 312 and the input terminal of detection block 320. In addition, a predetermined bias voltage Vbias1 is applied to the gate of pMOS transistor 314.

[0078] The drains of nMOS transistors 312 and 313 are connected to the power supply side, and such a circuit is called a source follower. The two source followers connected in a loop convert the photocurrent from the photoelectric conversion element 311 into a voltage signal corresponding to a logarithmic value. In addition, pMOS transistor 314 supplies a constant current to nMOS transistor 313.

[0079] Furthermore, the ground of the light receiving chip 201 and the ground of the detection chip 202 are separated from each other as a countermeasure against interference.

[0080] [Exemplary Configuration of Detection Block]

[0081] Figure 7 1 is a block diagram illustrating an exemplary configuration of the detection block 320 according to the first embodiment of the present technology. The detection block 320 includes a plurality of buffers 330, a plurality of differentiators 340, a selection unit 400, a comparison unit 500, and a transmission circuit 360. The buffers 330 and the differentiators 340 are configured for each logarithmic response unit 310 in the common block 221. For example, when the number of logarithmic response units 310 in the common block 221 is four, four buffers 330 and four differentiators 340 are provided.

[0082] The buffer 330 outputs the voltage signal from the corresponding logarithmic response unit 310 to the differentiator 340. The buffer 330 can be used to improve the driving force for driving the subsequent stage. In addition, the buffer 330 can be used to ensure noise isolation associated with the switching operation in the subsequent stage.

[0083] Differentiator 340 obtains the variation of the voltage signal as a differential signal. Differentiator 340 receives the voltage signal from the corresponding logarithmic response unit 310 via buffer 330 and obtains the variation of the voltage signal by differentiation. Differentiator 340 then supplies the differential signal to selection unit 400. The mth (m is an integer from 1 to M) differential signal Sin in detection block 320 is set to Sinm.

[0084] The selection unit 400 selects any one of the M differential signals according to a selection signal from the row driving circuit 251. The selection unit 400 includes selectors 410 and 420.

[0085] The M differential signals Sin are input to the selector 410. The selector 410 selects any one of the differential signals Sin according to the selection signal and supplies it as Sout+ to the comparison unit 500. The M differential signals Sin are also input to the selector 420. The selector 420 selects any one of the differential signals Sin according to the selection signal and supplies it as Sout- to the comparison unit 500.

[0086] The comparison unit 500 compares the differential signal (ie, the variation) selected by the selection unit 400 with a predetermined threshold value. The comparison unit 500 supplies a signal indicating the comparison result to the transmission circuit 360 as a detection signal.

[0087] The transmission circuit 360 transmits the detection signal to the signal processing circuit 240 according to the column driving signal from the column driving circuit 252 .

[0088] [Exemplary Configuration of Differentiator]

[0089] Figure 8 340 is a circuit diagram showing an exemplary configuration of a differentiator 340 according to the first embodiment of the present technology. The differentiator 340 includes capacitors 341 and 343 , an inverter 342 , and a switch 344 .

[0090] One end of the capacitor 341 is connected to the output end of the buffer 330, and the other end thereof is connected to the input end of the inverter 342. The capacitor 343 is connected in parallel with the inverter 342. The switch 344 opens and closes the path connecting both ends of the capacitor 343 according to the row driving signal.

[0091] The inverter 342 inverts the voltage signal input via the capacitor 341 , and outputs the inverted signal to the selection unit 400 .

[0092] When the switch 344 is turned on, the voltage signal V initis input to the buffer 330 side of the capacitor 341, and the opposite side becomes the virtual ground terminal. For convenience, the potential of the virtual ground terminal is set to zero. At this time, the charge Q accumulated in the capacitor 341 init It is expressed by the following formula, where the capacitance of capacitor 341 is C1. On the other hand, since both ends of capacitor 343 are short-circuited, the accumulated charge is zero.

[0093] Q init =C1×V init ...Formula 1

[0094] Next, consider that the switch 344 is turned off and the voltage on the buffer 330 side of the capacitor 341 becomes V after In the case of after It is expressed by the following formula.

[0095] Q after =C1×V after ...Formula 2

[0096] At the same time, the charge Q2 accumulated in the capacitor 343 is expressed by the following equation, where the output voltage is V out .

[0097] Q2=-C2×V out ...Formula 3

[0098] At this time, the total amount of charge of the capacitors 341 and 343 does not change, so the following formula is established.

[0099] Q init =Q after +Q2...Formula 4

[0100] When Formula 1 to Formula 3 are substituted into Formula 4 and converted, the following formula is obtained.

[0101] V out =-(C1 / C2)×(V after -V init )...Formula 5

[0102] Formula 5 represents the subtraction operation of the voltage signal, and the gain of the subtraction result is C1 / C2. Because it is generally desirable to maximize the gain, it is preferable to design C1 to be large and C2 to be small. At the same time, since kTC noise increases and noise characteristics may deteriorate when C2 is too small, the capacitance reduction of C2 is limited to a tolerable noise range. In addition, because the differentiator 340 is installed for each pixel, the capacitors C1 and C2 have area limitations. Taking the above into account, for example, C1 is set to a value of 20 to 200 femtofarads (fF), and C2 is set to a value of 1 to 20 femtofarads (fF).

[0103] [Exemplary Configuration of Comparison Unit]

[0104] Figure 9 5 is a circuit diagram illustrating an exemplary configuration of a comparison unit 500 according to a first embodiment of the present technology. The comparison unit 500 includes comparators 510 and 520.

[0105] Comparator 510 compares the differential signal Sout+ from selector 410 with a predetermined upper threshold value Vrefp. Comparator 510 provides the comparison result as a detection signal DET+ to transmission circuit 360. Detection signal DET+ indicates whether a switch-on event has occurred. Here, a switch-on event indicates that the amount of change in brightness exceeds a predetermined upper threshold value.

[0106] Comparator 520 compares the differential signal Sout- from selector 420 with a lower threshold value Vrefn, which is lower than an upper threshold value Vrefp. Comparator 520 provides the comparison result as a detection signal DET- to transmission circuit 360. Detection signal DET- indicates whether a disconnection event has occurred. Here, a disconnection event indicates that the amount of change in brightness is less than a predetermined lower threshold value. Note that while comparison unit 500 detects both a connection event and a disconnection event, it is also possible to detect only one of them.

[0107] It should be noted that the comparator 510 is an example of an upper limit side comparator described in the claims, and the comparator 520 is an example of a lower limit side comparator described in the claims.

[0108] Figure 10 is a circuit diagram illustrating an exemplary configuration of the differentiator 340 , the selector 410 , and the comparator 510 according to the first embodiment of the present technology.

[0109] Differentiator 340 includes capacitors 341 and 343, pMOS transistors 345 and 346, and an nMOS transistor 347. PMOS transistor 345 and nMOS transistor 347 are connected in series between a power supply terminal and a ground terminal, with pMOS transistor 345 positioned on the power supply side. Capacitor 341 is inserted between the gates of pMOS transistor 345 and nMOS transistor 347 and buffer 330. The connection point between pMOS transistor 345 and nMOS transistor 347 is connected to selector 410. With this connection configuration, pMOS transistor 345 and nMOS transistor 347 function as inverter 342.

[0110] Furthermore, a capacitor 343 and a pMOS transistor 346 are connected in parallel between a connection point of the pMOS transistor 345 and the nMOS transistor 347 and the capacitor 341. The pMOS transistor 346 functions as a switch 344.

[0111] Furthermore, a plurality of pMOS transistors 411 are provided in the selector 410 . The pMOS transistor 411 is provided for each differentiator 340 .

[0112] The pMOS transistor 411 is inserted between the corresponding differentiator 340 and the comparator 510. In addition, a selection signal SEL is input separately to the gate of each pMOS transistor 411. The selection signal SEL of the m-th pMOS transistor 411 is set to SELm. According to these selection signals SEL, the row driver circuit 251 can control any one of the M pMOS transistors 411 to be in the on state and control the others to be in the off state. Then, the differential signal Sout+ is output to the comparator 510 as a selected signal via the pMOS transistor 411 in the on state. It should be noted that the circuit configuration of the selector 420 is similar to that of the selector 410.

[0113] Comparator 510 includes a pMOS transistor 511 and an nMOS transistor 512. PMOS transistor 511 and nMOS transistor 512 are connected in series between a power supply terminal and a ground terminal. Furthermore, a differential signal Sout+ is input to the gate of pMOS transistor 511, and a voltage of an upper threshold value Vrefp is input to the gate of nMOS transistor 512. A detection signal DET+ is output from the connection point between pMOS transistor 511 and nMOS transistor 512. Note that the circuit configuration of comparator 520 is similar to that of comparator 510.

[0114] It should be noted that the circuit configurations of the differentiator 340, the selector 410, and the comparator 510 are not limited to the Figure 10 Those exemplified in Figure 7 For example, nMOS transistors and pMOS transistors can be interchanged.

[0115] Figure 11 2 is a timing diagram illustrating exemplary control of the row driver circuit 251 according to the first embodiment of the present technology. At time T0, the row driver circuit 251 selects the first row using the row driver signal L1 and drives the differentiator 340 of the selected row. The capacitor 343 in the differentiator 340 of the first row is initialized by the row driver signal L1. Furthermore, the row driver circuit 251 selects the upper left corner of the two rows and two columns in the common block 221 for a specific period of time using the select signal SEL1 and drives the select unit 400. With this arrangement, the presence or absence of an address event is detected in the odd-numbered columns of the first row.

[0116] Next, at time T1, the row driver circuit 251 drives the differentiator 340 of the first row again using the row driver signal L1. Furthermore, the row driver circuit 251 selects the upper right portion of the 2 rows × 2 columns in the shared block 221 for a specific period of time using the selection signal SEL2. With this arrangement, the presence or absence of an address event is detected in the even-numbered columns of the first row.

[0117] At time T2, the row driver circuit 251 drives the differentiator 340 of the second row with the row driver signal L2. The capacitor 343 in the differentiator 340 of the second row is initialized by the row driver signal L2. In addition, the row driver circuit 251 selects the lower left corner of the 2 rows × 2 columns in the common block 221 for a specific period of time using the select signal SEL3. With this arrangement, the presence or absence of an address event is detected in the odd-numbered columns of the second row.

[0118] Subsequently, at time T3, the row driver circuit 251 drives the differentiator 340 of the second row again using the row driver signal L2. In addition, the row driver circuit 251 selects the lower right portion of the 2 rows × 2 columns in the shared block 221 for a specific period of time using the selection signal SEL4. With this arrangement, the presence or absence of an address event is detected in the even-numbered columns of the second row.

[0119] Thereafter, the row driver circuit 251 sequentially selects the row in which the logarithmic response unit 310 is arranged, and drives the selected row using the row driver signal in a similar manner. Furthermore, each time the row driver circuit 251 selects a row, it sequentially selects each detection pixel 300 in the shared block 221 of the selected row using the selection signal. For example, if the detection pixels 300 are arranged in two rows and two columns in the shared block 221, the odd-numbered columns and even-numbered columns are sequentially selected each time a row is selected.

[0120] Note that the row drive circuit 251 may also sequentially select rows in which the common blocks 221 are arranged (ie, two rows of logarithmic response units 310). In this case, each time a row is selected, four detection pixels in the common block 221 of the selected row are sequentially selected.

[0121] Figure 12 is a block diagram illustrating an exemplary configuration of a detection pixel 300 and a detection circuit 305 according to the first embodiment of the present technology. In the detection block 320 shared by the plurality of logarithmic response units 310 in the shared block 221, the circuit including the selection unit 400, the comparison unit 500, and the transfer circuit 360 is referred to as the detection circuit 305. Furthermore, the circuit including the logarithmic response unit 310, the buffer 330, and the differentiator 340 is referred to as the detection pixel 300. As illustrated in the figure, the detection circuit 305 is shared by the plurality of detection pixels 300.

[0122] Each of the plurality of detection pixels 300 sharing a detection circuit 305 generates a voltage signal corresponding to the logarithmic value of the photocurrent. Each detection pixel 300 then outputs a differential signal Sin, representing the amount of change in the voltage signal, to the detection circuit 305 in response to a row drive signal. In each detection pixel 300, the logarithmic response unit 310 generates a voltage signal corresponding to the logarithmic value, and the differentiator 340 generates a differential signal.

[0123] The selection signals (e.g., selection signals SEL1 and SEL2) are commonly input to selectors 410 and 420 in the detection circuit 305. The detection circuit 305 selects the differential signal (i.e., the amount of change) of the detection pixel indicated by the selection signal from among the plurality of detection pixels 300 and detects whether the amount of change exceeds a predetermined threshold. The detection circuit 305 then transmits the detection signal to the signal processing circuit 240 based on the column drive signal. In the detection circuit 305, the selection unit 400 selects the differential signal, and the comparison unit 500 performs a comparison with the threshold. In addition, the transmission circuit 360 transmits the detection signal.

[0124] Here, in a conventional DVS, the comparison unit 500 and the transfer circuit 360 are configured for each detection pixel together with the logarithmic response unit 310, the buffer 330, and the differentiator 340. At the same time, the above configuration in which the detection circuit 305 including the comparison unit 500 and the transfer circuit 360 is shared by a plurality of detection pixels 300 can reduce the circuit scale of the solid-state imaging element 200 compared to a case where no sharing is performed. This contributes to miniaturization of the pixel.

[0125] Specifically, when using a stacked structure, the circuit scale of the detection chip 202 is larger than that of the conventional light receiving chip 201, which does not share the detection circuit 305. Consequently, the pixel density is limited by the circuitry on the detection chip 202 side, making pixel miniaturization difficult. However, when multiple detection pixels 300 share the detection circuit 305, the circuit scale of the detection chip 202 can be reduced, facilitating pixel miniaturization.

[0126] Note that although the buffer 330 is provided for each detection pixel 300 , the configuration is not limited thereto, and the buffer 330 may not be provided.

[0127] Furthermore, although the photoelectric conversion element 311 and the nMOS transistors 312 and 313 of the logarithmic response unit 310 are configured on the light receiving chip 201, and the pMOS transistor 314 and subsequent components are provided on the detection chip 202, the configuration is not limited to this. For example, only the photoelectric conversion element 311 may be provided on the light receiving chip 201, while the other components may be provided on the detection chip 202. Furthermore, only the logarithmic response unit 310 may be provided on the light receiving chip 201, while the buffer 330 and subsequent components may be provided on the detection chip 202. Furthermore, the logarithmic response unit 310 and the buffer 330 may be provided on the light receiving chip 201, while the differentiator 340 and subsequent components may be provided on the detection chip 202. Furthermore, the logarithmic response unit 310, the buffer 330, and the differentiator 340 may be provided on the light receiving chip 201, and the detection circuit 305 and subsequent components may be provided on the detection chip 202. Furthermore, elements up to the selection unit 400 may be provided on the light receiving chip 201 , and the comparison unit 500 and subsequent elements may be provided on the detection chip 202 .

[0128] [Exemplary Operation of Solid-State Imaging Element]

[0129] Figure 13 1 is a flowchart illustrating an exemplary operation of the solid-state imaging element 200 according to the first embodiment of the present technology. For example, when a predetermined application for detecting the presence or absence of an address event is executed, the operation starts.

[0130] The row driver circuit 251 selects one of the rows (step S901). The row driver circuit 251 then selects and drives any one detection pixel 300 in each shared block 221 in the selected row (step S902). The detection circuit 305 detects the presence or absence of an address event in the selected detection pixel 300 (step S903). After step S903, the solid-state imaging element 200 repeats step S901 and subsequent steps.

[0131] As described above, according to the first embodiment of the present technology, a plurality of detection pixels 300 share the detection circuit 305 for detecting the presence or absence of an address event, thereby reducing the circuit scale compared to a case where the detection circuit 305 is not shared. This contributes to miniaturization of the detection pixels 300.

[0132] [Variation]

[0133] In the first embodiment described above, the solid-state imaging element 200 selects detection pixels one by one and simultaneously detects the on-event and off-event of the detection pixels. However, the solid-state imaging element 200 may also select two detection pixels to detect the on-event of one detection pixel and the off-event of the other detection pixel. The solid-state imaging element 200 according to the modification of the first embodiment differs from the first embodiment in that the on-event is detected for one of the two detection pixels, and the off-event is detected for the other detection pixel.

[0134] Figure 14 is a block diagram illustrating an exemplary configuration of a detection pixel 300 and a detection circuit 305 according to a variation of the first embodiment of the present technology. The detection circuit 305 according to the variation of the first embodiment differs from the detection circuit of the first embodiment in that selection signals (such as selection signals SEL1p and SEL2p) are input to a selector 410, and selection signals such as selection signals SEL1n and SEL2n are input to a selector 420. In the variation of the first embodiment, two detection pixels 300 are selected, and the selector 410 selects the differential signal of one of the two detection pixels based on the selection signals SEL1p, SEL2p, etc. Simultaneously, the selector 420 selects the differential signal of the other detection pixel based on the selection signals SEL1n, SEL2n, etc.

[0135] Figure 15 This is a timing diagram illustrating exemplary control of the row driver circuit 251 according to a variation of the first embodiment of the present technology. Assume that two detection pixels are selected between time T0 and T2: the detection pixel 300 outputting the differential signal Sin1 and the detection pixel 300 outputting the differential signal Sin2. Between time T0 and T1, the row driver circuit 251 sets the selection signals SEL1p and SEL2n to a high level, and sets the selection signals SEL2p and SEL1n to a low level. With this configuration, an on-event is detected for the pixel corresponding to the differential signal Sin1, and an off-event is detected for the pixel corresponding to the differential signal Sin2.

[0136] Then, from time T1 to T2, the row driver circuit 251 sets the selection signals SEL1p and SEL2n to a low level, and sets the selection signals SEL2p and SEL1n to a high level. With this configuration, an on event is detected for the pixel corresponding to the differential signal Sin2, and an off event is detected for the pixel corresponding to the differential signal Sin1.

[0137] As described above, according to a variation of the first embodiment of the present technology, a turn-on event is detected for one of the two detection pixels, and a turn-off event is detected for the other of the two detection pixels, thereby enabling the turn-on event and the turn-off event to be detected simultaneously in a spatially parallel manner.

[0138] <2. Second embodiment>

[0139] Although the comparison unit 500 and the transfer circuit 360 are shared by the plurality of detection pixels 300 in the first embodiment, the circuit scale increases as the number of pixels increases. The solid-state imaging element 200 according to the second embodiment differs from the solid-state imaging element of the first embodiment in that, in addition to the comparison unit 500 and the transfer circuit 360, the plurality of detection pixels 300 share the differentiator 340, thereby reducing the circuit scale.

[0140] Figure 16 1 is a block diagram illustrating an exemplary configuration of a detection pixel 300 and a detection circuit 305 according to a second embodiment of the present technology. The detection circuit 305 according to the second embodiment differs from the detection circuit of the first embodiment in that it further includes a differentiator 340. However, each detection pixel 300 according to the second embodiment does not include the differentiator 340.

[0141] Furthermore, the selection unit 400 according to the second embodiment includes a plurality of switches 431. A switch 431 is provided for each detection pixel 300. The switch 431 opens and closes the path between the corresponding detection pixel 300 and the differentiator 340 according to the selection signal SEL. Any voltage signal of each of the plurality of detection pixels 300 is selected by the switches 431. The differentiator 340 in the subsequent stage obtains the amount of change in the selected voltage signal and outputs it to the comparison unit 500.

[0142] As illustrated in the figure, since the plurality of detection pixels 300 share the differentiator 340 in addition to the comparison unit 500 and the transfer circuit 360 , the circuit scale of the detection circuit 305 can be reduced compared to a case where the differentiator 340 is not shared.

[0143] As described above, according to the second embodiment of the present technology, the plurality of detection pixels 300 further share the differentiator 340 , whereby the circuit scale of the detection circuit 305 can be reduced compared to the first embodiment in which the differentiator 340 is not shared.

[0144] <3. Third embodiment>

[0145] While the differentiator 340 holds only the amount of change of the selected detection pixel 300 in the second embodiment described above, with this configuration, when an address event occurs in an unselected detection pixel 300, the address event may not be detected. The solid-state imaging element 200 according to the third embodiment differs from that of the second embodiment in that the amount of change of the unselected detection pixels 300 is also held to suppress missed detection of address events.

[0146] Figure 17 3 is a circuit diagram showing an exemplary configuration of a differentiator 340 according to a third embodiment of the present technology. In the differentiator 340 according to the third embodiment, a plurality of capacitors (e.g., capacitors 351 and 352) are provided on the front-stage side instead of the capacitor 341. These capacitors are provided for each detection pixel 300. In addition, on the rear-stage side, a plurality of switches (e.g., switches 353 and 354) and a plurality of capacitors (e.g., capacitors 355 and 356) are provided instead of the capacitor 343. These capacitors and switches are configured for each detection pixel 300. In the figure, capacitors and switches corresponding to the third and subsequent detection pixels 300 are omitted.

[0147] One end of each of the capacitors 351 and 352 on the front-stage side is connected to the corresponding switch 431, and the other end is commonly connected to the input terminal of the inverter 342. The switch 353 and the capacitor 355 are connected in series between the input terminal and the output terminal of the inverter 342. The switch 354 and the capacitor 356 are also connected in series between the input terminal and the output terminal of the inverter 342. The connection configuration of the switch 344 is similar to that of the first embodiment.

[0148] The row driving circuit 251 opens and closes the switch 353 using the selection signal SEL1, and opens and closes the switch 354 using the selection signal SEL2. The third and subsequent switches are also opened and closed in a similar manner by the selection signal SEL3 and subsequent signals.

[0149] Note that although the switch 431 for selection is provided between the logarithmic response unit 310 and the capacitors on the previous stage side (capacitor 351 and the like), the switch 431 may be arranged between these capacitors and the logarithmic response unit 310 .

[0150] Figure 18 : is a timing chart illustrating an exemplary operation of the solid-state imaging element 200 according to the third embodiment of the present technology.

[0151] The row driver circuit 251 provides a row driver signal L1 within a predetermined pulse period starting at time T0. With this arrangement, the capacitor 355 in the first row is initialized. Furthermore, the row driver circuit 251 uses the select signal SEL1 to select the upper left column (odd-numbered column) of the 2 rows × 2 columns in the common block 221 for a specific period of time. Assume that during the selection of the odd-numbered columns in the first row, the photocurrent PX1 of the photoelectric conversion element 311 in the odd-numbered column does not change. Therefore, the differential signal of the differentiator 340 in the first row remains at an intermediate potential, and no address event is detected.

[0152] Then, the row driving circuit 251 supplies the row driving signal L1 again during the pulse period from time T1. Furthermore, the row driving circuit 251 selects the upper right column (even column) of 2 rows×2 columns in the common block 221 for a specific period using the selection signal L2.

[0153] Assume that at time T2 during the selection cycle for the even columns of the first row, photocurrent PX1 in the unselected odd columns changes and decreases in level. Simultaneously, assume that at time T3 during the selection cycle, photocurrent PX2 in the selected even columns also changes and increases in level. Differentiator 340 uses capacitors 352 and 356 to store the change in selected photocurrent PX2 and outputs a differential signal at a level lower than the intermediate potential. With this arrangement, a disconnection event is detected for detection pixel 300 in the selected even column.

[0154] The row driver circuit 251 uses the selection signal L1 to reselect the odd columns for a specific period starting at time T4, at which the selection period for the even columns has already elapsed. However, the row driver signal L1 is not provided during the selection period. The differentiator 340 uses capacitors 351 and 355 in the differentiator 340 to store the change in photocurrent PX1 generated during the period when the odd columns were not selected, and outputs a differential signal at a level higher than the intermediate potential. With this configuration, a turn-on event occurring during the non-selected period is detected for the detection pixels 300 in the odd columns.

[0155] Here, in the case where capacitors 341 and 343 are provided only in the differentiator 340 as in the first embodiment, omission of detection of an address event may occur even when the control illustrated in the figure is executed. In the configuration of the first embodiment, the charge corresponding to the change in photocurrent PX2 is retained in capacitors 341 and 343 during the period from time T2 to time T4. Since these capacitors are not reset at time T4, the change in photocurrent PX1 generated at time T2 is not retained after time T4, and the differential signal does not change sufficiently. The thick dashed line in the figure represents the level of the differential signal in the first embodiment. Therefore, with the configuration of the first embodiment, even when an address event occurs in an unselected period, its detection may fail.

[0156] Meanwhile, according to the third embodiment, a capacitor is provided for each detection pixel 300, whereby the variation can be held for each detection pixel 300. With this arrangement, as shown in the figure, omission of detection of address events in a non-selected period can be suppressed.

[0157] Note that the second row is selected after the second selection cycle of the odd-numbered columns in the first row has passed. Control of the second and subsequent rows is similar to that of the first row.

[0158] As described above, according to the third embodiment of the present technology, the differentiator 340 holds the amount of change of each of the plurality of detection pixels 300 , and thus it is possible to suppress omission of detection of an address event.

[0159] <4. Fourth embodiment>

[0160] Although the comparator 510 for detecting an on-event and the comparator 520 for detecting an off-event are provided in the comparison unit 500 in the first embodiment, with this configuration, the circuit scale increases as the number of pixels increases. The solid-state imaging element 200 according to the fourth embodiment differs from the solid-state imaging element of the first embodiment in that a switch for switching the threshold is added and the number of comparators is reduced.

[0161] Figure 19 1 is a circuit diagram illustrating an exemplary configuration of a comparison unit 500 according to a fourth embodiment of the present technology. The comparison unit 500 according to the fourth embodiment differs from the comparison unit 500 of the first embodiment in that a switch 530 is provided in place of the comparator 520. Furthermore, the selection unit 400 according to the fourth embodiment differs from the selection unit 400 of the first embodiment in that the selector 420 is not provided.

[0162] The switch 530 selects the upper threshold Vrefp or the lower threshold Vrefn according to the selection signal SELv and provides it to the comparator 510. Then, the comparator 510 compares the selected threshold with the differential signal Sout from the selector 410.

[0163] Each time a detection pixel 300 is selected, the row driver circuit 251 sequentially selects the upper threshold value Vrefp and the lower threshold value Vrefn using the selection signal SELv. Furthermore, the comparator 510 outputs a detection signal DET+ indicating whether a turn-on event has occurred when the upper threshold value Vrefp is selected, and outputs a detection signal DET indicating whether a turn-off event has occurred when the lower threshold value Vrefn is selected.

[0164] As shown in the figure, the switch 530 switches the threshold value and provides it to the comparator 510 , whereby there is no need to configure the comparator 520 and the circuit scale of the comparison unit 500 can be reduced.

[0165] Note that the solid-state imaging element 200 according to the fourth embodiment can also employ those in the second and third embodiments.

[0166] As described above, according to the fourth embodiment of the present technology, the switch 530 selects the upper threshold or the lower threshold and supplies it to the comparator 510, thereby reducing the number of comparators 520. With this arrangement, the circuit scale of the detection circuit 305 can be reduced.

[0167] <5. Fifth embodiment>

[0168] In the first embodiment described above, the pMOS transistor 411 for selecting the differential signal is provided in the preceding stage of the comparators 510 and 520. However, the pMOS transistor for selecting the differential signal may be provided in the comparator. The solid-state imaging element 200 according to the fifth embodiment differs from the first embodiment in that the pMOS transistor for selecting the differential signal is provided in the comparator.

[0169] Figure 20 5 is a circuit diagram illustrating an exemplary configuration of a differentiator 340 and a comparator 510 according to a fifth embodiment of the present technology. The comparator 510 according to the fifth embodiment includes a plurality of pMOS transistors 511 , a plurality of pMOS transistors 513 , and an nMOS transistor 512 .

[0170] Each pMOS transistor 511 and 513 is provided for each differentiator 340. When the detection pixels 300 are arranged in two rows and two columns in the common block 221, four sets of pMOS transistors 511 and 513 are provided. These four sets are connected in parallel between the power supply terminal and the nMOS transistor 512. Furthermore, in each set, the pMOS transistors 511 and 513 are connected in series. The differential signal from the corresponding differentiator 340 is input to the gate of the pMOS transistor 511. The select signal SEL for the corresponding detection pixel 300 is input to the gate of the pMOS transistor 513.

[0171] Note that the circuit configuration of the comparator 520 is similar to that of the comparator 510 .

[0172] In the circuit configuration illustrated in the figure, the comparator 510 selects any one of the differential signals (variation amounts) of the plurality of differentiators 340 according to the selection signal SEL and compares the variation amount with a threshold value. The comparator 520 operates in a similar manner.

[0173] Note that the solid-state imaging element 200 according to the fifth embodiment can also employ those of the second to fourth embodiments.

[0174] As described above, according to the fifth embodiment of the present technology, the pMOS transistor 513 for selecting a differential signal is provided in the comparator 510 , thereby eliminating the need to provide the selection unit 400 at the preceding stage of the comparator 510 .

[0175] <6. Sixth embodiment>

[0176] Although the detection pixel 300 is provided in the first embodiment to detect the presence or absence of an address event for each pixel, it is not possible to generate a pixel signal according to the exposure amount. The solid-state imaging element 200 according to the sixth embodiment differs from the solid-state imaging element of the first embodiment in that grayscale pixels for generating pixel signals according to the exposure amount are further provided.

[0177] Figure 21 1 is an exemplary plan view of a light receiving chip 201 according to a sixth embodiment of the present technology. The light receiving chip 201 according to the sixth embodiment differs from the light receiving chip 201 of the first embodiment in that grayscale pixels 370 are further provided in a common block 221 .

[0178] Furthermore, the shared block 221 is divided into multiple detection areas. The areas enclosed by thick dashed lines in the figure represent detection areas. Multiple grayscale pixels 370 and one detection pixel 300 are arranged in each detection area. For example, a detection area may have two rows and two columns of pixels, one of which is a detection pixel 300 and the remaining three are grayscale pixels 370. The multiple detection pixels 300 in the shared block 221 share a detection circuit 305 in a manner similar to the first embodiment.

[0179] Note that although part of the logarithmic response unit 310 of the circuit in the detection pixel 300 is configured only in the light receiving chip 201 , technically speaking, the detection pixel 300 is shown in the light receiving chip 201 in the figure for ease of explanation.

[0180] The grayscale pixel 370 generates an analog signal corresponding to the exposure amount as a pixel signal.

[0181] For example, the row driving circuit 251 sequentially drives the rows of detection pixels 300. Then, when there is a detection pixel 300 in which an address event has occurred, three grayscale pixels 370 in the detection area corresponding to the detection pixel 300 are driven to output pixel signals.

[0182] Figure 22 FIG2 is an exemplary plan view of a detection chip 202 according to a sixth embodiment of the present technology. The detection chip 202 according to the sixth embodiment differs from the detection chip 202 of the first embodiment in that a column analog-to-digital converter (ADC) 270 is further provided.

[0183] Each grayscale pixel 370 provides an analog pixel signal to the column ADC 270 under the control of the row driving circuit 251. The column ADC 270 performs analog-to-digital (AD) conversion on the pixel signal of each pixel. The column ADC 270 provides the AD-converted digital signal to the signal processing circuit 240. The signal processing circuit 240 performs predetermined image processing on the image data including those digital signals.

[0184] Figure 23 370 is a circuit diagram showing an exemplary configuration of a grayscale pixel 370 according to a sixth embodiment of the present technology. The grayscale pixel 370 includes a photoelectric conversion element 371, a transfer transistor 372, a reset transistor 373, a floating diffusion layer 374, an amplification transistor 375, and a selection transistor 376.

[0185] The photoelectric conversion element 371 generates electric charge by photoelectric conversion, and the transfer transistor 372 transfers the electric charge from the photoelectric conversion element 371 to the floating diffusion layer 374 in response to the selection signal SELp from the row drive circuit 251 .

[0186] The reset transistor 373 extracts and initializes charges from the floating diffusion layer 374 according to a reset signal RST from the row driving circuit 251. The floating diffusion layer 374 accumulates the transferred charges and generates a voltage corresponding to the amount of the charges.

[0187] The amplification transistor 375 amplifies the voltage of the floating diffusion layer 374. The selection transistor 376 provides the amplified voltage signal as the pixel signal SIG to the column ADC 270 based on the selection signal SELp from the row driver circuit 251. The pixel signal SIG is converted into a digital signal with a bit depth greater than the bit depth of the detection signal. For example, when the detection signal is 2 bits, the pixel signal SIG is converted into a digital signal equal to or greater than 3 bits (16 bits, etc.). This arrangement enables the signal processing circuit 240 to obtain an image with a greater amount of information for the area where the address event has occurred.

[0188] Note that the solid-state imaging element 200 according to the sixth embodiment may also employ those of the second to fifth embodiments.

[0189] As described above, according to the sixth embodiment of the present technology, the grayscale pixel 370 for generating a pixel signal corresponding to the exposure amount is further configured, whereby an image having a larger amount of information for a region where an address event has occurred can be obtained.

[0190] <7. Seventh embodiment>

[0191] Although the comparators 510 and 520 are provided in the comparison unit 500 in the first embodiment, it is also possible to configure two stages of elements in the comparison unit 510 and share elements in the subsequent stages. The seventh embodiment differs from the first embodiment in that two stages of elements are configured in the comparison unit 510 and share elements in the subsequent stages.

[0192] Figure 24 1 is a circuit diagram illustrating an exemplary configuration of a comparison unit 500 according to a seventh embodiment of the present technology. The comparison unit 500 according to the seventh embodiment includes multiple capacitors 541, multiple comparators 542, multiple switches 543, a buffer 544, and switches 551 to 553. The capacitors 541, comparators 542, and switches 543 are provided for each detection pixel 300. Furthermore, in the seventh embodiment, the differentiator 340 is not provided in the detection pixel 300.

[0193] Capacitor 541 is inserted between the corresponding buffer 320 and the non-inverting input terminal (+) of comparator 542. Switch 543 opens and closes the path between the output terminal of the corresponding comparator 542 and buffer 544 according to the corresponding selection signal SEL. Switches 551 to 553 provide any one of the upper threshold value Vrefp, the lower threshold value Vrefn, or the reset voltage Vrst to the inverting input terminal (-) of each comparator 542 according to the selection signal SELv. As illustrated in the figure, multiple detection pixels 300 share the latter of the two stages of buffer 544 and comparator 542.

[0194] As described above, according to the seventh embodiment of the present technology, the buffer 544 in the latter stage of the two stages of the comparator 542 and the buffer 544 is shared, whereby the circuit scale can be reduced compared to the case where they are not shared.

[0195] <8. Application to Mobile Objects>

[0196] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device installed on any type of mobile body, such as a vehicle, an electric vehicle, a hybrid vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, an unmanned aerial vehicle, a ship, and a robot.

[0197] Figure 25 is a block diagram showing a schematic example configuration of a vehicle control system as an example of a mobile body control system to which the technology according to the present disclosure is applicable.

[0198] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. Figure 25In the illustrated example, a vehicle control system 12000 includes a drive system control unit 12010, a vehicle body system control unit 12020, a vehicle exterior information detection unit 12030, a vehicle interior information detection unit 12040, and an integrated control unit 12050. Furthermore, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network interface (I / F) 12053 are illustrated in the figure.

[0199] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 functions as a control device for a drive force generating device such as an internal combustion engine and a drive motor that generates the vehicle's drive force, a drive force transmission mechanism that transmits the drive force to the wheels, a steering mechanism that adjusts the vehicle's steering angle, and a braking device that generates the vehicle's braking force.

[0200] The vehicle system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the vehicle system control unit 12020 functions as a control device for a keyless entry system, a smart key system, power windows, and various lights such as the headlights, taillights, brake lights, turn indicators, and fog lights. In this case, radio waves transmitted from a portable device that replaces a key or signals from various switches can be input to the vehicle system control unit 12020. The vehicle system control unit 12020 receives these radio waves or signals and controls the vehicle's door locks, power windows, lights, and other functions.

[0201] Vehicle exterior information detection unit 12030 detects information related to the exterior of the vehicle in which vehicle control system 12000 is installed. For example, imaging unit 12031 is connected to vehicle exterior information detection unit 12030. Vehicle exterior information detection unit 12030 causes imaging unit 12031 to capture an image of the exterior of the vehicle and receives the captured image. Vehicle exterior information detection unit 12030 can perform object detection processing such as people, vehicles, obstacles, signs, and text on the road, or distance detection processing based on the received image.

[0202] Imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. Imaging unit 12031 can output the electrical signal as an image or as information related to distance measurement. In addition, the light received by imaging unit 12031 can be visible light or invisible light such as infrared light.

[0203] The vehicle interior information detection unit 12040 detects information about the vehicle interior. For example, a driver condition detection unit 12041 for detecting the driver's condition is connected to the vehicle interior information detection unit 12040. The driver condition detection unit 12041 includes, for example, a camera for imaging the driver, and the vehicle interior information detection unit 12040 can calculate the driver's fatigue level or concentration level, or can determine whether the driver is dozing off based on the detection information input from the driver condition detection unit 12041.

[0204] The microcomputer 12051 can calculate control target values for the driving force generation device, steering mechanism, or braking device based on information about the vehicle exterior / interior obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control to implement functions of an advanced driver assistance system (ADAS), including avoiding or mitigating vehicle collisions, following a vehicle based on the distance between vehicles, cruise control, vehicle collision warnings, and vehicle lane departure warnings.

[0205] In addition, the microcomputer 12051 controls the driving force generating device, steering mechanism, braking device, etc. based on the information about the vehicle surroundings obtained by the vehicle external information detection unit 12030 or the vehicle internal information detection unit 12040, thereby performing collaborative control for the purpose of autonomous driving with the purpose of automatic driving without relying on the operation of the driver, etc.

[0206] Furthermore, the microcomputer 12051 can output a control command to the vehicle body system control unit 12020 based on information about the exterior of the vehicle obtained by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control for glare prevention, such as switching from high beam to low beam, by controlling the headlights according to the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0207] The audio image output unit 12052 transmits an output signal of at least one of sound or image to an output device capable of notifying information to a passenger of the vehicle or the outside of the vehicle in a visual or auditory manner. Figure 22 In the example of FIG, an audio speaker 12061, a display 12062, and an instrument panel 12063 are exemplified as output devices. The display 12062 may include, for example, at least one of an onboard display or a head-up display.

[0208] Figure 26 12031 is a diagram illustrating an exemplary installation position of the imaging unit 12031.

[0209] exist Figure 26 , imaging units 12101 , 12102 , 12103 , 12104 , and 12105 are included as imaging unit 12031 .

[0210] For example, imaging units 12101, 12102, 12103, 12104, and 12105 are provided at locations such as the front nose, side mirrors, rear bumper, rear door, and upper portion of the vehicle's interior windshield of vehicle 12100. Imaging unit 12101 provided on the front nose and imaging unit 12105 provided on the upper portion of the vehicle's interior windshield primarily capture images in front of vehicle 12100. Imaging units 12102 and 12103 provided on the side mirrors primarily capture images of the sides of vehicle 12100. Imaging unit 12104 provided on the rear bumper or rear door primarily captures images behind vehicle 12100. Imaging unit 12105 provided on the upper portion of the vehicle's interior windshield primarily detects vehicles ahead, pedestrians, obstacles, traffic signals, traffic signs, lanes, and the like.

[0211] Note that the exemplary imaging range of the imaging units 12101 to 12104 is Figure 26 . Imaging range 12111 represents the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 represents the imaging range of imaging unit 12104 located on the rear bumper or rear door. For example, by superimposing the image data captured by imaging units 12101 to 12104, a bird's-eye view image of vehicle 12100 viewed from above can be obtained.

[0212] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element having pixels for detecting phase difference.

[0213] For example, based on the distance information obtained from imaging units 12101 to 12104, microcomputer 12051 calculates the distance to each three-dimensional object within imaging ranges 12111 to 12114 and the temporal change in that distance (relative speed to vehicle 12100). This allows microcomputer 12051 to specifically extract a three-dimensional object traveling at a predetermined speed (e.g., 0 km / h or higher) in approximately the same direction as vehicle 12100 as a lead vehicle, the closest three-dimensional object on the path of vehicle 12100. Furthermore, microcomputer 12051 can perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like by presetting the distance between vehicles to be maintained before the lead vehicle is guided. In this manner, cooperative control is intended to enable automated driving for autonomous driving that is independent of the driver's actions.

[0214] For example, based on the distance information obtained from imaging units 12101 to 12104, microcomputer 12051 can extract 3D object data related to the 3D objects after classifying them into motorcycles, ordinary cars, large vehicles, pedestrians, and other 3D objects such as utility poles. This data can then be used to automatically avoid obstacles. For example, microcomputer 12051 can distinguish obstacles around vehicle 12100 into obstacles that can be visually recognized by the driver of vehicle 12100 and obstacles that are less likely to be visually recognized. Microcomputer 12051 then determines a collision risk, indicating the degree of risk of collision with each obstacle. If the collision risk is equal to or higher than a set value and a collision is possible, a warning is output to the driver via audio speaker 12061 or display 12062, or forced deceleration or avoidance steering is executed by drive system control unit 12010, thereby providing driving support for conflict avoidance.

[0215] At least one of the imaging units 12101 to 12104 may be an infrared camera for detecting infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether a pedestrian is present in an image captured by the imaging units 12101 to 12104. This identification of a pedestrian may be performed, for example, by extracting feature points from the image captured by the imaging units 12101 to 12104, which are infrared cameras, and performing pattern matching on a series of feature points representing the outline of an object to determine whether it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the image captured by the imaging units 12101 to 12104 and identifies the pedestrian, the audio and video output unit 12052 controls the display 12062 to display a square outline of the identified pedestrian in a superimposed manner to emphasize the identification. Furthermore, the audio and video output unit 12052 may control the display 12062 to display an icon representing the pedestrian at a desired location.

[0216] An exemplary vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 in the above configuration. Specifically, Figure 1 The imaging device 100 in FIG. 1 can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, pixels are miniaturized and a captured image that is easier to view can be obtained, whereby driver fatigue can be reduced.

[0217] Note that the embodiments described above are examples for implementing the present technology, and that the matters in the embodiments correspond to the matters used to specify the present invention in the claims. Similarly, the matters used to specify the present invention in the claims correspond to the matters with the same names in the embodiments of the present technology. However, the present technology is not limited to the embodiments and can be implemented through various modified embodiments without departing from the gist of the present technology.

[0218] Note that the effects described here are merely examples and not limitations, and additional effects may be included.

[0219] Note that the present technology can also adopt the following configurations.

[0220] (1) A solid-state imaging element comprising:

[0221] a plurality of detection pixels, each detection pixel generating a voltage signal corresponding to a logarithmic value of the photocurrent; and

[0222] The detection circuit detects whether a change in a voltage signal of a detection pixel indicated by an input selection signal among the plurality of detection pixels exceeds a predetermined threshold.

[0223] (2) The solid-state imaging element described in (1) above, wherein

[0224] The detection circuit comprises:

[0225] a selection unit, selecting any of the voltage signals of each of the plurality of detection pixels;

[0226] a differentiator for obtaining and outputting a variation of a selected voltage signal; and

[0227] The comparison unit compares the output change with the threshold.

[0228] (3) The solid-state imaging element described in (2) above, wherein

[0229] The differentiator holds the selected variation and outputs the selected variation to the comparison unit.

[0230] (4) The solid-state imaging element described in (2) above, wherein

[0231] The differentiator holds the change amount of each of the plurality of detection pixels and outputs the change amount corresponding to the selected detection pixel to the comparison unit.

[0232] (5) The solid-state imaging device according to any one of (1) to (4) above, wherein

[0233] Each of the plurality of detection pixels comprises:

[0234] a logarithmic response unit, generating the voltage signal; and

[0235] A differentiator obtains a variation of the generated voltage signal and outputs the variation to the detection circuit.

[0236] (6) The solid-state imaging element according to (5) above, wherein the detection circuit includes a comparison unit that selects an amount of change of each of any of the plurality of detection pixels and compares the selected amount of change with the threshold value.

[0237] (7) The solid-state imaging element described in (5) above, wherein

[0238] The detection circuit comprises:

[0239] A selection unit that selects an amount of change of each of any of the plurality of detection pixels; and

[0240] A comparing unit compares the selected change amount with the threshold.

[0241] (8) The solid-state imaging element described in (7) above, wherein

[0242] The threshold value includes an upper threshold value and a lower threshold value that are different from each other, and

[0243] The detection circuit comprises:

[0244] an upper limit side comparator that compares the upper limit threshold with the change amount; and

[0245] The lower limit comparator compares the lower limit threshold with the change amount.

[0246] (9) The solid-state imaging element described in (7) above, wherein

[0247] The threshold value includes an upper threshold value and a lower threshold value that are different from each other, and

[0248] The detection circuit comprises:

[0249] A selection switch for selecting the upper threshold or the lower threshold; and

[0250] A comparator compares the selected threshold with the change amount.

[0251] (10) The solid-state imaging element according to any one of (1) to (9) above, further comprising: a plurality of grayscale pixels each generating a pixel signal corresponding to an exposure amount.

[0252] (11) The solid-state imaging element described in (1) above, wherein

[0253] The threshold value includes an upper threshold value and a lower threshold value that are different from each other, and

[0254] The detection circuit comprises:

[0255] an upper limit side selector for selecting the change amount of one detection pixel of the two detection pixels;

[0256] a lower limit side selector for selecting the change amount of the other detection pixel of the two detection pixels;

[0257] an upper limit side comparator that compares the amount of change of the selected one detection pixel with the upper limit threshold; and

[0258] The lower limit comparator compares the change amount of the selected another detection pixel with the lower limit threshold.

[0259] (12) The solid-state imaging element described in (1) above, wherein

[0260] The detection circuit comprises:

[0261] a plurality of comparators for comparing the change amounts of the detection pixels different from each other with a threshold value;

[0262] A selection unit, configured to select any comparison result of the comparator; and

[0263] Buffer, outputs the selected comparison result.

[0264] (13) The solid-state imaging device according to any one of (1) to (11) above, wherein

[0265] The plurality of detection pixels and a portion of the detection circuit are arranged on a predetermined light receiving chip, and

[0266] The plurality of detection pixels and the remaining portion of the detection circuit are configured on a predetermined detection chip.

[0267] (14) An imaging device comprising:

[0268] a plurality of detection pixels, each detection pixel generating a voltage signal corresponding to a logarithmic value of the photocurrent;

[0269] a detection circuit that detects whether a change in the voltage signal of a detection pixel indicated by an input selection signal among the plurality of detection pixels exceeds a predetermined threshold; and

[0270] A signal processing unit processes a detection signal indicating a detection result of the detection circuit.

[0271] (15) A method for controlling a solid-state imaging element, the method comprising:

[0272] a voltage signal generating step, wherein each of the plurality of detection pixels generates a voltage signal corresponding to a logarithmic value of the photocurrent; and

[0273] A detection step in which a detection circuit detects whether a change amount of the voltage signal of a detection pixel indicated by an input selection signal among the plurality of detection pixels exceeds a predetermined threshold value.

[0274] Reference Symbol List

[0275] 100 Imaging Device

[0276] 110 optical unit

[0277] 120 recording units

[0278] 130 control unit

[0279] 200 solid-state imaging element

[0280] 201 optical receiver chip

[0281] 202 Detection Chip

[0282] 211 to 213, 231 to 233 through-hole arrangement portion

[0283] 220 light receiving unit

[0284] 221 shared blocks

[0285] 240 signal processing circuit

[0286] 251 row driver circuit

[0287] 252 column driver circuit

[0288] 260 Address Event Detection Unit

[0289] 270 columns ADC

[0290] 300 detection pixels

[0291] 305 Detection Circuit

[0292] 310 Logarithmic Response Unit

[0293] 311, 371 Photoelectric conversion elements

[0294] 312, 313, 347, 512 nMOS transistors

[0295] 314, 345, 346, 411, 511, 513 pMOS transistors

[0296] 320 detection blocks

[0297] 330, 544 buffers

[0298] 340 Differentiator

[0299] 341, 343, 351, 352, 355, 356 capacitors

[0300] 342 Inverter

[0301] 344, 353, 354, 431, 530, 543, 544, 551 to 553 switches

[0302] 360 transmission circuit

[0303] 370 grayscale pixels

[0304] 372 pass transistor

[0305] 373 Reset transistor

[0306] 374 floating diffusion layer

[0307] 375 Amplifier Transistor

[0308] 376 Select transistor

[0309] 400 selection units

[0310] 410, 420 selectors

[0311] 500 comparison units

[0312] 510, 520, 542 comparators

[0313] 541, 542 capacitors

[0314] 12031 Imaging Unit

Claims

1. A solid-state imaging element, comprising: a plurality of detection pixels, each detection pixel generating a voltage signal corresponding to a logarithmic value of the photocurrent; as well as a detection circuit for detecting whether a change in the voltage signal of a detection pixel indicated by an input selection signal among the plurality of detection pixels exceeds a predetermined threshold value, Wherein, the detection circuit includes: a selection unit, configured to select any one of the voltage signals of each detection pixel of the plurality of detection pixels according to the input selection signal; a differentiator, obtaining and outputting a selected variation of the voltage signal; and a comparing unit, for comparing the outputted variation with the predetermined threshold value, The differentiator holds the variation of each of the plurality of detection pixels and outputs the variation corresponding to a selected detection pixel to the comparison unit.

2. The solid-state imaging element according to claim 1, wherein Each of the plurality of detection pixels comprises: The logarithmic response unit generates the voltage signal.

3. The solid-state imaging element according to claim 1, wherein The predetermined threshold value includes an upper threshold value and a lower threshold value that are different from each other, and The detection circuit comprises: A selection switch for selecting the upper threshold or the lower threshold; and A comparator compares the selected upper threshold or lower threshold with the change amount.

4. The solid-state imaging element according to claim 1 , further comprising: A plurality of grayscale pixels, each grayscale pixel generates a pixel signal corresponding to an exposure amount.

5. The solid-state imaging element according to claim 1, wherein The plurality of detection pixels and a portion of the detection circuit are provided on a predetermined light receiving chip, and The plurality of detection pixels and the rest of the detection circuit are arranged on a predetermined detection chip.

6. An imaging device comprising: a plurality of detection pixels, each detection pixel generating a voltage signal corresponding to a logarithmic value of the photocurrent; a detection circuit for detecting whether a change in the voltage signal of a detection pixel indicated by an input selection signal among the plurality of detection pixels exceeds a predetermined threshold; as well as a signal processing unit for processing a detection signal representing a detection result of the detection circuit; Wherein, the detection circuit includes: a selection unit, configured to select any one of the voltage signals of each detection pixel of the plurality of detection pixels according to the input selection signal; a differentiator, obtaining and outputting a selected variation of the voltage signal; and a comparing unit, for comparing the outputted variation with the predetermined threshold value, The differentiator holds the variation of each of the plurality of detection pixels and outputs the variation corresponding to a selected detection pixel to the comparison unit.

7. A method for controlling a solid-state imaging element, the method comprising: The voltage signal generating step includes: each of the plurality of detection pixels generating a voltage signal corresponding to a logarithmic value of the photocurrent; as well as Detection step: a detection circuit detects whether a change in the voltage signal of the detection pixel indicated by the input selection signal among the plurality of detection pixels exceeds a predetermined threshold value, Wherein, in the detecting step: The selection unit of the detection circuit selects any one of the voltage signals of each detection pixel of the plurality of detection pixels according to the input selection signal; The differentiator of the detection circuit obtains and outputs the selected variation of the voltage signal; and The comparison unit of the detection circuit compares the output variation with the predetermined threshold value. The differentiator holds the variation of each of the plurality of detection pixels and outputs the variation corresponding to a selected detection pixel to the comparison unit.

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