RRAM multiplication-addition operation circuit, method and model training method

Abstract

The present invention provides an RRAM multiplication-addition circuit, method, and model training method. The RRAM multiplication-addition circuit comprises a control switch unit, a current mirror unit, at least one inverter unit, at least one selection switch unit, and at least one resistor unit. The inverter unit is used to invert the input voltage and generate an inverted voltage. The resistor unit selects a resistor based on the inverted voltage. The control unit adjusts power consumption by controlling the resistor unit. The current mirror unit is used to limit current at the output of the resistor unit to reduce current fluctuations. This invention can reduce power consumption in current quantization multiplication-addition operations in neural networks.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to an RRAM multiplication-addition operation circuit, method, and model training method. Background Art

[0002] Memristors, or memristors, are nonvolatile memory devices used in resistive random access memory (RRAM). Memristors utilize the electrical resistance of non-conductive materials to reversibly switch between high and low resistance states under an applied electric field. Memristors represent the relationship between magnetic flux and charge. While a memristor has the same dimensions as a resistor, its resistance is determined by the charge flowing through it. Therefore, measuring the resistance of a memristor reveals the amount of charge flowing through it, effectively acting as a memory. The nonlinear nature of memristors can generate chaotic circuits, leading to numerous applications in secure communications.

[0003] RRAM and other memory circuits use input voltage to control current and perform multiplication and addition operations. However, this requires a stable reference voltage to maintain a constant current. This typically requires an operational amplifier (OPA) to limit current and minimize current fluctuations to achieve this reference voltage. However, the higher frequencies achieved by the OPA come at the expense of higher currents. Furthermore, because the sum of the currents is obtained by connecting to a reference potential, the operational array continues to consume power even when no relevant operations are required, unless the input voltage is equal to the reference voltage.

[0004] Therefore, it is necessary to provide a new RRAM multiplication-addition operation circuit, method and model training method to solve the above-mentioned problems existing in the prior art. Summary of the Invention

[0005] The object of the present invention is to provide an RRAM multiplication-addition operation circuit, method and model training method, which can reduce the power consumption of quantized multiplication-addition operations in neural networks.

[0006] To achieve the above-mentioned objectives, the RRAM multiplication-addition circuit of the present invention includes a control switch unit, a current mirror unit, at least one inverter unit, at least one selection switch unit, and at least one resistor unit. The inverter unit is used to invert an input voltage and generate an inverted voltage. The resistor unit selects a resistor according to the inverted voltage. The control unit adjusts power consumption by controlling the resistor unit. The current mirror unit is used to limit current at the output end of the resistor unit to reduce current fluctuation.

[0007] The resistance unit includes at least one selection resistor and at least one selection switch, and the control switch unit includes at least one control switch. The input end of the selection switch is electrically connected to the input end of the inverter unit, the output end of the selection switch is electrically connected to one end of the selection resistor, the output end of the inverter unit is electrically connected to one end of the selection switch unit, the other end of the selection switch unit is electrically connected to the control end of the selection switch, the other end of the selection resistor is electrically connected to one end of the control switch, and the other end of the control switch is electrically connected to the input end of the current mirror unit.

[0008] The RRAM multiplication-addition circuit according to the embodiment of the present invention has the following beneficial effects: the RRAM multiplication-addition circuit according to the present invention converts an input low voltage into a high voltage through an inverter unit to control the opening and closing of a resistance unit, and controls the selection switch unit so that the resistance unit completes the current multiplication-addition operation. After the operation is completed, the output current is voltage-limited through the current mirror unit to reduce voltage fluctuations. At the same time, after the entire operation circuit completes operation, the control switch unit is disconnected to reduce the power consumption of the entire operation circuit.

[0009] Optionally, the number of the inverter units is two, namely, a first inverter unit and a second inverter unit; the number of the selection switch units is two, namely, a first selection switch unit and a second selection switch unit; the number of the resistor units is two, namely, a first resistor unit and a second resistor unit; the first inverter unit and the second inverter unit are used to invert the input voltage signal and generate a first inverted voltage and a second inverted voltage; the first resistor unit selects a resistor according to the first inverted voltage; and the second resistor unit selects a resistor according to the second inverted voltage, wherein:

[0010] The output end of the first inverter unit is connected to one end of the first selection switch unit, the other end of the first selection switch unit is connected to one end of the first resistor unit, and the input end of the first inverter unit is also connected to the first resistor unit. The output end of the second inverter unit is connected to one end of the second selection switch unit, the other end of the second selection switch unit is connected to one end of the second resistor unit, and the input end of the second inverter unit is also connected to the second resistor unit. The other ends of the first resistor unit and the second resistor unit are both connected to one end of the control switch unit, and the other end of the control switch unit is connected to the current mirror unit.

[0011] Optionally, the control switch unit includes a first control switch and a second control switch, wherein one end of the first control switch is electrically connected to the first resistor unit and the second resistor unit, respectively, one end of the second control switch is also electrically connected to the first resistor unit and the second resistor unit, respectively, and the other end of the first control switch is electrically connected to the current mirror unit. This advantageously provides the following advantages: the outputs of the first resistor unit and the second resistor unit are controlled by the first control switch and the second control switch of the control switch unit, thereby disconnecting a branch of the entire circuit and reducing power consumption.

[0012] Optionally, the current mirror unit includes a first NMOS transistor and a second NMOS transistor, wherein the drain and gate of the first NMOS transistor are both electrically connected to the other end of the first control switch, the source of the first NMOS transistor and the source of the second NMOS transistor are both grounded, and the drain of the second NMOS transistor outputs the target current. This advantageously provides the following advantages: the output current is limited by the current mirror unit to reduce current fluctuations.

[0013] Optionally, the first resistance unit includes a first gate switch, a second gate switch, a first selection resistor, and a second selection resistor, wherein the source of the first gate switch and the source of the second gate switch are both connected to the input end of the first inverter unit, the gate of the first gate switch and the gate of the second gate switch are both connected to the first selection switch unit, the drain of the first gate switch is connected to one end of the first selection resistor, the drain of the second gate switch is connected to one end of the second selection resistor, the other end of the first selection resistor is connected to one end of the first control switch, and the other end of the second selection resistor is connected to one end of the second control switch;

[0014] The second resistance unit includes a third selection switch, a fourth selection switch, a third selection resistor, and a fourth selection resistor. The source of the third selection switch and the source of the fourth selection switch are both electrically connected to the input end of the second inverter unit, the gate of the third selection switch and the gate of the fourth selection switch are both connected to the second selection switch unit, the drain of the third selection switch is connected to one end of the third selection resistor, the drain of the fourth selection switch is connected to one end of the fourth selection resistor, the other end of the third selection resistor is connected to one end of the first control switch, and the other end of the fourth selection resistor is connected to one end of the second control switch.

[0015] Optionally, the first selection switch unit includes a first selection switch and a second selection switch, wherein the source of the first selection switch and the source of the second selection switch are both connected to the gate of the first selection switch and the gate of the second selection switch, the gate of the first selection switch is connected to the gate of the second selection switch, and the drain of the first selection switch is further connected to the output terminal of the first inverter unit;

[0016] The second selection switch unit includes a third selection switch and a fourth selection switch. The source of the third selection switch and the source of the fourth selection switch are both connected to the gate of the third selection switch and the gate of the fourth selection switch. The gate of the third selection switch is connected to the gate of the fourth selection switch. The drain of the third selection switch is also connected to the output end of the second inverter unit.

[0017] Optionally, the first inverter unit includes a first inverter, an input end of the first inverter is connected to the source of the first selection switch and the source of the second selection switch respectively, and an output end of the first inverter is connected to the drain of the first selection switch;

[0018] The second inverter unit includes a second inverter, the input end of the second inverter is connected to the source of the third selection switch and the source of the fourth selection switch respectively, and the output end of the second inverter is connected to the drain of the third selection switch.

[0019] The present invention also provides an RRAM multiplication and addition operation method, comprising:

[0020] Providing the above-mentioned RRAM multiplication-addition circuit;

[0021] Inputting a gating signal to at least one inverter unit, and causing the RRAM multiplication-addition circuit to enter a weight setting mode by controlling a switch state of a selection switch unit, so that the resistance unit obtains a target resistance;

[0022] Inputting an initial voltage signal to the inverter unit, and causing the RRAM multiplication-addition circuit to enter a current operation mode by controlling the switch state of the selection switch unit, so that when the selection switch of the resistance unit is turned on, the resistance unit is used as a pull-up network and outputs an intermediate current;

[0023] The control switch unit is turned on to output the intermediate current to the current mirror unit, and the intermediate current is output as a target current according to a preset ratio through the current mirror unit.

[0024] The RRAM multiplication-addition operation method of the present invention has the following beneficial effects: the RRAM multiplication-addition operation circuit of the present invention converts the input low voltage into a high voltage through the inverter unit to control the opening and closing of the resistance unit, and controls the selection switch unit so that the resistance unit completes the current multiplication-addition operation. After the operation is completed, the output current is limited by the current mirror unit to reduce current fluctuations. At the same time, after the operation of the entire operation circuit is completed, the control switch unit is disconnected to reduce the power consumption of the entire operation circuit.

[0025] Optionally, the number of the inverter units is two, namely, a first inverter unit and a second inverter unit; the number of the selection switch units is two, namely, a first selection switch unit and a second selection switch unit; the number of the resistor units is two, namely, a first resistor unit and a second resistor unit; and the inputting of a gating signal to at least one inverter unit and controlling a switching state of the selection switch unit so that the RRAM multiplication-addition circuit enters a weight setting mode so that the resistor unit obtains a target resistance includes:

[0026] Opening the second selection switch in the first selection switch unit and the fourth selection switch in the second selection switch unit, and closing the first selection switch and the third selection switch, so that the RRAM multiplication and addition operation circuit enters a weight setting mode;

[0027] Inputting the strobe signal to the first inverter unit and the second inverter unit to control the turning off of the first selection switch, the second selection switch, the third selection switch and the fourth selection switch through the strobe signal;

[0028] Inputting the selection signal to the first inverter unit and the second inverter unit to turn on the first selection switch, the second selection switch, the third selection switch and the fourth selection switch;

[0029] The resistances of the first selection resistor, the second selection resistor, the third selection resistor, and the fourth selection resistor are adjusted according to the end voltages in the first resistance unit and the second resistance unit so that the first selection resistor, the second selection resistor, the third selection resistor, and the fourth selection resistor respectively obtain the target resistance.

[0030] Optionally, the RRAM multiplication-addition operation method further includes turning off the first control switch and the second control switch after the intermediate current is output as a target current according to a preset ratio through the current mirror unit, so as to reduce circuit power consumption.

[0031] The present invention also provides a model training method for an RRAM multiplication-addition circuit, comprising:

[0032] Obtaining an operational curve between a target current and a target resistance according to the RRAM multiplication-addition operation method described above;

[0033] Obtaining a current correlation coefficient according to the operational curve, obtaining a functional relationship between an initial voltage signal and an output current according to the current correlation coefficient, and establishing an initialization model of the input voltage and output current according to the functional relationship;

[0034] Training the initialization model using each target current in the operational curve and the initial voltage signal corresponding to the target current as training parameters;

[0035] After determining that the neural network accuracy of the trained initialization model reaches a preset condition, the trained initialization model is used as the target model.

[0036] The beneficial effect of the model training method for the RRAM multiplication-addition circuit described in the present invention is that after obtaining the operation curve between the target current and the target resistance through the above-mentioned RRAM multiplication-addition operation method, an initialization model of the input voltage and output current is established according to the functional relationship, and the target current and initial voltage signals in the operation curve are used as training parameters to train the initialization model. After the accuracy of the trained neural network reaches a preset condition, the trained initialization model is used as the target model, thereby completing the model training process.

[0037] Optionally, the model training method of the RRAM multiplication-addition circuit further includes taking the ratio between the width-to-length ratio of the first NMOS tube and the width-to-length ratio of the second NMOS tube in the target model as a preset ratio of the current mirror unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 1 is a circuit diagram of an RRAM multiplication-addition circuit according to an embodiment of the present invention;

[0039] Figure 2 Flowchart of the RRAM multiplication-addition operation method according to an embodiment of the present invention;

[0040] Figure 3 Flowchart of a model training method for an RRAM multiplication-addition circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be the common meanings understood by people with ordinary skills in the field to which the present invention belongs. The words "including" and similar words used in this article mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0042] To address the problems of the prior art, embodiments of the present invention provide an RRAM multiplication-addition circuit, comprising a control switch unit, a current mirror unit, at least one inverter unit, at least one selection switch unit, and at least one resistor unit. The inverter unit is configured to invert an input voltage and generate an inverted voltage. The resistor unit selects a resistor based on the inverted voltage. The control unit adjusts power consumption by controlling the resistor unit. The current mirror unit is configured to limit current at the output end of the resistor unit to reduce current fluctuation.

[0043] The resistance unit includes at least one selection resistor and at least one selection switch, and the control switch unit includes at least one control switch. The input end of the selection switch is electrically connected to the input end of the inverter unit, the output end of the selection switch is electrically connected to one end of the selection resistor, the output end of the inverter unit is electrically connected to one end of the selection switch unit, the other end of the selection switch unit is electrically connected to the control end of the selection switch, the other end of the selection resistor is electrically connected to one end of the control switch, and the other end of the control switch is electrically connected to the input end of the current mirror unit.

[0044] In the above circuit, an inverter unit inverts the input voltage signal, allowing even a lower voltage to turn on the transistor in the resistor unit and generate a valid output. This effectively reduces the power consumption of the entire circuit operation, allowing the quantized multiplication and addition process of the neural network to be completed with lower power consumption. Furthermore, a current mirror unit limits the current at the output of the resistor unit to reduce current fluctuations, which also reduces power consumption to a certain extent. Furthermore, a switch unit is used to control the branches of the entire RRAM multiplication and addition circuit, allowing branches in the entire circuit to be disconnected to reduce power consumption.

[0045] It should be noted that in this solution, the at least one inverter unit, the at least one selection switch unit, and the at least one resistance unit include at least one selection resistor and at least one selection switch, and the control switch unit includes at least one control switch, so that the entire RRAM multiplication and addition circuit can perform multiplication and addition operations on the input voltage signal and output the final result, and can perform multiplication and addition operations on voltage signals of different multiple inputs. Each of the resistance units is controlled by the correspondingly connected selection switch unit, and each pair of connected selection resistors and selection switches in the resistance unit is controlled to be conductive by the correspondingly connected control switch, thereby realizing sharing of the selection switch unit and the control switch, so as to facilitate circuit control during circuit operation.

[0046] In some embodiments, as Figure 1 As shown, there are two inverter units, namely a first inverter unit 1 and a second inverter unit 2; there are two selection switch units, namely a first selection switch unit 3 and a second selection switch unit 4; there are two resistor units, namely a first resistor unit 5 and a second resistor unit 6; the first inverter unit 1 and the second inverter unit 2 are used to invert the input voltage signal and generate a first inverted voltage and a second inverted voltage; the first resistor unit 5 selects a resistance according to the first inverted voltage; the second resistor unit 6 selects a resistance according to the second inverted voltage; the control switch unit 7 adjusts power consumption by controlling the first resistor unit 5 and the second resistor unit 6; the current mirror unit 8 is used to limit current at the output ends of the first resistor unit 5 and the second resistor unit 6 to reduce current fluctuations, wherein:

[0047] The output end of the first inverter unit 1 is connected to one end of the first selection switch unit 3, the other end of the first selection switch unit 3 is connected to one end of the first resistor unit 5, and the input end of the first inverter unit 1 is also connected to the first resistor unit 5. The output end of the second inverter unit 2 is connected to one end of the second selection switch unit 4, the other end of the second selection switch unit 4 is connected to one end of the second resistor unit 6, and the input end of the second inverter unit 2 is also connected to the second resistor unit 6. The other ends of the first resistor unit 5 and the second resistor unit 6 are both connected to one end of the control switch unit 7, and the other end of the control switch unit 7 is connected to the current mirror unit 8.

[0048] In the aforementioned RRAM multiplication-addition circuit, the first inverter unit 1 and the second inverter unit 2 invert the input voltage signal, allowing even a relatively low voltage to turn on the transistors in the first resistor unit 5 and the second resistor unit 6 and generate a valid output. This effectively reduces the power consumption of the entire circuit operation, completing the quantized multiplication-addition process of the neural network with even lower power consumption. Furthermore, the current mirror unit 8 limits the current at the output ends of the first resistor unit 5 and the second resistor unit 6 to reduce current fluctuations, which also reduces power consumption to a certain extent. Simultaneously, the control of the branches of the entire RRAM multiplication-addition circuit is achieved by controlling the switch unit 7, allowing branches in the entire circuit to be disconnected to reduce power consumption.

[0049] In some embodiments, the control switch unit 7 includes a first control switch 701 and a second control switch 702, one end of the first control switch 701 is electrically connected to the first resistance unit 5 and the second resistance unit 6, respectively, one end of the second control switch 702 is also electrically connected to the first resistance unit 5 and the second resistance unit 6, respectively, and the other end of the first control switch 701 is electrically connected to the current mirror unit 8. The output ends of the first resistance unit 5 and the second resistance unit 6 are switched by the first control switch 701 and the second control switch 702, so that the branch is turned off when not in use, thereby reducing overall power consumption.

[0050] In some other embodiments, the current mirror unit 8 includes a first NMOS transistor 801 and a second NMOS transistor 802, the drain and gate of the first NMOS transistor 801 are electrically connected to the other end of the first control switch 701, the source of the first NMOS transistor 801 and the source of the second NMOS transistor 802 are grounded, and the drain of the second NMOS transistor 802 outputs a target current. In this embodiment, the currents output by the first resistance unit 5 and the second resistance unit 6 are superimposed together and then output to the drain of the first NMOS transistor 801 through the first control switch 701. A current mirror is formed between the first NMOS transistor 801 and the second NMOS transistor 802, so that the current output to the drain of the first NMOS transistor 801 is scaled according to the scaling ratio of the current mirror unit 8 and output as the target current through the drain of the second NMOS transistor 802, thereby completing current limiting of the output current to reduce current fluctuation and reduce circuit power consumption.

[0051] In some embodiments, the first resistance unit 5 includes a first gating switch 501, a second gating switch 502, a first selection resistor 503, and a second selection resistor 504. The source of the first gating switch 501 and the source of the second gating switch 502 are both connected to the input end of the first inverter unit 1, the gate of the first gating switch 501 and the gate of the second gating switch 502 are both connected to the first selection switch unit 3, the drain of the first gating switch 501 is connected to one end of the first selection resistor 503, the drain of the second gating switch 502 is connected to one end of the second selection resistor 504, the other end of the first selection resistor 503 is connected to one end of the first control switch 701, and the other end of the second selection resistor 504 is connected to one end of the second control switch 702.

[0052] The second resistance unit 6 includes a third selection switch 601, a fourth selection switch 602, a third selection resistor 603, and a fourth selection resistor 604. The source of the third selection switch 601 and the source of the fourth selection switch 602 are both electrically connected to the input end of the second inverter unit 2, the gate of the third selection switch 601 and the gate of the fourth selection switch 602 are both connected to the second selection switch unit 4, the drain of the third selection switch 601 is connected to one end of the third selection resistor 603, the drain of the fourth selection switch 602 is connected to one end of the fourth selection resistor 604, the other end of the third selection resistor 603 is connected to one end of the first control switch 701, and the other end of the fourth selection resistor 604 is connected to one end of the second control switch 702.

[0053] In the above-mentioned first resistance unit 5 and second resistance unit 6, since the output ends of the first selection resistor 503 and the third selection resistor 603 are both connected to one end of the first control switch 701, and the output ends of the second selection resistor 504 and the fourth selection resistor 604 are both connected to one end of the second control switch 702, the voltage signals input by the first inverter unit 1 and the second inverter unit 2 are inverted and then accumulated at one end of the first control switch 701 under the action of the first selection switch 501 and the third selection switch 601, and are also accumulated at one end of the second control switch 702 under the action of the second selection switch 502 and the fourth selection switch 602, respectively, thereby completing the current accumulation process.

[0054] In some embodiments, the first selection switch unit 3 includes a first selection switch 301 and a second selection switch 302. The source of the first selection switch 301 and the source of the second selection switch 302 are both connected to the gate of the first selection switch 501 and the gate of the second selection switch 502. The gate of the first selection switch 301 is connected to the gate of the second selection switch 3302. The drain of the first selection switch 301 is also connected to the output terminal of the first inverter unit 1.

[0055] The second selection switch unit 4 includes a third selection switch 401 and a fourth selection switch 402. The source of the third selection switch 401 and the source of the fourth selection switch 402 are both connected to the gate of the third selection switch 601 and the gate of the fourth selection switch 602. The gate of the third selection switch 401 is connected to the gate of the fourth selection switch 402. The drain of the third selection switch 401 is also connected to the output end of the second inverter unit 2.

[0056] The mode of the entire RRAM multiplication-addition circuit is adjusted by the first selection switch unit 3 and the second selection switch unit 4, so as to control the first resistance unit 5 and the second resistance unit 6 to select resistance and output the accumulated current according to the input voltage signal.

[0057] Specifically, by controlling the first selection switch unit 3 and the second selection switch unit 4, the entire RRAM multiplication-addition operation circuit is switched to the weight setting mode and the current operation mode respectively, so as to control the entire operation circuit to complete different processing processes.

[0058] In some embodiments, the first selection switch 301 in the first selection switch unit 3 is closed, the second selection switch 302 is opened, the third selection switch 401 in the second selection switch unit 4 is closed, and the fourth selection switch 402 is opened, so that the entire RRAM multiplication and addition circuit enters the weight setting mode. When the external voltage signal is input to the first inverter unit 1 and the second inverter unit 2, it is inverted to obtain an inverted voltage signal, and the first selection switch 501, the second selection switch 502, the third selection switch 601 and the fourth selection switch 602 are opened or closed according to the obtained inverted voltage signal, thereby selecting the first selection switch 501 and the second selection switch 502. The voltage on both sides of the first selection switch 501 and the first selection resistor 503 is used. The adjustment selection of the first selection resistor 503 is completed by the voltage on both sides of the second selection switch 502 and the second selection resistor 504, the adjustment selection of the second selection resistor 504 is completed by the voltage on both sides of the third selection switch 601 and the third selection resistor 603, and the adjustment increase selection of the fourth selection resistor 604 is completed by the voltage on both sides of the fourth selection switch 602 and the fourth selection resistor 604. In the weight setting mode, the resistance adjustment of the first selection resistor 503, the second selection resistor 504, the third selection resistor 603 and the fourth selection resistor 604 are respectively determined, so that in the subsequent current calculation mode, the currently adjusted resistance value can participate in the current calculation.

[0059] In some other embodiments, the first selection switch 301 in the first selection switch unit 3 is turned on and the second selection switch 302 is turned off, and the third selection switch 401 in the second selection switch unit 4 is turned on and the fourth selection switch 402 is turned off, so that the entire RRAM multiplication and addition operation current enters the current operation mode. The external voltage signal is input to the first inverter unit 1 and the second inverter unit 2 and then inverted to obtain an inverted voltage signal. The first selection switch 501, the second selection switch 502, the third selection switch 601 and the fourth selection switch 602 are turned on or off by the inverted voltage signal, so that the control switch unit 7 is turned on after the inverted voltage signal is operated, and the current is output to the current mirror unit 8 and finally the target current is output.

[0060] It should be noted that in the RRAM multiplication-addition circuit of this solution, the selection switches located in the same resistor unit share the control of the same group of selection switch units. For example, the first selection switch 501 and the second selection switch 502 in the first resistor unit 5 share the control of the first selection switch unit 3; and the third selection switch 601 and the fourth selection switch 602 in the second resistor unit 6 share the control of the second selection switch unit 4.

[0061] In some other embodiments, the first gating switch 501 , the second gating switch 502 , the third gating switch 601 and the fourth gating switch 602 may all be NMOS transistors, PMOS transistors and transmission gates. In this embodiment, PMOS transistors are used for illustration.

[0062] Specifically, the first selection switch 301 in the first selection switch unit 3 is turned on, the second selection switch 302 is turned off, the third selection switch 401 in the second selection switch unit 4 is turned on, and the fourth selection switch 402 is turned off, so that the entire RRAM multiplication and addition circuit enters the current operation mode. In the current operation mode, when the voltage signal vin input by the first inverter unit 1 and the second inverter unit 2 is at a low level, the output is a high level after being processed by the inverter, so that the first selection switch 501, the second selection switch 502, the third selection switch 601 and the fourth selection switch 602 are all turned off, thereby The branches of the first resistance unit 5 and the second resistance unit 6 are closed; and when the voltage signal vin input by the first inverter unit 1 and the second inverter unit 2 is at a high level, the output is a low level after being processed by the inverter, so that the first selection switch 501, the second selection switch 502, the third selection switch 601 and the fourth selection switch 602 are all turned on, so that the branches of the first resistance unit 5 and the second resistance unit 6 in the entire RRAM multiplication and addition circuit are turned on, so that the first resistance unit 5 and the second resistance unit 6 form a pull-up network, and the first NMOS transistor 801 in the current mirror unit 8 forms a pull-down network.

[0063] Assuming that the low resistance value of the memristor formed between the selection switch and the selection resistor in the first resistance unit 5 and the second resistance unit 6 is L, and the high resistance value is H, assuming that when the input voltage signal vin is at a low level, the branch circuit formed by the first resistance unit 5 and the second resistance unit 6 constitutes a pull-down network, and the pull-down network resistance at this time is infinite. Assuming that the number of circuit rows for operation is N, and the number of circuit rows in this embodiment is 2, the resistance variation range of the pull-up network is [L / N, H]. When the two input voltage signals vin0 and vin1 are both at a high level, and the corresponding resistance determined by the first resistance unit 5 and the second resistance unit 6 in the weight setting mode is low resistance, the pull-up resistance in the entire pull-up network reaches a minimum of L / N; when only one of the two input voltage signals vin0 and vin1 is at a high level, and the corresponding resistance determined by the first resistance unit 5 and the second resistance unit 6 in the weight setting mode is high resistance, the pull-up resistance in the entire pull-up network reaches a maximum of H.

[0064] Then, a DC scan is performed to obtain a variation curve of the pull-up resistance and the target current in the resistance variation range [L / N, H] with respect to the width-to-length ratio of the current mirror unit 8 , thereby obtaining a variation relationship between the pull-up resistance and the target current.

[0065] When the voltage signals vin0 and vin1 of the two inputs are both at low levels, it is easy to obtain the final output target current as 0.

[0066] After the circuit operation process is completed, the first control switch 701 and the second control switch 702 in the control switch unit 7 can be turned off, thereby shutting down the circuit branch formed by the first resistance unit 5 and the second resistance unit 6, thereby effectively saving circuit power consumption.

[0067] In some embodiments, the first inverter unit 1 includes a first inverter 101, wherein the input end of the first inverter 101 is respectively connected to the source of the first selection switch 501 and the source of the second selection switch 502, and the output end of the first inverter 101 is connected to the drain of the first selection switch 301; the second inverter unit 2 includes a second inverter 201, wherein the input end of the second inverter 201 is respectively connected to the source of the third selection switch 601 and the source of the fourth selection switch 602, and the output end of the second inverter 201 is connected to the drain of the third selection switch 401.

[0068] The input voltage signal is inverted by the first inverter unit 1 and the second inverter unit 2, so that a voltage signal with a smaller input voltage swing can also fully open the selection switches in the first resistor unit 5 and the second resistor unit 6, so that the entire circuit can complete the current multiplication and addition process with lower power consumption.

[0069] It should be noted that two operation branches are formed between the first resistance unit 5 and the second resistance unit 6, but this solution can also use multiple resistance units to form operation branches for current calculation. This solution is not limited to this and will not be repeated here.

[0070] The present invention further provides a RRAM multiplication and addition method, such as Figure 2 As shown, the following steps are included:

[0071] S200 , providing the above-mentioned RRAM multiplication-addition circuit.

[0072] S201 , inputting a selection signal to at least one inverter unit, and enabling the RRAM multiplication-addition circuit to enter a weight setting mode by controlling a switch state of a selection switch unit, so that the resistance unit obtains a target resistance.

[0073] In some embodiments, the number of the inverter units is two, namely a first inverter unit and a second inverter unit; the number of the selection switch units is two, namely a first selection switch unit and a second selection switch unit; the number of the resistor units is two, namely a first resistor unit and a second resistor unit; the above process includes:

[0074] Opening the second selection switch in the first selection switch unit and the fourth selection switch in the second selection switch unit, and closing the first selection switch and the third selection switch, so that the RRAM multiplication and addition operation circuit enters a weight setting mode;

[0075] Inputting the selection signal to the first inverter unit and the second inverter unit to turn on the first selection switch, the second selection switch, the third selection switch and the fourth selection switch;

[0076] The resistances of the first selection resistor, the second selection resistor, the third selection resistor, and the fourth selection resistor are adjusted according to the end voltages in the first resistance unit and the second resistance unit so that the first selection resistor, the second selection resistor, the third selection resistor, and the fourth selection resistor respectively obtain the target resistance.

[0077] S202: Input an initial voltage signal to the inverter unit, and control the switching state of the selection switch unit so that the RRAM multiplication-addition circuit enters a current operation mode, so that when the selection switch of the resistance unit is turned on, the resistance unit is used as a pull-up network and outputs an intermediate current.

[0078] S203 , turning on the control switch unit to output the intermediate current to the current mirror unit, and outputting the intermediate current to the target current according to a preset ratio through the current mirror unit.

[0079] In some embodiments, the RRAM multiplication-addition operation method further includes turning off the first control switch and the second control switch after the current mirror unit outputs the target current according to a preset ratio to reduce circuit power consumption.

[0080] Through the above-mentioned RRAM multiplication-addition operation method, after the first inverter unit and the second inverter unit convert the input voltage signal into a high voltage, the selection switches in the first resistor unit and the second resistor unit are turned on, so that the selection switches can be turned on with a relatively low voltage, effectively reducing the power consumption of the entire circuit. The first resistor unit and the second resistor unit are controlled to be turned on and off. Then, by controlling the first selection switch unit and the second selection switch unit respectively, the first resistor unit and the second resistor unit complete the current multiplication-addition operation and output the intermediate current. After the control switch unit is turned on, the output current is current-limited by the current mirror unit to reduce current fluctuations. At the same time, after the entire operation circuit is completed, the control switch unit is turned off to reduce the power consumption of the entire operation circuit.

[0081] Since the working principle of the above RRAM multiplication-addition operation method corresponds one-to-one to the aforementioned RRAM multiplication-addition operation circuit, it will not be described in detail here.

[0082] The present invention also discloses a model training method for an RRAM multiplication-addition circuit, such as Figure 3 As shown, the following steps are included:

[0083] S301, obtaining an operation curve between a target current and a target resistance according to the above-mentioned RRAM multiplication and addition operation method;

[0084] S302, obtaining a current correlation coefficient according to the operational curve, obtaining a functional relationship between an initial voltage signal and an output current according to the current correlation coefficient, and establishing an initialization model of the input voltage and output current according to the functional relationship;

[0085] S303, training the initialization model using each target current in the operational curve and the initial voltage signal corresponding to the target current as training parameters;

[0086] S304: After determining that the neural network accuracy of the trained initialization model reaches a preset condition, the trained initialization model is used as a target model.

[0087] Decompose the multiplication and addition operation in the neural network into bit-by-bit multiplication and addition operations. The input voltage is Vin, the reference voltage is 0, and the pull-up resistor is R. Then, under normal circumstances, the output current of the circuit is:

[0088] Where x is the input signal and w is the coefficient of the binarization of the neural network weight.

[0089] In the present solution, due to the current limiting effect of the current mirror unit, the reference voltage is not stable. Therefore, the current correlation coefficient is obtained based on the operation curve of the target current and target resistance obtained above, and the functional relationship between the initial voltage signal and the output current is obtained based on the current correlation coefficient. An initialization model of the input voltage and output current is established based on the functional relationship, and each target current in the operation curve and the initial voltage signal corresponding to the target current are used as training parameters to train the initialization model. After determining that the neural network accuracy of the trained initialization model meets the preset conditions, the trained initialization model is used as the target model to complete the training of the neural network model, and an RRAM multiplication-addition operation circuit that meets the requirements is obtained.

[0090] Specifically, the calculation formula of the multiplication and addition operation results in the neural network is replaced with the operation rules of the operation curve of the target current and target resistance obtained above, and the initial model can be obtained:

[0091]

[0092] The trained parameters are the weighted pull-up resistor R and the width-to-length ratio W / L of the current mirror unit, and the output is the target current.

[0093] The initial model is then trained using the initial voltage signal and target current in the operational curve of the target current and target resistance. When the accuracy of the input and output data of the initial model reaches a preset condition, the final initial model is used as the target model, and the ratio between the width-to-length ratio of the first NMOS transistor and the width-to-length ratio of the second NMOS transistor in the target model is used as the preset ratio of the current mirror unit, thereby obtaining the final RRAM multiplication-addition circuit, completing the model training process of the RRAM multiplication-addition circuit.

[0094] While the embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations of these embodiments are possible. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the claims. Furthermore, the invention described herein is susceptible to other embodiments and may be practiced or implemented in a variety of ways.

Claims

1. An RRAM multiplication-addition circuit, characterized in that: The device comprises a control switch unit, a current mirror unit, at least one inverter unit, at least one selection switch unit, and at least one resistor unit. The inverter unit is used to invert an input voltage and generate an inverted voltage. The resistor unit selects a resistor according to the inverted voltage. The control switch unit adjusts power consumption by controlling the resistor unit. The current mirror unit is used to limit current at the output end of the resistor unit to reduce current fluctuation. The resistor unit includes at least one selection resistor and at least one gate switch, and the control switch unit includes at least one control switch; each resistor unit is controlled by the corresponding selection switch unit, and each pair of selection resistors and gate switches connected in the resistor unit is conductively controlled by the corresponding control switch unit, thereby achieving sharing of the selection switch unit and the control switch unit; For one of the resistance units, the input end of each of the selection switches is electrically connected to the input end of the inverter unit corresponding to the resistance unit, the output end of each of the selection switches is electrically connected to one end of the corresponding selection resistor, the output end of the inverter unit is electrically connected to one end of the selection switch unit corresponding to the selection resistor, the other end of the selection switch unit is electrically connected to the control end of each of the selection switches, the other end of one of the selection resistors is electrically connected to one end of one of the control switches, and the other end of each of the control switches is electrically connected to the input end of the current mirror unit.

2. The RRAM multiplication-addition circuit according to claim 1, wherein: There are two inverter units, namely a first inverter unit and a second inverter unit; there are two selection switch units, namely a first selection switch unit and a second selection switch unit; there are two resistor units, namely a first resistor unit and a second resistor unit; the first inverter unit and the second inverter unit are used to invert an input voltage signal and generate a first inverted voltage and a second inverted voltage; the first resistor unit selects a resistor according to the first inverted voltage; and the second resistor unit selects a resistor according to the second inverted voltage, wherein: The output end of the first inverter unit is connected to one end of the first selection switch unit, the other end of the first selection switch unit is connected to one end of the first resistor unit, and the input end of the first inverter unit is also connected to the first resistor unit. The output end of the second inverter unit is connected to one end of the second selection switch unit, the other end of the second selection switch unit is connected to one end of the second resistor unit, and the input end of the second inverter unit is also connected to the second resistor unit. The other ends of the first resistor unit and the second resistor unit are both connected to one end of the control switch unit, and the other end of the control switch unit is connected to the current mirror unit.

3. The RRAM multiplication-addition circuit according to claim 2, wherein: The control switch unit includes a first control switch and a second control switch, one end of the first control switch is electrically connected to the first resistance unit and the second resistance unit respectively, one end of the second control switch is also electrically connected to the first resistance unit and the second resistance unit respectively, and the other end of the first control switch is electrically connected to the current mirror unit.

4. The RRAM multiplication-addition circuit according to claim 3, wherein: The current mirror unit includes a first NMOS transistor and a second NMOS transistor, the drain and gate of the first NMOS transistor are electrically connected to the other end of the first control switch, the source of the first NMOS transistor and the source of the second NMOS transistor are both grounded, and the drain of the second NMOS transistor outputs the target current.

5. The RRAM multiplication-addition circuit according to claim 3, wherein: The first resistor unit includes a first gate switch, a second gate switch, a first selection resistor, and a second selection resistor. The source of the first gate switch and the source of the second gate switch are both connected to the input end of the first inverter unit, the gate of the first gate switch and the gate of the second gate switch are both connected to the first selection switch unit, the drain of the first gate switch is connected to one end of the first selection resistor, the drain of the second gate switch is connected to one end of the second selection resistor, the other end of the first selection resistor is connected to one end of the first control switch, and the other end of the second selection resistor is connected to one end of the second control switch; The second resistance unit includes a third selection switch, a fourth selection switch, a third selection resistor, and a fourth selection resistor. The source of the third selection switch and the source of the fourth selection switch are both electrically connected to the input end of the second inverter unit, the gate of the third selection switch and the gate of the fourth selection switch are both connected to the second selection switch unit, the drain of the third selection switch is connected to one end of the third selection resistor, the drain of the fourth selection switch is connected to one end of the fourth selection resistor, the other end of the third selection resistor is connected to one end of the first control switch, and the other end of the fourth selection resistor is connected to one end of the second control switch.

6. The RRAM multiplication-addition circuit according to claim 5, wherein: The first selection switch unit includes a first selection switch and a second selection switch, wherein the source of the first selection switch and the source of the second selection switch are both connected to the gate of the first selection switch and the gate of the second selection switch, the gate of the first selection switch is connected to the gate of the second selection switch, and the drain of the first selection switch is also connected to the output terminal of the first inverter unit; The second selection switch unit includes a third selection switch and a fourth selection switch. The source of the third selection switch and the source of the fourth selection switch are both connected to the gate of the third selection switch and the gate of the fourth selection switch. The gate of the third selection switch is connected to the gate of the fourth selection switch. The drain of the third selection switch is also connected to the output end of the second inverter unit.

7. The RRAM multiplication-addition circuit according to claim 6, wherein: The first inverter unit includes a first inverter, wherein an input terminal of the first inverter is connected to a source of the first selection switch and a source of the second selection switch respectively, and an output terminal of the first inverter is connected to a drain of the first selection switch; The second inverter unit includes a second inverter, the input end of the second inverter is connected to the source of the third selection switch and the source of the fourth selection switch respectively, and the output end of the second inverter is connected to the drain of the third selection switch.

8. A RRAM multiplication and addition method, characterized in that: include: Provide the RRAM multiplication-addition circuit according to any one of claims 1 to 7; Inputting a gating signal to at least one inverter unit, and causing the RRAM multiplication-addition circuit to enter a weight setting mode by controlling a switch state of a selection switch unit, so that the resistance unit obtains a target resistance; Inputting an initial voltage signal to the inverter unit, and causing the RRAM multiplication-addition circuit to enter a current operation mode by controlling the switch state of the selection switch unit, so that when the selection switch of the resistance unit is turned on, the resistance unit is used as a pull-up network and outputs an intermediate current; The control switch unit is turned on to output the intermediate current to the current mirror unit, and the intermediate current is output as a target current according to a preset ratio through the current mirror unit.

9. The RRAM multiplication-addition operation method according to claim 8, wherein: There are two inverter units, namely a first inverter unit and a second inverter unit; there are two selection switch units, namely a first selection switch unit and a second selection switch unit; there are two resistor units, namely a first resistor unit and a second resistor unit; inputting a selection signal to at least one inverter unit and controlling the switching state of the selection switch unit so that the RRAM multiplication and addition circuit enters a weight setting mode so that the resistor unit obtains a target resistance, including: Opening the second selection switch in the first selection switch unit and the fourth selection switch in the second selection switch unit, and closing the first selection switch and the third selection switch, so that the RRAM multiplication and addition operation circuit enters a weight setting mode; Inputting the selection signal to the first inverter unit and the second inverter unit to turn on the first selection switch, the second selection switch, the third selection switch and the fourth selection switch; The resistances of the first selection resistor, the second selection resistor, the third selection resistor, and the fourth selection resistor are adjusted according to the end voltages in the first resistance unit and the second resistance unit so that the first selection resistor, the second selection resistor, the third selection resistor, and the fourth selection resistor respectively obtain the target resistance.

10. The RRAM multiplication-addition operation method according to claim 8, wherein: The RRAM multiplication-addition operation method further includes turning off the first control switch and the second control switch after the intermediate current is output to the target current according to a preset ratio through the current mirror unit to reduce circuit power consumption.

11. A model training method for an RRAM multiplication-addition circuit, characterized in that: include: Obtaining an operational curve between a target current and a target resistance according to the RRAM multiplication-addition operation method according to any one of claims 8 to 10; Obtaining a current correlation coefficient according to the operational curve, obtaining a functional relationship between an initial voltage signal and an output current according to the current correlation coefficient, and establishing an initialization model of input voltage and output current according to the functional relationship; Training the initialization model using each target current in the operational curve and the initial voltage signal corresponding to the target current as training parameters; After determining that the neural network accuracy of the trained initialization model reaches a preset condition, the trained initialization model is used as the target model.

12. The model training method for the RRAM multiplication-addition circuit according to claim 11, characterized in that: The model training method of the RRAM multiplication-addition circuit further includes using the ratio between the width-to-length ratio of the first NMOS tube and the width-to-length ratio of the second NMOS tube in the target model as a preset ratio of the current mirror unit.

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