Engineered Substrate Structures for Power and RF Applications

Abstract

The present invention discloses an engineered substrate structure for power applications and radio frequency applications. The substrate includes a support structure, which includes: a polycrystalline ceramic core; a first adhesion layer coupled to the polycrystalline ceramic core; a conductive layer coupled to the first adhesion layer; a second adhesion layer coupled to the conductive layer; and a barrier layer coupled to the second adhesion layer. The substrate further includes: a silicon oxide layer coupled to the support structure; a substantially single-crystalline silicon layer coupled to the silicon oxide layer; and an epitaxial III-V layer coupled to the substantially single-crystalline silicon layer.

Description

[0001] This application is a divisional application of a Chinese patent application with an application date of June 13, 2017, an application number of 2017800496916, and an invention title of "Engineered Substrate Structures for Power and Radio Frequency Applications".

[0002] Cross - reference to related applications

[0003] This application claims priority to U.S. Provisional Patent Application No. 62 / 350,084, filed on June 14, 2016, entitled "Engineered Substrate Structures for Power and Radio Frequency Applications", and U.S. Provisional Patent Application No. 62 / 350,077, filed on June 14, 2016, entitled "Engineered Substrate Structures and Fabrication Methods". The entire contents of which are incorporated herein by reference for all purposes.

[0004] The following two U.S. patent applications were filed concurrently with this application, and the entire disclosures of these two applications are incorporated herein by reference for all purposes:

[0005] Application No. 15 / 621,335, filed on June 13, 2017, entitled "Engineered Substrate Structures for Power and Radio Frequency Applications" (Attorney Docket No. 098825 - 1049529 - 001110US), and

[0006] Application No. 15 / 621,338, filed on June 13, 2017, entitled "Engineered Substrate Structures and Fabrication Methods" (Attorney Docket No. 098825 - 1049532 - 001610US). Background of the Invention

[0007] Light - emitting diode (LED) structures are typically grown epitaxially on sapphire substrates. Many current products use LED devices, including lighting, computer monitors, and other display devices.

[0008] Since the substrate and the epitaxial layer are composed of different materials, the growth of gallium nitride - based LED structures on sapphire substrates is a heteroepitaxial growth process. Due to the heteroepitaxial growth process, the epitaxially grown material can exhibit various adverse effects, including a reduction in uniformity and a decrease in metrics associated with the electronic / optical properties of the epitaxial layer. Therefore, there is a need in the art for improved methods and systems related to the epitaxial growth process and substrate structures. Summary of the Invention

[0009] The present invention generally relates to an engineered substrate structure. More specifically, the present invention relates to methods and systems suitable for use in an epitaxial growth process. By way of example only, the present invention has been applied to methods and systems for providing a substrate structure suitable for epitaxial growth, the substrate structure being characterized by having a coefficient of thermal expansion (CTE) that substantially matches that of the epitaxial layer grown thereon. The methods and techniques can be applied to a variety of semiconductor processing operations.

[0010] According to an embodiment of the present invention, a substrate is provided. The substrate includes a support structure that includes: a polycrystalline ceramic core; a first adhesion layer coupled to the polycrystalline ceramic core; a conductive layer coupled to the first adhesion layer; a second adhesion layer coupled to the conductive layer; and a barrier layer coupled to the second adhesion layer. The substrate further includes: a silicon oxide layer coupled to the support structure; a substantially single-crystalline silicon layer coupled to the silicon oxide layer; and an epitaxial III-V layer coupled to the substantially single-crystalline silicon layer.

[0011] According to another embodiment of the present invention, a method of manufacturing a substrate is provided. The method includes forming a support structure by: providing a polycrystalline ceramic core; encapsulating the polycrystalline ceramic core in a first adhesion shell; encapsulating the first adhesion shell in a conductive shell; encapsulating the conductive shell in a second adhesion shell; and encapsulating the second adhesion shell in a barrier shell. The method further includes: bonding a bonding layer to the support structure; bonding a substantially single-crystalline silicon layer to the bonding layer, forming an epitaxial silicon layer by epitaxial growth on the substantially single-crystalline silicon layer; and forming an epitaxial III-V layer by epitaxial growth on the epitaxial silicon layer.

[0012] According to a specific embodiment of the present invention, an engineered substrate structure is provided. The engineered substrate structure includes a support structure, a bonding layer coupled to the support structure, a substantially single-crystalline silicon layer coupled to the adhesion layer; and an epitaxial single-crystalline silicon layer coupled to the substantially single-crystalline silicon layer. The support structure includes: a polycrystalline ceramic core; a first adhesion layer coupled to the polycrystalline ceramic core; a conductive layer coupled to the first adhesion layer; a second adhesion layer coupled to the conductive layer; and a barrier shell coupled to the second adhesion layer.

[0013] Advantageous over conventional techniques, many benefits can be achieved through the present invention. For example, embodiments of the present invention provide an engineered substrate structure that is CTE-matched with gallium nitride-based epitaxial layers suitable for optical, electronic, and optoelectronic applications. A encapsulation layer that serves as a component of the engineered substrate structure prevents impurities present in the central portion of the substrate from diffusing into the semiconductor process environment where the engineered substrate is used. The key properties associated with the substrate material (including coefficient of thermal expansion, lattice mismatch, thermal stability, and topography control) are engineered independently to improve (e.g., optimize) the match with the gallium nitride-based epitaxial layer and device layer, as well as with different device architectures and performance goals. Since the substrate material layers are integrated together in conventional semiconductor manufacturing processes, process integration is simplified. These and other embodiments of the present invention, along with many of their advantages and features, are described in more detail in conjunction with the following text and the drawings.

[0014] Brief Description of the Drawings

[0015] Figure 1 is a simplified schematic diagram showing an engineered substrate structure according to an embodiment of the present invention.

[0016] Figure 2A is a SIMS profile showing the concentration of species as a function of depth for an engineered structure according to an embodiment of the present invention.

[0017] Figure 2B is a SIMS profile showing the concentration of species as a function of depth for an annealed engineered structure according to an embodiment of the present invention.

[0018] Figure 2C is a SIMS profile showing the concentration of species as a function of depth for an annealed engineered structure with a silicon nitride layer according to an embodiment of the present invention.

[0019] Figure 3 is a simplified schematic diagram showing an engineered substrate structure according to another embodiment of the present invention.

[0020] Figure 4 is a simplified schematic diagram showing an engineered substrate structure according to yet another embodiment of the present invention.

[0021] Figure 5 is a simplified flowchart showing a method of manufacturing an engineered substrate according to an embodiment of the present invention.

[0022] Figure 6 is a simplified schematic diagram showing an epitaxial / engineered substrate structure for RF applications and power applications according to an embodiment of the present invention.

[0023] Figure 7 is a simplified schematic diagram showing a III-V epitaxial layer on an engineered substrate structure according to an embodiment of the present invention.

[0024] Figure 8 is a simplified flowchart showing a method of fabricating an engineered substrate according to another embodiment of the present invention.

[0025] Detailed Description of the Specific Embodiments

[0026] Embodiments of the present invention relate to engineered substrate structures. More specifically, the present invention relates to methods and systems suitable for an epitaxial growth process. By way of example only, the present invention has been applied to methods and systems for providing a substrate structure suitable for epitaxial growth, the substrate structure being characterized by having a coefficient of thermal expansion (CTE) substantially matched to that of an epitaxial layer grown thereon. The methods and techniques can be applied to various semiconductor processing operations.

[0027] Figure 1 is a simplified schematic diagram showing an engineered substrate structure according to an embodiment of the present invention. Figure 1 The engineered substrate 100 shown in is suitable for various electronic and optical applications. The engineered substrate includes a core 110, which may have a CTE substantially matched to that of an epitaxial material whose coefficient of thermal expansion (CTE) will be grown on the engineered substrate 100. The epitaxial material 130 is shown as optional because it is not required as a component of the engineered substrate but will typically be grown on the engineered substrate.

[0028] For applications involving the growth of gallium nitride (GaN)-based materials (including epitaxial layers based on GaN layers), the core 110 may be a polycrystalline ceramic material, such as polycrystalline aluminum nitride (AlN), which may include a binder material such as yttrium oxide. Other materials may be used in the core 110, including polycrystalline gallium nitride (GaN), polycrystalline aluminum gallium nitride (AlGaN), polycrystalline silicon carbide (SiC), polycrystalline zinc oxide (ZnO), polycrystalline gallium trioxide (Ga2O3), etc.

[0029] The thickness of the core may be on the order of about 100 μm to 1,500 μm (e.g., 725 μm). The core 110 is encapsulated in a first adhesion layer 112, which may be referred to as a shell or encapsulation shell. In one embodiment, the first adhesion layer 112 includes a layer of tetraethyl orthosilicate (TEOS) having a thickness of on the order of. In other embodiments, the thickness of the first adhesion layer varies, e.g., from to Although TEOS is used for the adhesion layer in some embodiments, according to embodiments of the present invention, other materials that provide adhesion between a later deposited layer and the underlying layer or material (such as ceramics, especially polycrystalline ceramics) may be used. For example, SiO2 or other silicon oxides (Si x O y)Adheres well to the ceramic material and provides a suitable surface for subsequent deposition (e.g., deposition of a conductive material). In some embodiments, the first adhesion layer 112 completely surrounds the core 110 to form a fully encapsulated core, and can be formed using an LPCVD process. The first adhesion layer 112 provides a surface on which subsequent layers adhere to form components of the engineered substrate structure.

[0030] In addition to using an LPCVD process, a furnace-based process, etc. to form the encapsulating first adhesion layer, other semiconductor processes can be used according to embodiments of the present invention, including CVD processes or similar deposition processes. As an example, a deposition process that coats a portion of the core can be utilized, the core can be flipped, and the deposition process can be repeated to coat additional portions of the core. Thus, although an LPCVD technique is utilized in some embodiments to provide a fully encapsulated structure, other film-forming techniques can be used depending on the specific application.

[0031] A conductive layer 114 is formed around the adhesion layer 112. In one embodiment, the conductive layer 114 is a polysilicon (i.e., polycrystalline silicon) shell formed around the first adhesion layer 112, because polysilicon can exhibit poor adhesion to the ceramic material. In embodiments where the conductive layer is polysilicon, the thickness of the polysilicon layer can be (e.g., ) of the order of magnitude. In some embodiments, the polysilicon layer can be formed as a shell to completely surround the first adhesion layer 112 (e.g., a TEOS layer), thereby forming a fully encapsulated first adhesion layer, and it can be formed using an LPCVD process. In other embodiments, as described below, the conductive material can be formed on a portion of the adhesion layer, e.g., the lower half of the substrate structure. In some embodiments, the conductive material can be formed as a fully encapsulated layer and then removed on one side of the substrate structure.

[0032] In one embodiment, the conductive layer 114 can be a doped polysilicon layer to provide a highly conductive material, e.g., doped with boron to provide a p-type polysilicon layer. In some embodiments, the doping of boron is at 1×10 19 cm -3 [[ID= / / ID=17]]to 1×10 20 cm -3 level to provide high conductivity. Other dopants with different doping concentrations (e.g., dopants with a doping concentration range of 1×10 16 cm -3 to 5×10 18 cm -3 such as phosphorus, arsenic, bismuth, etc.) can be used to provide n-type or p-type semiconductor materials suitable for the conductive layer. Those of ordinary skill in the art will recognize many variations, modifications, and alternatives.

[0033] During the electrostatic adsorption of an engineered substrate to a semiconductor processing tool (e.g., a tool having an electrostatic chuck (ESC)), the presence of the conductive layer 114 is useful. The conductive layer 114 enables rapid removal of the adsorption after processing in a semiconductor processing tool. Thus, the substrate structure provided by embodiments of the present invention can be processed in the same manner as conventional silicon wafers. Those of ordinary skill in the art will recognize many variations, modifications, and alternatives.

[0034] A second adhesion layer 116 (e.g., a TEOS layer on the order of magnitude) 116 is formed around the conductive layer 114. In some embodiments, the second adhesion layer 116 completely surrounds the conductive layer 114 to form a fully encapsulated structure, and can be formed using an LPCVD process, a CVD process, or any other suitable deposition process, including depositing spin-on dielectrics.

[0035] A barrier layer 118, such as a silicon nitride layer, is formed around the second adhesion layer 116. In one embodiment, the barrier layer 118 is a silicon nitride layer 118, the thickness of which is to on the order of magnitude. In some embodiments, the barrier layer 118 completely surrounds the second adhesion layer 116 to form a fully encapsulated structure, and this barrier layer can be formed using an LPCVD process. In addition to a silicon nitride layer, amorphous materials (including SiCN, SiON, AlN, SiC, etc.) can be used as the barrier layer. In some embodiments, the barrier layer 118 includes multiple sub-layers that are constructed to form the barrier layer. Thus, the term barrier layer is not intended to represent a single layer or a single material, but rather encompasses one or more materials layered in a composite manner. Those of ordinary skill in the art will recognize many variations, modifications, and alternatives.

[0036] In some embodiments, the barrier layer 118 (e.g., a silicon nitride layer) prevents elements (e.g., yttrium oxide (i.e., yttria), oxygen, metal impurities, other trace elements, etc.) present in the core 110 from diffusing and / or outgassing into the environment of the semiconductor processing chamber where the engineered substrate can be present (e.g., during a high-temperature (e.g., 1000 °C) epitaxial growth process). With the encapsulation layer described herein, ceramic materials can be utilized in semiconductor process flows and cleanroom environments, and such ceramic materials include polycrystalline AlN designed for non-cleanroom environments.

[0037] Figure 2A is a secondary ion mass spectrometry (SIMS) profile showing the concentration of substances in an engineered structure as a function of depth according to an embodiment of the present invention. The engineered structure does not include the barrier layer 118. Refer to Figure 2A, several substances present in the ceramic core (e.g., yttrium, calcium, and aluminum) are reduced to negligible concentrations in the engineered layers 120 / 122. The concentrations of calcium, yttrium, and aluminum decrease by three, four, and six orders of magnitude, respectively.

[0038] Figure 2B is a SIMS profile showing the concentration of substances in an engineered structure without a barrier layer after annealing according to an embodiment of the present invention as a function of depth. As discussed above, during semiconductor processing operations, e.g., during the epitaxial growth of GaN-based layers, the engineered substrate structure provided by embodiments of the present invention can be exposed to high temperatures (∼1,100 °C) for several hours.

[0039] For Figure 2B the profile shown in, the engineered substrate structure was annealed at 1,100 °C for 4 hours. As Figure 2B shown, calcium, yttrium, and aluminum, which were initially present at low concentrations in the as-deposited sample, have diffused into the engineered layers to reach concentrations similar to those of other elements.

[0040] Figure 2C is a SIMS profile showing the concentration of substances in an engineered structure with a barrier layer after annealing according to an embodiment of the present invention as a function of depth. Incorporating the diffusion barrier layer 118 (e.g., a silicon nitride layer) into the engineered substrate structure prevents calcium, yttrium, and aluminum from diffusing into the engineered layers during the annealing process that occurs in the absence of the diffusion barrier layer. As Figure 2C shown, calcium, yttrium, and aluminum present in the ceramic core remain at low concentrations in the engineered layers after annealing. Thus, the use of the barrier layer 118 (e.g., a silicon nitride layer) prevents these elements from diffusing through the diffusion barrier layer, thereby preventing their release into the environment surrounding the engineered substrate. Similarly, any other impurities contained in the bulk ceramic material will be trapped by the barrier layer.

[0041] Typically, the ceramic material used to form the core 110 is fired at a temperature of 1,800 °C. It is expected that this process will expel a large number of impurities present in the ceramic material. These impurities can include yttrium, which is generated by using yttrium oxide as a sintering agent, calcium, and other elements and compounds. Subsequently, during the epitaxial growth process at a much lower temperature in the range of 800 °C to 1,100 °C, it can be expected that the subsequent diffusion of these impurities will be negligible. However, contrary to conventional expectations, the inventors have determined that significant diffusion of elements can occur through the layers of the engineered substrate even during the epitaxial growth process at temperatures far below the firing temperature of the ceramic material. Accordingly, embodiments of the present invention incorporate a barrier layer 118 (e.g., a silicon nitride layer) to prevent backside elements from diffusing outwards from the polycrystalline ceramic material (e.g., AlN) into the engineered layers 120 / 122 and the epitaxial layer, such as an optional GaN layer 130. The silicon nitride layer 118 encapsulating the underlying layers and materials provides the required barrier layer function.

[0042] As Figure 2B shown, elements initially present in the core 110, including yttrium, diffuse into and through the first TEOS layer 112, the polysilicon layer 114, and the second TEOS layer 116. However, as Figure 2C shown, the presence of the silicon nitride layer 118 prevents these elements from diffusing through the silicon nitride layer, thereby preventing their release into the environment surrounding the engineered substrate.

[0043] Referring again to Figure 1 , a bonding layer 120 (e.g., a silicon oxide layer) is deposited on a portion of the barrier layer 118 (e.g., the top surface of the barrier layer), and the bonding layer 120 is subsequently used during the bonding of the substantially single-crystalline layer 122. In some embodiments, the thickness of the bonding layer 120 can be approximately 1.5 μm.

[0044] The substantially single-crystalline layer 122 is suitable for use as a growth layer during the epitaxial growth process to form the epitaxial material 130. In some embodiments, the epitaxial material 130 includes a GaN layer having a thickness of 2 μm to 10 μm, which can be used as one of the multiple layers used in optoelectronic devices, RF devices, power devices, etc. In one embodiment, the substantially single-crystalline layer 122 includes a substantially single-crystalline silicon layer attached to the silicon oxide layer 118 using a layer transfer process.

[0045] Figure 3 is a simplified schematic diagram showing an engineered substrate structure according to an embodiment of the present invention. Figure 3The engineered substrate 300 shown in is suitable for a variety of electronic and optical applications. The engineered substrate includes a core 110 that may have a coefficient of thermal expansion (CTE) that substantially matches the CTE of the epitaxial material 130 that will be grown on the engineered substrate 300. The epitaxial material 130 is shown as optional because it is not required as a component of the engineered substrate structure but will typically be grown on the engineered substrate structure.

[0046] For applications that include the growth of gallium nitride (GaN)-based materials (including epitaxial layers based on GaN layers), the core 110 can be a polycrystalline ceramic material, such as polycrystalline aluminum nitride (AlN). The thickness of the core can be on the order of about 100 to 1,500 μm, such as 725 μm. The core 110 is encapsulated in a first adhesion layer 112, which can be referred to as a shell or encapsulation shell. In this embodiment, the first adhesion layer 112 completely encapsulates the core, but as will be discussed in further detail with respect to Figure 4 this is not required by the present invention.

[0047] In one embodiment, the first adhesion layer 112 includes a layer of tetraethyl orthosilicate (TEOS) having a thickness of about on the order of. In other embodiments, the thickness of the first adhesion layer varies, such as from to Although TEOS is used for the adhesion layer in some embodiments, according to embodiments of the present invention, other materials that provide adhesion between a subsequently deposited layer and a underlying layer or material (such as a ceramic, particularly a polycrystalline ceramic) can be used. For example, SiO2 or other silicon oxides (Si x O y ) adhere well to ceramic materials and provide a suitable surface for subsequent depositions (such as the deposition of conductive materials). In some embodiments, the first adhesion layer 112 completely surrounds the core 110 to form a completely encapsulated core, and an LPCVD process can be used. The adhesion layer provides a surface to which subsequent layers adhere to form components of the engineered substrate structure.

[0048] In addition to using an LPCVD process, a furnace-based process, etc. to form the encapsulation adhesion layer, other semiconductor processes can be used according to embodiments of the present invention. As an example, a deposition process that coats a portion of the core, such as CVD, PECVD, etc., can be utilized, the core can be flipped, and the deposition process can be repeated to coat additional portions of the core.

[0049] The conductive layer 314 is formed on at least a portion of the first adhesion layer 112. In one embodiment, the conductive layer 314 includes polysilicon (i.e., polycrystalline silicon), which is formed by a deposition process on the lower portion of the core / adhesion layer structure (e.g., the lower half of the back side). In embodiments where the conductive layer is polysilicon, the thickness of the polysilicon layer can be on the order of several thousand angstroms, e.g., In some embodiments, the polysilicon layer can be formed using an LPCVD process.

[0050] In one embodiment, the conductive layer 314 can be a doped polysilicon layer to provide a highly conductive material. For example, the conductive layer 314 can be doped with boron to provide a p-type polysilicon layer. In some embodiments, the doping of boron is at a level of about 1×10 19 cm -3 to 1×10 20 cm -3 to provide high conductivity. The presence of the conductive layer is useful during electrostatic chucking of the engineered substrate to a semiconductor processing tool (e.g., a tool having an electrostatic chuck (ESC)). The conductive layer 314 enables rapid removal of the chucking after processing. Thus, embodiments of the present invention provide a substrate structure that can be processed in a manner similar to that of conventional silicon wafers. Those of ordinary skill in the art will recognize many variations, modifications, and alternatives.

[0051] A second adhesion layer 316 (e.g., a second TEOS layer) is formed around the conductive layer 314 (e.g., the polysilicon layer). The thickness of the second adhesion layer 316 is on the order of In some embodiments, the second adhesion layer 316 can completely surround the conductive layer 314 as well as the first adhesion layer 112 to form a completely encapsulated structure, and can be formed using an LPCVD process. In other embodiments, the second adhesion layer 316 only partially surrounds the conductive layer 314, e.g., terminating at a position shown by plane 317, which can be aligned with the top surface of the conductive layer 314. In this example, the top surface of the conductive layer 314 will contact a portion of the barrier layer 118. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0052] A barrier layer 118 (e.g., a silicon nitride layer) is formed around the second adhesion layer 316. In some embodiments, the thickness of the barrier layer 118 is on the order of to In some embodiments, the barrier layer 118 completely surrounds the second adhesion layer 316 to form a completely encapsulated structure, and can be formed using an LPCVD process.

[0053] In some embodiments, the use of a silicon nitride barrier layer prevents, for example, during a high-temperature (e.g., 1000 °C) epitaxial growth process, elements present in the core 110 (e.g., yttrium oxide (i.e., yttria), oxygen, metal impurities, other trace elements, etc.) from diffusing and / or outgassing into the environment of the semiconductor processing chamber in which the engineered substrate may be present. With the encapsulation layer described herein, ceramic materials can be utilized in semiconductor processing flows and cleanroom environments, the ceramic materials including polycrystalline AlN designed for non-cleanroom environments.

[0054] Figure 4 is a simplified schematic diagram showing an engineered substrate structure according to another embodiment of the present invention. In Figure 4 the embodiment shown, a first adhesion layer 412 is formed on at least a portion of the core 110, but does not encapsulate the core 110. In this embodiment, as described more fully below, the first adhesion layer 412 is formed on the lower surface (the back side of the core 110) of the core 110 in order to enhance the adhesion of a subsequently formed conductive layer 414. Although the adhesion layer 412 is shown only on Figure 4 the lower surface of the core 110 in, it should be understood that the deposition of the adhesion layer material on other portions of the core will not adversely affect the performance of the engineered substrate structure, and such material may be present in various embodiments. Those of ordinary skill in the art will recognize many variations, modifications, and alternatives.

[0055] The conductive layer 414 does not encapsulate the first adhesion layer 412 and the core 110, but is substantially aligned with the first adhesion layer 412. Although the conductive layer 414 is shown as extending along the bottom or back side and up a portion of the sides of the first adhesion layer 412, the present invention does not require the extension along the vertical sides. Thus, embodiments may utilize deposition on one side of the substrate structure, masking one side of the substrate structure, etc. The conductive layer 414 may be formed on a portion of one side of the first adhesion layer 412, e.g., the bottom / back side. The conductive layer 414 provides electrical conduction on one side of the engineered substrate structure, which can be advantageous in radio frequency and high-power applications. As discussed with respect to Figure 1 the conductive layer 114 in, the conductive layer may include doped polysilicon.

[0056] A portion of the core 110, a portion of the first adhesion layer 412, and the conductive layer 414 are covered with a second adhesion layer 416 in order to enhance the adhesion of the barrier layer 418 to the underlying materials. As discussed above, the barrier layer 418 forms an encapsulation structure to prevent diffusion from the underlying layers.

[0057] In addition to semiconductor-based conductive layers, in other embodiments, the conductive layer 414 is a metal layer, such as titanium, etc.

[0058] Referring again to Figure 4 , depending on the implementation, one or more layers may be removed. For example, layers 412 and 414 may be removed, leaving only a single adhesion shell 416 and a barrier layer 418. In another embodiment, only layer 414 may be removed. In this embodiment, layer 412 may also balance the stress and wafer bending caused by the layer 120 deposited on top of layer 418. The construction of a substrate structure having an insulating layer on the top side of the core 110 (e.g., having only an insulating layer between the core 110 and the layer 120) will provide benefits for power / radio frequency applications where a highly insulating substrate is required.

[0059] In another embodiment, the barrier layer 418 may directly encapsulate the core 110, followed by the conductive layer 414 and then the adhesion layer 416. In this embodiment, the layer 120 may be deposited directly on the adhesion layer 416 from the top side. In yet another embodiment, the adhesion layer 416 may be deposited on the core 110, followed by the barrier layer 418, and then the conductive layer 414 and another adhesion layer 412.

[0060] Although some embodiments have been discussed in terms of layers, the term "layer" should be understood such that a layer may include multiple sub-layers, which are constructed to form the layer of interest. Thus, the term "layer" is not intended to represent a single layer composed of a single material, but rather encompasses one or more materials layered in a composite manner to form the desired structure. Those of ordinary skill in the art will recognize many variations, modifications, and alternatives.

[0061] Figure 5 is a simplified flowchart showing a method of manufacturing an engineered substrate according to an embodiment of the present invention. This method can be used to manufacture a substrate that is CTE-matched to one or more epitaxial layers grown on the substrate. Method 500 includes forming a support structure by the following steps: providing a polycrystalline ceramic core (510), encapsulating the polycrystalline ceramic core in a shell formed by a first adhesion layer (e.g., a tetraethyl orthosilicate (TEOS) shell) (512), and encapsulating the first adhesion layer in a conductive shell (e.g., a polysilicon shell) (514). The first adhesion layer may be formed as a single layer of TEOS. The conductive shell may be formed as a single layer of polysilicon.

[0062] The method further includes encapsulating the conductive shell in a second adhesion layer (e.g., a second TEOS shell) (516), and encapsulating the second adhesion layer in a barrier layer shell (518). The second adhesion layer may be formed as a single layer of TEOS. The barrier layer shell may be formed as a single layer of silicon nitride.

[0063] Once the support structure is formed through steps 510 - 518, the method further includes bonding a bonding layer (e.g., a silicon oxide layer) to the support structure (520), and bonding a substantially single crystal layer (e.g., a substantially single crystal silicon layer) to the silicon oxide layer (522). According to embodiments of the present invention, other substantially single crystal layers can be used, including SiC, sapphire, GaN, AlN, SiGe, Ge, diamond, Ga2O3, ZnO, etc. The bonding of the bonding layer can include depositing a bonding material and then performing a planarization process as described herein. In the embodiments described below, bonding a substantially single crystal layer (e.g., a substantially single crystal silicon layer) to the bonding layer utilizes a layer transfer process in which the layer is a single crystal silicon layer transferred from a silicon wafer.

[0064] Reference Figure 1 , the bonding layer 120 can be formed by depositing a thick (e.g., 4 μm thick) oxide layer and then performing a chemical mechanical polishing (CMP) process to thin the oxide to a thickness of about 1.5 μm. The thick initial oxide is used to fill voids and surface features present on the support structure, which may be present after manufacturing a polycrystalline core and continue to exist when forming Figure 1 the encapsulation layer shown. The CMP process provides a substantially flat surface free of voids, particles, or other features, which can then be used during the wafer transfer process to bond the substantially single crystal layer 122 (e.g., a substantially single crystal silicon layer) to the bonding layer 120. It should be understood that the bonding layer 120 need not be characterized by an atomically flat surface, but should provide a substantially flat surface that supports the bonding of the substantially single crystal layer (e.g., a substantially single crystal silicon layer) with the desired reliability.

[0065] The substantially single crystal silicon layer 122 can be bonded to the bonding layer 120 using a layer transfer process. In some embodiments, a silicon wafer (e.g., a silicon (111) wafer) is implanted to form a cleavage plane. After wafer bonding, the silicon substrate can be removed together with a portion of the single crystal silicon layer below the cleavage plane, resulting in Figure 1 the peeled single crystal silicon layer 122 shown in. The thickness of the substantially single crystal layer 122 can vary to meet the specifications of various applications. In addition, the crystal orientation of the substantially single crystal layer 122 can be changed to meet the specifications of the application. Additionally, the doping level and distribution in the substantially single crystal layer 122 can be changed to meet the specifications of a particular application.

[0066] Figure 5The method shown may also include smoothing the substantially single-crystalline layer (524). In some embodiments, the thickness and surface roughness of the substantially single-crystalline layer 122 may be further modified for high-quality epitaxial growth. Different device applications may have slightly different specifications regarding the thickness and surface smoothness of the substantially single-crystalline layer 122. The cleavage process delaminates the substantially single-crystalline layer 122 from the bulk single-crystalline silicon wafer at the peak of the implanted ion distribution. After cleavage, the substantially single-crystalline layer 122 may be adjusted or modified in several aspects before being used as a growth surface for the epitaxial growth of other materials (such as gallium nitride).

[0067] First, the transferred substantially single-crystalline layer 122 may contain a small residual hydrogen concentration and may have some crystal damage from the implants. Therefore, it may be beneficial to remove the thin portion of the transferred substantially single-crystalline layer 122 in which the lattice is damaged. In some embodiments, the depth of the implants may be adjusted to be greater than the desired final thickness of the substantially single-crystalline layer 122. The additional thickness allows the damaged thin portion of the transferred substantially single-crystalline layer to be removed, leaving an undamaged portion with the desired final thickness.

[0068] Second, it may be desirable to adjust the total thickness of the substantially single-crystalline layer 122. Generally, it may be desirable to make the substantially single-crystalline layer 122 thick enough to provide a high-quality lattice template for the subsequent growth of one or more epitaxial layers, but thin enough to be "compliant". The substantially single-crystalline layer 122 may be referred to as "compliant" when its physical properties are less constrained and very similar to the surrounding materials, with a low tendency to generate crystal defects. The compliance of the substantially single-crystalline layer 122 may be inversely related to the thickness of the substantially single-crystalline layer 122. Higher compliance may result in a lower defect density in the epitaxial layer grown on the template and enable the growth of a thicker epitaxial layer. In some embodiments, the thickness of the substantially single-crystalline layer 122 may be increased by epitaxially growing silicon on the exfoliated silicon layer.

[0069] Third, it may be beneficial to improve the smoothness of the substantially single-crystalline layer 122. The smoothness of this layer may be related to the total hydrogen dose, the presence of any co-implanted species, and the annealing conditions used to form the hydrogen-based cleavage plane. As discussed below, the initial roughness caused by layer transfer (i.e., the cutting step) can be mitigated by thermal oxidation and oxide stripping.

[0070] In some embodiments, the removal of the damaged layer and the adjustment of the final thickness of the substantially single-crystalline layer 122 can be achieved by thermally oxidizing the top of the exfoliated silicon layer and then stripping the oxide layer with hydrofluoric (HF) acid. For example, a thermally oxidized silicon layer with an initial thickness of 0.5 μm can be used to produce a silicon dioxide layer with a thickness of approximately 420 nm. After removing the grown thermal oxide, the remaining silicon thickness in the transfer layer may be approximately 53 nm. During thermal oxidation, the implanted hydrogen can migrate towards the surface. Therefore, some damage can be removed by subsequent oxide layer stripping. Moreover, thermal oxidation is typically carried out at a temperature of 1000 °C or higher. The elevated temperature can also repair lattice damage.

[0071] The silicon dioxide layer formed on the top of the substantially single-crystalline layer during thermal oxidation can be stripped using HF acid etching. By adjusting the temperature and concentration of the HF solution, as well as the stoichiometry and density of the silicon dioxide, the etching selectivity of the HF acid between the silicon dioxide and silicon (SiO2:Si) can be adjusted. The etching selectivity refers to the etching rate of one material relative to another material. For (SiO2:Si), the selectivity range of the HF solution can be from approximately 10:1 to approximately 100:1. High etching selectivity can reduce the surface roughness by a factor similar to the initial surface roughness. However, the surface roughness of the resulting substantially single-crystalline layer 122 may still be greater than the desired surface roughness. For example, the bulk Si(111) surface can have a root mean square (RMS) surface roughness of less than 0.1 nm, which is determined by a 2 μm × 2 μm atomic force microscope (AFM) scan before additional processing. In some embodiments, the desired surface roughness of gallium nitride material epitaxially grown on Si(111) can be, for example, less than 1 nm, less than 0.5 nm, or less than 0.2 nm in a 30 μm × 30 μm AFM scan area.

[0072] If the surface roughness of the substantially single-crystalline layer 122 exceeds the desired surface roughness after thermal oxidation and oxide layer stripping, additional surface smoothing can be performed. There are several methods for smoothing silicon surfaces. These methods may include hydrogen annealing, laser trimming, plasma smoothing, and touch polishing (e.g., chemical mechanical polishing or CMP). These methods may involve the preferential erosion of high aspect ratio surface peaks. Therefore, high aspect ratio features on the surface can be removed faster than low aspect ratio features, resulting in a smoother surface.

[0073] It should be understood that Figure 5 the specific steps shown provide a particular method for manufacturing an engineered substrate according to an embodiment of the present invention. According to alternative embodiments, other step sequences may also be performed. For example, alternative embodiments of the present invention may perform the steps outlined above in a different order. Additionally, Figure 5The individual steps shown may include multiple sub-steps, which may be performed in various orders suitable for the individual steps. Additionally, depending on the particular application, additional steps may be added or removed. Those of ordinary skill in the art will recognize many variations, modifications, and alternatives.

[0074] Figure 6 is a simplified schematic diagram showing an epitaxial / engineered substrate structure for RF and power applications according to an embodiment of the present invention. In some LED applications, the engineered substrate structure provides a growth substrate capable of growing high-quality GaN layers, and the engineered substrate structure is subsequently removed. However, for RF and power device applications, the engineered substrate structure forms part of the finished device, and thus, the electrical, thermal, and other properties of the engineered substrate structure or components of the engineered substrate structure are important for a particular application.

[0075] Reference Figure 1 , the single-crystalline silicon layer 122 is typically a lift-off layer separated from a silicon donor wafer using implantation and lift-off techniques. Typical implants are hydrogen and boron. For power and RF device applications, the electrical properties of the layers and materials in the engineered substrate structure are important. For example, some device architectures utilize a highly insulating silicon layer with a resistance greater than 10 3 Ohm-cm to reduce or eliminate leakage through the substrate and the interface layer. Other applications utilize a design including a conductive silicon layer of a predetermined thickness (e.g., 1 μm) to connect the source of the device to other components. Thus, in these applications, it is necessary to control the size and properties of the single-crystalline silicon layer. In designs using implantation and lift-off techniques during layer transfer, there are residual implanted atoms, such as hydrogen or boron, in the silicon layer, thereby changing the electrical properties. Additionally, it may be difficult to control the thickness, conductivity, and other properties of the thin silicon layer using adjustments of the implantation dose, which may affect the conductivity of the implantation profile and the full width at half maximum (FWHM) of the semiconductor, adjustments of the surface roughness and cleavage plane position accuracy, and adjustments of the implantation depth that can affect the layer thickness.

[0076] According to an embodiment of the present invention, silicon epitaxy on the engineered substrate structure is utilized to achieve the desired characteristics of the single-crystalline silicon layer suitable for a particular device design.

[0077] Reference Figure 6 , the epitaxial / engineered substrate structure 600 includes an engineered substrate structure 610 and a silicon epitaxial layer 620 formed thereon. The engineered substrate structure 610 may be the same as Figure 1, The engineered substrate structures shown in FIGS. 3 and 4 are similar. Generally, after layer transfer, the substantially single-crystalline silicon layer 122 is on the order of about 0.5 μm. In some processes, a surface conditioning process can be used to reduce the thickness of the single-crystalline silicon layer 122 to about 0.3 μm. To increase the thickness of the single-crystalline silicon layer to about 1 μm for achieving reliable ohmic contacts, for example, an epitaxial single-crystalline silicon layer 620 is grown on the substantially single-crystalline silicon layer 122 formed by the layer transfer process using an epitaxial process. Various epitaxial growth processes can be used to grow the epitaxial single-crystalline silicon layer 620, including CVD, ALD, MBE, etc. The thickness of the epitaxial single-crystalline silicon layer 620 can be in the range of about 0.1 μm to about 20 μm, for example, between 0.1 μm and 10 μm.

[0078] Figure 7 is a simplified schematic diagram showing a III-V epitaxial layer on an engineered substrate structure according to an embodiment of the present invention. Figure 7 The structure shown in FIG. can be referred to as a double-epitaxial structure as described below. As Figure 7 shown, the engineered substrate structure 710 including the epitaxial single-crystalline silicon layer 620 has a III-V epitaxial layer 720 formed thereon. In one embodiment, the III-V epitaxial layer includes gallium nitride (GaN).

[0079] Depending on the desired function, the desired thickness of the III-V epitaxial layer 720 can vary significantly. In some embodiments, the thickness of the III-V epitaxial layer 720 can vary between 0.5 μm and 100 μm, for example, the thickness is greater than 5 μm. The resulting breakdown voltage of the device fabricated on the III-V epitaxial layer 720 can vary depending on the thickness of the III-V epitaxial layer 720. Some embodiments provide a breakdown voltage of at least 100V, 300V, 600V, 1.2kV, 1.7kV, 3.3kV, 5.5kV, 13kV or 20kV.

[0080] To provide conductivity between the parts of the III-V epitaxial layer 720 (which may include multiple sub-layers), a set of vias 724 is formed. In this example, the vias 724 enter the epitaxial single-crystalline silicon layer 620 through the top surface of the III-V epitaxial layer 720. The vias 724 are lined with an insulating layer (not shown) such that they are insulated from the III-V epitaxial layer 720. As an example, these vias can be used to connect the electrodes of a diode or a transistor to the underlying silicon layer by providing ohmic contacts through the vias, thereby discharging the charge accumulated in the device.

[0081] If a III-V epitaxial layer is grown on a single-crystalline silicon layer 122, it is difficult to achieve such an ohmic contact through a via because it would be difficult to terminate the via etch in the single-crystalline silicon layer 122: for example, etching through 5 μm of GaN and reliably terminating the etch in a 0.3 μm silicon layer across the wafer. Embodiments of the present invention can provide a single-crystalline silicon layer with a thickness of multiple microns, which is difficult to achieve using an implantation and lift-off process because achieving a large implantation depth requires a high implantation energy. Furthermore, the thick silicon layer enables applications such as the vias shown, which enables a wide variety of device designs.

[0082] In addition to increasing the thickness of the silicon "layer" by epitaxially growing a single-crystalline silicon layer 620 on the single-crystalline silicon layer 122, other adjustments can be made to the original properties of the single-crystalline silicon layer 122, including modifications to conductivity, crystallinity, etc. For example, if a silicon layer on the order of 10 μm is required before additional epitaxial growth of a III-V layer or other material, such a thick layer can be grown according to embodiments of the present invention.

[0083] Because the implantation process can affect the properties of the single-crystalline silicon layer 122, for example, residual boron / hydrogen atoms can affect the electrical properties of silicon, embodiments of the present invention remove a portion of the single-crystalline silicon layer 122 prior to the epitaxial growth of the single-crystalline silicon layer 620. For example, the single-crystalline silicon layer 122 can be thinned to form a layer with a thickness of 0.1 μm or less, removing most or all of the residual boron / hydrogen atoms. Then the subsequent growth of the single-crystalline silicon layer 620 is used to provide a single-crystalline material with electrical and / or other properties that are substantially independent of the corresponding properties of the layers formed using a layer transfer process.

[0084] In addition to increasing the thickness of the single-crystalline silicon material coupled to the engineered substrate structure, the electrical properties (including the conductivity of the epitaxial single-crystalline silicon layer 620) can be different from the electrical properties of the single-crystalline silicon layer 122. Doping of the epitaxial single-crystalline silicon layer 620 during growth can produce p-type silicon by doping with boron and n-type silicon by doping with phosphorus. Undoped silicon can be grown to provide high-resistivity silicon for use in devices with insulating regions. In particular, insulating layers can be used in RF devices.

[0085] The lattice constant of the epitaxial single-crystalline silicon layer 620 can be adjusted during growth to be different from the lattice constant of the single-crystalline silicon layer 122 to produce strained epitaxial material. In addition to silicon, other elements can be epitaxially grown to provide layers including strained layers (which include silicon germanium, etc.). For example, a buffer layer can be grown on the single-crystalline silicon layer 122, on the epitaxial single-crystalline silicon layer 620, or between the layers to enhance subsequent epitaxial growth. These buffer layers can include strained III-V layers, silicon germanium strained layers, etc. Additionally, the buffer layer and other epitaxial layers can be graded by mole fraction, dopant, polarity, etc. Those of ordinary skill in the art will recognize many variations, modifications, and alternatives.

[0086] In some embodiments, the strain present in the single-crystalline silicon layer 122 or the epitaxial single-crystalline silicon layer 620 can be released during the growth of subsequent epitaxial layers, including III-V epitaxial layers.

[0087] Figure 8 FIG. 5 is a simplified flowchart showing a method of fabricating an engineered substrate according to another embodiment of the present invention. The method includes forming a support structure by providing a polycrystalline ceramic core (810) and forming a first adhesion layer (812) coupled to at least a portion of the polycrystalline ceramic core. The first adhesion layer can include a tetraethyl orthosilicate (TEOS) layer. The method further includes forming a conductive layer (814) coupled to the first adhesion layer. The conductive layer can be a polysilicon layer. The first adhesion layer can be formed as a single layer of TEOS. The conductive layer can be formed as a single layer of polysilicon.

[0088] The method further includes forming a second adhesion layer (816) coupled to at least a portion of the conductive layer and forming a barrier shell (818). The second adhesion layer can be formed as a single layer of TEOS. The barrier shell can be formed as a single layer of silicon nitride or a series of sub-layers forming the barrier shell.

[0089] Once the support structure is formed by steps 810-818, the method further includes bonding a bonding layer (e.g., a silicon oxide layer) to the support structure (820) and bonding a substantially single-crystalline silicon layer or a substantially single-crystalline layer to the silicon oxide layer (822). The bonding of the bonding layer can include deposition of a bonding material followed by a planarization process as described herein.

[0090] The substantially single-crystalline silicon layer 122 can be bonded to the bonding layer 120 using a layer transfer process. In some embodiments, a silicon wafer is implanted (e.g., a silicon (111) wafer) to form a cleavage plane. After wafer bonding, the silicon substrate can be removed along with a portion of the single-crystalline silicon layer under the cleavage plane, resulting in Figure 1 the exfoliated single-crystalline silicon layer 122 shown in FIG. 6. The thickness of the substantially single-crystalline silicon layer 122 can vary to meet the specifications of various applications. Additionally, the crystal orientation of the substantially single-crystalline layer 122 can be changed to meet the specifications of the application. Additionally, the doping level and distribution in the substantially single-crystalline layer 122 can be changed to meet the specifications of a particular application. In some embodiments, the substantially single-crystalline silicon layer 122 can be smoothed as described above.

[0091] Figure 8 The method shown in FIG. can further include forming an epitaxial silicon layer (824) by epitaxial growth on the substantially single-crystalline silicon layer and forming an epitaxial III-V layer (826) by epitaxial growth on the epitaxial silicon layer. In some embodiments, the epitaxial III-V layer can include gallium nitride (GaN).

[0092] It should be understood that Figure 8The specific steps shown provide a particular method of fabricating an engineered substrate in accordance with another embodiment of the present invention. According to alternative embodiments, other sequences of steps may also be performed. For example, alternative embodiments of the present invention may perform the steps outlined above in a different order. Additionally, Figure 8 the individual steps shown may include multiple sub-steps which may be performed in a variety of sequences suitable for the individual steps. Additionally, depending on the particular application, additional steps may be added or removed. Those of ordinary skill in the art will recognize many variations, modifications, and alternatives.

[0093] It should also be understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes thereto may be made by those skilled in the art, and such various modifications or changes are included within the spirit and scope of this application and the scope of the appended claims.

Claims

1. A method of manufacturing a substrate, the method comprising: forming a support structure by the following steps: providing a polycrystalline ceramic core, forming a first adhesion layer coupled to the polycrystalline ceramic core, forming a conductive layer coupled to the first adhesion layer, forming a second adhesion layer coupled to the conductive layer, and forming a barrier layer coupled to the second adhesion layer; forming a bonding layer coupled to the support structure; bonding a single crystal silicon layer to the bonding layer; and forming one or more epitaxial III-V layers coupled to the single crystal silicon layer.

2. The method according to claim 1, wherein, The polycrystalline ceramic core includes aluminum nitride.

3. The method according to claim 2, wherein The one or more epitaxial III-V layers include an epitaxial gallium nitride layer.

4. The method according to claim 3, wherein, The epitaxial gallium nitride layer has a thickness of 5 μm or greater.

5. The method according to claim 3, wherein The one or more epitaxial III-V layers further include an epitaxial aluminum nitride layer, or an epitaxial aluminum gallium nitride layer, or a combination thereof.

6. The method according to claim 1, wherein The bonding of the single crystal silicon layer is performed by lift-off.

7. The method according to claim 6, further comprising, before forming the one or more epitaxial III-V layers: forming an epitaxial silicon layer coupled to the single crystal silicon layer; wherein the one or more epitaxial III-V layers are coupled to the epitaxial silicon layer.

8. The method according to claim 7, wherein the epitaxial silicon layer is strained.

9. The method according to claim 1, wherein: the first adhesion layer includes tetraethyl orthosilicate; the conductive layer includes polycrystalline silicon; the second adhesion layer includes tetraethyl orthosilicate; the barrier layer includes silicon nitride; and the bonding layer includes silicon oxide.

10. The method according to claim 9, wherein: the first adhesion layer encapsulates the polycrystalline ceramic core; the conductive layer encapsulates the first adhesion layer; the second adhesion layer encapsulates the conductive layer; and the barrier layer encapsulates the second adhesion layer.

11. An engineered substrate structure, comprising: a support structure, comprising: a polycrystalline ceramic core, a first adhesion layer coupled to the polycrystalline ceramic core, a conductive layer coupled to the first adhesion layer, a second adhesion layer coupled to the conductive layer, and a barrier layer coupled to the second adhesion layer; a bonding layer coupled to the support structure; and a single crystal gallium oxide layer coupled to the bonding layer.

12. The engineered substrate structure according to claim 11, wherein, The polycrystalline ceramic core includes aluminum nitride.

13. The engineered substrate structure according to claim 12, wherein: the first adhesion layer includes a first tetraethyl orthosilicate layer encapsulating the polycrystalline ceramic core; the conductive layer includes a polycrystalline silicon layer encapsulating the first tetraethyl orthosilicate layer; the second adhesion layer includes a second tetraethyl orthosilicate layer encapsulating the polycrystalline silicon layer; the barrier layer includes a silicon nitride layer encapsulating the second tetraethyl orthosilicate layer; and the bonding layer includes silicon oxide.

14. The engineered substrate structure according to claim 11, wherein, The single crystal gallium oxide layer includes a lift-off single crystal gallium oxide layer.

15. The engineered substrate structure according to claim 14, further comprising: an epitaxial gallium oxide layer coupled to the single crystal gallium oxide layer.

16. The engineered substrate structure according to claim 11, wherein, The single crystal gallium oxide layer includes a lift-off single crystal gallium oxide layer and an epitaxial gallium oxide layer grown on the lift-off single crystal gallium oxide layer.

17. The engineered substrate structure according to claim 16, further comprising: An epitaxial layer coupled to the gallium oxide layer of the single crystal.

18. The engineered substrate structure according to claim 17, wherein, The epitaxial layer includes an epitaxial III-V layer.

19. The engineered substrate structure according to claim 18, wherein, The epitaxial III-V layer includes an epitaxial gallium nitride layer and / or an epitaxial aluminum gallium nitride layer.

20. The engineered substrate structure according to claim 17, further comprising a plurality of vias extending from the epitaxial layer to the epitaxial gallium oxide layer.

21. The engineered substrate structure according to claim 17, further comprising one or more buffer layers disposed between the gallium oxide layer of the single crystal and the epitaxial layer.

22. A substrate, comprising: A support structure, the support structure comprising: A polycrystalline ceramic core, A first adhesion layer coupled to the polycrystalline ceramic core, A conductive layer coupled to the first adhesion layer, A second adhesion layer coupled to the conductive layer, and A barrier layer coupled to the second adhesion layer; A bonding layer coupled to the support structure; A single crystal gallium oxide layer coupled to the bonding layer; and An epitaxial layer coupled to the single crystal gallium oxide layer.

23. The substrate according to claim 22, wherein, The polycrystalline ceramic core includes aluminum nitride.

24. The substrate according to claim 23, wherein, The bonding layer includes silicon oxide.

25. The substrate according to claim 22, wherein, The epitaxial layer includes an epitaxial III-V layer.

26. The substrate according to claim 25, wherein, The epitaxial III-V layer includes an epitaxial gallium nitride layer.

27. The substrate according to claim 22, wherein, The epitaxial layer has a thickness of 5 μm or greater.

28. The substrate according to claim 22, wherein, The single crystal gallium oxide layer includes a lifted-off gallium oxide layer.

29. The substrate according to claim 22, wherein, The single crystal gallium oxide layer includes a lifted-off gallium oxide layer and an epitaxial gallium oxide layer on the lifted-off gallium oxide layer.

30. The substrate according to claim 22, wherein: The polycrystalline ceramic core includes polycrystalline gallium nitride; The first adhesion layer includes tetraethyl orthosilicate; The conductive layer includes polysilicon; The second adhesion layer includes tetraethyl orthosilicate; The barrier layer includes silicon nitride; and The bonding layer includes silicon oxide.

31. A substrate, comprising: A support structure, the support structure comprising: A polycrystalline ceramic core, A first adhesion layer coupled to the polycrystalline ceramic core, A conductive layer coupled to the first adhesion layer, A second adhesion layer coupled to the conductive layer, and A barrier layer coupled to the second adhesion layer; A bonding layer coupled to the support structure; A single crystal silicon layer coupled to the bonding layer; and An epitaxial III-V layer coupled to the single crystal silicon layer or an epitaxial single crystal silicon layer coupled to the single crystal silicon layer.

32. The substrate according to claim 31, wherein the polycrystalline ceramic core includes aluminum nitride.

33. The substrate according to claim 31, wherein the epitaxial III-V layer includes an epitaxial gallium nitride layer.

34. The substrate according to claim 33, wherein the epitaxial gallium nitride layer has a thickness of 5 μm or greater.

35. The substrate according to claim 31, wherein the single crystal silicon layer includes a lifted-off silicon layer and an epitaxial silicon layer grown on the lifted-off silicon layer, and wherein the single crystal silicon layer has a thickness of 0.5 μm.

36. The substrate according to claim 31, wherein: The first adhesion layer includes a first tetraethyl orthosilicate layer encapsulating the polycrystalline ceramic core; The conductive layer includes a polysilicon layer encapsulating the first tetraethyl orthosilicate layer; The second adhesion layer includes a second tetraethyl orthosilicate layer encapsulating the polysilicon layer; and The barrier layer includes a silicon nitride layer encapsulating the second tetraethyl orthosilicate layer.

37. The substrate according to claim 36, wherein: The thickness of the first tetraethyl orthosilicate layer is 100 nm; The thickness of the polysilicon layer is 300 nm; The thickness of the second tetraethyl orthosilicate layer is 100 nm; and The thickness of the silicon nitride layer is 400 nm.

38. The substrate according to claim 31, wherein the bonding layer is a silicon oxide layer.

39. The substrate according to claim 31, wherein the substrate includes the epitaxial single-crystalline silicon layer, and the substrate further includes an epitaxial III-V layer coupled to the epitaxial single-crystalline silicon layer and a plurality of vias leading from the epitaxial III-V layer to the epitaxial single-crystalline silicon layer.

40. A method of manufacturing a substrate, the method comprising: Forming a support structure by the following steps: Providing a polycrystalline ceramic core, Encapsulating the polycrystalline ceramic core in a first adhesion shell, Encapsulating the first adhesion shell in a conductive shell, Encapsulating the conductive shell in a second adhesion shell, and Encapsulating the second adhesion shell in a barrier shell; Bonding a bonding layer to the support structure; Bonding a single-crystalline silicon layer to the bonding layer; Forming an epitaxial silicon layer on the single-crystalline silicon layer by epitaxial growth; And Forming one or more epitaxial III-V layers by epitaxial growth on the epitaxial silicon layer.

41. The method according to claim 40, further comprising: Forming a plurality of vias leading from the one or more epitaxial III-V layers to the epitaxial silicon layer.

42. The method according to claim 40, wherein The polycrystalline ceramic core includes aluminum nitride.

43. The method according to claim 40, wherein, The one or more epitaxial III-V layers include an epitaxial gallium nitride layer.

44. The method according to claim 43, wherein, The one or more epitaxial III-V layers further include an epitaxial aluminum nitride layer or an epitaxial aluminum gallium nitride layer or a combination thereof.

45. The method according to claim 40, wherein: The first adhesion shell includes a first tetraethyl orthosilicate shell; The conductive shell includes a polysilicon shell; The second adhesion shell includes a second tetraethyl orthosilicate shell; The barrier shell includes a silicon nitride shell; and The bonding layer includes silicon oxide.

46. The method according to claim 45, wherein: The first tetraethyl orthosilicate shell includes a single layer of tetraethyl orthosilicate; The polysilicon shell includes a single layer of polysilicon; The second tetraethyl orthosilicate shell includes a single layer of tetraethyl orthosilicate; And 47. The method according to claim 40, wherein The silicon nitride shell includes a single layer of silicon nitride.

48. The method according to claim 40, wherein The one or more epitaxial III-V layers have a thickness of 5 μm or greater.

49. The method according to claim 48, wherein, The bonding of the single-crystalline silicon layer is performed by lift-off. The single-crystalline silicon layer has a thickness of 0.5 μm.

50. A substrate, comprising: A support structure, comprising: A polycrystalline ceramic core, A first adhesion layer encapsulating the polycrystalline ceramic core, A barrier layer encapsulating the first adhesion layer, A second adhesion layer coupled to the barrier layer, and A conductive layer coupled to the second adhesion layer; A bonding layer coupled to the support structure; A single-crystalline silicon layer coupled to the bonding layer; and 51. The substrate according to claim 50, wherein, An epitaxial semiconductor layer coupled to the single-crystalline silicon layer.

52. The substrate according to claim 50, wherein, The polycrystalline ceramic core includes aluminum nitride.

53. The substrate according to claim 50, wherein, The bonding layer includes silicon oxide.

54. The substrate according to claim 53, wherein, The epitaxial semiconductor layer includes an epitaxial III-V layer. The epitaxial III-V layer includes an epitaxial gallium nitride layer.

55. The substrate according to claim 54, wherein, The epitaxial gallium nitride layer has a thickness of 5 μm or greater.

56. The substrate according to claim 50, wherein, The epitaxial semiconductor layer includes an epitaxial single-crystalline silicon layer.

57. The substrate according to claim 56, further comprising an epitaxial III-V layer coupled to the epitaxial single-crystalline silicon layer.

58. The substrate according to claim 57, further comprising a plurality of vias extending from the epitaxial III-V layer to the epitaxial single-crystalline silicon layer.

59. The substrate according to claim 50, wherein, The single-crystalline silicon layer includes a detached silicon layer.

60. The substrate according to claim 50, wherein, The single-crystalline silicon layer includes a detached silicon layer and an epitaxial silicon layer grown on the detached silicon layer, and the single-crystalline silicon layer has a thickness of 0.5 μm.

61. The substrate according to claim 50, wherein: The first adhesion layer includes a first tetraethyl orthosilicate layer that encapsulates the polycrystalline ceramic core; The barrier layer includes a silicon nitride layer; The second adhesion layer includes a second tetraethyl orthosilicate layer; and The conductive layer includes a polysilicon layer.

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