Semiconductor structure and method for forming the same

Abstract

The present application provides a semiconductor structure and a method for forming the same. The formation method comprises: providing a substrate, the substrate comprising a drift region and a first isolation structure and a second isolation structure located in the drift region; forming a gate structure on a portion of the drift region surface between the first isolation structure and the second isolation structure; forming a first body region in the drift region between the gate structure and the first isolation structure, and forming a second body region in the drift region between the gate structure and the second isolation structure, wherein both the first body region and the second body region extend to the lower portion of the gate structure; forming a first source region and a second source region in the first body region and the second body region on both sides of the gate structure, respectively; and forming a first drain and a second drain in the drift region, wherein the first isolation structure separates the first drain and the first source, and the second isolation structure separates the second drain and the second source. The semiconductor structure and the method for forming the semiconductor structure of the technical solution of the present application can optimize device performance.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Lateral Double-Diffused MOSFET (LDMOS) is a type of power field-effect transistor with many advantages, such as better thermal stability and frequency stability, higher gain and durability, lower feedback capacitance and thermal resistance, constant input impedance and simpler bias circuit.

[0003] Currently, LDMOS devices and their manufacturing processes still face numerous challenges, resulting in devices failing to meet requirements. For example, electric field peaks are easily generated at the gate edge at the source, leading to breakdown or TDDB issues. Forming the body region requires an additional gate etch process, increasing production capacity and costs. Because the photoresist serves as a mask for both gate etching and ion implantation, it is thick and has poor profile stability. The ion implantation process is highly dependent on the photoresist profile, which can easily lead to poor uniformity in the MOS tube. Summary of the Invention

[0004] The technical problem solved by the present application is to provide a semiconductor structure and a method for forming the same, which can optimize device performance.

[0005] To solve the above technical problems, the present application provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a drift region and a first isolation structure and a second isolation structure located in the drift region; forming a gate structure on a surface of a portion of the drift region between the first isolation structure and the second isolation structure; forming a first body region in the drift region between the gate structure and the first isolation structure and forming a second body region in the drift region between the gate structure and the second isolation structure, wherein both the first body region and the second body region extend to the lower portion of the gate structure; forming a first source region and a second source region in the first body region and the second body region on both sides of the gate structure respectively; and forming a first drain and a second drain in the drift region, wherein the first isolation structure separates the first drain and the first source, and the second isolation structure separates the second drain and the second source.

[0006] In an embodiment of the present application, the process of forming a gate structure on the surface of a portion of the drift region between the first isolation structure and the second isolation structure includes: depositing a gate dielectric layer and a gate electrode layer on the surface of the first isolation structure, the second isolation structure and the drift region in sequence; etching the gate dielectric layer and the gate electrode layer on the surfaces of the first isolation structure and the second isolation structure and on the surface of the portion of the drift region between the first isolation structure and the second isolation structure to form a gate structure.

[0007] In an embodiment of the present application, the process of forming the first body region and the second body region includes: using an ion implantation process to form a first body region in the drift region between the first isolation structure and the gate structure, and forming a second body region in the drift region between the second isolation structure and the gate structure; and performing heat treatment to extend the first body region and the second body region to the lower portion of the gate structure.

[0008] In an embodiment of the present application, a process for forming a first body region and a second body region using an ion implantation process includes: forming a patterned photoresist layer on the surface of the substrate and the gate structure, the patterned photoresist layer exposing a portion of the drift region surface between the gate structure and the first isolation structure and the second isolation structure and completely covering the side wall of the gate structure; performing a first ion implantation using the patterned photoresist layer as a mask to form a first ion implantation region; trimming the patterned photoresist layer so that the patterned photoresist layer only covers a portion of the surface of the gate structure; performing a second ion implantation using the patterned photoresist layer as a mask to form a second ion implantation region, the depth of the second ion implantation region being less than that of the first ion implantation region.

[0009] In an embodiment of the present application, before forming the first source region and the second source region, the method further includes: forming a sidewall spacer on the sidewall of the gate structure.

[0010] In the embodiment of the present application, the first source region, the second source region, the first drain region and the second drain region are formed by a source-drain ion implantation process.

[0011] In an embodiment of the present application, after forming the first drain region and the second drain region, it also includes: forming a first heavily doped region between the first source region and the first isolation structure, and forming a second heavily doped region between the second source region and the second isolation structure, wherein the first heavily doped region and the second heavily doped region have different doping types from the first source region and the second source region.

[0012] In an embodiment of the present application, an ion implantation process is used to form the first heavily doped region and the second heavily doped region.

[0013] In an embodiment of the present application, the substrate further includes a first deep well region, the first deep well region is located below the drift region, and the first deep well region and the drift region have different doping types.

[0014] In an embodiment of the present application, the substrate further includes a second deep well region, and the doping type of the second deep well region is different from that of the first deep well region.

[0015] In order to solve the above technical problems, the technical solution of the present application also provides a semiconductor structure, including: a substrate, the substrate including a drift region and a first isolation structure and a second isolation structure located in the drift region; a gate structure, located on a portion of the drift region surface between the first isolation structure and the second isolation structure; a first body region, located in the drift region between the gate structure and the first isolation structure, and extending to the lower part of the gate structure; a second body region, located in the drift region between the gate structure and the second isolation structure, and extending to the lower part of the gate structure; a first source region and a second source region, respectively located in the first body region and the second body region on both sides of the gate structure; a first drain region and a second drain region, both located in the drift region, wherein the first isolation structure separates the first drain and the first source, and the second isolation structure separates the second drain and the second source.

[0016] In an embodiment of the present application, the substrate further includes a first deep well region, the first deep well region is located below the drift region, and the first deep well region and the drift region have different doping types.

[0017] In an embodiment of the present application, the substrate further includes a second deep well region, and the doping type of the second deep well region is different from that of the first deep well region.

[0018] In an embodiment of the present application, both side walls of the gate structure further include sidewalls.

[0019] In an embodiment of the present application, the semiconductor structure further includes: a first heavily doped region, located between the first source region and the first isolation structure; a second heavily doped region, located between the second source region and the second isolation structure; wherein the first heavily doped region, the second heavily doped region, and the first source region, the second source region have different doping types.

[0020] Compared with the prior art, the semiconductor structure and the method for forming the same in the technical solution of the present application have the following beneficial effects:

[0021] The gate structure can be formed and the position of the body region can be defined through only one etching, which saves costs and alleviates production capacity pressure; the patterned photoresist layer formed is thin, the contour is easy to control, and the uniformity of the device is improved; the body region is formed in the drift region, and the drift region is folded under the body region. Under the same breakdown voltage, the area of ​​the drift region can be greatly reduced, achieving the purpose of reducing the size of the device; the problem of the electric field peak at the edge of the gate structure near the drain region in the prior art is avoided, the breakdown voltage is further improved, and the TDDB problem is avoided at the same time; the body region, the first deep well region, and the drift region form a Double-RESURF structure, which makes it easier for the device to obtain a larger breakdown voltage and a smaller on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The following figures describe in detail exemplary embodiments disclosed in this application. Identical reference numerals denote similar structures in several views of the drawings. Those skilled in the art will appreciate that these embodiments are non-limiting, exemplary embodiments, and that the drawings are for illustration and description purposes only and are not intended to limit the scope of this application. Other embodiments may also achieve the same inventive intent as described in this application. It should be understood that the drawings are not drawn to scale. Among them:

[0023] Figures 1 to 7 A schematic structural diagram corresponding to each step of a method for forming an LDMOS device;

[0024] Figure 8 A schematic flow chart of a method for forming a semiconductor structure according to an embodiment of the present application;

[0025] Figures 9 to 15 Schematic diagram of the structure corresponding to each step of the method for forming a semiconductor structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0026] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content of this application. Various local modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but is intended to be of the widest scope consistent with the claims.

[0027] refer to Figure 1 A conventional process for forming an LDMOS device includes providing a substrate 10, the substrate 10 including a deep well region 11 and a drift region 12. A plurality of spaced-apart isolation structures 13 are formed in the drift region 12. A gate dielectric layer 14 and a gate layer 15 are sequentially deposited on the surface of the drift region 12.

[0028] refer to Figure 2 and Figure 3 , the gate layer 15 is etched for the first time to expose a portion of the surface of the gate dielectric layer 14, providing space for ion implantation to form the source electrode in the subsequent process. The exposed surface of the gate dielectric layer 14 and the partial surface of the gate layer 15 are covered with a patterned photoresist layer 20. The patterned photoresist layer 20 defines the shape and size of the gate structure. Since the patterned photoresist layer 20 not only serves as a mask for etching the gate layer 15, but also serves as a mask for subsequent ion implantation, the thickness of the patterned photoresist layer 20 is relatively large, making it difficult to control the profile of the patterned photoresist layer 20. Therefore, the profile stability of the patterned photoresist layer 20 is poor, which in turn affects the progress of the subsequent process.

[0029] refer to Figure 4 , using the patterned photoresist layer 20 as a mask, the gate layer 15 is etched for the second time to form a first gate structure 31 and a second gate structure 32, providing space for ion implantation in the body region. During this etching process, in order to prevent etching from damaging the substrate 10, a gate dielectric layer 14 of a certain thickness is usually required to remain. If the remaining gate dielectric layer 14 is too thin, it is easy to cause the threshold voltage of the MOS to change and easily damage the substrate 10; if the remaining gate dielectric layer 14 is too thick, the gate layer 15 may not be completely etched, causing a short circuit between the gate and the source. Moreover, when etching the gate dielectric layer 14, the remaining thickness is uneven, and the energy is relatively low when performing surface body region ion implantation, resulting in uneven ion implantation. Therefore, the accuracy requirements for the second etching process are high, and the process is difficult to implement. In addition, the process requires two etching processes to define the ion implantation space in the body region, which increases cost and production capacity pressure.

[0030] refer to Figure 5 and Figure 6 Using the patterned photoresist layer 20 as a mask, an ion implantation process is performed to form the body region 40. Then, a heat treatment is performed to extend the body region 40 to the same depth as the drift region 12. Because the patterned photoresist layer 20 formed by the aforementioned process is relatively thick and has poor profile stability, and the ion implantation process for forming the body region 40 is highly dependent on the profile of the patterned photoresist layer 20, the uniformity of the MOS transistor is poor.

[0031] refer to Figure 7 Spacers 50 are formed on the sidewalls of the first gate structure 31 and the second gate structure 32. Ion implantation is used to form a source region 71 and a drain region 61 of the first gate structure 31, as well as a source region 72 and a drain region 62 of the second gate structure 32. A doped region 80 is formed between the source region 61 and the source region 62, with carrier paths shown as dashed lines in the figure.

[0032] There are some other LDMOS devices with similar structures. Figure 7 The difference is that the isolation structure between the gate structure 31 and the drain 61 and between the gate structure 32 and the drain 62 is omitted. This device structure has a very serious defect. The edge of the gate structure at the drain end is prone to generate an electric field peak, which makes it easy to break down or cause TDDB problems.

[0033] Based on this, the technical solution of the present application improves the structure of the LDMOS device and folds the drift region under the body region. Under the same carrier movement path, the device size can be greatly reduced, wherein the body region, drift region and deep well region can form a Double-RESURF structure, which has a higher breakdown voltage and smaller on-resistance than the traditional structure, and will not have the problems of gate structure edge breakdown and TDDB, and can simplify the process steps and improve the process accuracy.

[0034] The technical solution of the present invention is described in detail below with reference to the embodiments and drawings.

[0035] refer to Figure 8 The present invention provides a method for forming a semiconductor structure, which can form an LDMOS device, including:

[0036] Step S1: providing a substrate, wherein the substrate includes a drift region and a first isolation structure and a second isolation structure located in the drift region;

[0037] Step S2: forming a gate structure on a surface of a portion of the drift region between the first isolation structure and the second isolation structure;

[0038] Step S3: forming a first body region in the drift region between the gate structure and the first isolation structure, and forming a second body region in the drift region between the gate structure and the second isolation structure, wherein both the first body region and the second body region extend to a lower portion of the gate structure;

[0039] Step S4: forming a first source region and a second source region in the first body region and the second body region on both sides of the gate structure respectively, and forming a first drain and a second drain in the drift region, wherein the first isolation structure separates the first drain and the first source, and the second isolation structure separates the second drain and the second source.

[0040] refer to Figure 8 and Figure 9 , providing a substrate 100 , wherein the substrate 100 includes a drift region 130 and a first isolation structure 141 and a second isolation structure 142 located in the drift region 131 .

[0041] The substrate 100 may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon-on-insulator (SiO2) substrate, a germanium-on-insulator (GeO2) substrate, or a substrate comprising other elemental semiconductors or compound semiconductors, such as silicon carbide, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, aluminum indium arsenide, indium gallium arsenide, antimony gallium phosphide, or indium phosphide. In the embodiment of the present application, the material of the substrate 100 is silicon.

[0042] The first isolation structure 141 and the second isolation structure 142 are used to increase the conduction path of the LDMOS transistor, thereby increasing the breakdown voltage of the LDMOS transistor. In some embodiments, other isolation structures may also be included, such as a third isolation structure 143 and a fourth isolation structure 144, which primarily serve as isolation. The first isolation structure 141, the second isolation structure 142, the third isolation structure 143, and the fourth isolation structure 144 may all be shallow trench isolation.

[0043] In some embodiments, the formation process of the first isolation structure 141, the second isolation structure 142, the third isolation structure 143 and the fourth isolation structure 144 is as follows: forming a mask layer (not shown in the figure) on the substrate 100, the mask layer having an opening exposing the surface of the substrate; etching the substrate 100 along the opening to form a groove in the substrate 100; forming an isolation material layer covering the mask layer and filling the groove; flattening the isolation material layer until the surface of the substrate 100 is exposed, and forming a shallow trench isolation structure in the groove.

[0044] The drift region 130 is formed through an ion implantation process. Prior to forming the drift region 130, a first deep well region 120 and a second deep well region 110 may also be formed within the substrate 100 through an ion implantation process. The first deep well region 120 is located below the drift region 130, while the second deep well region 110 is located below the first deep well region 120. The first deep well region 120 and the drift region 130 have different doping types, while the second deep well region 110 and the drift region 130 have the same doping type. The first deep well region 120 facilitates depletion of the drift region 130. Together, the first deep well region 120, the drift region 130, and the body region formed in subsequent processes form a double-RESURF structure, significantly improving the breakdown voltage. The second deep well region 110 provides isolation to meet the ESD performance requirements of high-voltage devices. In other embodiments, the second deep well region 110 may be omitted or comprise multiple layers, depending on specific needs.

[0045] In some embodiments, the formed LDMOS is of P-type, the first deep well region 120 is doped with N-type impurity ions, and the drift region 130 is doped with P-type impurity ions. In another embodiment, the formed LDMOS is of N-type, the first deep well region 120 is doped with P-type impurity ions, and the drift region 130 is doped with N-type impurity ions. The N-type impurity ions are one or more of phosphorus ions, arsenic ions, and antimony ions; and the P-type impurity ions are one or more of boron ions, indium ions, and gallium ions.

[0046] Combine Figure 9 and Figure 10 A gate structure 200 is formed on a surface of a portion of the drift region 130 between the first isolation structure 141 and the second isolation structure 142 .

[0047] A gate dielectric layer 210 and a gate electrode layer 220 are sequentially deposited on the surfaces of the first isolation structure 141, the second isolation structure 142, and the drift region 130. In the embodiment of the present application, a gate dielectric layer 210 and a gate electrode layer 220 are also deposited on the surfaces of the third isolation structure 143 and the fourth isolation structure 144. The gate dielectric layer 210 and the gate electrode layer 220 are etched on the surfaces of the first isolation structure 141, the second isolation structure 142, the third isolation structure 143, and the fourth isolation structure 144; the surface of the drift region 130 between the first isolation structure 141 and the third isolation structure 143; the surface of the drift region 130 between the second isolation structure 142 and the fourth isolation structure 144; and the portion of the surface of the drift region 130 between the first isolation structure 141 and the second isolation structure 142 to form the gate structure 200. A dry etching process can be used to etch the gate dielectric layer 210 and the gate electrode layer 220. In some embodiments, the material of the gate dielectric layer 210 includes silicon oxide or a high-K dielectric material, such as HfO2, TiO2, HfZrO, HfSiNO, etc., and the material of the gate electrode layer 220 is a metal, such as W, Cu, Al, etc.

[0048] The embodiment of the present application can define the location of the body region through a single etching process, simplifying the process steps and reducing costs and production capacity pressures. In addition, when etching to form the gate structure, a patterned photoresist layer (not shown) is formed on the surface of the gate electrode layer 220. This patterned photoresist layer only serves as a mask for etching the gate electrode layer 220 and the gate dielectric layer 210, and does not serve as a mask for subsequent body region ion implantation. Therefore, the patterned photoresist layer does not need to be deposited very thickly, and its profile can be well controlled during the process.

[0049] Next, a first body region may be formed in the drift region between the gate structure and the first isolation structure, and a second body region may be formed in the drift region between the gate structure and the second isolation structure, both of which extend to the lower portion of the gate structure.

[0050] refer to Figure 11 A patterned photoresist layer 300 is formed on the surfaces of the substrate 100 and the gate structure 200. The patterned photoresist layer 300 exposes a portion of the surface of the drift region 130 between the gate structure 200 and the first isolation structure 141 and the second isolation structure 142, and completely covers the sidewalls of the gate structure 200. Because the body region to be formed in the embodiment of the present application does not need to be connected to the first deep well region, the ion implantation capability during ion implantation is relatively low. Therefore, the thickness of the patterned photoresist layer 300 is also thinner than that of the prior art. This solves the problem in the prior art of difficult control of the profile of the photoresist layer due to the thick photoresist layer, thereby improving the uniformity of the MOS transistor.

[0051] It should be noted that in the embodiment of the present application, the patterned photoresist layer 300 needs to cover the sidewalls of the gate structure 200. On the one hand, when multiple ion implantation processes are subsequently performed, the energy of the first or first few ion implantations is relatively large, and ions can penetrate the gate structure 200 and enter the drift region 130. In order to ensure that the ions are only implanted into the drift region between the gate structure 200 and the first isolation structure 141, and between the gate structure 200 and the second isolation structure 142; on the other hand, the patterned photoresist layer 300 on the sidewalls of the gate structure 200 can act as a sidewall, protecting the sidewalls of the gate structure 200 from damage by ion implantation. Of course, in other embodiments, the sidewalls of the patterned photoresist layer 300 can also be coplanar with the sidewalls of the gate structure 200.

[0052] refer to Figure 12 , using the patterned photoresist layer 300 as a mask, a first ion implantation is performed to form a first ion implantation region 401 and a first ion implantation region 402. The intensity of the first ion implantation is relatively high, forming the lower part of the body region to define the position of the body region. The first ion implantation region 401 and the first ion implantation region 402 serve the purpose of isolation and forming a RESURF structure with the drift region. The concentration of the first ion implantation region 401 and the first ion implantation region 402 needs to be controlled. If the concentration of the first ion implantation region 401 and the first ion implantation region 402 is too low, the breakdown voltage of the MOS tube is small; if the concentration of the first ion implantation region 401 and the first ion implantation region 402 is too high, the drift region is completely depleted and the MOS tube cannot work normally. The ion dose and ion energy of the first ion implantation are determined according to the actual situation.

[0053] The first ion implantation may include a single ion implantation, or may be performed in multiple steps. The multiple ion implantations may make the ions in the first ion implantation region 401 more uniformly distributed.

[0054] Then, the patterned photoresist layer 300 is trimmed so that it only covers a portion of the surface of the gate structure 200. The purpose is to expose the sidewalls of the gate structure 200. Since the energy of the second ion implantation is relatively low, the ions are implanted along the edge of the gate structure 200 and do not pass through the gate structure 200, achieving self-aligned ion implantation with high process precision and ensuring uniform electrical parameters between MOS devices. In the embodiment of the present application, oxygen can be introduced to react with the patterned photoresist layer 300 to trim the patterned photoresist layer 300.

[0055] refer to Figure 13 A second ion implantation is performed using the patterned photoresist layer 300 as a mask to form second ion implantation regions 411 and 412. The depths of the second ion implantation regions 411 and 412 are less than the depths of the first ion implantation regions 401 and 402. The energy of the second ion implantation is sufficiently low so that the ions cannot pass through the gate structure 200. The ion dose and ion energy of the second ion implantation are determined based on actual conditions.

[0056] The first ion implantation region 401 and the second ion implantation region 411 constitute a first body region 410 , and the first ion implantation region 402 and the second ion implantation region 412 constitute a second body region 420 . In order to extend the first body region 410 and the second body region 420 to below the gate structure 200 to form a channel, heat treatment is required.

[0057] refer to Figure 14 The first body region 410 and the second body region 420 are extended below the gate structure 200 through heat treatment. The heat treatment can ensure that the first body region 410 and the second body region 420 have the same width below the gate structure 200. The width of the channel can be adjusted by adjusting the temperature and time of the heat treatment. In some embodiments, the temperature and time of the heat treatment are adjusted based on actual conditions.

[0058] In some embodiments, the formed LDMOS is of P-type, and N-type impurity ions are doped into the first body region 410 and the second body region 420. In some embodiments, the formed LDMOS is of N-type, and P-type impurity ions are doped into the first body region 410 and the second body region 420. The N-type impurity ions are one or more of phosphorus ions, arsenic ions, and antimony ions; and the P-type impurity ions are one or more of boron ions, indium ions, and gallium ions.

[0059] Reference Figure 15 , forming a sidewall spacer 500 on the sidewall of the gate structure 200. The sidewall spacer 500 protects the sidewall of the gate structure 200 from being damaged by implantation when the source and drain are subsequently formed. The sidewall spacer 500 can be a single-layer or multi-layer (≥2-layer) structure, and the material of the sidewall spacer 500 is silicon oxide, silicon nitride, or other suitable materials.

[0060] A first source region 610 and a second source region 620 are respectively formed in the first body region 410 and the second body region 420 on both sides of the gate structure 200, and a first drain 710 and a second drain 720 are formed in the drift region 310, wherein the first isolation structure 141 separates the first drain 710 and the first source 610, and the second isolation structure 142 separates the second drain 720 and the second source 620.

[0061] The first source region 610, the second source region 620, the first drain 710 and the second drain 720 are formed by a source-drain ion implantation process. In some embodiments, the implantation dose and implantation energy of the source-drain ion implantation process are determined according to actual conditions.

[0062] In some embodiments, the formed LDMOS is of P type, and the first source region 610, the second source region 620, the first drain 710, and the second drain 720 are doped with P type impurity ions. In other embodiments, the formed LDMOS is of N type, and the first source region 610, the second source region 620, the first drain 710, and the second drain 720 are doped with N type impurity ions. The N type impurity ions are one or more of phosphorus (P) ions, arsenic (As) ions, and antimony (Te) ions; the P type impurity ions are one or more of boron (B) ions, boron fluoride (BF2) ions, indium (In) ions, and gallium (Ga) ions.

[0063] Continue to refer Figure 15After forming the first source region 610, the second source region 620, the first drain 710, and the second drain 720, the method further includes: forming a first heavily doped region 810 between the first source region 610 and the first isolation structure 141, and forming a second heavily doped region 820 between the second source region 620 and the second isolation structure 420, wherein the first heavily doped region 810 and the second heavily doped region 820 have a different doping type from the first source region 610 and the second source region 620. The first heavily doped region 810 and the second heavily doped region 820 function to connect the first body region 410 and the second body region 420. In some embodiments, the first heavily doped region and the second heavily doped region are formed using an ion implantation process, and the ion implantation dose and implantation energy are determined based on actual conditions.

[0064] In some embodiments, the formed LDMOS is of P-type, and the first heavily doped region 810 and the second heavily doped region 820 are doped with N-type impurity ions. In other embodiments, the formed LDMOS is of N-type, and the first heavily doped region 810 and the second heavily doped region 820 are doped with P-type impurity ions. The N-type impurity ions are one or more of phosphorus (P) ions, arsenic (As) ions, and antimony (Te) ions; the P-type impurity ions are one or more of boron (B) ions, boron fluoride (BF2) ions, indium (In) ions, and gallium (Ga) ions.

[0065] In the method for forming a semiconductor structure provided in an embodiment of the present application, a gate structure can be formed and the position of the body region can be defined by only one etching, which saves costs and alleviates production capacity pressure; the patterned photoresist layer formed is thin, and its contour is relatively easy to control, thereby improving the uniformity of the device; a body region is formed in the drift region, and the drift region is folded under the body region. Under the same breakdown voltage, the area of ​​the drift region can be greatly reduced, thereby achieving the purpose of reducing the size of the LOMOS; the problem of the electric field peak at the edge of the gate structure near the drain region in the prior art is avoided, the breakdown voltage is further improved, and the TDDB problem is avoided at the same time; the body region, the first deep well region, and the drift region form a Double-RESURF structure, which makes it easier for the device to obtain a larger breakdown voltage and a smaller on-resistance.

[0066] refer to Figure 15The present application also provides a semiconductor structure, comprising: a substrate 100, wherein the substrate 100 includes a drift region 130 and a first isolation structure 141 and a second isolation structure 142 located in the drift region 130; a gate structure 200 located on a surface of a portion of the drift region 130 between the first isolation structure 141 and the second isolation structure 142; a first body region 410 located in the drift region 130 between the gate structure 200 and the first isolation structure 141 and extending to a lower portion of the gate structure 200; and a second body region 420 located in the drift region 130. The first source region 610 and the second source region 620 are located in the drift region 130 between the gate structure 200 and the second isolation structure 142, and extend to the lower part of the gate structure 200; the first source region 610 and the second source region 620 are respectively located in the first body region 410 and the second body region 420 on both sides of the gate structure 200; the first drain region 710 and the second drain region 720 are both located in the drift region 130, wherein the first isolation structure 141 separates the first drain 610 and the first source 710, and the second isolation structure 142 separates the second drain 720 and the second source 620.

[0067] In some embodiments, the substrate 100 further includes a first deep well region 120, the first deep well region 120 being located below the drift region 130, and having a different doping type from the drift region 130. In some embodiments, the substrate 100 further includes a second deep well region 110, and the second deep well region 110 having a different doping type from the first deep well region 120.

[0068] The formed LDMOS is of P-type, with N-type impurity ions doped into the first deep well region 120 and P-type impurity ions doped into the drift region 130. In another embodiment, the formed LDMOS is of N-type, with P-type impurity ions doped into the first deep well region 120 and N-type impurity ions doped into the drift region 130. The N-type impurity ions are one or more of phosphorus ions, arsenic ions, and antimony ions; and the P-type impurity ions are one or more of boron ions, indium ions, and gallium ions.

[0069] In some embodiments, both sidewalls of the gate structure 200 further include sidewall spacers 500. A first heavily doped region 810 is formed between the first source region 610 and the first isolation structure 141, and a second heavily doped region 820 is formed between the second source region 620 and the second isolation structure 142. The first heavily doped region 810 and the second heavily doped region 820 function to connect the first body region 410 and the second body region 420.

[0070] The first heavily doped region 810 and the second heavily doped region 820 have different doping types from the first source region 610 and the second source region 620. In some embodiments, the formed LDMOS is P-type, and the first heavily doped region 810 and the second heavily doped region 820 are doped with N-type impurity ions. In other embodiments, the formed LDMOS is N-type, and the first heavily doped region 810 and the second heavily doped region 820 are doped with P-type impurity ions. The N-type impurity ions are one or more of phosphorus (P), arsenic (As), and antimony (Te); and the P-type impurity ions are one or more of boron (B), boron fluoride (BF2), indium (In), and gallium (Ga).

[0071] In the semiconductor structure of the embodiment of the present application, the body region is located in the drift region, and the drift region is folded under the body region. Under the same breakdown voltage, the area of ​​the drift region can be greatly reduced, thereby achieving the purpose of reducing the size of the LOMOS. By changing the position of the body region, the path of the carriers is changed, thereby avoiding the problem of the electric field peak at the edge of the gate structure near the drain region in the prior art, further improving the breakdown voltage, and avoiding the TDDB problem. In addition to serving as a well region, the body region forms a Double-RESURF structure with the first deep well region and the drift region, making it easier for the LDMOS to obtain a large breakdown voltage and a small on-resistance.

[0072] In summary, after reading the contents of this application, those skilled in the art will understand that the foregoing contents are presented by way of example only and are not intended to be limiting. Although not expressly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. Such changes, improvements, and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0073] It should be understood that the term "and / or" used in this embodiment includes any and all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may be present.

[0074] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" indicates the absence of intervening elements. It should also be understood that the terms "comprising," "including," "include," or "comprising," when used in this specification, indicate the presence of recited features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0075] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the present application, the first element in some embodiments may be referred to as the second element in other embodiments. The same reference numerals or the same reference designators represent the same elements throughout the specification.

[0076] In addition, this specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a drift region and a first isolation structure and a second isolation structure located in the drift region; forming a gate structure on a surface of a portion of the drift region between the first isolation structure and the second isolation structure; An ion implantation process is used to form a first body region in the drift region between the gate structure and the first isolation structure, and a second body region in the drift region between the gate structure and the second isolation structure, wherein both the first body region and the second body region extend to the lower portion of the gate structure. The method comprises: forming a patterned photoresist layer on the surface of the substrate and the gate structure, wherein the patterned photoresist layer exposes a portion of the drift region surface between the gate structure and the first isolation structure and the second isolation structure and completely covers the sidewalls of the gate structure; performing a first ion implantation using the patterned photoresist layer as a mask to form a first ion implantation region; trimming the patterned photoresist layer so that the patterned photoresist layer only covers a portion of the surface of the gate structure; performing a second ion implantation using the patterned photoresist layer as a mask to form a second ion implantation region, wherein the depth of the second ion implantation region is smaller than that of the first ion implantation region; and performing a heat treatment so that the first body region and the second body region extend to the lower portion of the gate structure. forming a first source region and a second source region in the first body region and the second body region on both sides of the gate structure respectively; and A first drain region and a second drain region are formed in the drift region, wherein the first isolation structure separates the first drain region and the first source region, and the second isolation structure separates the second drain region and the second source region.

2. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming a gate structure on a surface of a portion of the drift region between the first isolation structure and the second isolation structure includes: sequentially depositing a gate dielectric layer and a gate electrode layer on the surfaces of the first isolation structure, the second isolation structure and the drift region; The gate dielectric layer and the gate electrode layer on the surfaces of the first isolation structure and the second isolation structure and on the surface of a portion of the drift region between the first isolation structure and the second isolation structure are etched to form a gate structure.

3. The method for forming a semiconductor structure according to claim 1, wherein: Before forming the first source region and the second source region, the method further includes: forming a sidewall spacer on the sidewall of the gate structure.

4. The method for forming a semiconductor structure according to claim 1, wherein: The first source region, the second source region, the first drain region and the second drain region are formed by a source-drain ion implantation process.

5. The method for forming a semiconductor structure according to claim 1, wherein: After forming the first drain region and the second drain region, it also includes: forming a first heavily doped region between the first source region and the first isolation structure, and forming a second heavily doped region between the second source region and the second isolation structure, wherein the first heavily doped region and the second heavily doped region have different doping types from the first source region and the second source region.

6. The method for forming a semiconductor structure according to claim 5, wherein: The first heavily doped region and the second heavily doped region are formed by an ion implantation process.

7. The method for forming a semiconductor structure according to claim 1, wherein: The substrate further includes a first deep well region, which is located below the drift region. The first deep well region and the drift region have different doping types.

8. The method for forming a semiconductor structure according to claim 7, wherein: The substrate further includes a second deep well region, and the second deep well region has a different doping type from the first deep well region.

9. A semiconductor structure, characterized in that Formed by any one of the methods of claims 1 to 8, comprising: a substrate comprising a drift region and a first isolation structure and a second isolation structure located in the drift region; a gate structure located on a surface of a portion of the drift region between the first isolation structure and the second isolation structure; a first body region located in a drift region between the gate structure and the first isolation structure and extending to a lower portion of the gate structure; a second body region located in the drift region between the gate structure and the second isolation structure and extending to a lower portion of the gate structure; A first source region and a second source region are respectively located in the first body region and the second body region on both sides of the gate structure; The first drain region and the second drain region are both located in the drift region, wherein the first isolation structure separates the first drain region and the first source region, and the second isolation structure separates the second drain region and the second source region.

10. The semiconductor structure according to claim 9, wherein: The substrate further includes a first deep well region, which is located below the drift region. The first deep well region and the drift region have different doping types.

11. The semiconductor structure according to claim 10, wherein: The substrate further includes a second deep well region, and the second deep well region has a different doping type from the first deep well region.

12. The semiconductor structure according to claim 9, wherein: Both side walls of the gate structure further include sidewalls.

13. The semiconductor structure according to claim 9, wherein: Also includes: a first heavily doped region, located between the first source region and the first isolation structure; a second heavily doped region, located between the second source region and the second isolation structure; The first heavily doped region and the second heavily doped region have different doping types from the first source region and the second source region.

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