Electronic packaging component and manufacturing method thereof

Abstract

The present invention relates to an electronic package and a manufacturing method thereof, including disposing a second electronic component and a third electronic component on a first electronic component serving as a carrier structure, so that there is no need to match the wiring dimensions of the existing packaging substrate. Therefore, the first electronic component can be designed as a system-on-chip with a smaller size to improve the process yield.

Description

Technical Field

[0001] The present invention relates to a semiconductor chip packaging technology, and more particularly to an electronic package and a manufacturing method thereof that can improve the yield rate. Background Art

[0002] With the vigorous development of the electronics industry, electronic products are gradually moving towards the trend of multi-function and high performance. Currently, the technologies applied in the field of chip packaging include flip-chip type packaging modules such as Chip Scale Package (CSP), Direct Chip Attached (DCA), or Multi-Chip Module (MCM), or 3D integrated circuit (3D IC) chip stacking technology that integrates chips in a three-dimensional stack.

[0003] Figure 1 FIG. 12 is a cross-sectional schematic view of an existing 3D chip stacking package structure 1. As Figure 1 shown, the package structure 1 includes a Through Silicon Interposer (TSI) 1a, which has a silicon plate body 10 and a plurality of Through-Silicon Vias (TSVs) 101 formed therein, and a Redistribution layer (RDL) for electrically connecting the TSVs 101 is formed on the surface of the silicon plate body 10. Specifically, the redistribution layer includes a dielectric layer 11 and a circuit layer 12 formed on the dielectric layer 11. The circuit layer 12 is electrically connected to the TSVs 101, and an insulating protective layer 13 is formed on the dielectric layer 11 and the circuit layer 12, and the exposed part of the insulating protective layer 13 is the circuit layer 12 to bond a plurality of first conductive elements 14 such as solder bumps.

[0004] In addition, another insulating protective layer 15 can be formed on the silicon plate body 10, and the end faces of the TSVs 101 are exposed by the insulating protective layer 15 to bond a plurality of second conductive elements 16 on the end faces of the TSVs 101. The second conductive element 16 is electrically connected to the TSV 101. Among them, the second conductive element 16 contains a solder material or a copper bump, and an Under Bump Metallurgy (UBM) 160 for placing the second conductive element 16 can be selectively formed on the end face of the TSV 101.

[0005] In addition, the packaging structure 1 further includes a packaging substrate 19, on which the silicon interposer 1a is disposed via the second conductive elements 16, such that the packaging substrate 19 is electrically connected to the conductive silicon vias 101, and the second conductive elements 16 are coated with an underfill 191.

[0006] In addition, the packaging structure 1 further includes a plurality of semiconductor chips 17, which are disposed on the first conductive elements 14, such that the semiconductor chips 17 are electrically connected to the circuit layer 12. Among them, the semiconductor chips 17 are bonded to the first conductive elements 14 in a flip-chip manner, and the first conductive elements 14 are coated with an underfill 171, and a packaging material 18 is formed on the packaging substrate 19 to cover the semiconductor chips 17 and the silicon interposer 1a with the packaging material 18.

[0007] In subsequent applications, a plurality of solder balls 192 can be formed on the lower side of the packaging substrate 19 to be placed on an electronic device (not shown) such as a circuit board.

[0008] However, the electro-functional capabilities of current end products are becoming more and more advanced. Therefore, more and more electronic components (such as semiconductor chips 17) are placed on the silicon interposer 1a, which increases the bonding area of the silicon interposer 1a. As a result, the number of conductive silicon vias 101 to be arranged also increases. However, it is difficult to fabricate a large number of conductive silicon vias 101 in the manufacturing process, resulting in a decrease in the yield of the packaging structure 1.

[0009] In addition, if semiconductor components, such as a system-on-chip (SoC), are configured on the packaging substrate 19 to replace the silicon interposer 1a, the semiconductor components need to be designed as large-sized system-on-chips according to the wiring dimensions of the packaging substrate 19. Therefore, a photomask with a scale factor greater than 1X (1X reticle) needs to be used for manufacturing, resulting in a decrease in the wafer yield (such as 20-30%). Moreover, based on the requirement of stable power supply, more passive components (such as variable resistors) need to be configured on the packaging substrate 19, which leads to an increase in the area of the packaging substrate 19, making it difficult to meet the miniaturization requirement.

[0010] Therefore, how to overcome the various problems of the above-mentioned prior art has actually become an urgent issue to be solved currently. Summary of the Invention

[0011] In view of the various defects of the above-mentioned prior art, the present invention provides an electronic package to improve the manufacturing yield.

[0012] The electronic package of the present invention includes: a first electronic component having an active surface and electrode pads provided on the active surface; a second electronic component provided on the active surface of the first electronic component and having opposite first and second sides and a plurality of conductive vias connecting the first side and the second side, so that the second electronic component is joined to the active surface with its first side, and the plurality of conductive vias are electrically connected to the electrode pads; and a third electronic component provided on the active surface of the first electronic component and electrically connected to the electrode pads.

[0013] The present invention also provides a method for manufacturing an electronic package, including: providing a first electronic component having an active surface and electrode pads provided on the active surface; disposing a second electronic component on the active surface of the first electronic component, wherein the second electronic component has opposite first and second sides and a plurality of conductive vias connecting the first side and the second side, so that the second electronic component is joined to the active surface with its first side, and the plurality of conductive vias are electrically connected to the electrode pads; and disposing a third electronic component on the active surface of the first electronic component, and electrically connecting the third electronic component to the electrode pads.

[0014] In the foregoing electronic package and its manufacturing method, the first electronic component joins the second electronic component and the third electronic component via a conductor.

[0015] In the foregoing electronic package and its manufacturing method, a plurality of the third electronic components stacked on each other are arranged on the active surface of the first electronic component.

[0016] In the foregoing electronic package and its manufacturing method, a plurality of conductive vias are formed inside the third electronic component.

[0017] In the foregoing electronic package and its manufacturing method, the first electronic component is an active component.

[0018] In the foregoing electronic package and its manufacturing method, the second electronic component and / or the third electronic component is a passive component.

[0019] In the foregoing electronic package and its manufacturing method, a circuit structure is further formed on the second side of the second electronic component. For example, the circuit structure is also formed on the third electronic component. Further, a conductive component is formed on the circuit structure.

[0020] In the foregoing electronic package and its manufacturing method, a packaging layer is further formed on the active surface to cover the second electronic component and the third electronic component.

[0021] As can be seen from the above, in the electronic package and its manufacturing method of the present invention, mainly by using the first electronic component as a carrier structure, passive components (such as the second electronic component or the third electronic component) with fine circuits and fine-pitch semiconductor materials are arranged thereon. Therefore, there is no need to match the wiring size of the existing packaging substrate. Thus, the first electronic component can be designed as a smaller system-on-chip to improve the process yield.

[0022] In addition, through the design of the conductors of the first electronic component, after bonding the passive components of these semiconductor materials, not only can the power supply stability be improved, but also high power can be provided. Even at high current, better Cu migration can be generated.

[0023] In addition, the required passive components can be arranged on the first electronic component 21 as needed, so that the number of conductive vias can be designed as needed, and the number of conductive vias of a single passive component can be greatly reduced, making it easy to fabricate the conductive vias in the process. Therefore, it is beneficial to improve the yield of the electronic package.

[0024] In addition, by using the first electronic component as a carrier structure to stack the required passive components of semiconductor materials thereon, there is no need to use the existing packaging substrate. Therefore, compared with the prior art, the electronic package 2 of the present invention is beneficial to the design requirements of miniaturization and thinning. Description of the Drawings

[0025] Figure 1 It is a cross-sectional schematic view of an existing packaging structure.

[0026] Figures 2A to 2D It is a cross-sectional schematic view of the first embodiment of the manufacturing method of the electronic package of the present invention.

[0027] Figures 3A to 3D It is a cross-sectional schematic view of the second embodiment of the manufacturing method of the electronic package of the present invention.

[0028] Description of the Reference Numerals

[0029] 1: Packaging structure

[0030] 1a: Silicon interposer

[0031] 10: Silicon plate body

[0032] 101: Conductive silicon via

[0033] 11: Dielectric layer

[0034] 12: Circuit layer

[0035] 13, 15: Insulating protective layer

[0036] 14: First conductive element

[0037] 16: Second conductive element

[0038] 160: Metal layer under bump

[0039] 17: Semiconductor chip

[0040] 171, 191: Underfill

[0041] 18: Encapsulant

[0042] 19: Package substrate

[0043] 192: Solder ball

[0044] 2, 3: Electronic package

[0045] 20: Support plate

[0046] 21: First electronic component

[0047] 21a: Active surface

[0048] 21b: Non-active surface

[0049] 210: Electrode pad

[0050] 211: Conductor

[0051] 22: Second electronic component

[0052] 22a: First side

[0053] 22b: Second side

[0054] 220, 230: Conductive via

[0055] 23, 33: Electronic assembly

[0056] 23a, 23b, 23c, 33a, 33b: Third electronic component

[0057] 231: Conductive material

[0058] 24: Coating layer

[0059] 26, 36: Circuit structure

[0060] 260: Insulating layer

[0061] 261: Circuit redistribution layer

[0062] 27: Conductive element

[0063] 35: Encapsulation layer

[0064] 35a: First surface

[0065] 35b: Second surface

[0066] H: Height

[0067] H1,H2: Total height

[0068] P1, P2: height position

[0069] S: Accommodation space. DETAILED DESCRIPTION

[0070] The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0071] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions under which the present invention can be implemented, so they have no substantial technical significance. Any structural modification, change in proportional relationship, or adjustment in size should still fall within the scope of the technical contents disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "on", "first", "second", and "one" cited in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical contents.

[0072] Figures 2A to 2D It is a cross-sectional schematic diagram of a first embodiment of a method for manufacturing an electronic package 2 of the present invention.

[0073] like Figure 2A As shown, a first electronic component 21 is provided on a support plate 20 , so that the first electronic component 21 serves as a supporting structure of the electronic package 2 .

[0074] In this embodiment, the first electronic component 21 is an active component of a semiconductor material, such as a system on a chip (SoC), and its active surface 21a has a plurality of electrode pads 210, and a plurality of conductors 211 are formed on the electrode pads 210. For example, the conductors 211 are in the shape of bumps, which include metal pillars of solder material or copper or other appropriate structures, or such as metal blocks coated with insulating blocks, or solder balls with core copper balls (Cu core balls), etc., without special limitation.

[0075] In addition, an insulating material (not shown in the figure) covering the conductors 211 may be formed on the functional surface 21a of the first electronic component 21 as required. The insulating material is a non-conductive film (Non-conductive Film, abbreviated as NCF), such as anisotropic conductive paste (Anisotropic conductive past, abbreviated as ACP), anisotropic conductive film (Anisotropic Conductive Film, abbreviated as ACF), or other structures.

[0076] In addition, the support plate 20 is, for example, a circular plate made of a semiconductor material (such as silicon or glass). Its size can be a wafer form substrate or a general full-panel form substrate according to requirements. An anti-adhesive layer (not shown in the figure) and an adhesive layer (not shown in the figure) can be sequentially formed on the support plate 20 by coating as required, so that the first electronic component 21 is disposed on the adhesive layer with its non-functional surface 21b opposite to the functional surface 21a.

[0077] As Figure 2B shown, at least one second electronic component 22 is disposed on the functional surface 21a of the first electronic component 21. The second electronic component 22 has opposite first side 22a and second side 22b, so that the second electronic component 22 is electrically connected to the first electronic component 21 through the conductors 211 with its first side 22a, and a circuit structure 26 electrically connected to the second electronic component 22 is formed on the second side 22b of the second electronic component 22.

[0078] In this embodiment, the second electronic component 22 is a passive component made of semiconductor material, such as a variable resistor (Variable Resistor, abbreviated as VR). At least one conductive via 220 connecting the first side 22a and the second side 22b, such as a through-silicon via (Through-silicon via, abbreviated as TSV), is configured inside the second electronic component 22 to electrically connect the circuit structure 26. It should be understood that there are many embodiments of the conductive via 220, such as having a pad at the end, and there is no particular limitation.

[0079] In addition, the circuit structure 26 has at least one insulating layer 260 and a redistribution layer (RDL) 261 disposed in the insulating layer 260, and the outermost insulating layer 260 can serve as a solder mask layer to expose the outermost redistribution layer 261 to the solder mask layer. Alternatively, the circuit structure 26 may also include only a single insulating layer 260 and a single redistribution layer 261. For example, the material forming the redistribution layer 261 is copper, and the material forming the insulating layer 260 is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), or others.

[0080] In addition, the circuit structure 26 contacts the second side 22b of the second electronic component 22 with its insulating layer 260 and electrically connects the conductive vias 220 of the second electronic component 22 with its redistribution layer 261.

[0081] In addition, a plurality of the second electronic components 22 are spaced apart and disposed on the working surface 21a of the first electronic component 21 to form at least one accommodating space S between the second electronic components 22.

[0082] As Figure 2C shown, at least one third electronic component 23a is disposed on the working surface 21a of the first electronic component 21 in the accommodating space S to enable the third electronic component 23a to be electrically connected to the first electronic component 21 via the conductors 211.

[0083] In this embodiment, the third electronic component 23a is a passive component made of semiconductor material, such as an integrated passive device (IPD). For example, a plurality of third electronic components 23a, 23b, 23c can be electrically stacked as required to form an electronic assembly 23, wherein the total height H1 of the electronic assembly 23 relative to the working surface 21a can be adjusted as required, such as being higher than (or lower than or equal to) the total height H2 of the second electronic component 22 and the circuit structure 26 relative to the working surface 21a.

[0084] In addition, at least one through-conductive via 230, such as a through-silicon via (TSV), may be disposed inside each of the third electronic components 23a, 23b, 23c to electrically connect the conductor 211 and each of the third electronic components 23a, 23b, 23c. For example, each of the third electronic components 23a, 23b, 23c may be electrically connected to each other via a conductive material 231, and the conductive material 231 is in a bump shape, which includes a solder material, a metal pillar of copper, or other suitable structures, or a metal block coated with an insulating block, or a solder ball having a core copper ball (Cu core ball), etc., without particular limitation.

[0085] In addition, a coating layer 24 such as an underfill may be formed as needed between the working surface 21a of the first electronic component 21 and the first side 22a of the second electronic component 22 and / or between the working surface 21a of the first electronic component 21 and the third electronic component 23a.

[0086] As Figure 2D As shown, the support plate 20 is removed, and a plurality of conductive components 27 are formed on the circuit structure 26 to electrically connect the conductive components 27 to the circuit redistribution layer 261, so that the electronic package 2 can be externally connected to an electronic device such as a circuit board (not shown) via the conductive components 27.

[0087] In this embodiment, the conductive component 27 is a bump or a sphere, which includes a solder material, a metal pillar of copper, or other suitable structures, or a metal block coated with an insulating block, or a solder ball having a core copper ball (Cu core ball), etc., without particular limitation.

[0088] In addition, the height position P2 of the conductive component 27 relative to the working surface 21a of the first electronic component 21 is higher than the height position P1 of the electronic component 23 relative to the working surface 21a of the first electronic component 21, so as to facilitate the external connection of the conductive components 27 to an electronic device.

[0089] Therefore, in the manufacturing method of the present invention, the first electronic component 21 is used as a carrier structure, and passive components such as fine circuits and semiconductor materials with fine pitches (such as the second electronic component 22 or the third electronic components 23a, 23b, 23c) are disposed thereon. Therefore, there is no need to match the wiring dimensions of the existing packaging substrate, so the first electronic component 21 can be designed as a smaller system-on-chip (SoC) to improve the manufacturing yield.

[0090] In addition, through the design of the conductor 211 of the first electronic component 21, after bonding passive components of these semiconductor materials (such as the second electronic component 22 or the third electronic components 23a, 23b, 23c), not only can the power supply stability be improved, but also high power can be provided. Even under high current, better Cu migration can be generated.

[0091] In addition, required passive components (such as the second electronic component 22 or the third electronic components 23a, 23b, 23c) can be arranged on the first electronic component 21 as needed, so that the number of conductive vias 220, 230 can be designed as needed, and the number of conductive vias 220, 230 of a single passive component can be greatly reduced, making it easy to fabricate the conductive vias 220, 230 in the manufacturing process. Therefore, it is beneficial to improve the yield of the electronic package 2.

[0092] In addition, the first electronic component 21 is used as a carrier structure to stack required passive components of semiconductor materials (such as the second electronic component 22 or the third electronic components 23a, 23b, 23c) thereon. Therefore, there is no need to use an existing packaging substrate. Therefore, compared with the prior art, the electronic package 2 of the present invention is beneficial to miniaturization and thinning design.

[0093] Figures 3A to 3D It is a schematic cross-sectional view of the second embodiment of the manufacturing method of the electronic package 3 of the present invention. The difference between this embodiment and the first embodiment lies in the manufacturing steps of the circuit structure, and other manufacturing processes are roughly the same. Therefore, the same parts will not be described in detail below.

[0094] As Figure 3A shown, following the manufacturing process shown, at least one second electronic component 22 and a plurality of third electronic components 33a, 33b are arranged on the functional surface 21a of the first electronic component 21. Figure 2A

[0095] In this embodiment, no circuit structure is formed on the second side 22b of the second electronic component 22, and the plurality of third electronic components 33a, 33b are passive components of semiconductor materials without conductive vias 230.

[0096] In addition, the height H of the electronic component 33 (including two third electronic components 23a, 23b) relative to the functional surface 21a is equal to (or lower than) the height H of the second electronic component 22 relative to the functional surface 21a.

[0097] Figure 3B As Figure 3BAs shown, an encapsulation layer 35 is formed on the first electronic component 21 to cause the encapsulation layer 35 to cover the second electronic component 22 and the electronic assembly 33. Among them, the encapsulation layer 35 has opposite first surface 35a and second surface 35b, and its first surface 35a is bonded to the working surface 21a. Then, through a planarization process, the second surface 35b of the encapsulation layer 35 is made flush with the second side 22b of the second electronic component 22 (even flush with the upper surface of the electronic assembly 33), so that the second side 22b of the second electronic component 22 (even the electronic assembly 33) is exposed on the second surface 35b of the encapsulation layer 35.

[0098] In this embodiment, the encapsulation layer 35 is an insulating material, such as an encapsulation colloid of epoxy resin, which can be formed on the first electronic component 21 by lamination or molding.

[0099] In addition, through the grinding method in the planarization process, part of the material of the encapsulation layer 35 is removed, and even part of the material of the second side 22b of the second electronic component 22 (or the electronic assembly 33) is removed.

[0100] As Figure 3C shown, a circuit structure 36 is formed on the second surface 35b of the encapsulation layer 35, and the circuit structure 36 is electrically connected to the conductive vias 220 of the second electronic component 22 (or the electronic assembly 33).

[0101] In this embodiment, the circuit structure 36 is also formed on the third electronic components 33a, 33b to be electrically connected to the third electronic component 33b.

[0102] As Figure 3D shown, the support plate 20 is removed, and a plurality of conductive elements 27 are formed on the circuit structure 36 to cause the conductive elements 27 to be electrically connected to the circuit structure 36, so that the electronic package 3 is externally connected to an electronic device such as a circuit board (not shown) through the conductive elements 27.

[0103] Therefore, in the manufacturing method of the present invention, the first electronic component 21 is used as a carrier structure, and passive components of semiconductor materials with fine circuits and fine pitches (such as the second electronic component 22 or the third electronic components 33a, 33b) are arranged thereon. Therefore, there is no need to match the wiring dimensions of the existing encapsulation substrate. Therefore, the first electronic component 21 can be designed as a smaller system-on-chip (System on Chip) to improve the manufacturing yield.

[0104] In addition, through the design of the conductor 211 of the first electronic component 21, after bonding passive components of these semiconductor materials (such as the second electronic component 22 or the third electronic components 33a, 33b), not only can the power supply stability be improved, but also high power can be provided. Even under high current, better Cu migration can be generated.

[0105] In addition, passive components (such as the second electronic component 22 or the third electronic components 33a, 33b) required can be arranged on the first electronic component 21 as needed, so that the number of conductive vias 220 arranged can be designed as needed, and the number of conductive vias 220 of a single passive component can be greatly reduced, making it easy to fabricate the conductive vias 220 in the process. Therefore, it is beneficial to improve the yield of the electronic package 3.

[0106] In addition, the first electronic component 21 is used as a carrier structure to stack passive components of semiconductor materials (such as the second electronic component 22 or the third electronic components 33a, 33b) required thereon. Therefore, there is no need to use an existing packaging substrate. Therefore, compared with the prior art, the electronic package 3 of the present invention is beneficial to miniaturization and thinning design.

[0107] The present invention also provides an electronic package 2, 3, including: a first electronic component 21, a second electronic component 22, and third electronic components 23a, 23b, 23c, 33a, 33b.

[0108] The first electronic component 21 has an active surface 21a and electrode pads 210 provided on the active surface 21a.

[0109] The second electronic component 22 is provided on the active surface 21a of the first electronic component 21 and has opposite first side 22a and second side 22b and a plurality of conductive vias 220 connecting the first side 22a and the second side 22b, so that the second electronic component 22 is bonded to the active surface 21a with its first side 22a, and the plurality of conductive vias 220 are electrically connected to the electrode pads 210.

[0110] The third electronic components 23a, 23b, 23c, 33a, 33b are provided on the active surface 21a of the first electronic component 21 and are electrically connected to the electrode pads 210.

[0111] In one embodiment, the first electronic component 21 bonds the second electronic component 22 and the third electronic components 23a, 23b, 23c, 33a, 33b through a conductor 211.

[0112] In one embodiment, a plurality of the third electronic components 23a, 23b, 23c, 33a, 33b stacked on each other are disposed on the functional surface 21a of the first electronic component 21.

[0113] In one embodiment, a plurality of conductive vias 230 are formed inside the third electronic components 23a, 23b, 23c.

[0114] In one embodiment, the first electronic component 21 is an active component.

[0115] In one embodiment, the second electronic component 22 and / or the third electronic components 23a, 23b, 23c, 33a, 33b are passive components.

[0116] In one embodiment, the electronic packages 2, 3 further include a circuit structure 26, 36 formed on a second side 22b of the second electronic component 22. For example, the circuit structure 36 is further formed on the third electronic components 33a, 33b. Further, the electronic packages 2, 3 further include a plurality of conductive components 27 formed on the circuit structure 26, 36.

[0117] In one embodiment, the electronic package 3 further includes a packaging layer 35 formed on the functional surface 21a to cover the second electronic component 22 and the third electronic components 33a, 33b.

[0118] In summary, for the electronic package and its manufacturing method of the present invention, by using the first electronic component as a carrier structure and disposing passive components of semiconductor materials with fine circuits and fine pitches thereon, there is no need to match the wiring dimensions of the existing packaging substrate. Therefore, the first electronic component can be designed as a smaller system-on-chip to improve the process yield.

[0119] In addition, through the design of the conductors of the first electronic component, after bonding the passive components of the semiconductor materials, not only can the power supply stability be improved, but also high power can be provided. Even under a large current, better copper migration can be generated.

[0120] Moreover, on the first electronic component, the required passive components can be disposed as needed, so that the number of the conductive vias arranged can be designed as needed, and the number of the conductive vias of a single passive component can be greatly reduced, making it easy to fabricate the conductive vias in the process. Therefore, it is beneficial to improve the yield of the electronic package.

[0121] In addition, by using the first electronic component as a carrier structure and stacking the required passive components of semiconductor materials thereon, there is no need to use the existing packaging substrate. Therefore, the electronic package of the present invention is beneficial to the design of miniaturization and thinning.

[0122] The above embodiments are only used to illustrate the principles and effects of the present invention by way of example, rather than to limit the present invention. Any person skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the protection of the rights of the present invention shall be as set forth in the claims.

Claims

1. An electronic package, characterized in that, Comprising: A first electronic component having an active surface and electrode pads provided on the active surface; A second electronic component disposed on the active surface of the first electronic component and having opposite first and second sides and a plurality of conductive vias connecting the first and second sides, so that the second electronic component engages the active surface with its first side, and the plurality of conductive vias of the second electronic component are electrically connected to the electrode pads on the active surface of the first electronic component; And A plurality of third electronic components stacked on the active surface of the first electronic component, the plurality of third electronic components being electrically connected to each other via a conductive material, and the plurality of third electronic components electrically connected by the conductive material being electrically connected to the electrode pads on the active surface of the first electronic component.

2. The electronic package according to claim 1, wherein The first electronic component joins the second and third electronic components via a conductor.

3. The electronic package according to claim 1, wherein A plurality of conductive vias are formed inside the third electronic component.

4. The electronic package according to claim 1, characterized in that, The first electronic component is an active component.

5. The electronic package according to claim 1, characterized in that, The second electronic component and / or the third electronic component is a passive component.

6. The electronic package according to claim 1, wherein The electronic package further includes a circuit structure formed on the second side of the second electronic component.

7. The electronic package according to claim 6, characterized in that, The circuit structure is also formed on the third electronic component.

8. The electronic package according to claim 6 or 7, characterized in that, The electronic package further includes a conductive component formed on the circuit structure.

9. The electronic package according to claim 1, wherein, The electronic package further includes a packaging layer formed on the active surface to cover the second and third electronic components.

10. A method for manufacturing an electronic package, characterized in that, Comprising: Providing a first electronic component having an active surface and electrode pads provided on the active surface; Disposing a second electronic component on the active surface of the first electronic component, wherein the second electronic component has opposite first and second sides and a plurality of conductive vias connecting the first and second sides, so that the second electronic component engages the active surface with its first side, and the plurality of conductive vias of the second electronic component are electrically connected to the electrode pads on the active surface of the first electronic component; and Stacking a plurality of third electronic components on the active surface of the first electronic component, wherein the plurality of third electronic components are electrically connected to each other via a conductive material, and the plurality of third electronic components electrically connected by the conductive material are electrically connected to the electrode pads on the active surface of the first electronic component.

11. The method for manufacturing an electronic package as described in claim 10, wherein, The first electronic component joins the second and third electronic components via a conductor.

12. The method for manufacturing an electronic package according to claim 10, wherein, A plurality of conductive vias are formed inside the third electronic component.

13. The method for manufacturing an electronic package according to claim 10, wherein, The first electronic component is an active component.

14. The method for manufacturing an electronic package according to claim 10, wherein, The second electronic component and / or the third electronic component is a passive component.

15. The method for manufacturing an electronic package according to claim 10, characterized in that, The manufacturing method further includes forming a circuit structure on the second side of the second electronic component.

16. The method for manufacturing an electronic package according to claim 15, wherein, The circuit structure is also formed on the third electronic component.

17. The method for manufacturing an electronic package according to claim 15 or 16, characterized in that, The manufacturing method further includes forming a conductive component on the circuit structure.

18. The method for manufacturing an electronic package according to claim 10, characterized in that, The manufacturing method further includes forming a packaging layer on the active surface to cover the second and third electronic components.

Images