Method of manufacturing a flash memory device

Abstract

The application provides a preparation method of a flash memory device, comprising the following steps: providing a substrate with a stacked floating gate layer, an ONO layer and a control gate layer formed thereon, the substrate is provided with a groove, and the groove is provided with a side wall structure; forming a conductive contact layer by using a self-aligned silicide process; performing selective etching on the side wall structure by using an SPT process; and forming an interlayer insulating medium layer. The application performs selective etching on the side wall structure by using an SPT (stress proximity technique) process. Since the etching selectivity of the SPT process on some material layers (silicon nitride layers) is high, the filling of the interlayer insulating medium layer in the groove is improved by performing targeted thinning on some material layers in the side wall structure after the formation of the conductive contact layer (self-aligned silicide process), so that the filling of the interlayer insulating medium layer can be improved without affecting the electrical performance of the device, the void defects are avoided, and the device yield is further improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor device manufacturing technology, and specifically to a method for preparing a flash memory device. Background Technology

[0002] Some of the cell regions of flash memory devices have polysilicon layers (such as floating gate polysilicon, control gate polysilicon, word line polysilicon, select gate polysilicon, etc.). For example, in Nor Flash devices, two polysilicon layers are stacked; in NORD Flash devices, four polysilicon layers are stacked. All of these devices exhibit a relatively high height of the stacked polysilicon material in the Y-axis direction.

[0003] Flash device nodes are continuously shrinking with technological advancements, but the reduction in critical dimensions of polysilicon films along the Y-axis has been relatively minor. This presents a significant challenge in filling the large aspect ratio trenches within the polysilicon film with an ILD (Interlayer Insulating Diode). The large aspect ratio of the trenches makes it easy for voids to form within the ILD. Voids in the ILD can cause a series of problems in flash memory devices. For example, voids can cause metal from subsequently deposited metal films to penetrate into the voids, leading to short circuits and even mass scrapping of flash memory devices. Summary of the Invention

[0004] This application provides a method for fabricating a flash memory device, which can solve the problem of void defects generated when filling ILDs in trenches with a large aspect ratio.

[0005] On one hand, embodiments of this application provide a method for fabricating a flash memory device, including:

[0006] A substrate is provided on which stacked floating gate layers, ONO layers and control gate layers are formed, wherein trenches are formed in the control gate layers, the ONO layers and the floating gate layers, and sidewall structures are formed in the trenches, the sidewall structures covering the sidewalls and part of the bottom wall of the trenches;

[0007] A conductive contact layer is formed using a self-aligned silicide process, the conductive contact layer covering the control gate layer and the substrate exposed at the bottom wall of the trench;

[0008] The sidewall structure was selectively etched using the SPT process; and,

[0009] An interlayer insulating dielectric layer is formed, which fills the trench.

[0010] Optionally, in the method for fabricating the flash memory device, the sidewall structure includes a silicon oxide layer and a silicon nitride layer, wherein the silicon oxide layer covers the sidewalls and part of the bottom wall of the trench, and the silicon nitride layer covers the silicon oxide layer.

[0011] Optionally, in the method for fabricating the flash memory device, during the selective etching of the sidewall structure using the SPT process, the ratio of the etching rate of the silicon nitride layer to the etching rate of the silicon oxide layer is 8 to 10; and the ratio of the etching rate of the silicon nitride layer to the etching rate of the control gate layer is 5 to 8.

[0012] Optionally, in the method for fabricating the flash memory device, selective etching of the sidewall structure using the SPT process includes:

[0013] The process involves etching away a certain length of the silicon nitride layer at the top of the sidewall of the trench to make the opening at the top of the trench shaped like an inverted V; etching away a certain length of the silicon nitride layer near the center of the trench on the bottom wall to make the opening at the bottom wall of the trench shaped like an inverted V; etching away a portion of the thickness of the silicon nitride layer on the remaining sidewall of the trench away from the top; and etching away a portion of the thickness of the silicon nitride layer on a portion of the bottom wall of the trench.

[0014] Optionally, in the method for fabricating the flash memory device, the length of the silicon nitride layer etched away from the top of the trench sidewall is 20 nm to 30 nm.

[0015] Optionally, in the method for fabricating the flash memory device, the length of the silicon nitride layer near the center of the trench on the bottom wall of the trench that is etched away is 2 nm to 5 nm.

[0016] Optionally, in the method for fabricating the flash memory device, the thickness of the silicon nitride layer on the remaining sidewalls of the trench away from the top, after being etched away, is [thickness missing]. The thickness of the silicon nitride layer, which is a portion of the bottom wall of the trench, is etched away.

[0017] Optionally, in the method for fabricating the flash memory device, the remaining thickness of the silicon nitride layer on the remaining sidewalls of the trench away from the top is [missing information]. The remaining thickness of the silicon nitride layer on a portion of the bottom wall of the trench is [thickness value missing].

[0018] Optionally, in the method for fabricating the flash memory device, the aspect ratio of the trench is 2 to 5.

[0019] Optionally, in the method for fabricating the flash memory device, after selectively etching the sidewall structure using the SPT process and before forming the interlayer insulating dielectric layer, the method further includes:

[0020] A buffer layer is formed, which covers the sidewall structure and the conductive contact layer, and the interlayer insulating dielectric layer covers the buffer layer.

[0021] The technical solution of this application has at least the following advantages:

[0022] This application employs SPT (Stress Proximity Technique) to selectively etch the sidewall structure. Because SPT has a high selectivity for certain material layers (silicon nitride layers), it allows for targeted thinning of certain material layers in the sidewall structure after the formation of the conductive contact layer (self-aligned silicide process) to improve the filling of the interlayer insulating dielectric layer in the trenches. Furthermore, by selectively etching the sidewall structure using SPT after the formation of the conductive contact layer, all ion implantation of the devices is complete. The selective etching process of SPT avoids accidental etching of other insensitive material layers in the device, thus not affecting device performance. This improves the filling of the interlayer insulating dielectric layer without affecting the device's electrical performance, avoiding void defects. This prevents metal from subsequently depositing metal films from drilling into void defects and causing short circuits, ensuring device reliability and improving device yield.

[0023] Furthermore, the SPT process used in this application selectively thins certain material layers (silicon nitride layers) in the sidewall structure without reducing the short-channel characteristics of the device. The self-aligned silicide (conductive contact layer) can maintain a certain distance from the channel, thereby avoiding the situation where the self-aligned silicide is connected to the channel and ensuring the safety of the device. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0025] Figure 1 This is a flowchart of a method for fabricating a flash memory device according to an embodiment of the present invention;

[0026] Figures 2-6 This is a schematic diagram of the semiconductor structure in each process step of fabricating a flash memory device according to an embodiment of the present invention;

[0027] The reference numerals in the attached figures are explained as follows:

[0028] 100-Substrate, 101-Base, 102-Deep N-type well region, 103-High voltage P-type well region, 104-Source / drain region, 105-Lightly doped drain region, 110-Pad oxide layer, 120-Floating gate layer, 130-ONO layer, 140-Control gate layer, 150-Sidewall structure, 151-Silicon oxide layer, 152-Silicon nitride layer, 153-Silicon oxide layer, 160-Conductive contact layer, 170-Interlayer insulating dielectric layer, 200-Trench. Detailed Implementation

[0029] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0030] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0031] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0032] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0033] This application provides a method for fabricating a flash memory device, referring to... Figure 1 , Figure 1 This is a flowchart of a method for fabricating a flash memory device according to an embodiment of the present invention, including:

[0034] S10: A substrate is provided, on which stacked floating gate layers, ONO layers and control gate layers are formed, wherein trenches are formed in the control gate layers, the ONO layers and the floating gate layers, and sidewall structures are formed in the trenches, the sidewall structures covering the sidewalls and part of the bottom wall of the trenches;

[0035] S20: A conductive contact layer is formed using a self-aligned silicide process, the conductive contact layer covering the control gate layer and the substrate exposed at the bottom wall of the trench;

[0036] S30: Selective etching of the sidewall structure is performed using the SPT process;

[0037] S40: Form an interlayer insulating dielectric layer, which fills the trench.

[0038] For details, please refer to Figures 2-6 , Figures 2-6 This is a schematic diagram of the semiconductor structure in each process step of fabricating a flash memory device according to an embodiment of the present invention.

[0039] First, such as Figure 3 As shown, a substrate 100 is provided, on which stacked pad oxide layer 110, floating gate layer 120, ONO layer 130, and control gate layer 140 are formed. Trench 200 is formed in the control gate layer 140, ONO layer 130, floating gate layer 120, and pad oxide layer 110. Sidewall structures 150 are formed in the trench 200, covering the sidewalls and part of the bottom wall of the trench 200. Specifically, the substrate 100 can be a silicon substrate. The aspect ratio of the trench 200 can be 2 to 5. In the substrate 100, at least one ion implantation is performed on different parts of the substrate 101 according to the actual requirements of the formed flash memory device to form a deep N-type well region 102, a high-voltage P-type well region 103, a source / drain region 104, and a lightly doped drain region 105, etc. The floating gate layer 120 and the control gate layer 140 are both made of polycrystalline silicon. Furthermore, the sidewall structure 150 includes a silicon oxide layer 151 and a silicon nitride layer 152, wherein the silicon oxide layer 151 covers the sidewall and part of the bottom wall of the trench 200, and the silicon nitride layer 152 covers the silicon oxide layer 151.

[0040] In this embodiment, as Figure 2 and 3 As shown, the steps for forming the sidewall structure 150 may include:

[0041] First step: Deposit the silicon oxide layer 151, the silicon nitride layer 152, and the silicon monoxide layer 153 respectively, wherein the silicon oxide layer 151 covers the sidewalls and bottomwalls of the trench 200 and the control gate layer 140, the silicon nitride layer 152 covers the silicon oxide layer 151, and the silicon oxide layer 153 covers the silicon nitride layer 152.

[0042] The second step is to etch away the silicon oxide layer 153, silicon nitride layer 152, and silicon oxide layer 151 on the surface of the control gate layer 140.

[0043] Third step: Etch away the silicon oxide layer 153, silicon nitride layer 152 and silicon oxide layer 151 on the bottom wall of the trench near the center of the trench to expose the substrate 100.

[0044] Fourth step: Perform a pre-cleaning process on the semiconductor structure formed in the third step to remove the silicon oxide layer 153, and retain the silicon nitride layer 152 and silicon oxide layer 151 covering the sidewalls and part of the bottom wall of the trench 200, thereby obtaining the sidewall structure 150.

[0045] Then, as Figure 4 As shown, a conductive contact layer 160 is formed using a self-aligned silicide process. The conductive contact layer 160 covers the control gate layer 140 and the substrate 100 exposed on the bottom wall of the trench 200. Specifically, the steps for forming the conductive contact layer 160 using the self-aligned silicide process may include: first, forming a conductive material layer that covers the control gate layer 140, the sidewall structure 150, and the substrate 100 exposed in the trench 200; then, under certain conditions, the conductive material layer chemically reacts with the control gate layer 140 (polysilicon) and the substrate 100 (silicon substrate) to generate the conductive contact layer 160 (self-aligned silicide); finally, a wet cleaning process is used to remove the unreacted conductive material layer on the sidewall structure 150.

[0046] Next, as Figure 5As shown, the sidewall structure 150 is selectively etched using the SPT process. Specifically, the selective etching of the sidewall structure 150 using the SPT process includes: (1) etching away a certain length of the silicon nitride layer 152 at the top of the sidewall of the trench 200 to make the opening at the top of the trench 200 form an inverted V-shape; (2) etching away a certain length of the silicon nitride layer 152 on the bottom wall of the trench 200 near the center of the trench 200 to make the opening on the bottom wall of the trench 200 form an inverted V-shape; (3) etching away a portion of the thickness of the silicon nitride layer 152 on the remaining sidewall of the trench 200 away from the top; and (4) etching away a portion of the thickness of the silicon nitride layer 152 on a portion of the bottom wall of the trench 200. The length of the silicon nitride layer 152 etched away from the top of the sidewall of the trench 200 can be 20nm to 30nm; the length of the silicon nitride layer 152 etched away from the bottom wall of the trench 200 near the center of the trench 200 can be 2nm to 5nm; the thickness of the silicon nitride layer 152 etched away from the top of the remaining sidewall of the trench 200 is [missing information]. The thickness of the silicon nitride layer 152, which is a portion of the bottom wall of the trench 200, is etched away. In this embodiment, the opening at the top of the trench 200 is enlarged and etched into an inverted V-shape, the opening at the bottom wall of the trench 200 is enlarged and etched into an inverted V-shape, and the silicon nitride layer 152 at other locations is thinned to a certain thickness. This improves the morphology of the trench 200 with a large depth-to-width ratio, thereby improving the filling of the subsequent interlayer insulating dielectric layer. It can avoid void defects, thus preventing the metal in the subsequently deposited metal film layer from drilling into the void defects and causing short circuits in the device, ensuring the reliability of the device and improving the device yield.

[0047] In this embodiment, the remaining thickness of the silicon nitride layer 152 on the remaining sidewalls of the trench 200 away from the top can be [missing information]. The remaining thickness of the silicon nitride layer 152 on a portion of the bottom wall of the trench 200 is...

[0048] In this embodiment, during the selective etching of the sidewall structure 150 using the SPT process, the ratio of the etching rate of the silicon nitride layer 152 to the etching rate of the silicon oxide layer 151 can be 8 to 10; the ratio of the etching rate of the silicon nitride layer 152 to the etching rate of the control gate layer 140 can be 5 to 8. The SPT process used in this application selectively thins the silicon nitride layer 152 in the sidewall structure 150 without reducing the short-channel characteristics of the device. The self-aligned silicide (conductive contact layer) can maintain a certain distance from the channel, thereby avoiding communication between the self-aligned silicide and the channel and ensuring device safety.

[0049] Preferably, after selectively etching the sidewall structure 150 using the SPT process, the fabrication method of the flash memory device further includes: forming a buffer layer (not shown), the buffer layer covering the sidewall structure 150 and the conductive contact layer 160. The buffer layer may include stacked SiON and SiN layers, the SiON layer covering the sidewall structure 150 and the conductive contact layer 160, and the SiN layer covering the SiON layer. The thickness of the SiON layer can be [missing information]. The thickness of the SiN layer can be [missing information].

[0050] Finally, as Figure 6 As shown, an interlayer insulating dielectric layer 170 is formed, which fills the trench 200. Specifically, the interlayer insulating dielectric layer 170 covers the buffer layer.

[0051] This application employs SPT (Stress Proximity Technique) to selectively etch the sidewall structure. Because SPT has a high selectivity for silicon nitride etching, the silicon nitride layer 152 in the sidewall structure 150 is selectively thinned after the formation of the conductive contact layer 160 (self-aligned silicide process) to improve the filling of the interlayer insulating dielectric layer 170 in the trench 200. Furthermore, by selectively etching the sidewall structure 150 after the formation of the conductive contact layer 160 using SPT, at which point ion implantation of all devices has been completed, the selective etching process of SPT will not mistakenly etch other insensitive materials, thus not affecting the device performance. This improves the filling of the interlayer insulating dielectric layer without affecting the electrical performance of the device, avoiding void defects. This prevents the metal in the subsequently deposited metal film from drilling into void defects and causing short circuits in the device, ensuring device reliability and improving device yield.

[0052] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method of fabricating a flash memory device, comprising: The method comprises the following steps: providing a substrate, a stack of a floating gate layer, an ONO layer and a control gate layer are formed on the substrate, wherein a trench is formed in the control gate layer, the ONO layer and the floating gate layer, and a side wall structure is formed in the trench, the side wall structure covers the side wall and part of the bottom wall of the trench; forming a conductive contact layer by using a self-aligned silicide process, the conductive contact layer covers the control gate layer and the substrate exposed by the bottom wall of the trench; selectively etching the side wall structure by using a stress proximity technique process, wherein the side wall structure at least comprises two material layers, and during the selective etching, the material layer far away from the side wall of the trench is thinned intentionally; and forming an interlayer dielectric layer, the interlayer dielectric layer fills the trench.

2. The method of claim 1, wherein the method further comprises: The side wall structure comprises a silicon oxide layer and a silicon nitride layer, the silicon oxide layer covers the side wall and part of the bottom wall of the trench, and the silicon nitride layer covers the silicon oxide layer.

3. The method of claim 2, wherein the method further comprises: During the selective etching of the side wall structure by using the stress proximity technique process, the ratio of the etching rate of the silicon nitride layer to the etching rate of the silicon oxide layer is 8-10; The ratio of the etching rate of the silicon nitride layer to the etching rate of the control gate layer is 5-8.

4. The method of claim 2, wherein the method further comprises: The selective etching of the side wall structure by using the stress proximity technique process comprises: etching to remove a certain length of the silicon nitride layer at the top end of the side wall of the trench to make the opening at the top end of the trench in an inverted eight-shaped type, etching to remove a certain length of the silicon nitride layer on the bottom wall of the trench close to the center of the trench to make the opening of the bottom wall of the trench in an inverted eight-shaped type, etching to remove part of the thickness of the silicon nitride layer on the remaining side wall of the trench far away from the top end, and etching to remove part of the thickness of the silicon nitride layer on part of the bottom wall of the trench.

5. The method of claim 4, wherein the method further comprises: The length of the silicon nitride layer etched and removed at the top end of the side wall of the trench is 20-30 nm.

6. The method of claim 4, wherein the method further comprises: The length of the silicon nitride layer etched and removed on the bottom wall of the trench close to the center of the trench is 2-5 nm.

7. The method of claim 4, wherein the method further comprises: The thickness of the portion of the thickness of the silicon nitride layer on the remaining sidewall of the trench distal of the top end that is etched away is The thickness of the portion of the thickness of the silicon nitride layer on the portion of the bottom wall of the trench that is etched away is 8. The method of claim 4, wherein the method further comprises: a thickness of the remaining thickness of the silicon nitride layer on the remaining sidewall of the trench away from the top end is a thickness of the remaining thickness of the silicon nitride layer on the portion of the bottom wall of the trench is 9. The method of claim 1, wherein the method further comprises: The aspect ratio of the trench is 2-5.

10. The method of claim 1, wherein the method further comprises: After the selective etching of the side wall structure by using the stress proximity technique process and before the formation of the interlayer dielectric layer, the method for manufacturing the flash memory device further comprises: forming a buffer layer, the buffer layer covers the side wall structure and the conductive contact layer, and the interlayer dielectric layer covers the buffer layer.

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