Clock circuit and control method
Through the combination of the ring vibration clock module, the filter feedback module, the analog-to-digital conversion module and the digital processing module, the problems of low accuracy, large power consumption and large temperature drift of the clock circuit are solved, and high-precision and low-power consumption clock signal output is realized, which is suitable for highly integrated electronic systems.
Patent Information
- Application Number
- CN202111557194.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-12-18
- Publication Date
- 2025-08-15
- Estimated Expiration
- 2041-12-18
AI Technical Summary
Existing clock circuits have problems such as low accuracy, large power consumption and large temperature drift, which are difficult to meet the needs of high integration, low power consumption and high stability.
The closed-loop control structure of the ring vibration clock module combined with the filter feedback module, the analog-to-digital conversion module and the digital processing module is adopted. Through the combination of positive and negative temperature characteristic resistance and digital signal processing, the feedback adjustment of the clock frequency is realized, and the frequency is kept within the preset deviation range.
It realizes high-precision clock signal output with low cost and low loss, reduces the impact of temperature changes on frequency, and meets the needs of high integration and low power consumption electronic system.
Smart Images
Figure CN114257176B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of electronic circuits, and in particular to a clock circuit and a control method thereof. Background Art
[0002] With the development of semiconductor and electronic technologies, mixed-analog electronic systems are becoming increasingly integrated, low-power, and highly stable. As an essential component of electronic systems, clock modules are one of the foundations of external communication, and their performance directly affects system performance.
[0003] There are various ways to generate clocks, including crystal oscillator clocks, RC charge-discharge clocks, and ring oscillator clocks. Each of these structures has its own unique characteristics. For example, crystal oscillator clock circuits can provide a high-precision, low-drift clock source, but they require an off-chip crystal oscillator device, increasing circuit manufacturing costs. RC charge-discharge clock circuits offer low power consumption, but they also have low clock frequency accuracy and large errors, which can easily cause data exchange errors in high-frequency communications. Ring oscillator clock circuits have the simplest structure, but their clock frequency varies significantly with process deviations and temperature. Improving clock accuracy, reducing power consumption, and minimizing temperature variations in output frequency have become key priorities in clock circuit design. Summary of the Invention
[0004] Based on this, it is necessary to provide a clock circuit and a control method to address the above technical issues, so as to solve the problems of low precision, high power consumption and large temperature drift of traditional clock circuits.
[0005] On one hand, the present application provides a clock circuit, including a ring oscillator clock module, a filter feedback module, an analog-to-digital conversion module and a digital processing module, wherein the ring oscillator clock module is used to generate a clock signal; the filter feedback module is connected to the ring oscillator clock module, and is used to generate a feedback control analog signal according to a data selection signal and the clock signal; the analog-to-digital conversion module is connected to the filter feedback module, and is used to generate a feedback control digital signal according to the feedback control analog signal; the digital processing module is connected to the ring oscillator clock module, the filter feedback module and the analog-to-digital conversion module, and is used to generate a frequency correction signal according to the feedback control digital signal and a preset reference signal to control the ring oscillator clock module to generate a frequency-corrected clock signal; and / or control the filter feedback module to generate the feedback control analog signal according to the clock signal according to the data selection signal.
[0006] In the clock circuit described in the above embodiment, a ring oscillator clock module is used to generate a clock signal, which has low cost, low loss, and a simple circuit structure. By providing a filter feedback module, on the one hand, temperature drift is controlled so that the clock circuit does not experience large frequency deviations due to external temperature changes. On the other hand, the filter feedback module and the digital processing module are used to feedback and adjust the frequency of the clock signal generated by the ring oscillator clock module, so that the output clock frequency of the clock circuit is always maintained within a preset deviation range, thereby ensuring the high precision requirements of the clock circuit.
[0007] In one embodiment, the data selection signal includes a first state and a second state; and the filtering feedback module includes:
[0008] a first filtering circuit, connected to the ring oscillator clock module, and configured to generate a first feedback control analog signal according to the received clock signal;
[0009] a second filtering circuit, connected to the ring oscillator clock module, and configured to generate a second feedback control analog signal according to the received clock signal;
[0010] A data selection unit is connected to both the first filtering circuit and the second filtering circuit, and the data selection unit is configured to: control the first filtering circuit to be connected to the analog-to-digital conversion module when the data selection signal is in a first state; and control the second filtering circuit to be connected to the analog-to-digital conversion module when the data selection signal is in a second state.
[0011] In one embodiment, the first filtering circuit includes a first resistor, a second resistor, a first capacitor, and a second capacitor;
[0012] The first resistor is configured such that: a first end is connected to the ring oscillator clock module, and a second end is connected to the first end of the second capacitor via the first capacitor;
[0013] The second resistor is configured as follows: a first end is connected to the first end of the second capacitor, and a second end is grounded;
[0014] The second capacitor is configured as follows: a first end is connected to the data selection unit, and a second end is grounded;
[0015] Wherein, the first resistor and the second resistor are both positive temperature characteristic resistors.
[0016] In one embodiment, the second filtering circuit includes a third resistor, a fourth resistor, a third capacitor, and a fourth capacitor;
[0017] The third resistor is configured as follows: a first end is connected to the ring oscillator clock module, and a second end is connected to the first end of the fourth capacitor via the third capacitor;
[0018] The fourth resistor is configured as follows: a first end is connected to the first end of the fourth capacitor, and a second end is grounded;
[0019] The fourth capacitor is configured as follows: a first end is connected to the data selection unit, and a second end is grounded;
[0020] Wherein, the third resistor and the fourth resistor are both negative temperature characteristic resistors.
[0021] In one embodiment, it further includes:
[0022] The first filter circuit and the second filter circuit are controlled to be connected to the analog-to-digital conversion module for equal times according to the data selection signal.
[0023] In one embodiment, it further includes:
[0024] The analog-to-digital conversion module generates a first feedback control digital signal according to the first feedback control analog signal;
[0025] The analog-to-digital conversion module generates a second feedback control digital signal according to the second feedback control analog signal;
[0026] The first feedback control digital signal and the second feedback control digital signal are superimposed according to a preset proportional coefficient, and the feedback control digital signal is generated by the digital processing module, so that the feedback control digital signal can be maintained within a preset value range under different temperature conditions.
[0027] In one embodiment, the ring oscillator clock module includes a first oscillator circuit, a second oscillator circuit, and a third oscillator circuit connected in series, wherein a first end of the first oscillator circuit is connected to a second end of the third oscillator circuit;
[0028] Wherein, the first oscillation circuit is used to generate a first clock signal according to the frequency correction signal;
[0029] The second oscillation circuit is configured to generate a second clock signal according to the frequency correction signal;
[0030] The third oscillation circuit is used to generate a third clock signal according to the frequency correction signal;
[0031] The ring oscillator clock module is used to generate the frequency-corrected clock signal according to the first clock signal, the second clock signal and the third clock signal, and output the frequency-corrected clock signal through the second end of the third oscillation circuit.
[0032] In one embodiment, it further includes:
[0033] The first oscillation circuit includes a first controllable switch unit, a second controllable switch unit, a first variable resistor, and a fifth capacitor, wherein a source of the first controllable switch unit is connected to a power supply, a gate of the first controllable switch unit is connected to a gate of the second controllable switch unit, a drain of the first controllable switch unit is connected to a drain of the second controllable switch unit, a source of the second controllable switch unit is grounded, and a drain of the first controllable switch unit is grounded via the first variable resistor and the fifth capacitor;
[0034] The second oscillation circuit includes a third controllable switch unit, a fourth controllable switch unit, a second variable resistor, and a sixth capacitor, wherein a source of the third controllable switch unit is connected to a power supply, a gate of the third controllable switch unit is connected to a gate of the fourth controllable switch unit and a port of the fifth capacitor away from a ground terminal, a drain of the third controllable switch unit is connected to a drain of the fourth controllable switch unit, a source of the fourth controllable switch unit is grounded, and a drain of the third controllable switch unit is grounded via the second variable resistor and the sixth capacitor;
[0035] The third oscillation circuit includes a fifth controllable switch unit, a sixth controllable switch unit, a third variable resistor, and a seventh capacitor, wherein a source of the fifth controllable switch unit is connected to a power supply, a gate of the fifth controllable switch unit is connected to the gate of the sixth controllable switch unit and a port of the sixth capacitor away from the ground end, a drain of the fifth controllable switch unit is connected to the drain of the sixth controllable switch unit, a source of the sixth controllable switch unit is grounded, a drain of the fifth controllable switch unit is grounded via the third variable resistor and the seventh capacitor, and a port of the seventh capacitor away from the ground end is connected to the gate of the first controllable switch unit;
[0036] The resistance values of the first variable resistor, the second variable resistor, and the third variable resistor are adjusted so that the port of the seventh capacitor away from the ground terminal outputs the frequency-corrected clock signal.
[0037] A second aspect of the present application provides a clock circuit control method, comprising:
[0038] Control the ring oscillator clock module to generate a clock signal;
[0039] The control filter feedback module generates a feedback control analog signal according to the data selection signal and the clock signal;
[0040] The control analog-to-digital conversion module generates a feedback control digital signal according to the feedback control analog signal;
[0041] generating a frequency correction signal according to the feedback control digital signal and a preset reference signal to control the ring oscillator clock module to generate a frequency-corrected clock signal; and / or
[0042] The filtering feedback module is controlled according to the data selection signal to generate the feedback control analog signal according to the clock signal.
[0043] In one embodiment, the filter feedback module includes a first filter circuit and a second filter circuit connected to the ring oscillator clock module, and further includes:
[0044] Acquire a data selection signal; the data selection signal includes a first state and a second state;
[0045] Wherein, when the data selection signal is in the first state, the first filtering circuit is controlled to be connected to the analog-to-digital conversion module;
[0046] When the data selection signal is in the second state, controlling the second filtering circuit to be connected to the analog-to-digital conversion module;
[0047] The time during which the first filtering circuit is connected to the analog-to-digital conversion module is equal to the time during which the second filtering circuit is connected to the analog-to-digital conversion module. BRIEF DESCRIPTION OF THE DRAWINGS
[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0049] Figure 1 A schematic diagram of the structure of a clock circuit in an embodiment provided in this application;
[0050] Figure 2 A circuit structure diagram of a filter circuit in one embodiment provided in this application;
[0051] Figure 3 A characteristic curve diagram of resistance changing with temperature in an embodiment provided in this application;
[0052] Figure 4 This is a schematic structural diagram of a filtering feedback module in an embodiment provided in this application;
[0053] Figure 5 A circuit structure diagram of a first filtering circuit and a second filtering circuit in an embodiment provided by the present application;
[0054] Figure 6A circuit diagram of a ring oscillator clock module according to an embodiment of the present application;
[0055] Figure 7 A flowchart of a clock circuit control method in an embodiment provided in this application. DETAILED DESCRIPTION
[0056] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.
[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.
[0058] It will be understood that the terms "first," "second," etc. used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element.
[0059] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intervening element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc., if there is transmission of electrical signals or data between the connected objects.
[0060] When used herein, the singular forms "a", "an", and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.
[0061] In recent years, with the rapid development of semiconductor technology, the application of integrated circuits has become increasingly extensive. Clock frequencies for integrated circuits have reached over GHz. High-performance circuits, particularly high-precision, low-power chips with low temperature drift, have become a hot topic in integrated circuit development. This places higher demands on the clock signals that drive these circuits.
[0062] Based on this, the present application provides a clock circuit and a control method, which will be described below through specific embodiments.
[0063] In one embodiment provided in this application, Figure 1 As shown, a clock circuit is provided, including a ring oscillator clock module 100, a filter feedback module 200, an analog-to-digital conversion module 300 and a digital processing module 400, wherein the ring oscillator clock module 100 is used to generate a clock signal; the filter feedback module 200 is connected to the ring oscillator clock module 100, and is used to generate a feedback control analog signal according to a data selection signal and a clock signal; the analog-to-digital conversion module 300 is connected to the filter feedback module 200, and is used to generate a feedback control digital signal according to the feedback control analog signal; the digital processing module 400 is connected to the ring oscillator clock module 100, the filter feedback module 200 and the analog-to-digital conversion module 300, and is used to generate a frequency correction signal according to the feedback control digital signal and a preset reference signal to control the ring oscillator clock module 100 to generate a frequency-corrected clock signal; and / or controls the filter feedback module 200 to generate a feedback control analog signal according to the clock signal through the data selection signal.
[0064] Specifically, the ring oscillator clock module 100 generates a clock signal clk, and the filter feedback module 200 generates a feedback control analog signal V fb , the data is converted by the analog-to-digital conversion module 300 to generate a feedback control digital signal D O The digital processing module 400 generates a frequency correction signal R-trim, which controls the ring oscillator clock module 100 to generate a frequency-corrected clock signal, thereby forming a closed-loop control to make the output clock signal accurate. At the same time, the digital control module 400 controls the operation of the filter feedback module 200 by sending a data selection signal mux_sel.
[0065] In the clock circuit described in the above embodiment, the ring oscillator clock module 100 is used to generate a clock signal, which has low cost, low loss, and a simple circuit structure. By providing a filter feedback module, on the one hand, temperature drift is controlled so that the clock circuit does not experience large frequency deviation due to external temperature changes. On the other hand, the filter feedback module and the digital processing module provide feedback adjustment on the clock signal frequency generated by the ring oscillator clock module, so that the output clock frequency of the clock circuit is always maintained within a preset deviation range, thereby ensuring the high precision requirements of the clock circuit.
[0066] As an example, Figure 2 The figure shows a filter circuit. Through circuit analysis and calculation, the relationship between the output voltage and the input voltage can be obtained:
[0067]
[0068] From the above formula, we can see that the filtered voltage is determined by the filter resistor R, filter capacitor C and the frequency f of the input clock signal. Assuming that the input signal frequency f remains unchanged, the temperature characteristics of the output voltage are affected by the temperature characteristics of the filter resistor R and filter capacitor C. However, the temperature characteristics of capacitors in general integrated circuits are good, and the change in capacitance with temperature can be ignored. Therefore, the temperature characteristics of the output voltage are mainly determined by the temperature characteristics of the filter resistor R. In the integrated circuit process, there are usually two types of resistors with positive temperature characteristics and negative temperature characteristics, such as Figure 3 As shown in Figure (a), the resistance value R of the resistor with positive temperature characteristics p It increases linearly with increasing temperature. Figure 3 As shown in Figure (b), the resistance value R of the resistor with negative temperature characteristics n It decreases linearly with increasing temperature. It can be seen that by linearly combining the two temperature-characteristic resistors, it is not difficult to obtain a constant resistance R that does not change with temperature. cmb In some embodiments, the clock circuit may be provided with two filtering circuits, one of which has a positive temperature characteristic and the other has a negative temperature characteristic, so that the output signals of the two filtering circuits have a low temperature drift characteristic after linear superposition.
[0069] In one embodiment provided in this application, Figure 4 As shown, the filtering feedback module 200 includes: a first filtering circuit 210, a second filtering circuit 220 and a data selection unit 230, wherein the first filtering circuit 210 is connected to the ring oscillator clock module 100, and is used to generate a first feedback control analog signal according to the received clock signal; the second filtering circuit 220 is connected to the ring oscillator clock module 100, and is used to generate a second feedback control analog signal according to the received clock signal; the data selection unit 230 is connected to both the first filtering circuit 210 and the second filtering circuit 220, and the data selection unit 230 is configured to: control the first filtering circuit 210 to be connected to the analog-to-digital conversion module 300 when the data selection signal is in the first state; and control the second filtering circuit 220 to be connected to the analog-to-digital conversion module 300 when the data selection signal is in the second state.
[0070] As an example, Figure 5 As shown in FIG. 2( a ), the first filter circuit 210 includes a first resistor R1 , a second resistor R2 , a first capacitor C1 , and a second capacitor C2 ;
[0071] The first resistor R1 is configured as follows: a first end is connected to the ring oscillator clock module 100 , and a second end is connected to a first end of the second capacitor C2 via the first capacitor C1 ;
[0072] The second resistor R2 is configured as follows: a first end is connected to the first end of the second capacitor C2, and a second end is grounded;
[0073] The second capacitor C2 is configured as follows: a first end is connected to the data selection unit 300, and a second end is grounded;
[0074] The first resistor R1 and the second resistor R2 are both positive temperature characteristic resistors.
[0075] As an example, Figure 5 As shown in FIG. 2( b ), the second filtering circuit 220 includes a third resistor R3 , a fourth resistor R4 , a third capacitor C3 , and a fourth capacitor C4 ;
[0076] The third resistor R3 is configured as follows: a first end is connected to the ring oscillator clock module 100 , and a second end is connected to the first end of the fourth capacitor C4 via the third capacitor C3 ;
[0077] The fourth resistor R4 is configured as follows: a first end is connected to the first end of the fourth capacitor C4, and a second end is grounded;
[0078] The fourth capacitor C4 is configured as follows: a first end is connected to the data selection unit 300 and a second end is grounded;
[0079] The third resistor R3 and the fourth resistor R4 are both negative temperature characteristic resistors.
[0080] Specifically, according to Figure 2 According to the analysis of the embodiment, the embodiment sets a first filter circuit 210 with a positive temperature characteristic and a second filter circuit 210 with a negative temperature characteristic, and the two are connected in parallel. The digital processing module 400 controls the data selection unit 230 through the data selection signal, so that the two filter circuits are turned on in turn in time sharing, and the on-time of the two filter circuits is controlled to be equal. In one clock cycle, the clock signal clk passes through the first filter circuit 210 to generate a first feedback control analog signal V with a positive temperature characteristic. fb1 , after passing through the second filter circuit 220, a second feedback control analog signal V with a negative temperature characteristic is generated. fb2 , and the two are processed by the analog-to-digital conversion module 300, and the first feedback control digital signal D is output to the digital processing module 400. O1 and the second feedback control digital signal D O2 In the digital processing module 400, the feedback control digital signal D is generated by superimposing the linear coefficients of the two. O =D O1 +aD O2 .
[0081] Furthermore, as an example, in order to correct the temperature drift, a clock signal is generated by an external precise clock source in the production test, and the test is performed at temperatures T1 and T2, and the quantitative results D of the first filter circuit at temperature T1 are obtained respectively. O1_T1 , the quantitative result D at temperature T2O1_T2 , and the quantization result D of the second filter circuit at temperature T1 O2_T1 , the quantitative result D at temperature T2 O2_T2 By linearly superimposing the quantization result of the first filter circuit and the quantization result of the second filter circuit, the feedback control digital signal of the clock circuit at temperature T1 can be obtained as D O_T1 =D O1_T1 +aD O2_T1 , the feedback control digital signal at temperature T2 is D O_T2 =D O1_T2 +aD O2_T2 , since the clock signal is a calibrated accurate signal with constant frequency, in order to make the feedback control digital signal unaffected by temperature, let D O_T1 =D O_T2 , we can get D O1_T1 +aD O2_T1 =D O1_T2 +aD O2_T2 , from which we can obtain:
[0082]
[0083] Under any temperature conditions, as long as the clock signal frequency remains unchanged, the feedback control digital signal generated by the circuit of the above embodiment remains unchanged, and its value is D O =D O_T1 =D O_T2 When the frequency of the clock signal generated by the ring oscillator clock module shifts, the feedback control digital signal D O ′≠D O The digital processing module 400 performs compensation according to the offset value, generates a frequency correction signal to adjust the ring oscillator clock module 100, and makes the generated feedback control digital signal consistent with D O equal.
[0084] As an example, Figure 6 As shown, the ring oscillator clock module 100 includes a first oscillator circuit 110, a second oscillator circuit 120 and a third oscillator circuit 130 connected in series, and a first end of the first oscillator circuit 110 is connected to a second end of the third oscillator circuit 130;
[0085] The first oscillator circuit 110 is configured to generate a first clock signal according to the frequency correction signal;
[0086] The second oscillator circuit 120 is used to generate a second clock signal according to the frequency correction signal;
[0087] The third oscillator circuit 130 is used to generate a third clock signal according to the frequency correction signal;
[0088] The ring oscillator clock module 100 generates a frequency-corrected clock signal according to the first clock signal, the second clock signal, and the third clock signal, and outputs the frequency-corrected clock signal through the second terminal of the third oscillator circuit 130 .
[0089] As an example, please refer to Figure 6 The first oscillating circuit 110 includes a first controllable switch unit K1, a second controllable switch unit K2, a first variable resistor R c1 and a fifth capacitor C5, wherein the source of the first controllable switch unit K1 is connected to the power supply, the gate of the first controllable switch unit K1 is connected to the gate of the second controllable switch unit K2, the drain of the first controllable switch unit K1 is connected to the drain of the second controllable switch unit K2, the source of the second controllable switch unit K2 is grounded, and the drain of the first controllable switch unit K1 is connected to the power supply via the first variable resistor R c1 and a fifth capacitor C5 connected to ground;
[0090] The second oscillation circuit includes a third controllable switch unit K3, a fourth controllable switch unit K4, a second variable resistor R c2 and the sixth capacitor C6, wherein the source of the third controllable switch unit K3 is connected to the power supply, the gate of the third controllable switch unit K3 is connected to the gate of the fourth controllable switch unit K4 and the port of the fifth capacitor C5 away from the ground end, the drain of the third controllable switch unit K3 is connected to the drain of the fourth controllable switch unit K4, the source of the fourth controllable switch unit K4 is grounded, and the drain of the third controllable switch unit K3 is connected to the power supply via the second variable resistor R c2 and a sixth capacitor C6 connected to ground;
[0091] The third oscillation circuit includes a fifth controllable switch unit K5, a sixth controllable switch unit K6, a third variable resistor R c3 and the seventh capacitor C7, wherein the source of the fifth controllable switch unit K5 is connected to the power supply, the gate of the fifth controllable switch unit K5 is connected to the gate of the sixth controllable switch unit K6 and the port of the sixth capacitor C6 away from the ground end, the drain of the fifth controllable switch unit K5 is connected to the drain of the sixth controllable switch unit K6, the source of the sixth controllable switch unit K6 is grounded, and the drain of the fifth controllable switch unit K5 is connected to the drain of the sixth controllable switch unit K6 via the third variable resistor R c3 The seventh capacitor C7 is grounded, and a terminal of the seventh capacitor C7 away from the ground terminal is connected to the gate of the first controllable switch unit K1;
[0092] By adjusting the first variable resistor R c1 , the second variable resistor R c2 and the third variable resistor R c3 The resistance value of the seventh capacitor C7 is such that the port away from the ground terminal outputs a frequency-corrected clock signal.
[0093] In one embodiment provided in this application, Figure 7 As shown, a clock circuit control method is provided, comprising:
[0094] Step 22, controlling the ring oscillator clock module to generate a clock signal;
[0095] Step 24, controlling the filter feedback module to generate a feedback control analog signal according to the data selection signal and the clock signal;
[0096] Wherein, the data selection signal includes a first state and a second state;
[0097] Specifically, when the data selection signal is in the first state, the first filter circuit is controlled to be connected to the analog-to-digital conversion module to generate a first feedback control analog signal; when the data selection signal is in the second state, the second filter circuit is controlled to be connected to the analog-to-digital conversion module to generate a second feedback control analog signal; the time when the first filter circuit is connected to the analog-to-digital conversion module is equal to the time when the second filter circuit is connected to the analog-to-digital conversion module.
[0098] Step 26, controlling the analog-to-digital conversion module to generate a feedback control digital signal according to the feedback control analog signal;
[0099] Specifically, the first feedback control analog signal is converted into a first feedback control digital signal through the analog-to-digital conversion module, and the second feedback control analog signal is converted into a second feedback control digital signal through the analog-to-digital conversion module. The two are linearly superimposed to generate a low-temperature drift feedback control digital signal.
[0100] Step 28, generating a frequency correction signal according to the feedback control digital signal and a preset reference signal to control the ring oscillator clock module to generate a frequency-corrected clock signal; and / or controlling the filter feedback module to generate the feedback control analog signal according to the clock signal according to the data selection signal.
[0101] Specifically, the low-temperature drift feedback control digital signal generated in step 26 is used as the preset reference signal, and the clock signal generated by the ring oscillator clock module is filtered and analog-to-digital converted to generate a feedback control digital signal. After comparing the two, a frequency correction signal is generated to control the ring oscillator clock module to adjust the output clock signal frequency to remain constant.
[0102] It should be noted that in the embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the system embodiments described above are merely schematic. For example, the division of the units can be a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.
[0103] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.
[0104] In addition, the functional units in the various embodiments of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated units may be implemented in the form of hardware.
[0105] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not limiting. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solutions, which should all be included in the scope of the claims of the present invention.
Claims
1. A clock circuit, characterized in that: include: Ring oscillator clock module, used to generate clock signals; a filter feedback module connected to the ring oscillator clock module, and configured to generate a feedback control analog signal according to a data selection signal and the clock signal; an analog-to-digital conversion module, connected to the filtering feedback module, and configured to generate a feedback control digital signal according to the feedback control analog signal; a digital processing module, connected to the ring oscillator clock module, the filter feedback module, and the analog-to-digital conversion module, for generating a frequency correction signal based on the feedback control digital signal and a preset reference signal to control the ring oscillator clock module to generate a frequency-corrected clock signal; and / or controlling the filtering feedback module to generate the feedback control analog signal according to the clock signal according to the data selection signal; The data selection signal includes a first state and a second state; The filtering feedback module includes: a first filtering circuit, connected to the ring oscillator clock module, and configured to generate a first feedback control analog signal according to the received clock signal; a second filtering circuit, connected to the ring oscillator clock module, and configured to generate a second feedback control analog signal according to the received clock signal; A data selection unit is connected to both the first filtering circuit and the second filtering circuit, and the data selection unit is configured to: control the first filtering circuit to be connected to the analog-to-digital conversion module when the data selection signal is in a first state; and control the second filtering circuit to be connected to the analog-to-digital conversion module when the data selection signal is in a second state.
2. The clock circuit according to claim 1, wherein: The first filtering circuit includes a first resistor, a second resistor, a first capacitor and a second capacitor; The first resistor is configured such that: a first end is connected to the ring oscillator clock module, and a second end is connected to the first end of the second capacitor via the first capacitor; The second resistor is configured as follows: a first end is connected to the first end of the second capacitor, and a second end is grounded; The second capacitor is configured as follows: a first end is connected to the data selection unit, and a second end is grounded; Wherein, the first resistor and the second resistor are both positive temperature characteristic resistors.
3. The clock circuit according to claim 1, wherein: The second filtering circuit includes a third resistor, a fourth resistor, a third capacitor and a fourth capacitor; The third resistor is configured as follows: a first end is connected to the ring oscillator clock module, and a second end is connected to the first end of the fourth capacitor via the third capacitor; The fourth resistor is configured as follows: a first end is connected to the first end of the fourth capacitor, and a second end is grounded; The fourth capacitor is configured as follows: a first end is connected to the data selection unit, and a second end is grounded; Wherein, the third resistor and the fourth resistor are both negative temperature characteristic resistors.
4. The clock circuit according to any one of claims 1 to 3, wherein: Also includes: The first filter circuit and the second filter circuit are controlled to be connected to the analog-to-digital conversion module for equal times according to the data selection signal.
5. The clock circuit according to claim 3, wherein: Also includes: The analog-to-digital conversion module generates a first feedback control digital signal according to the first feedback control analog signal; The analog-to-digital conversion module generates a second feedback control digital signal according to the second feedback control analog signal; The first feedback control digital signal and the second feedback control digital signal are superimposed according to a preset proportional coefficient, and the feedback control digital signal is generated by the digital processing module, so that the feedback control digital signal can be maintained within a preset value range under different temperature conditions.
6. The clock circuit according to claim 5, wherein: The ring oscillator clock module includes a first oscillation circuit, a second oscillation circuit and a third oscillation circuit connected in series, wherein a first end of the first oscillation circuit is connected to a second end of the third oscillation circuit; Wherein, the first oscillation circuit is used to generate a first clock signal according to the frequency correction signal; The second oscillation circuit is configured to generate a second clock signal according to the frequency correction signal; The third oscillation circuit is used to generate a third clock signal according to the frequency correction signal; The ring oscillator clock module is used to generate the frequency-corrected clock signal according to the first clock signal, the second clock signal and the third clock signal, and output the frequency-corrected clock signal through the second end of the third oscillation circuit.
7. The clock circuit according to claim 6, wherein: The first oscillation circuit includes a first controllable switch unit, a second controllable switch unit, a first variable resistor, and a fifth capacitor, wherein a source of the first controllable switch unit is connected to a power supply, a gate of the first controllable switch unit is connected to a gate of the second controllable switch unit, a drain of the first controllable switch unit is connected to a drain of the second controllable switch unit, a source of the second controllable switch unit is grounded, and a drain of the first controllable switch unit is grounded via the first variable resistor and the fifth capacitor; The second oscillation circuit includes a third controllable switch unit, a fourth controllable switch unit, a second variable resistor, and a sixth capacitor, wherein a source of the third controllable switch unit is connected to a power supply, a gate of the third controllable switch unit is connected to a gate of the fourth controllable switch unit and a port of the fifth capacitor away from a ground terminal, a drain of the third controllable switch unit is connected to a drain of the fourth controllable switch unit, a source of the fourth controllable switch unit is grounded, and a drain of the third controllable switch unit is grounded via the second variable resistor and the sixth capacitor; The third oscillation circuit includes a fifth controllable switch unit, a sixth controllable switch unit, a third variable resistor, and a seventh capacitor, wherein a source of the fifth controllable switch unit is connected to a power supply, a gate of the fifth controllable switch unit is connected to the gate of the sixth controllable switch unit and a port of the sixth capacitor away from the ground end, a drain of the fifth controllable switch unit is connected to the drain of the sixth controllable switch unit, a source of the sixth controllable switch unit is grounded, a drain of the fifth controllable switch unit is grounded via the third variable resistor and the seventh capacitor, and a port of the seventh capacitor away from the ground end is connected to the gate of the first controllable switch unit; The resistance values of the first variable resistor, the second variable resistor, and the third variable resistor are adjusted so that the port of the seventh capacitor away from the ground terminal outputs the frequency-corrected clock signal.
8. A clock circuit control method, characterized in that: include: Control the ring oscillator clock module to generate a clock signal; The control filter feedback module generates a feedback control analog signal according to the data selection signal and the clock signal; The control analog-to-digital conversion module generates a feedback control digital signal according to the feedback control analog signal; generating a frequency correction signal according to the feedback control digital signal and a preset reference signal to control the ring oscillator clock module to generate a frequency-corrected clock signal; and / or controlling the filtering feedback module to generate the feedback control analog signal according to the clock signal according to the data selection signal; The filter feedback module includes a first filter circuit and a second filter circuit connected to the ring oscillator clock module, and further includes: Acquire a data selection signal; the data selection signal includes a first state and a second state; Wherein, when the data selection signal is in the first state, the first filtering circuit is controlled to be connected to the analog-to-digital conversion module; When the data selection signal is in the second state, controlling the second filtering circuit to be connected to the analog-to-digital conversion module; The time during which the first filtering circuit is connected to the analog-to-digital conversion module is equal to the time during which the second filtering circuit is connected to the analog-to-digital conversion module.