System and method for driving logic circuits with uncertain clock edge variations

Abstract

The present disclosure relates to a system and method for driving a logic circuit with uncertain clock edge changes. Embodiments of the present disclosure provide a system and method for operating a logic circuit with uncertain clock edge changes. A system may include: a clock coupled to a logic circuit, the logic circuit having a source latch group coupled to a capture latch group through a logic cone group. The clock includes: a fixed clock component configured to generate a clock signal having a first clock edge; and a jitter clock component coupled to the fixed clock component and configured to modify the clock signal to have a second clock edge based on an uncertain value. The clock sends a clock signal having the second clock edge to drive the source latch group and the capture latch group of the logic circuit. A clock controller coupled to the jitter clock component generates an uncertain value.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the operation of logic circuits. More specifically, embodiments of the present disclosure provide systems and methods for driving logic circuits with uncertain clock edge variations, thereby hiding the internal functions of a product from various forms of external analysis. Background Art

[0002] In the field of integrated circuit (IC) technology, there is growing interest in the ability of a product's functionality to be easily analyzed externally while it is active. This type of analysis can be referred to as an "active attack" on the product. Active attacks can be performed by analyzing voltage comparisons across parts of the product while it is operating. Active attacks rely on repeatedly cycling various functions and observing target energy levels (potentials) within the target circuit. For example, this observation can be performed using a scanner such as an X-ray machine.

[0003] During an active attack, the analyzer can capture multiple samples of circuit operation within a given time span. X-ray analysis of the samples can indicate the logic values ​​(e.g., high voltage and low voltage) of the connections between parts in the product. The logic values ​​can be correlated with the clock edges that operate over the determined time samples. This correlation is achieved by automatically starting the trigger time of the X-ray analysis based on the clock frequency of the device being analyzed. Active attacks have been proven to be effective for reverse engineering many logic states in devices. The logic state of the active circuit cannot be determined by analyzing only the inactive device. Summary of the Invention

[0004] Some aspects of the present disclosure provide a system comprising: a clock coupled to a logic circuit, the logic circuit having a source latch group coupled to a capture latch group through a logic cone group, wherein the clock comprises: a fixed clock component configured to generate a clock signal having a first clock edge, and a dithered clock component coupled to the fixed clock component and configured to modify the clock signal to have a second clock edge based on an uncertain value, wherein the clock sends the clock signal having the second clock edge to drive the source latch group and the capture latch group of the logic circuit; and a clock controller coupled to the dithered clock component, wherein the clock controller generates the uncertain value.

[0005] Other aspects of the present disclosure provide an integrated circuit (IC) structure comprising: a source latch group configured to propagate an input logic signal; a logic cone group coupled to the source latch group and configured to convert the input logic signal into an output logic signal via one of a plurality of signal paths; a capture latch group coupled to the logic cone group and configured to process the output logic signal from the logic cone group; a clock coupled to the source latch group and the capture latch group, the clock comprising: a fixed clock component configured to generate a clock signal having a first clock edge, and a dithered clock component coupled to the fixed clock component and configured to modify the clock signal to have a second clock edge based on an indeterminate value, wherein the clock sends the clock signal having the second clock edge to drive the source latch group and the capture latch group; and a clock controller coupled to the dithered clock component, wherein the clock controller generates the indeterminate value.

[0006] Other aspects of the present disclosure provide a method comprising: generating a clock signal having a first clock edge; generating an indeterminate value via a clock controller; modifying the clock signal from the first clock edge to a second clock edge based on the indeterminate value; and sending the clock signal having the second clock edge to a logic circuit having a source latch group coupled to a capture latch group through a logic cone group, such that the clock signal having the second clock edge drives each of the source latch group and the capture latch group. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] These and other features of the present disclosure will be more readily understood from the following detailed description of various aspects of the disclosure taken in conjunction with the accompanying drawings which depict various embodiments of the disclosure, in which:

[0008] FIG1 shows an example arrangement for actively attacking a product via an X-ray device.

[0009] Figure 2 A schematic diagram of a system for driving a logic circuit with uncertain clock edge variation according to an embodiment of the present disclosure is shown.

[0010] Figure 3 A magnified view of a signal path through a logic cone from a set of source latches to a set of capture latches in an embodiment of the present disclosure is provided.

[0011] Figure 4 A digital circuit diagram of a system for driving a logic circuit with uncertain clock edge variation according to an embodiment of the present disclosure is provided.

[0012] Figure 5A comparative clock diagram illustrating three possible delayed clocks and the initial clock C1 that may be selected in an embodiment of the present disclosure is provided.

[0013] Figure 6 An example flow chart of a method for driving a logic circuit with uncertain clock edge variation according to an embodiment of the present disclosure is provided.

[0014] It should be noted that the drawings of the present disclosure are not necessarily drawn to scale. These drawings are intended to depict only typical aspects of the present disclosure and therefore should not be considered to limit the scope of the present disclosure. In the accompanying drawings, the same reference numerals represent the same elements between the drawings. DETAILED DESCRIPTION

[0015] In the following description, reference is made to the accompanying drawings, which form a part thereof, which show, by way of illustration, specific exemplary embodiments in which the present teachings may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it is understood that other embodiments may be used and changes may be made without departing from the scope of the present teachings. Therefore, the following description is merely exemplary.

[0016] Embodiments of the present disclosure provide systems and methods for driving the operation of a logic circuit with uncertain clock edge variations. Clock edges refer to the rising and falling edges of the voltage within a clock signal used to drive the operation of the logic circuit. Uncertain clock edge variations can reduce the impact of active attacks on integrated circuits, for example by making it difficult or impossible to trigger an X-ray capture of the voltage state within the product logic circuit. A system according to the present disclosure provides a clock coupled to a logic circuit. The logic circuit includes a source latch group coupled to a capture latch group via a logic cone group. The timing of the clock edges sent to the logic circuit affects which logic cones will send signals to the capture latch group.

[0017] A clock may include a fixed clock component for generating a clock signal having a first clock edge (i.e., a set of rising and falling signals at corresponding instances in time), and a dithered clock component coupled to the fixed clock component for modifying the clock signal to have a second clock edge (i.e., rising and falling signals at different instances in time, but with substantially the same frequency). In some implementations, a clock control system is coupled to and / or included in a dithered clock controller to generate an indeterminate number ("N") of delayed clocks so that the clock entering the latch shifts the relative clock on a cycle-by-cycle basis. The indeterminate control system selects which delayed clock to create a difference, cycle-by-cycle, between the clock signal having the first clock edge and the second clock edge. The clock sends a clock value having the second clock edge to drive the source latch group and the capture latch group. In this configuration, a capture device, such as an X-ray, cannot reliably trigger its sampling of the logic circuit in accordance with the clock edge variations. Thus, embodiments of the present disclosure obfuscate the functionality of the logic circuit coupled to the clock and the clock controller.

[0018] 1 shows an example of how an attacker might attempt to analyze the functionality of device 10 using, for example, a scanner 12 (e.g., an X-ray machine). It will be understood that scanner 12 may also include other types of imaging tools (e.g., thermal imaging devices) with other types of attacks or settings. Device 10 may be in the form of a single logic circuit and / or a partial or complete device having multiple logic circuits to be analyzed. Scanner 12 may be configured to capture images of device 10 while device 10 is operating. An oscilloscope 14 or similar power tool may be connected to device 10. Oscilloscope 14 may generate a supply voltage and / or other input to drive a clock signal within device 10, thereby causing device 10 to operate in an activated state.

[0019] Attack controller 16 can be electrically coupled to device 10 via oscilloscope 14 to attempt to force device 10 to perform various logic functions. Attack controller 16 can also be electrically coupled to scanner 12 to trigger the capture of X-ray images of device 10 during operation. In this manner, attack controller 16 can control each of device 10, scanner 12, and / or oscilloscope 14 to analyze the voltage state of device 10 while device 10 is operating. In this configuration, attack controller 16 can potentially derive the logic functions of device 10 by triggering scanner 12 synchronously with clock edges pulsed by a clock internal to device 10 or otherwise connected to device 10. Embodiments of the present disclosure provide systems and methods for protecting logic circuits (e.g., within device 10) from detection and analysis by attack controller 16 and interconnecting elements (e.g., scanner 12 and oscilloscope 14).

[0020] refer to Figure 2 , a system 100 according to an embodiment of the present disclosure is shown as being operatively coupled to a logic circuit 102. The logic circuit 102 may include a group of source latches 104 for propagating input logic signals through the logic circuit 102. The source latches 104 may be coupled to a group of capture latches 106 via a group of logic cones 108. The logic cones 108 are arranged to convert the input logic signals propagated from the source latches 104 into one or more corresponding output logic signals via corresponding signal paths. The signal paths through the logic cones 108 may depend on the signal information to be processed and / or the clock edges of the clock signal driving the logic circuit 102. The capture latches 106 in the logic circuit 102 may receive the output logic signals from the group of logic cones 108 to process these logic signals and transmit them to other components.

[0021] The set of source latches 104 can have a plurality of different latches 104a, 104b, 104c, 104d. The set of capture latches 106 can also have a plurality of different latches 106a, 106b, 106c, 106d. The total number of latches in each set of latches 104, 106 varies from product to product. In some cases, logic circuit 102 can include hundreds or thousands of latches in each set of latches 104, 106. Logic circuit 102 can be part of any conceivable circuit configured to transmit data in the form of serial or parallel data strings. More specifically, logic circuit 102 can be included in part or all of a product such as device 10 (FIG. 1). Source latch 104 and capture latch 106 can take the form of digital memory circuits for recording high or low voltage values ​​(i.e., "0" or "1"). Each latch within source latch 104 and capture latch 106 may take the form of any circuit having two stable states and that can be used to store state information, including various types of digital memory.

[0022] Logic cone 108 may be one or more logic gates configured to receive logic signals from source latch 104 and / or other logic cones 108 to implement various functions. These functions may include basic logic (e.g., OR, AND, XOR, XOR, NOR, NOR, NOR, etc.) and / or combinations of these functions. A group of capture latches 106 may receive and / or store outputs from logic cone 108 to process and send these outputs to other parts of the device. Such parts may be within or outside of logic circuit 102. The structure and function of source latch 104 and capture latch 106 are well known in the art and will not be described in further detail.

[0023] System 100 can interact with or be part of logic circuit 102 to prevent active attacks. System 100 can include a variable control system 110 having a clock 112 for providing a digital clock input (e.g., a periodic high-low waveform with a predetermined frequency and corresponding clock edges at different time points) to logic circuit 102. Logic circuit 102 can be configured to operate using a clock signal sent from clock 112. Unlike conventional clock mechanisms for logic circuit 102, clock 112 in embodiments of the present disclosure provides a clock signal in which the clock edge is uncertain (e.g., random) to drive logic circuit 102. Thus, clock 112 can cause a logic signal to propagate from source latch 104 to the set of capture latches 106 at uncertain times. Variable control system 110 can provide some control over the clock edge of the signal sent to logic circuit 102. The use of uncertain values ​​to create clock edge variations may hinder or prevent devices such as the attack controller 16 ( FIG. 1 ) from being able to trigger a detection tool (e.g., scanner 12) in synchronization with the propagation and capture of a logic signal. As used herein, the term "uncertain value" may refer to a random value, but need not necessarily refer to a purely mathematically random value. Other types of numerical values ​​determined without user input (e.g., pseudorandom values) or other mechanisms for providing uncertain digital outputs may be used to create the "uncertain values" discussed herein.

[0024] To generate a clock signal with varying clock edges, the clock 112 of the variable control system 110 may include multiple components for generating a signal with a clock edge that is nondeterministic but still within the jitter limits of the logic circuit 102 connected thereto. For example, the clock 112 may include a fixed clock component 114 for generating a clock signal 115 having a first (e.g., initial) clock edge. The first clock edge in the clock signal 115 may be a predetermined, specified instance in which the logic circuit 102 will detect a rising and / or falling edge with respect to a logic cycle and / or may be a signal propagation with the lowest possible amount of jitter. The fixed clock component 114 may include or otherwise be coupled to a clock generator (e.g., one or more electronic oscillators, such as a crystal oscillator or any type of local oscillator (LO) circuit on the device) for driving and synchronizing the operation of the logic circuit 102. The fixed clock component 114 may include various subcomponents, such as a resonant circuit, an amplifier, a power supply coupling, etc., for generating a waveform at a desired frequency. The clock signal 115 generated by the fixed clock component 114 may be deterministic, ie, the clock edges of the generated clock signal do not vary based on the input signal to the clock 112 .

[0025] Clock 112 may also include a jitter clock component 116 operably coupled to fixed clock component 114. Jitter clock component 116 may lack a clock generator or similar oscillating circuitry; instead, it may be a different circuit that modifies the clock edges of a signal based on an indeterminate value (e.g., changes their timing without affecting the frequency). Thus, jitter clock component 116 can alter the timing of clock edges emitted by clock 112, for example by using an indeterminate value to alter the output edge of the original clock edge. "Jitter" refers to the timing shift (i.e., phase difference) between two clock signal timings with two different sets of clock edges, where there is no difference in the frequency or amplitude of the signals. In some implementations, jitter clock component 116 may be a component for intentionally jittering the clock signal by delaying it by an indeterminate (e.g., random) amount of time (e.g., measured in nanoseconds). Thus, jitter clock component 116 causes clock 112 to emit a clock signal 118 having a second clock edge, and the emitted clock signal 118 is sent to logic circuit 102, as discussed elsewhere herein.

[0026] Clock controller 120 is operably coupled to jitter clock component 116 to provide an uncertainty value for determining the amount of jitter (i.e., the variation between a first clock edge and a second clock edge). Clock controller 120 can therefore take the form of any currently known or later developed tool for generating an uncertainty variable, which can be randomly generated, pseudo-randomly generated, and / or generated by any mechanism that cannot be accurately predicted by an observer. Such a tool may, for example, include a random number generator (RNG) or a pseudo-random number generator (PRNG) in the form of a digital circuit for generating random values ​​based on any conceivable function, algorithm, etc. In a further implementation, clock controller 120 may include or take the form of a physically unclonable function (PUF), a physical object that produces a unique output in response to various inputs. Due to its unique output, a PUF can produce a seemingly random output in response to an input voltage signal. The input voltage signal, in turn, can itself be transmitted by an RNG or similar element to provide further variation in the uncertainty value from clock controller 120.

[0027] Without regard to the uncertain values ​​from the clock controller 120, the clock 112 optionally includes or is coupled to various components that act on a dithered clock component 116. These components can control or limit the extent to which the dithered clock component 116 modifies the clock signal from the fixed clock component 114. In one example, the clock 112 can be coupled to a dither switch 122 to selectively enable or disable the dithered clock component 116 during operation of the system 100. In a simple example, the dither switch 122 can take the form of an electrical switch, fuse, transistor, and / or similar component that controls whether the dithered clock component 116 modifies the clock edge of a signal emitted from the fixed clock component 114 before the signal passes to the logic circuit 102. In further examples, the dither switch 122 can be a separate controller that detects and / or issues commands to obfuscate the functionality of the logic circuit 102 by enabling the dithered clock component 116 and / or to enable the logic circuit 102 to operate without clock edge variations by disabling the dithered clock component 116.

[0028] Regardless of how it is embodied, the dithering switch 122 can control whether the system 100 affects the operating frequency of the logic circuit 102 based on whether the manufacturer wishes to hide the functionality of the logic circuit 102. The dithering switch 122 can enable or disable the dithering clock component 116 during product manufacturing and / or after field deployment. More specifically, the dithering switch 122 can receive commands from the obfuscated logic circuit 102 (e.g., from a user or manufacturer) and, in response, can cause the dithering clock component 116 to change the clock edge in the clock signal 118 sent to the source latch 104 and the capture latch 106. In some cases, the dithering switch 122 can be omitted entirely, such that the dithering clock component 116 is always operational.

[0029] System 100 and / or clock 112 may also include a jitter controller 124 operatively coupled to jitter clock component 116 and / or clock controller 120 to ensure that the amount of jitter in the clock signal remains below a target. Where jitter controller 124 is coupled to clock controller 120, jitter controller 124 may limit uncertainty values ​​from clock controller 120 so that they produce at least a minimum frequency for operation of logic circuit 102. Where jitter controller 124 is coupled to clock 112, jitter controller 124 may reduce the variation between a first clock edge and a second clock edge. During operation, clock controller 120 and / or jitter controller 124 may calculate a jitter limit for clock signal 118 based on one or more properties of logic circuit 102 (e.g., the arrangement of logic cones). Once the jitter limit is calculated, clock controller 120 may generate the uncertainty value and / or jitter clock component 116 may generate clock signal 118 to prevent the jitter limit from being exceeded.

[0030] Clock 112 can generate a clock signal 118 with a varying clock edge to drive various components of logic circuit 102. More specifically, clock signal 118 with a second (i.e., uncertain) clock edge can be sent to source latch 104 in addition to capture latch 106. With this arrangement, system 100 can ensure that each set of latches 104, 106 propagates and captures the signal as desired, even after the initial clock edge sent by fixed clock component 114 has been modified by the jittering clock component 116 from its value. An operator of logic circuit 102 may wish to delay the transmission of clock signal 118 to each set of latches 104, 106. In such cases, system 100 can include one or more clock buffers 130 coupled between clock 112 and source latch 104 and / or capture latch 106 to delay (e.g., by a predetermined number of milliseconds) the propagation of clock signal 118 to logic circuit 102. A buffer is an electronic component that does not affect the amplitude, frequency, and / or other properties of an electrical signal passing through it, but only delays the travel time from one element to another. In one example, each clock buffer 130 may include an AND gate having a set of inverters coupled to one terminal, such that a signal will not pass through the clock buffer 130 until it passes through all of the inverters. The clock buffers 130 may be identical or different, and the delay in each buffer may be selected so that the clock signal 118 emitted from the clock 112 arrives at the source latch 104 and the capture latch 106 at substantially the same time.

[0031] Steering Figure 3 , an enlarged view of logic circuit 102 provides an example of the effect that system 100 may have on the operation of logic circuit 102. Figure 3 In the example of FIG. 1 , a group of latches 104 having seven source latches 104a-104g may be connected through several logic cones 108 (e.g., in FIG. Figure 3 In the example, six (six in the example) logic signals are propagated to a group of latches 106 having three capture latches 106a-106c. The path from the group of source latches 104 to the group of capture latches 106 is not fixed relative to the clock edges of the clock signal sent to the logic circuit 102. That is, the structure and coupling across the logic cone 108 can cause the logic signal to propagate along one path of the clock signal 118 having one set of clock edges, but along different paths having the same frequency but different clock edges. As a result, the logic circuit 102 includes non-deterministic logic paths that are at least partially dependent on the clock edges of the clock signal 118 used to drive the group of source latches 104 and the group of capture latches 106. The difference in the paths ensures that data can be accurately propagated from the source latches 104 and recorded in the capture latches 106 according to timing requirements.

[0032] Figure 3 Two example timing paths P1, P2 from source latch 104 to capture latch 106b through the group of logic cones 108 are provided. Figure 2 ) and logic circuit 102 can be configured to accommodate a second (i.e., uncertain) clock edge in clock signal 118 emitted from clock 112. This can be ensured via design and timing analysis of logic circuit 102 that provides slack to accommodate clock signal 118 having different clock edges. The term "slack" refers to the difference between the arrival time (e.g., deterministically or statistically expressed) of a logic signal from an input (e.g., one of source latches 104a-104g) to a particular merge point (e.g., one of capture latches 106a-c) and the required arrival time for the merge point. The term "propagation time" refers to the amount of time required for a signal to travel from the input to the merge point.

[0033] exist Figure 3 In the example shown in FIG1 , when the clock signal propagates with a first clock edge, the logic signal may propagate through the logic circuit 102 via timing path P1, but when the clock signal propagates with a second clock edge, the logic signal may propagate through the logic circuit 102 via timing path P2. In either case, the slack of paths P1 and P2 is greater than the total propagation time required for the clock signal to travel from the set of source latches 104 to the set of capture latches 106. As a result, the logic signals traveling through the logic circuit 102 will take different paths with different clock edges while still implementing the functionality of the logic circuit 102. Therefore, the system 100 that generates the clock signal 118 with varying clock edges will cause the signal to take an undefined path through the logic circuit 102 at different time intervals. This may hinder an attacker from identifying when to trigger a tool such as the scanner 12 ( FIG1 ), as well as hinder understanding the functionality implemented by the logic circuit 102.

[0034] Steering Figure 4 and Figure 5 , which discusses digital circuits for varying the amount of jitter in clock signal 118. A schematic diagram of logic circuit 102 and digital circuitry for system 100 is provided in Figure 4 As shown in Figure 5 Shows that the Figure 4148c. The embodiment of the system 100 shown in FIG. 148a illustrates an example of three possible clock signals 118a, 118b, 118c generated by a fixed clock component 114. The fixed clock component 114 may generate a clock signal 115 having a predetermined first clock edge. The clock signal 115 may then be sent to a dithered clock component 116. As discussed herein, the dithered clock component 116 converts the clock signal 115 having the first clock edge into a clock signal 118 having a second clock edge for sending to the source latch 104. The clock controller 120 may provide an uncertain value for controlling the amount of dither in the clock signal 118 sent to the logic circuit 102. According to one example, the dithered clock component 116 may use corresponding delay buffers 148a, 148b, 148c to separate the clock signal 115 into three different clock signals. Although three delay buffers 148a, 148b, 148c are provided as an example, any number of delay buffers may be included. Each delay buffer provides a corresponding clock signal 118a, 118b, 118c ( Figure 5 ), which clock signals represent one of a set of possible clock signals to be output from the dithered clock component 116. Clock signals 118a, 118b, 118c, in turn, have different time delays d1, d2, and d3 relative to the clock edge of clock signal 115. It will therefore be appreciated that all possible clock signals 118a, 118b, and 118c will be generated in the dithered clock component 116 without taking into account the uncertain value output from the clock controller 120. The dithered clock component 116 may also include a signal demultiplexer ("demux") 150 for selecting one of the multiple clock signals 118a, 118b, and 118c as the clock signal 118 to be sent to the source latch 104. Thus, the clock controller 120 uses the uncertain value to cause the demux 150 to select only one of the multiple clock signals, and therefore the corresponding amount of dither, to drive the logic circuit 102.

[0035] The set of source latches 104 driven by clock signals 118a, 118b, 118c can propagate through the logic cone 108 to the set of capture latches 106. The set of capture latches 106 can, in turn, be coupled to a multiplexer 152 ("mux"). The mux 152 can be electrically coupled to the clock controller 120 such that the same indeterminate value provided to the demux 150 also causes the mux 152 to receive and process the output logic signal at the speed of the selected clock signal 118, regardless of the mechanism used to generate the indeterminate value to select one of the clock signals 118a, 118b, 118c. The mux 152 then provides the output data to the capture latches 106. Thus, the functionality of the logic circuit 102 can be driven by the selected clock edge of the clock signal 118 without interfering with the intended functionality of the logic circuit 102.

[0036] Now let’s refer to Figure 2 and Figure 6 Embodiments of the present disclosure provide a method for driving logic circuit 102 with clock edge variation, for example, using system 100 according to embodiments of the present disclosure. In process P1 according to embodiments of the present disclosure, fixed clock component 114 of clock 112 may generate a clock signal having a first clock edge. The method then proceeds to decision D1, where variable control system 110 determines whether it is necessary to obfuscate the signal passing through logic circuit 102. Decision D1 may, for example, include detecting or not detecting a signal from dither switch 122 and / or other mechanism for controlling the operation of dither clock component 116, with dither switch 122 being placed in an on or off position. If obfuscation is not desired (i.e., the result of decision D1 is "no"), system 100 may use the first clock edge from clock 112 to drive logic circuit 102 (i.e., as indicated by the line to process P6). If obfuscation is desired (i.e., the result of decision D1 is "yes"), the method proceeds to further steps to vary the clock edge. In some cases (eg, the dither switch 122 is omitted from the system 100 or is permanently on), decision D1 may be omitted.

[0037] In a method according to an embodiment of the present disclosure, process P2 may include generating an uncertain value via clock controller 120. As discussed elsewhere herein, the uncertain value may be generated using any currently known or later developed randomization component (e.g., RNG, PUF, etc.). The uncertain value may be sent to jitter clock component 116, for example, as an encoded electrical signal. In process P3, jitter clock component 116 uses the uncertain value to generate clock signal 118 having a second clock edge, for example, by selecting from one of several possible clock signals having different clock edges. For example, mux 150 ( Figure 4 ) and / or any currently known or later developed digital solution for associating an indeterminate value with a possible clock signal to be sent to the logic circuit 102 to implement this conversion. In a simplified example, as discussed elsewhere herein, the method of the present disclosure can continue with further operations to output a clock signal having a second clock edge to the logic circuit 102 (i.e., as indicated by the dashed line to process P5).

[0038] In some implementations, the disclosed method may include further processes to ensure that the timing of the second clock edge transitioning from the uncertain value is within the jitter limits of logic circuit 102. Process P4, for example, may include evaluating the jitter limits of logic circuit 102. The jitter limits may be pre-recorded in jitter controller 124 and / or actively calculated by jitter controller 124 based on various characteristics of logic circuit 102. Regardless of the evaluation, process P4 may output a maximum allowable jitter for operating logic circuit 102 to ensure that logic circuit 102 operates for a sufficient time for the signal to propagate from the set of source latches 104 to the set of capture latches 106. Thereafter, jitter controller 124 may implement decision D2 to determine whether the second clock edge from process P3 is within the jitter limits evaluated in process P4. If the second clock edge is not within the jitter limits (i.e., the result of decision D2 is "no"), jitter controller 124 may cause the clock controller to generate a new uncertain value (i.e., repeat process P2) to select a new second clock edge for evaluation. If the second clock edge is within the jitter limit (i.e., the result of decision D2 is "yes"), the clock signal having the second clock edge can be used to drive each group of latches 104, 106, as discussed herein. In further implementations, the jitter clock component 116 can be configured to never cause the second clock edge to be outside the jitter limit of the logic circuit 102.

[0039] In a method according to an embodiment of the present disclosure, process P5 may include outputting a clock signal 118 having a second clock edge from the variable control system 110 to drive the operation of the latches 104 and 106. The second clock edge is selected indeterminately based on the uncertain value generated in process P2, thereby obscuring the processing of the signal in the logic circuit 102 while preserving the desired frequency. In a method according to the present disclosure, process P6 may include sending the clock signal 118 to the group of latches 104 and the group of latches 106 in any conceivable manner (e.g., through the clock buffer 130). In the event that processes P2-P5 and / or decision D2 are omitted (i.e., the result of decision D1 is "no"), process P6 may include driving the logic circuit 102 with a clock signal having only a fixed set of clock edges.

[0040] Embodiments of the present disclosure provide various technical and commercial advantages, some of which are described herein by way of example. Systems and methods according to the present disclosure provide an architecture for selectively obscuring the functionality and / or signal paths of logic circuits 102 without otherwise modifying the structure and / or clock frequency of the logic circuits 102. System 100 can be coupled to as many or as few logic circuits 102 as desired in a single device, thereby allowing the functionality of sensitive components to be hidden while otherwise conserving space and power in non-sensitive components of the device. In an example implementation, a single device may include several logic circuits that are not connected to an embodiment of system 100, while also including several logic circuits 102 coupled to an embodiment of system 100, as discussed herein. Thus, methods according to the present disclosure may include, via embodiments of the system 100 and / or method described herein, operating non-target logic circuits 102 with a determined clock edge while operating other logic circuits 102 with a clock edge variation.

[0041] Some aspects of the present disclosure are described above with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box of the flowchart and / or block diagram, and the combination of boxes in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device create a method for implementing the function / action specified in one or more boxes in the flowchart and / or block diagram.

[0042] As used herein, the terms "configuration," "configured to," and / or "configured for" may refer to a specific mode of use of the components described herein. For example, a system or device configured to perform a function may include a computer system or computing device that is programmed or otherwise modified to perform that specific function. In other cases, program codes stored on a computer-readable medium (e.g., a storage medium) may be configured to cause the computing device to perform various functions when they are executed on at least one computing device. In these cases, when executed, the arrangement of the program codes triggers specific functions in the computing device. In other examples, a device configured to interact with and / or act on other components may be specifically shaped and / or designed to effectively interact with and / or act on these components. In some such cases, the device is configured to interact with another component because at least a portion of its shape is complementary to at least a portion of the shape of the other component. In some cases, the size of at least a portion of the device is designed to interact with at least a portion of another component. The physical relationship between the device and the other component (e.g., complementary, dimensional consistency, etc.) can help perform functions, such as replacement of one or more of the device or the other component, joining of one or more of the device or the other component, etc.

[0043] The description of various embodiments of the present disclosure has been given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A system for operating a logic circuit, comprising: a clock coupled to the logic circuit, the logic circuit having a set of source latches coupled to a set of capture latches through a set of logic cones, wherein the clock comprises: a fixed clock component configured to generate a clock signal having a first clock edge, and a dithered clock component coupled to the fixed clock component and configured to modify the clock signal to have a second clock edge based on an uncertain value, wherein the clock sends the clock signal having the second clock edge to drive the source latch group and the capture latch group of the logic circuit; and a clock controller coupled to the dithered clock component, wherein the clock controller generates the uncertainty value, Wherein, modifying the clock signal from having the first clock edge to having the second clock edge causes the logic cone group to modify a signal path from the source latch group to the capture latch group.

2. The system according to claim 1, wherein: The clock controller is configured to enable the dithered clock component in response to detecting a command to obscure the logic circuit.

3. The system according to claim 1, wherein: The clock controller includes a physical unclonable function for generating the indeterminate value.

4. The system according to claim 1, wherein: The clock controller includes a random number generator for generating the uncertain value.

5. The system according to claim 1, wherein: The jitter clock component is further configured to modify the clock signal so that the second clock edge is within a jitter limit of the logic circuit.

6. The system according to claim 5, wherein: The slack of each of the plurality of signal paths through the logic cone group is greater than a propagation time from the source latch group to the capture latch group at the second clock edge.

7. The system according to claim 1, wherein: The clock is coupled to the set of source latches and the set of capture latches of the logic circuit through a clock buffer configured to delay the clock signal.

8. A system for operating a logic circuit, comprising: The logic circuit comprises: a set of source latches configured to propagate an input logic signal; a logic cone group coupled to the source latch group and configured to convert the input logic signal into an output logic signal via one of a plurality of signal paths; and a set of capture latches coupled to the logic cone set and configured to process the output logic signals from the logic cone set; a clock coupled to the source latch group and the capture latch group, the clock comprising: a fixed clock component configured to generate a clock signal having a first clock edge, and a dithered clock component coupled to the fixed clock component and configured to modify the clock signal to have a second clock edge based on an uncertain value, wherein the clock sends the clock signal having the second clock edge to drive the source latch group and the capture latch group; and a clock controller coupled to the dithered clock component, wherein the clock controller generates the uncertainty value, Wherein, modifying the clock signal from having the first clock edge to having the second clock edge causes the logic cone group to modify a signal path from the source latch group to the capture latch group.

9. The system according to claim 8, wherein: The plurality of signal paths of the logic cone group include a first signal path for the clock signal having the second clock edge, and a second signal path for the clock signal having the second clock edge.

10. The system according to claim 8, wherein: The clock controller includes one of a physical unclonable function or a random number generator.

11. The system according to claim 8, wherein The slack of each of the plurality of signal paths through the logic cone group is greater than a propagation time from the source latch group to the capture latch group at the second clock edge.

12. The system according to claim 8, wherein: The jitter clock component is further configured to modify the clock signal so that the second clock edge is within a jitter limit of the logic circuit.

13. The system according to claim 12, wherein: The slack of each of the plurality of signal paths through the logic cone group is greater than a propagation time from the source latch group to the capture latch group at the second clock edge.

14. The system of claim 8, further comprising: A clock buffer is coupled between each of the set of source latches and the set of capture latches and the clock, the clock buffer being configured to delay the clock signal.

15. A method for operating a logic circuit, comprising: generating a clock signal having a first clock edge; generating an indeterminate value via a clock controller; Based on the uncertain value, modifying the clock signal from the first clock edge to a second clock edge; as well as sending a clock signal having the second clock edge to a logic circuit having a set of source latches coupled to a set of capture latches through a set of logic cones such that the clock signal having the second clock edge drives each of the set of source latches and the set of capture latches, Wherein, modifying the clock signal from the first clock edge to the second clock edge causes the logic cone group to modify a signal path from the source latch group to the capture latch group.

16. The method according to claim 15, wherein The clock controller includes one of a physical unclonable function or a random number generator.

17. The method according to claim 15, further comprising: calculating a jitter limit of the clock signal based on the logic circuit; as well as The uncertainty value is generated such that the second clock edge is within a jitter limit of the logic circuit.

18. The method according to claim 15, further comprising: The clock controller is enabled in response to detecting a command to obfuscate the logic circuit.

19. The method according to claim 15, wherein Sending the clock signal having the second clock edge to the logic circuit includes passing the clock signal through a clock buffer to delay the clock signal.

Images