A charge pump circuit and a phase-locked loop circuit

Abstract

An embodiment of the present application discloses a charge pump circuit and a phase-locked loop circuit. The charge pump circuit includes: a charge and discharge module enters a charge and discharge state or a sampled state under the control of a PFD; the voltage of a filter capacitor is used to control the frequency of a VCO; a sampling control circuit generates a control signal according to the output result of the PFD to control the conduction of an operational amplifier for voltage sampling or stop voltage sampling; after the operational amplifier is turned on, it samples the voltages at multiple charge and discharge connection ends on the charge and discharge path, and generates a bias voltage according to the sampled voltage to be provided to the charge and discharge module; a voltage sampling and holding module samples the bias voltage of the operational amplifier when the charge and discharge module is in the sampled state, and holds and transmits the bias voltage to the charge and discharge module when the charge and discharge module enters the charge and discharge state. Through the solution of this embodiment, the problem of current mismatch existing in the current charge pump circuit is solved.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of charge pump circuit design, and particularly to a charge pump circuit and a phase-locked loop circuit. Background Art

[0002] A phase-locked loop (PLL) is an important module in a mixed-signal circuit, which can track the phase and frequency of an input signal and output a clock signal with low jitter. It has become an essential module in dedicated chips such as communication systems, digital circuits, hard disk drive circuits, and CPUs (central processing units).

[0003] Charge pumps are widely used in phase-locked loop circuits. The addition of a charge pump can provide infinite loop gain and capture range for the loop. In a phase-locked loop circuit, a charge pump is used to convert the digital signal output by a phase-frequency detector (PFD) into an analog signal, and this analog signal controls the frequency change of a voltage-controlled oscillator (VCO). The performance of the charge pump directly affects the quality of the VCO output frequency. The selection and application of a high-performance charge pump circuit play a crucial role in improving the overall performance of the PLL. There are non-ideal factors such as charge sharing, channel charge injection, clock feedthrough, and current mismatch in charge pumps, which restrict the performance of charge pump phase-locked loops (CPPLLs).

[0004] A charge pump structure widely used in engineering currently is as follows Figure 1 As shown in the figure, when S1 and S2 are disconnected, S3 and S4 are closed. The operational amplifier (OPAMP) makes the voltages at points X and Y the same as the Vc voltage through feedback, avoiding the charge sharing effect of the parasitic capacitances at points X and Y on the Vc voltage when S1 and S2 are closed next time. Although this structure improves charge sharing, it cannot avoid the current mismatch between I1 and I2. Summary of the Invention

[0005] The embodiments of the present application provide a charge pump circuit and a phase-locked loop circuit, which can solve the current mismatch problem existing in the current charge pump circuit.

[0006] The embodiments of the present application also provide a charge pump circuit, which may include: a charge and discharge module, an operational amplifier, a sampling control circuit, and a voltage sampling and holding module;

[0007] The charge and discharge module is configured to enter a charge and discharge state of a filter capacitor at the subsequent stage of the charge pump circuit or enter a sampled state for the operational amplifier to perform voltage sampling under the control of a preset phase-frequency detector PFD; wherein, the PFD controls the state (charge and discharge state or sampled state) of the charge and discharge module according to the feedback signal of the VCO; the voltage of the filter capacitor is used to control the frequency of the voltage-controlled oscillator VCO.

[0008] The sampling control circuit is configured to obtain the output result of the PFD, generate a corresponding control signal according to the output result of the PFD, and control the operational amplifier to turn on to start voltage sampling or control the operational amplifier to turn off to stop voltage sampling according to the control signal; wherein, the output result of the PFD is used to control the charge and discharge module to be in the charge and discharge state or the sampled state;

[0009] The operational amplifier is configured to sample the voltages at a plurality of charge and discharge connection ends on the charge and discharge path in the charge and discharge module after being turned on under the control of the sampling control circuit, and output a corresponding bias voltage according to the obtained sampling voltage, and input the bias voltage to the bias voltage input end of the charge and discharge module to realize negative feedback through the bias voltage and control the voltages at the plurality of charge and discharge connection ends to be consistent;

[0010] The voltage sampling and holding module is configured to sample the bias voltage output by the operational amplifier when the charge and discharge module is in the sampled state, hold the sampled bias voltage when the charge and discharge module enters the charge and discharge state, and input the held bias voltage to the bias voltage input end of the charge and discharge module to maintain the current in the charge and discharge module unchanged.

[0011] In an exemplary embodiment of the present application, the charge and discharge connection ends may include: a first charge and discharge connection end Vc and a second charge and discharge connection end Vm;

[0012] The multiple charge and discharge paths of the charge and discharge module may include: a first charge path, a second charge path, a first discharge path, and a second discharge path;

[0013] Wherein, the first charge path and the first discharge path are connected to the first charge and discharge connection end Vc, and the second charge path and the second discharge path are connected to the second charge and discharge connection end Vm;

[0014] The first charge and discharge connection end Vc is connected to the negative input end of the operational amplifier, and the second charge and discharge connection end Vm is connected to the positive input end of the operational amplifier.

[0015] In an exemplary embodiment of the present application, the charge and discharge module may include: a first P-type MOS transistor MP1, a first N-type MOS transistor MN1, a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4;

[0016] The source of the first P-type MOS transistor MP1 is connected to the power supply. The gate serves as the bias voltage input terminal and is connected to the voltage output terminal of the operational amplifier and the voltage output terminal of the voltage sampling and holding module. The drain is respectively connected to the first terminal of the second switch S2 and the first terminal of the fourth switch S4;

[0017] The second terminal of the second switch S2 is connected to the first charge and discharge connection terminal Vc; the second terminal of the fourth switch S4 is connected to the second charge and discharge connection terminal Vm;

[0018] The first P-type MOS transistor MP1 and the second switch S2 form the first charging path; the first P-type MOS transistor MP1 and the fourth switch S4 form the second charging path;

[0019] The source of the first N-type MOS transistor MN1 is grounded. The gate is connected to a preset bias voltage Vbn. The drain is respectively connected to the first terminal of the first switch S1 and the first terminal of the third switch S3;

[0020] The second terminal of the first switch S1 is connected to the first charge and discharge connection terminal Vc; the second terminal of the third switch S3 is connected to the second charge and discharge connection terminal Vm;

[0021] The first N-type MOS transistor MN1 and the first switch S1 form the first discharging path; the first N-type MOS transistor MN1 and the third switch S3 form the second discharging path.

[0022] In an exemplary embodiment of the present application, the voltage sampling and holding module may include: a fifth switch S5 and a first capacitor; the controlled terminal of the fifth switch S5 serves as the first controlled terminal of the voltage sampling and holding module;

[0023] The voltage output terminal of the operational amplifier is connected to the bias voltage input terminal of the charge and discharge module through the fifth switch S5; wherein, the first terminal of the fifth switch serves as the sampling input terminal of the voltage sampling and holding module and is connected to the voltage output terminal of the operational amplifier; the second terminal of the fifth switch is connected to the gate of the first P-type MOS transistor MP1;

[0024] The first terminal of the first capacitor serves as the bias voltage output terminal of the voltage sampling and holding module and is connected to the gate of the first P-type MOS transistor MP1. The second terminal of the first capacitor is connected to the power supply;

[0025] The first terminal of the first capacitor serves as the voltage output terminal of the voltage sampling and holding module for outputting the held bias voltage.

[0026] In an exemplary embodiment of the present application, the sampling control circuit includes: a logic operation circuit;

[0027] The logic operation circuit obtains the output result of the PFD, including:

[0028] Obtaining the voltage output by the PFD for controlling the on / off states of different charge / discharge paths of the charge / discharge module; the on / off states of the different charge / discharge paths are used to indicate that the charge / discharge module is in the charge / discharge state or the sampled state;

[0029] The logic operation circuit generates a corresponding control signal according to the output result of the PFD, and controls the operational amplifier to conduct to start voltage sampling or controls the operational amplifier to disconnect to stop voltage sampling according to the control signal, including:

[0030] Performing a logic calculation on the voltages on the different charge / discharge paths collected, obtaining the control signal of the fifth switch S5, and controlling the fifth switch S5 to close through the control signal, so as to control the operational amplifier to conduct, or controlling the fifth switch S5 to open through the control signal, so as to control the operational amplifier to disconnect.

[0031] In an exemplary embodiment of the present application, the charge / discharge module enters the charge / discharge state of the filter capacitor at the rear stage of the charge pump circuit or enters the sampled state for the operational amplifier to perform voltage sampling under the control of a preset phase frequency detector PFD, which may include:

[0032] When controlling the second switch S2 and the first switch S1 to be alternately opened; and, when controlling the third switch S3 and the fourth switch S4 to be alternately opened, controlling the charge / discharge module to enter the charge / discharge state;

[0033] When controlling the second switch S2 and the first switch S1 to be both opened and controlling the third switch S3 and the fourth switch S4 to be both closed, controlling the charge / discharge module to enter the sampled state;

[0034] When controlling the second switch S2 and the first switch S1 to be both closed and controlling the third switch S3 and the fourth switch S4 to be both opened, this state is short-lived, and the short pulse of this state is used to eliminate the phase discrimination dead zone. At this time, the charge / discharge module does not perform charge / discharge operations on the rear-stage capacitor, and the rear-stage capacitor maintains the original voltage unchanged.

[0035] In an exemplary embodiment of the present application, the logic operation circuit may include: a second AND gate;

[0036] One input terminal of the second AND gate is set to input the first voltage upb output by the PFD for controlling the on / off state of the fourth switch S4; the first voltage upb is used to control the on / off state of the second charging path;

[0037] The other input terminal of the second AND gate is set to input the second voltage dnb output by the PFD for controlling the on / off state of the third switch S4; the second voltage dnb is used as the one for controlling the on / off state of the second discharging path;

[0038] The output terminal of the second AND gate serves as the output terminal of the sampling control circuit and is connected to the fifth switch S5, and is set to control the opening or closing of the fifth switch S5 through the output signal of the second AND gate.

[0039] In an exemplary embodiment of the present application, the charge pump circuit may further include: an initial bias voltage providing module;

[0040] The bias voltage output terminal of the initial bias voltage providing module is connected to the bias voltage input terminal of the charge and discharge module, and is set to provide the bias voltage for the charge and discharge module when the phase-locked loop has not reached the locked state.

[0041] In an exemplary embodiment of the present application, the bias voltage output terminal of the initial bias voltage providing module is connected to the bias voltage input terminal of the charge and discharge module through the voltage sampling and holding module;

[0042] The voltage sampling and holding module is further set to control the initial bias voltage providing module to disconnect the connection with the charge and discharge module before sampling the bias voltage of the operational amplifier.

[0043] In an exemplary embodiment of the present application, the sampling control circuit may further be set to: detect whether the phase-locked loop has reached the locked state, and jointly generate the control signal and the on / off control signal of the initial bias voltage providing module according to the detection result of whether the phase-locked loop has reached the locked state and the output result of the PFD; before sampling the bias voltage of the operational amplifier, control the initial bias voltage providing module to disconnect the connection with the charge and discharge module according to the on / off control signal.

[0044] In an exemplary embodiment of the present application, the sampling control circuit may include: a lock detection circuit and a logic operation circuit;

[0045] The lock detection circuit is set to detect whether the phase-locked loop has reached the locked state and output the detection result; the detection result includes a first detection result for indicating that the phase-locked loop has reached the locked state and a second detection result for indicating that the phase-locked loop has not reached the locked state;

[0046] The logic operation circuit is configured to obtain the output result of the PFD, generate the control signal based on the detection result of whether the phase-locked loop reaches the locked state and the output result of the PFD, and control the operational amplifier to turn on to start voltage sampling or control the operational amplifier to turn off to stop voltage sampling according to the control signal; and before sampling the bias voltage of the operational amplifier, control the initial bias voltage providing module to disconnect the connection with the charge and discharge module according to the on / off control signal.

[0047] In an exemplary embodiment of the present application, the lock detection circuit detects whether the phase-locked loop reaches the locked state and outputs a detection result, which may include:

[0048] Obtain the feedback signal of the VCO, divide the frequency of the feedback signal, and obtain the signal phase φ of the divided signal div , and use the signal phase φ div Compare with the preset reference source phase φ re f. When the phase difference between the signal phase φ div and the preset reference source phase φ re f is less than the preset phase difference threshold, output the first detection result; when the phase difference between the signal phase φ div and the preset reference source phase φ re f is greater than or equal to the preset phase difference threshold, output the second detection result;

[0049] The logic operation circuit obtains the output result of the PFD, which may include:

[0050] Obtain the voltage output by the PFD for controlling the on / off states of different charge and discharge paths of the charge and discharge module; the on / off states of the different charge and discharge paths are used to indicate that the charge and discharge module is in the charge and discharge state or the sampled state.

[0051] In an exemplary embodiment of the present application, the logic operation circuit obtains the voltage output by the PFD for controlling the on / off states of different charge and discharge paths of the charge and discharge module, which may include:

[0052] Obtain the first voltage upb output by the PFD for controlling the on / off of the fourth switch S4; the first voltage upb is used as the voltage for controlling the on / off state of the second charge path;

[0053] Obtain the second voltage dnb output by the PFD for controlling the on / off of the third switch S3; the second voltage dnb is used as the voltage for controlling the on / off state of the second discharge path.

[0054] In an exemplary embodiment of the present application, the initial bias voltage providing module may include: a second P-type MOS transistor MP2 and a second N-type MOS transistor MN2;

[0055] The source of the second P-type MOS transistor MP2 is connected to the power supply, and the drain of the second P-type MOS transistor MP2 is connected to the gate of the second P-type MOS transistor MP2 and the drain of the second N-type MOS transistor MN2;

[0056] The gate of the second P-type MOS transistor MP2 serves as the bias voltage output terminal of the initial bias voltage providing module and is connected to the bias voltage input terminal of the charge and discharge module;

[0057] The source of the second N-type MOS transistor MN2 is grounded; the gate of the second N-type MOS transistor MN2 is connected to a preset bias voltage Vbn.

[0058] In an exemplary embodiment of the present application, the voltage sampling and holding module may include: a fifth switch S5, a sixth switch S6, and a first capacitor; the controlled terminal of the fifth switch S5 serves as the first controlled terminal of the voltage sampling and holding module; the controlled terminal of the sixth switch S6 serves as the second controlled terminal of the voltage sampling and holding module;

[0059] The voltage output terminal of the operational amplifier is connected to the bias voltage input terminal of the charge and discharge module through the fifth switch S5;

[0060] The bias voltage output terminal of the initial bias voltage providing module is connected to the bias voltage input terminal of the charge and discharge module through the sixth switch S6;

[0061] The first end of the first capacitor is connected to the bias voltage input terminal of the charge and discharge module, and the second end of the first capacitor is connected to the power supply VDD;

[0062] The first end of the first capacitor serves as the voltage output terminal of the voltage sampling and holding module for outputting the held bias voltage;

[0063] The gate of the second P-type MOS transistor MP2 is connected to the bias voltage input terminal of the charge and discharge module through the sixth switch.

[0064] In an exemplary embodiment of the present application, the lock detection circuit may include: a first delay unit, a second delay unit, a first flip-flop, and a second flip-flop; the logic operation circuit may include: a first AND gate, a second AND gate, and a first NOT gate; the difference between the second delay duration of the second delay unit and the first delay duration of the first delay unit is a preset phase difference threshold;

[0065] The input end of the first delay unit is set to input the phase φ of the reference source ref , and the output end of the first delay unit is respectively connected to the first input end of the first flip-flop and the first input end of the second flip-flop;

[0066] The input end of the second delay unit is set to input the phase φ of the signal obtained by dividing the feedback signal of the VCO div , and the output end of the second delay unit is respectively connected to the second input end of the first flip-flop and the second input end of the second flip-flop;

[0067] The output end of the first flip-flop is connected to the first input end of the first AND gate;

[0068] The output end of the second flip-flop is connected to the second input end of the first AND gate;

[0069] The output end of the first AND gate is connected to the first input end of the second AND gate;

[0070] The second input end of the second AND gate is set to input the first voltage upb output by the PFD for controlling the on / off of the fourth switch S4; the first voltage upb is used to control the on / off state of the second charging path;

[0071] The third input end of the second AND gate is set to input the second voltage dnb output by the PFD for controlling the on / off of the third switch S4; the second voltage dnb is used to control the on / off state of the second discharging path;

[0072] The output end of the second AND gate serves as the first output end of the sampling control circuit and is connected to the controlled end of the fifth switch S5, and is set to control the opening or closing of the five switches S5 through the output signal of the second AND gate;

[0073] The input end of the first NOT gate is connected to the output end of the first AND gate, and the output end of the first NOT gate serves as the second output end of the sampling control circuit and is connected to the controlled end of the sixth switch S6.

[0074] In the exemplary embodiment of the present application, the logic operation circuit jointly generates the control signal according to the detection result of whether the phase-locked loop reaches the locked state and the output result of the PFD, and controls the operational amplifier to conduct to start voltage sampling or controls the operational amplifier to disconnect to stop voltage sampling according to the control signal; and before sampling the bias voltage of the operational amplifier, controls the initial bias voltage providing module to disconnect the connection with the charge and discharge module according to the on / off control signal, including:

[0075] Perform logical calculations on the first detection result or the second detection result and the voltages on different charge and discharge paths collected, obtain the control signals for the fifth switch S5 and the sixth switch S6, control the sixth switch S6 to turn on through the control signal for the sixth switch S6, control the fifth switch S5 to close through the control signal for the fifth switch S5, thereby controlling the initial bias voltage providing module to disconnect and the operational amplifier to conduct, or control the fifth switch S5 to turn on through the control signal, thereby controlling the operational amplifier to disconnect, so as to provide a bias voltage for the charge and discharge module through the voltage sampling and holding module.

[0076] The embodiment of the present application also provides a phase-locked loop circuit, which may include: the charge pump circuit 1 described in any one of the above, a filter capacitor connected to the charge pump circuit, a phase frequency detector PFD, a voltage controlled oscillator VCO connected to the filter capacitor, and a frequency divider connecting the VCO and the PFD.

[0077] Compared with the related art, the charge pump circuit according to the embodiments of the present application may include: a charge and discharge module, an operational amplifier, a sampling control circuit, and a voltage sampling and holding module; the charge and discharge module is configured to enter a charge and discharge state of a filter capacitor at the subsequent stage of the charge pump circuit under the control of a preset phase frequency detector (PFD), or enter a sampled state for the operational amplifier to perform voltage sampling; wherein, the PFD controls the state (charge and discharge state or sampled state) of the charge and discharge module according to the feedback signal of the VCO; the voltage of the filter capacitor is used to control the frequency of a voltage controlled oscillator (VCO); the sampling control circuit is configured to obtain the output result of the PFD, generate a corresponding control signal according to the output result of the PFD, and control the operational amplifier to conduct to start voltage sampling or control the operational amplifier to disconnect to stop voltage sampling according to the control signal; wherein, the output result of the PFD is used to control the charge and discharge module to be in the charge and discharge state or the sampled state; the operational amplifier is configured to sample the voltages at a plurality of charge and discharge connection ends on the charge and discharge path in the charge and discharge module after being conducted under the control of the sampling control circuit, and output a corresponding bias voltage according to the obtained sampling voltage, and input the bias voltage to the bias voltage input end of the charge and discharge module to implement negative feedback through the bias voltage and control the voltages at the plurality of charge and discharge connection ends to be consistent; the voltage sampling and holding module is configured to sample the bias voltage output by the operational amplifier when the charge and discharge module is in the sampled state, hold the sampled bias voltage when the charge and discharge module enters the charge and discharge state, and input the held bias voltage to the bias voltage input end of the charge and discharge module to maintain the current in the charge and discharge module unchanged. Through the solution of this embodiment, the problem of current mismatch existing in the current charge pump circuit is solved.

[0078] Other features and advantages of the present application will be described in the subsequent specification, and part of them will become obvious from the specification, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained through the solutions described in the specification and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0079] The drawings are used to provide an understanding of the technical solutions of the present application, and constitute a part of the specification. They are used together with the embodiments of the present application to explain the technical solutions of the present application, and do not constitute a limitation to the technical solutions of the present application.

[0080] Figure 1 It is a schematic structural diagram of a charge pump circuit in the related art;

[0081] Figure 2 It is a schematic structural diagram of the charge pump circuit according to the embodiment of the present application;

[0082] Figure 3 Schematic connection diagram of the charge pump circuit according to an embodiment of the present application;

[0083] Figure 4 Schematic structural diagram of the charge pump circuit including an initial bias voltage providing module according to an embodiment of the present application;

[0084] Figure 5 Schematic diagram of another sampling control circuit according to an embodiment of the present application;

[0085] Figure 6 Signal waveform diagram of the lock detector circuit according to an embodiment of the present application in different states;

[0086] Figure 7 Block diagram of the phase-locked loop circuit according to an embodiment of the present application. Detailed implementation manners

[0087] The present application describes multiple embodiments, but the description is exemplary rather than restrictive, and it will be obvious to those of ordinary skill in the art that there can be more embodiments and implementation schemes within the scope of the embodiments described in the present application. Although many possible feature combinations are shown in the drawings and discussed in the detailed implementation manners, many other combination ways of the disclosed features are also possible. Unless specifically restricted, any feature or element of any embodiment can be combined with any other feature or element in any other embodiment, or can replace any other feature or element in any other embodiment.

[0088] The present application includes and contemplates combinations with features and elements known to those of ordinary skill in the art. The disclosed embodiments, features, and elements of the present application can also be combined with any conventional features or elements to form a unique invention scheme defined by the claims. Any feature or element of any embodiment can also be combined with features or elements from other invention schemes to form another unique invention scheme defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in the present application can be implemented alone or in any appropriate combination. Therefore, the embodiments are not subject to other restrictions except those made according to the appended claims and their equivalent replacements. In addition, various modifications and changes can be made within the scope of protection of the appended claims.

[0089] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not depend on the specific order of the steps described herein, the method or process should not be limited to the specific order of the steps described. As will be understood by those of ordinary skill in the art, other step sequences are possible. Therefore, the specific order of the steps set forth in the specification should not be construed as a limitation on the claims. In addition, the claims directed to the method and / or process should not be limited to performing their steps in the order written, as those skilled in the art can readily understand that these orders can vary and still remain within the spirit and scope of the embodiments of the present application.

[0090] An embodiment of the present application also provides a charge pump circuit 1, as Figure 2 shown, which may include: a charge and discharge module 11, an operational amplifier 12, a sampling control circuit 13, and a voltage sampling and holding module 14;

[0091] The state control terminal of the charge and discharge module 11 is connected to the control output terminal of a preset phase frequency detector (PFD); the charge and discharge connection terminal of the charge and discharge module 11 is connected to the input terminal of a filter capacitor at the subsequent stage; the output terminal of the filter capacitor at the subsequent stage is connected to the input terminal of a voltage controlled oscillator (VCO);

[0092] The charge and discharge module 11 may be configured to enter a charge and discharge state of the filter capacitor at the subsequent stage of the charge pump circuit under the control of the PFD, or enter a sampled state for the operational amplifier to perform voltage sampling; wherein, the PFD controls the state (charge and discharge state or sampled state) of the charge and discharge module according to the feedback signal of the VCO; the voltage of the filter capacitor is used to control the frequency of the voltage controlled oscillator VCO;

[0093] The input terminal of the sampling control circuit 13 is connected to the result output terminal of the PFD; the first output terminal of the sampling control circuit 13 is connected to the first controlled terminal of the voltage sampling and holding module 14;

[0094] The sampling control circuit 13 may be configured to obtain the output result of the PFD, generate a corresponding control signal according to the output result of the PFD, and control the operational amplifier to turn on to start voltage sampling or control the operational amplifier to turn off to stop voltage sampling according to the control signal;

[0095] The voltage output terminal of the operational amplifier 12 is connected to the bias voltage input terminal of the charge and discharge module 11 through the voltage sampling and holding module 14; the positive input terminal and the negative input terminal of the operational amplifier 12 are respectively connected to different charge and discharge connection terminals of the charge and discharge module 11;

[0096] The operational amplifier 12 can be set to sample the voltages at multiple charge and discharge connection ends on the charge and discharge path in the charge and discharge module 11 after being turned on under the control of the sampling control circuit 13, and output a corresponding bias voltage according to the obtained sampled voltage, and input the bias voltage to the bias voltage input end of the charge and discharge module 11, so as to achieve negative feedback through the bias voltage and control the voltages at the multiple charge and discharge connection ends to be consistent.

[0097] The sampling input end of the voltage sampling and holding module 14 is connected to the voltage output end of the operational amplifier 12, and the bias voltage output end of the voltage sampling and holding module 14 is connected to the bias voltage input end of the charge and discharge module 11.

[0098] The voltage sampling and holding module 14 is configured to sample the bias voltage output by the operational amplifier 12 when the charge and discharge module 11 is in the sampled state, hold the sampled bias voltage when the charge and discharge module 11 enters the charge and discharge state, and input the held bias voltage to the bias voltage input end of the charge and discharge module 11 to keep the current in the charge and discharge module 11 unchanged.

[0099] In an exemplary embodiment of the present application, a specific embodiment of the charge pump circuit of the solution of the embodiment of the present application is given below. As Figure 3 shown, the circuit of this embodiment may include an operational amplifier 12, a charging current branch (i.e., the charge and discharge module 11, i.e., OPAMP) and multiple switches. Among them, the multiple switches (such as S1_S4) in the charge and discharge module 11 have the same function as those in the traditional charge pump circuit. The fifth switch S5 and the first capacitor Cs in the voltage sampling and holding module 14 realize the function of sampling and holding. The fifth switch S5 and the first capacitor Cs sample the output voltage of the operational amplifier 12 for a period of time in each reference frequency period and hold it on the first capacitor Cs to keep the current of MP1 unchanged. The function of the operational amplifier 12 is to generate a suitable bias voltage Vbp through negative feedback to maintain Vm and Vc equal, thereby eliminating the charge sharing effect. When the charge and discharge module 11 is in the sampling stage (i.e., in the sampled state), the current of MP1 all flows into MN1. At this time, it can be ensured that the currents of the two transistors (MP1 and MN1) are perfectly matched. At this time, the bias voltage Vbp of MP1 is recorded. When the charge pump charges or discharges the filter capacitor at the subsequent stage, and when the first switch S1 and the second switch S2 are turned on simultaneously, this voltage Vbp is used to bias MP1, and the current mismatch can be well eliminated. The circuit recharges the first capacitor Cs in each cycle, thereby continuously updating and adjusting the magnitude of the current of MP1 and avoiding the decrease of the Vbp voltage caused by leakage.

[0100] In an exemplary embodiment of the present application, the following will introduce in detail the Figure 3 composition structure of the charge pump circuit in

[0101] In an exemplary embodiment of the present application, the charge and discharge connection terminals may include: a first charge and discharge connection terminal Vc and a second charge and discharge connection terminal Vm;

[0102] The multiple charge and discharge paths of the charge and discharge module 11 may include: a first charge path, a second charge path, a first discharge path, and a second discharge path;

[0103] Among them, the first charge path and the first discharge path are connected to the first charge and discharge connection terminal Vc, and the second charge path and the second discharge path are connected to the second charge and discharge connection terminal Vm;

[0104] The first charge and discharge connection terminal Vc is connected to the negative input terminal of the operational amplifier, and the second charge and discharge connection terminal Vm is connected to the positive input terminal of the operational amplifier.

[0105] In an exemplary embodiment of the present application, the charge and discharge module 11 may include: a first P-type MOS transistor MP1, a first N-type MOS transistor MN1, a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4;

[0106] The source of the first P-type MOS transistor MP1 is connected to the power supply, the gate serves as the bias voltage input terminal, and is connected to the voltage output terminal of the operational amplifier and the voltage output terminal of the voltage sampling and holding module. The drain is respectively connected to the first end of the second switch S2 and the first end of the fourth switch S4;

[0107] The second end of the second switch S2 is connected to the first charge and discharge connection terminal Vc; the second end of the fourth switch S4 is connected to the second charge and discharge connection terminal Vm;

[0108] The first P-type MOS transistor MP1 and the second switch S2 constitute the first charge path; the first P-type MOS transistor MP1 and the fourth switch S4 constitute the second charge path;

[0109] The source of the first N-type MOS transistor MN1 is grounded, the gate is connected to a preset bias voltage Vbn, and the drain is respectively connected to the first end of the first switch S1 and the first end of the third switch S3;

[0110] The second end of the first switch S1 is connected to the first charge and discharge connection terminal Vc; the second end of the third switch S3 is connected to the second charge and discharge connection terminal Vm;

[0111] The first N-type MOS transistor MN1 and the first switch S1 form the first discharge path; the first N-type MOS transistor MN1 and the third switch S3 form the second discharge path.

[0112] In an exemplary embodiment of the present application, the state control terminal of the charge and discharge module 11 may refer to the controlled terminals of the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4, and this controlled terminal can control the opening or closing of the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4.

[0113] In an exemplary embodiment of the present application, the voltage sampling and holding module 14 may include: a fifth switch S5 and a first capacitor; the controlled terminal of the fifth switch S5 serves as the first controlled terminal of the voltage sampling and holding module;

[0114] The voltage output terminal of the operational amplifier 12 is connected to the bias voltage input terminal of the charge and discharge module 11 through the fifth switch S5; wherein, the first end of the fifth switch serves as the sampling input terminal of the voltage sampling and holding module 14 and is connected to the voltage output terminal of the operational amplifier 12; the second end of the fifth switch is connected to the gate of the first P-type MOS transistor MP1;

[0115] The first end of the first capacitor serves as the bias voltage output terminal of the voltage sampling and holding module and is connected to the gate of the first P-type MOS transistor MP1, and the second end of the first capacitor is connected to the power supply;

[0116] The first end of the first capacitor serves as the voltage output terminal of the voltage sampling and holding module 14 for outputting the held bias voltage.

[0117] In an exemplary embodiment of the present application, the operational amplifier 12 samples or stops sampling the charge and discharge module 11 under the control of the sampling control circuit 13; wherein, when the sampling control circuit 13 controls the operational amplifier is determined by detecting the output result of the PFD. Among them, the output result of the PFD can be used to control the state of the charge and discharge module 11 (whether it is in the charge and discharge state or in the sampled state), and according to the state of the charge and discharge module 11, it can be determined when to control the operational amplifier. Among them, when in the sampled state, the operational amplifier 12 can be controlled to conduct and start sampling, and when in the charge and discharge state, the operational amplifier 12 can be controlled to disconnect and stop sampling.

[0118] In an exemplary embodiment of the present application, the sampling control circuit 13 includes: a logic operation circuit;

[0119] The logic operation circuit obtains the output result of the PFD, including:

[0120] Obtain the voltage output by the PFD for controlling the on / off states of different charge / discharge paths of the charge / discharge module; the on / off states of the different charge / discharge paths are used to indicate that the charge / discharge module is in the charge / discharge state or the sampled state;

[0121] The logic operation circuit generates corresponding control signals according to the output result of the PFD, and controls the operational amplifier to conduct to start voltage sampling or controls the operational amplifier to disconnect to stop voltage sampling according to the control signals, including:

[0122] Perform logical calculation on the voltages on the different charge / discharge paths collected, obtain the control signal of the fifth switch S5, and control the fifth switch S5 to close through the control signal, so as to control the operational amplifier to conduct, or control the fifth switch S5 to open through the control signal, so as to control the operational amplifier to disconnect.

[0123] In an exemplary embodiment of the present application, based on the circuit embodiment of the charge / discharge module 11 described above, the charge / discharge module enters the charge / discharge state of the filter capacitor at the subsequent stage of the charge pump circuit or enters the sampled state for the operational amplifier to perform voltage sampling under the control of a preset phase frequency detector PFD, which may include:

[0124] When controlling the second switch S2 and the first switch S1 to be selectively opened; and, when controlling the third switch S3 and the fourth switch S4 to be selectively opened, control the charge / discharge module to enter the charge / discharge state;

[0125] When controlling the second switch S2 and the first switch S1 to be both opened and controlling the third switch S3 and the fourth switch S4 to be both closed, control the charge / discharge module to enter the sampled state;

[0126] When controlling the second switch S2 and the first switch S1 to be both closed and controlling the third switch S3 and the fourth switch S4 to be both opened, this state is short-lived, and the short pulse of this state is used to eliminate the phase discrimination dead zone. At this time, the charge / discharge module does not perform charge / discharge operations on the subsequent-stage capacitor, and the subsequent-stage capacitor maintains the original voltage unchanged.

[0127] In an exemplary embodiment of the present application, based on the circuit embodiment of the charge / discharge module 11 described above, the obtaining of the voltage output by the PFD for controlling the on / off states of different charge / discharge paths of the charge / discharge module 11 may include:

[0128] Obtain the first voltage upb output by the PFD for controlling the on / off of the fourth switch S4; the first voltage upb is used as the voltage for controlling the on / off state of the second charge path;

[0129] Obtain a second voltage dnb of the PFD output for controlling the first end of the third switch S3; the second voltage dnb is used as a voltage for controlling the on / off state of the second discharge path.

[0130] In an exemplary embodiment of the present application, when the charge / discharge module 11 is in different states (charge / discharge state or sampled state), the on / off states of the switches on different charge / discharge paths are different, and the voltage values output by the PFD for the switches on different charge / discharge paths are also different. Therefore, the state of the charge / discharge module 11 can be determined according to the output voltage of the PFD for the switches on different charge / discharge paths.

[0131] In an exemplary embodiment of the present application, the sampling control circuit 13 can perform logical calculations on the obtained output voltage of the PFD, and finally obtain a control signal for controlling the operational amplifier.

[0132] In an exemplary embodiment of the present application, as Figure 3 shown, the logic operation circuit can include: a second AND gate 136;

[0133] One input terminal of the second AND gate 136 is set to input a first voltage upb of the PFD output for controlling the on / off of the fourth switch S4; the first voltage upb is used to control the on / off state of the second charge path;

[0134] The other input terminal of the second AND gate 136 is set to input a second voltage dnb of the PFD output for controlling the on / off of the third switch S4; the second voltage dnb is used to control the on / off state of the second discharge path;

[0135] The output terminal of the second AND gate 136 serves as the output terminal of the sampling control circuit and is connected to the fifth switch S5, and is set to control the opening or closing of the fifth switch S5 through the output signal of the second AND gate 136.

[0136] In an exemplary embodiment of the present application, as Figure 4 shown, the charge pump circuit may further include: an initial bias voltage providing module 15;

[0137] The bias voltage output terminal of the initial bias voltage providing module 15 is connected to the bias voltage input terminal of the charge / discharge module 11, and is set to provide the bias voltage for the charge / discharge module 11 when the phase-locked loop has not reached the locked state.

[0138] In an exemplary embodiment of the present application, the bias voltage output terminal of the initial bias voltage providing module 15 is connected to the bias voltage input terminal of the charge / discharge module 11 through the voltage sampling and holding module 14;

[0139] The voltage sampling and holding module 14 is further configured to control the initial bias voltage providing module 15 to disconnect the connection with the charge and discharge module 11 before sampling the bias voltage of the operational amplifier 12.

[0140] In an exemplary embodiment of the present application, after starting to sample the bias voltage of the operational amplifier 12, the initial bias voltage providing module 15 no longer functions (no longer provides a bias voltage for the charge and discharge module 11), and thereafter, the voltage sampling and holding module 14 can provide the bias voltage.

[0141] In an exemplary embodiment of the present application, the sampling control circuit 13 can also be configured to: detect whether the phase-locked loop reaches a locked state, and jointly generate the control signal and the on / off control signal of the initial bias voltage providing module according to the detection result of whether the phase-locked loop reaches a locked state and the output result of the PFD; before sampling the bias voltage of the operational amplifier, control the initial bias voltage providing module to disconnect the connection with the charge and discharge module according to the on / off control signal.

[0142] In an exemplary embodiment of the present application, the operational amplifier 12 samples or stops sampling the charge and discharge module 11 under the control of the sampling control circuit 13; wherein, when the sampling control circuit 13 controls the operational amplifier is determined by detecting the magnitude of the phase difference between the output result of the PFD and the feedback signal of the VCO circuit. Among them, the output result of the PFD can also be used to control the state of the charge and discharge module 11 (whether it is in a charge / discharge state or in a sampled state, and when in the sampled state, the operational amplifier 12 can be controlled to conduct and start sampling); the magnitude of the phase difference of the feedback signal of the VCO circuit can reflect whether the phase-locked loop reaches a locked state; when the phase-locked loop reaches a locked state, when the phase-locked loop does not reach a locked state, the operational amplifier can be controlled to stop sampling.

[0143] In an exemplary embodiment of the present application, the sampling control circuit 13 can perform a logical calculation on the obtained output voltage of the PFD and the obtained phase comparison result, and finally obtain a control signal for controlling the operational amplifier and the initial bias voltage providing module 15.

[0144] In an exemplary embodiment of the present application, the sampling control circuit 13 may include: a lock detection circuit and a logic operation circuit;

[0145] The lock detection circuit is configured to detect whether the phase-locked loop reaches a locked state and output a detection result; the detection result includes a first detection result for indicating that the phase-locked loop reaches a locked state, and a second detection result for indicating that the phase-locked loop does not reach a locked state;

[0146] The logic operation circuit is configured to obtain the output result of the PFD, generate the control signal based on the detection result of whether the phase-locked loop reaches the locked state and the output result of the PFD, and control the operational amplifier to turn on to start voltage sampling or control the operational amplifier to turn off to stop voltage sampling according to the control signal; and before sampling the bias voltage of the operational amplifier, control the initial bias voltage providing module to disconnect the connection with the charge and discharge module according to the on-off control signal.

[0147] In an exemplary embodiment of the present application, the lock detection circuit detects whether the phase-locked loop reaches the locked state and outputs a detection result, which may include:

[0148] Obtain the feedback signal of the VCO, divide the frequency of the feedback signal, and obtain the signal phase φ of the divided signal div , and use the signal phase φ div to compare with the preset reference source phase φ re f. When the phase difference between the signal phase φ div and the preset reference source phase φ re f is less than the preset phase difference threshold, output the first detection result; when the phase difference between the signal phase φ div and the preset reference source phase φ re f is greater than or equal to the preset phase difference threshold, output the second detection result;

[0149] The logic operation circuit obtains the output result of the PFD, which may include:

[0150] Obtain the voltage output by the PFD for controlling the on-off states of different charge and discharge paths of the charge and discharge module; the on-off states of the different charge and discharge paths are used to indicate that the charge and discharge module is in the charge and discharge state or the sampled state.

[0151] In an exemplary embodiment of the present application, the logic operation circuit obtains the voltage output by the PFD for controlling the on-off states of different charge and discharge paths of the charge and discharge module, which may include:

[0152] Obtain the first voltage upb output by the PFD for controlling the on-off of the fourth switch S4; the first voltage upb is used as the voltage for controlling the on-off state of the second charge path.

[0153] Obtain the second voltage dnb output by the PFD for controlling the on / off state of the third switch S3; the second voltage dnb serves as the voltage for controlling the on / off state of the second discharge path. In an exemplary embodiment of the present application, the initial bias voltage providing module 15 may include: a second P-type MOS transistor MP2 and a second N-type MOS transistor MN2;

[0154] The source of the second P-type MOS transistor MP2 is connected to the power supply, and the drain of the second P-type MOS transistor MP2 is connected to the gate of the second P-type MOS transistor MP2 and the drain of the second N-type MOS transistor MN2;

[0155] The gate of the second P-type MOS transistor MP2 serves as the bias voltage output terminal of the initial bias voltage providing module and is connected to the bias voltage input terminal of the charge and discharge module;

[0156] The source of the second N-type MOS transistor MN2 is grounded; the gate of the second N-type MOS transistor MN2 is connected to a preset bias voltage Vbn.

[0157] In an exemplary embodiment of the present application, when there is an initial bias voltage providing module 15, before sampling the bias voltage of the operational amplifier 12, the sampling control circuit 13-1 (this sampling control circuit 13-1 is different from the sampling control circuit 13 in the charge pump circuit when there is no initial bias voltage providing module 15 described above and can be regarded as an optimization of the aforementioned sampling control circuit 13) can control the voltage sampling and holding module 14-1 (this voltage sampling and holding module 14-1 is different from the voltage sampling and holding module 14 in the charge pump circuit when there is no initial bias voltage providing module 15 described above and can be regarded as an optimization of the aforementioned voltage sampling and holding module 14) to disconnect the initial bias voltage providing module 15.

[0158] In an exemplary embodiment of the present application, as Figure 4 shown, the voltage sampling and holding module 14-1 may include: a fifth switch S5, a sixth switch S6, and a first capacitor Cs; the controlled terminal of the fifth switch S5 serves as the first controlled terminal of the voltage sampling and holding module; the controlled terminal of the sixth switch S6 serves as the second controlled terminal of the voltage sampling and holding module;

[0159] The voltage output terminal of the operational amplifier 12 is connected to the bias voltage input terminal of the charge and discharge module through the fifth switch S5; wherein, the first end of the fifth switch serves as the sampling input terminal of the voltage sampling and holding module and is connected to the voltage output terminal of the operational amplifier; the second end of the fifth switch S5 is connected to the gate of the first P-type MOS transistor MP1;

[0160] The bias voltage output terminal of the initial bias voltage providing module 15 is connected to the bias voltage input terminal of the charge and discharge module 11 through the sixth switch S6; wherein, the first end of the sixth switch is connected to the gate of the second P-type MOS transistor MP2; the second end of the sixth switch S6 is connected to the gate of the first P-type MOS transistor MP1;

[0161] The first end of the first capacitor Cs is connected to the bias voltage input terminal of the charge and discharge module 11, and the second end of the first capacitor Cs is connected to the power supply VDD; wherein, the first end of the first capacitor Cs is connected to the gate of the first P-type MOS transistor MP1, and the second end of the first capacitor is connected to the power supply VDD;

[0162] The first end of the first capacitor Cs serves as the voltage output terminal of the voltage sampling and holding module 14 for outputting the held bias voltage;

[0163] The gate of the second P-type MOS transistor MP2 is connected to the bias voltage input terminal of the charge and discharge module 11 through the sixth switch S6.

[0164] In an exemplary embodiment of the present application, the logic operation circuit jointly generates the control signal according to the detection result of whether the phase-locked loop reaches the locked state and the output result of the PFD, and controls the operational amplifier to conduct to start voltage sampling or controls the operational amplifier to disconnect to stop voltage sampling according to the control signal; and before sampling the bias voltage of the operational amplifier, controls the initial bias voltage providing module to disconnect the connection with the charge and discharge module according to the on-off control signal, including:

[0165] Performing a logic calculation on the first detection result or the second detection result and the voltages on different charge and discharge paths collected to obtain the control signals of the fifth switch S5 and the sixth switch S6, controlling the sixth switch S6 to open through the control signal of the sixth switch S6, controlling the fifth switch S5 to close through the control signal of the fifth switch S5, thereby controlling the initial bias voltage providing module to disconnect and controlling the operational amplifier to conduct, or controlling the fifth switch S5 to open through the control signal to control the operational amplifier to disconnect, so as to provide a bias voltage for the charge and discharge module through the voltage sampling and holding module.

[0166] In an exemplary embodiment of the present application, as Figure 5As shown, the sampling control circuit may include: a first delay unit 131, a second delay unit 132, a first flip-flop 133, and a second flip-flop 134; the logic operation circuit may include: a first AND gate 135, a second AND gate 136, and a first NOT gate 137; the difference between the second delay duration of the second delay unit 132 and the first delay duration of the first delay unit 131 is a preset phase difference threshold;

[0167] The input end of the first delay unit 131 is set to input the reference source phase φ ref , and the output end of the first delay unit 131 is respectively connected to the first input end of the first flip-flop 133 and the first input end of the second flip-flop 134;

[0168] The input end of the second delay unit 132 is set to input the phase φ of the signal after frequency division of the feedback signal of the VCO div , and the output end of the second delay unit 132 is respectively connected to the second input end of the first flip-flop 133 and the second input end of the second flip-flop 134;

[0169] The output end of the first flip-flop 133 is connected to the first input end of the first AND gate 135;

[0170] The output end of the second flip-flop 134 is connected to the second input end of the first AND gate 135;

[0171] The output end of the first AND gate 135 is connected to the first input end of the second AND gate 136;

[0172] The second input end of the second AND gate 136 is set to input the first voltage upb output by the PFD for controlling the on / off of the fourth switch S4; the first voltage upb is used to control the on / off state of the second charging path;

[0173] The third input end of the second AND gate 136 is set to input the second voltage dnb output by the PFD for controlling the on / off of the third switch S4; the second voltage dnb is used to control the on / off state of the second discharging path;

[0174] The output end of the second AND gate 136 serves as the first output end of the sampling control circuit and is connected to the controlled end of the fifth switch S5, and is set to control the opening or closing of the five switches S5 through the output signal of the second AND gate 136;

[0175] The input end of the first NOT gate 137 is connected to the output end of the first AND gate 135, and the output end of the first NOT gate 137 serves as the second output end of the sampling control circuit 13 and is connected to the controlled end of the sixth switch S6.

[0176] In an exemplary embodiment of the present application, the lock detection circuit may be composed of two delay units (a first delay unit 131 and a second delay unit 132) and two flip - flops (a first flip - flop 133 and a second flip - flop 134). The delay durations of the two delay units may be T and 2T respectively (such that the phase difference threshold is T), and the two delay units may each be composed of a plurality of inverters. Wherein, ctr is the AND logic of the three signals upb, dnb, and lock. When φ ref and φ div have a phase difference less than T (a preset phase difference threshold), it is considered that the two signals are close to being locked, and the output of lock can be at a high level; when the phase difference between φ ref and φ div is greater than T, the output of lock can be at a low level. In an exemplary embodiment of the present application, when the phase φ ref of the reference source of the phase - locked loop and the phase φ div of the signal after feedback frequency division differ by more than T, at this time lockb is at a high level, while ctr is at a low level, switch S5 is turned off, and switch S6 is turned on. At this time, the voltage of Vbp comes from the Vgs voltage generated by the diode connection of MP2 tube, and the current matching circuit (i.e., operational amplifier 12) in the circuit does not work.

[0177] In an exemplary embodiment of the present application, when the phase φ ref of the reference source of the phase - locked loop and the phase φ div of the signal after feedback frequency division differ by less than T, lock is at a high level, lockb is at a low level, at this time switch S6 is turned off, and the left - hand MP1 circuit no longer functions. The current matching circuit (i.e., operational amplifier 12) starts to work. When both switch S1 and S2 are turned off and both switch S3 and S4 are turned on, the control signal ctr of S5 is at a high level, and S5 is in a conducting state. At this time, it is in the sampling stage. The negative feedback effect of operational amplifier 12 makes the voltage at the Vm point and the voltage at the Vc point approximately equal, so that the voltages of X and Y are approximately equal to the voltage at the VC point to avoid charge sharing. When φ ref and φ div are not completely aligned, one of S1 and S2 is turned off and the other is turned on, that is, when the charge pump charges or discharges externally, at this time one of upb and dnb will be at a low level. Since ctr is the AND logic of the three signals upb, dnb, and lock, ctr is at a low potential at this time, switch S5 is turned off, and the circuit enters the holding state (at this time, the charge - discharge module 11 is in the charge - discharge state), that is, the first capacitor Cs will hold the voltage of Vbp at the moment when S5 is turned off. When both up and dn signals are at a high level, both upb and dnb signals are at a low level. At this time, the circuit maintains the original holding state, and the operation of this holding state is the same as the state after the phase - locked loop is locked. At this time, φref and φ div When φ and φ are perfectly aligned, the inherent pulse turns on both switches S1 and S2 and turns off both switches S3 and S4. Vbp maintains the previous sampled voltage value unchanged, and the output voltage of operational amplifier 12 has no effect. The small changes in the voltages at the Vm and Vc points do not affect the current matching.

[0178] In an exemplary embodiment of the present application, as Figure 6 shown, it is the signal waveform of the lock detection circuit in different states, where C refers to sampling and B refers to holding.

[0179] In an exemplary embodiment of the present application, Figure 5 the left figure shows the situation when there is a large phase difference between φ ref and φ div Assuming that the phase of φ ref is advanced, when both the up and dn signals are at low level, the circuit is in the sampling state. In the initial stage of sampling, there will be a building process in the loop of the phase-locked loop where the operational amplifier is located, so the Vbp voltage will have a brief oscillation. When the loop of the phase-locked loop stabilizes, the loop will control the output of the operational amplifier to charge the sampling capacitor. When the up signal first appears at high level, the logic operation circuit controls the voltage acquisition and holding circuit to enter the holding state. At this time, the sampling ends, the voltage on the sampling capacitor is held, and the voltage on Vbp will not change. The charge pump is controlled to charge the subsequent filter capacitor.

[0180] In an exemplary embodiment of the present application, Figure 6 the right figure shows the situation when the phase difference between φ ref and φ div is 0. When both the up and dn signals are at low level, the circuit is in the sampling state. In the initial stage of sampling, there will be a building process in the loop of the phase-locked loop where the operational amplifier is located, so the Vbp voltage will have a brief oscillation. When the loop of the phase-locked loop stabilizes, the loop will control the output of the operational amplifier to charge the sampling capacitor. When both up and dn first appear at high level simultaneously, the logic operation circuit controls the voltage acquisition and holding circuit to enter the holding state. At this time, the sampling ends, the voltage on the sampling capacitor is held, and the voltage on Vbp will not change. The charge pump is controlled to charge the subsequent filter capacitor.

[0181] In an exemplary embodiment of the present application, it has at least the following advantages:

[0182] 1. The currents of MP1 and MN1 can be precisely matched, eliminating the influence of the channel length modulation effect caused by the change in the Vc voltage. And since after the phase-locked loop is locked, the reference branch no longer works, the current matching will not be affected by manufacturing process deviations.

[0183] 2. The current in the branch where MP2 is located can be less than 1 / 20 of that in the branch where MP1 is located. In the current similar solutions, the current in the branch where MP2 is located is the same as that in the branch where MP1 is located. Therefore, the current power consumption of the solution in the embodiment of the present application is small. Especially after the phase-locked loop is locked, the current in the branch where MP2 is located can be turned off to further reduce the power consumption.

[0184] 3. Only one operational amplifier is adopted in the solution of the embodiment of the present application, which eliminates the charge sharing effect and matches the charging and discharging currents at the same time, reducing the circuit complexity.

[0185] The embodiment of the present application also provides a phase-locked loop circuit 2, as Figure 7 shown, which may include: the charge pump circuit 1 described in any one of the above, a filter capacitor 2 connected to the charge pump circuit 1, a phase frequency detector PFD, a voltage controlled oscillator VCO connected to the filter capacitor 2, and a frequency divider 3 connecting the VCO and the PFD.

[0186] In the exemplary embodiment of the present application, any embodiment of the foregoing charge pump circuit is applicable to this phase-locked loop circuit, and will not be elaborated one by one here.

[0187] Those of ordinary skill in the art will understand that all or some of the steps in the methods disclosed above, and the functional modules / units in systems and devices, can be implemented as software, firmware, hardware, and appropriate combinations thereof. In the hardware implementation, the division of functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be executed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transitory medium). As is well known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, as is well known to those of ordinary skill in the art, communication media typically contains computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and can include any information delivery medium.

Claims

1. A charge pump circuit, characterized in that, Including: A charge and discharge module, an operational amplifier, a sampling control circuit, and a voltage sampling and holding module; The charge and discharge module is configured to enter a charge and discharge state of a filter capacitor at the subsequent stage of a charge pump circuit under the control of a preset phase frequency detector (PFD), or enter a sampled state for the operational amplifier to perform voltage sampling; the voltage of the filter capacitor is used to control the frequency of a voltage controlled oscillator (VCO); The sampling control circuit is configured to obtain the output result of the PFD, generate a corresponding control signal according to the output result of the PFD, and control the operational amplifier to conduct to start voltage sampling or control the operational amplifier to disconnect to stop voltage sampling according to the control signal; wherein, the output result of the PFD is used to control the charge and discharge module to be in the charge and discharge state or the sampled state; The operational amplifier is configured to sample the voltages at multiple charge and discharge connection ends on a charge and discharge path in the charge and discharge module after being conducted under the control of the sampling control circuit, and output a corresponding bias voltage according to the obtained sampled voltage, and input the bias voltage to a bias voltage input end of the charge and discharge module to implement negative feedback through the bias voltage and control the voltages at the multiple charge and discharge connection ends to be consistent; The voltage sampling and holding module is configured to sample the bias voltage output by the operational amplifier when the charge and discharge module is in the sampled state, hold the sampled bias voltage when the charge and discharge module enters the charge and discharge state, and input the held bias voltage to the bias voltage input end of the charge and discharge module to maintain the current in the charge and discharge module unchanged; Wherein, the voltage sampling and holding module includes a fifth switch and a first capacitor, and a voltage output end of the operational amplifier is connected to the bias voltage input end of the charge and discharge module through the fifth switch; the sampling control circuit includes a logic operation circuit, and the logic operation circuit generates a corresponding control signal according to the output result of the PFD, and controls the operational amplifier to conduct to start voltage sampling or controls the operational amplifier to disconnect to stop voltage sampling according to the control signal, including: performing logical calculation on the voltages on different charge and discharge paths collected, obtaining the control signal of the fifth switch, and controlling the fifth switch to close through the control signal to control the operational amplifier to conduct, or controlling the fifth switch to open through the control signal to control the operational amplifier to disconnect.

2. The charge pump circuit according to claim 1, wherein The charge and discharge connection ends include: a first charge and discharge connection end Vc and a second charge and discharge connection end Vm; The multiple charge and discharge paths of the charge and discharge module include: a first charge path, a second charge path, a first discharge path, and a second discharge path; Wherein, the first charge path and the first discharge path are connected to the first charge and discharge connection end Vc, and the second charge path and the second discharge path are connected to the second charge and discharge connection end Vm; The first charge and discharge connection terminal Vc is connected to the negative input terminal of the operational amplifier, and the second charge and discharge connection terminal Vm is connected to the positive input terminal of the operational amplifier.

3. The charge pump circuit according to claim 2, characterized in that, The charge and discharge module includes: a first P-type MOS transistor MP1, a first N-type MOS transistor MN1, a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4; The source of the first P-type MOS transistor MP1 is connected to the power supply, the gate serves as the bias voltage input terminal, and is connected to the voltage output terminal of the operational amplifier and the voltage output terminal of the voltage sampling and holding module. The drain is respectively connected to the first terminal of the second switch S2 and the first terminal of the fourth switch S4; The second terminal of the second switch S2 is connected to the first charge and discharge connection terminal Vc; the second terminal of the fourth switch S4 is connected to the second voltage output terminal Vm; The first P-type MOS transistor MP1 and the second switch S2 form the first charging path; the first P-type MOS transistor MP1 and the fourth switch S4 form the second charging path; The source of the first N-type MOS transistor MN1 is grounded, the gate is connected to a preset bias voltage Vbn, and the drain is respectively connected to the first terminal of the first switch S1 and the first terminal of the third switch S3; The second terminal of the first switch S1 is connected to the first charge and discharge connection terminal Vc; the second terminal of the third switch S3 is connected to the second voltage output terminal Vm; The first N-type MOS transistor MN1 and the first switch S1 form the first discharging path; the first N-type MOS transistor MN1 and the third switch S3 form the second discharging path.

4. The charge pump circuit according to claim 3, wherein The first terminal of the fifth switch is connected to the voltage output terminal of the operational amplifier; the second terminal of the fifth switch is connected to the gate of the first P-type MOS transistor MP1; The first terminal of the first capacitor is connected to the gate of the first P-type MOS transistor MP1, and the second terminal of the first capacitor is connected to the power supply; The first terminal of the first capacitor serves as the voltage output terminal of the voltage sampling and holding module, and is used to output the held bias voltage.

5. The charge pump circuit according to claim 4, wherein The logic operation circuit obtains the output result of the PFD, including: Obtaining the voltage output by the PFD for controlling the on / off states of different charge and discharge paths of the charge and discharge module; the on / off states of the different charge and discharge paths are used to indicate that the charge and discharge module is in the charge and discharge state or the sampled state.

6. The charge pump circuit according to claim 5, wherein The logic operation circuit includes: a second AND gate; One input terminal of the second AND gate is set to input the first voltage upb output by the PFD for controlling the on / off of the fourth switch S4; the first voltage upb is used to control the on / off state of the second charging path; The other input terminal of the second AND gate is set to input the second voltage dnb output by the PFD for controlling the on / off of the third switch S4; the second voltage dnb is used to control the on / off state of the second discharging path; The output terminal of the second AND gate is connected to the fifth switch S5, and is set to control the fifth switch S5 to open or close through the output signal of the second AND gate.

7. The charge pump circuit according to claim 3, wherein Further included are: An initial bias voltage providing module; The bias voltage output terminal of the initial bias voltage providing module is connected to the bias voltage input terminal of the charge and discharge module, and is configured to provide the bias voltage for the charge and discharge module when the phase-locked loop has not reached the locked state.

8. The charge pump circuit according to claim 7, wherein The voltage sampling and holding module, connected to the initial bias voltage providing module, is further configured to control the initial bias voltage providing module to disconnect the connection with the charge and discharge module before sampling the bias voltage of the operational amplifier.

9. The charge pump circuit according to claim 8, wherein The sampling control circuit is further configured to: detect whether the phase-locked loop has reached the locked state, and jointly generate the control signal and the on / off control signal of the initial bias voltage providing module according to the detection result of whether the phase-locked loop has reached the locked state and the output result of the PFD; before sampling the bias voltage of the operational amplifier, control the initial bias voltage providing module to disconnect the connection with the charge and discharge module according to the on / off control signal.

10. The charge pump circuit according to claim 9, characterized in that, The sampling control circuit includes: a lock detection circuit and a logic operation circuit; The lock detection circuit is configured to detect whether the phase-locked loop has reached the locked state and output a detection result; the detection result includes a first detection result for indicating that the phase-locked loop has reached the locked state and a second detection result for indicating that the phase-locked loop has not reached the locked state; The logic operation circuit is configured to obtain the output result of the PFD, jointly generate the control signal according to the detection result of whether the phase-locked loop has reached the locked state and the output result of the PFD, and control the operational amplifier to conduct to start voltage sampling or control the operational amplifier to disconnect to stop voltage sampling according to the control signal; and before sampling the bias voltage of the operational amplifier, control the initial bias voltage providing module to disconnect the connection with the charge and discharge module according to the on / off control signal.

11. The charge pump circuit according to claim 10, wherein The lock detection circuit detects whether the phase-locked loop has reached the locked state and outputs a detection result, including: Obtain the feedback signal of the VCO, divide the frequency of the feedback signal, and obtain the signal phase φ of the frequency-divided signal div , and use the signal phase φ div to compare with the preset reference source phase φ re f. When the phase difference between the signal phase φ div and the preset reference source phase φ re f is less than the preset phase difference threshold, output the first detection result; when the phase difference between the signal phase φ div and the preset reference source phase φ re f is greater than or equal to the preset phase difference threshold, output the second detection result; The logic operation circuit obtains the output result of the PFD, including: Obtaining the voltage for controlling the on / off states of different charge and discharge paths of the charge and discharge module output by the PFD; the on / off states of the different charge and discharge paths are used to indicate that the charge and discharge module is in the charge and discharge state or the sampled state.

12. The charge pump circuit according to claim 5 or 11, characterized in that, The logic operation circuit obtains the voltage for controlling the on / off states of different charge and discharge paths of the charge and discharge module output by the PFD, including: Obtaining the first voltage upb for controlling the on / off of the fourth switch S4 output by the PFD; the first voltage upb is used as the voltage for controlling the on / off state of the second charge path; Obtaining the second voltage dnb for controlling the on / off of the third switch S3 output by the PFD; the second voltage dnb is used as the voltage for controlling the on / off state of the second discharge path.

13. The charge pump circuit according to claim 10 or 11, characterized in that, The initial bias voltage providing module includes: a second P-type MOS transistor MP2 and a second N-type MOS transistor MN2; The source of the second P-type MOS transistor MP2 is connected to the power supply, and the drain of the second P-type MOS transistor MP2 is connected to the gate of the second P-type MOS transistor MP2 and the drain of the second N-type MOS transistor MN2; The gate of the second P-type MOS transistor MP2 serves as the bias voltage output terminal of the initial bias voltage providing module and is connected to the bias voltage input terminal of the charge and discharge module; The source of the second N-type MOS transistor MN2 is grounded; the gate of the second N-type MOS transistor MN2 is connected to a preset bias voltage Vbn.

14. The charge pump circuit according to claim 13, wherein The voltage sampling and holding module includes: a fifth switch S5, a sixth switch S6, and a first capacitor; The voltage output terminal of the operational amplifier is connected to the bias voltage input terminal of the charge and discharge module through the fifth switch S5; The bias voltage output terminal of the initial bias voltage providing module is connected to the bias voltage input terminal of the charge and discharge module through the sixth switch S6; The first end of the first capacitor is connected to the bias voltage input terminal of the charge and discharge module, and the second end of the first capacitor is connected to the power supply VDD; The first end of the first capacitor serves as the voltage output terminal of the voltage sampling and holding module for outputting the held bias voltage; The gate of the second P-type MOS transistor MP2 is connected to the bias voltage input terminal of the charge and discharge module through the sixth switch.

15. The charge pump circuit according to claim 14, wherein, The lock detection circuit includes: a first delay unit, a second delay unit, a first flip-flop, and a second flip-flop; the logic operation circuit includes: a first AND gate, a second AND gate, and a first NOT gate; the difference between the second delay duration of the second delay unit and the first delay duration of the first delay unit is a preset phase difference threshold; The input terminal of the first delay unit is set to input the reference source phase φ ref , and the output terminal of the first delay unit is respectively connected to the first input terminal of the first flip-flop and the first input terminal of the second flip-flop; The input end of the second delay unit is set to input the signal phase φ after frequency division of the feedback signal of the VCO. div The output end of the second delay unit is respectively connected to the second input end of the first flip-flop and the second input end of the second flip-flop. The output terminal of the first flip-flop is connected to the first input terminal of the first AND gate; The output terminal of the second flip-flop is connected to the second input terminal of the first AND gate; The output terminal of the first AND gate is connected to the first input terminal of the second AND gate; The second input terminal of the second AND gate is set to input the first voltage upb output by the PFD for controlling the on / off of the fourth switch S4; the first voltage upb is used to control the on / off state of the second charging path; The third input terminal of the second AND gate is set to input the second voltage dnb output by the PFD for controlling the on / off of the third switch S4; the second voltage dnb is used to control the on / off state of the second discharging path; The output terminal of the second AND gate is connected to the fifth switch S5, and is set to control the opening or closing of the fifth switch S5 through the output signal of the second AND gate; The input terminal of the first NOT gate is connected to the output terminal of the first AND gate, and the output terminal of the first NOT gate is connected to the sixth switch S6.

16. The charge pump circuit according to claim 15, wherein The logic operation circuit generates the control signal based on the detection result of whether the phase-locked loop reaches the locked state and the output result of the PFD, and controls the operational amplifier to turn on to start voltage sampling or controls the operational amplifier to turn off to stop voltage sampling according to the control signal; and before sampling the bias voltage of the operational amplifier, controls the initial bias voltage providing module to disconnect the connection with the charge and discharge module according to the on / off control signal, including: Performing a logic calculation on the first detection result or the second detection result and the voltages on different charge and discharge paths collected to obtain the control signal of the fifth switch S5 and the control signal of the sixth switch S6, controlling the sixth switch S6 to open through the control signal of the sixth switch S6, controlling the fifth switch S5 to close through the control signal of the fifth switch S5, thereby controlling the disconnection of the initial bias voltage providing module and controlling the conduction of the operational amplifier, or controlling the fifth switch S5 to open through the control signal to control the disconnection of the operational amplifier, so as to provide a bias voltage for the charge and discharge module through the voltage sampling and holding module.

17. A phase-locked loop circuit, characterized in that, Including: A charge pump circuit according to any one of claims 1-16, a filter capacitor and a phase frequency detector PFD connected to the charge pump circuit, a voltage controlled oscillator VCO connected to the filter capacitor, and a frequency divider connecting the VCO and the PFD.

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