Coding method, coding device and encoder

Abstract

The present application provides a coding method, coding device and encoder, the method comprising: dividing a data block to obtain multiple code blocks, the code length of the code block is less than a predetermined code length; padding multiple code blocks to obtain multiple code blocks to be coded, the code length of the code blocks to be coded is equal to the predetermined code length; performing LDPC coding on the coded code blocks to be coded to obtain multiple coded code blocks, the code rate of the coded code blocks is equal to the target code rate, the target code rate is greater than or equal to the minimum code rate, and the minimum code rate is equal to the ratio of the predetermined code length to the maximum code length of the coded code block. Compared with the prior art in which the code length of the coded code block obtained by coding calculation is equal to the maximum code length, and then rate matching is performed, the method reduces the amount of coding calculation, reduces coding delay and power consumption, and thus solves the problem of delay of the coding method in the prior art.

Description

Technical Field

[0001] The present application relates to the field of wireless communications, and in particular, to a coding method, a coding device, a computer-readable storage medium, a processor, and an encoder. Background Art

[0002] With the development of wireless communications, people's demand for large-capacity, low-latency, high-reliability, high-speed, high-connection, and high-energy-efficiency communications will increase significantly. The application scenarios are not only wide-area coverage, but also dense hotspots, machine-to-machine communications, Internet of Vehicles, large open-air gatherings, subways, etc. These applications can be roughly divided into three scenarios: enhanced mobile broadband eMBB, low-latency and high-reliability URLLC, and massive Internet of Things mMTC. Channel coding is the most basic technology of the physical layer, which will play a direct and indirect role in various performance indicators of the 5G system, so the 5G system has high requirements for channel coding. The high peak rate requires the decoder of the data channel to reach 20Gbit / s downlink and 10Gbit / s uplink at high bit rates. Since the system has high requirements for the delay of the user plane and the control plane, the delay of the channel coding decoder is generally from a few microseconds to more than ten microseconds, and the decoder is required to have a reasonable chip area and power consumption.

[0003] LDPC was first proposed by Robert Gallager in his doctoral thesis in 1963. In 2005, the quasi-cyclic LDPC code based on the cyclic shift matrix of the unit matrix, namely QC-LDPC, also known as structured LDPC code, was first applied in the WiMAX standard. Later, the QC LDPC scheme similar to the WiMAX LDPC structure was adopted by IEEE802.11n and IEEE802.11ad. In order to improve the channel coding efficiency of 5G NR and adapt to the transmission requirements of 5G large data volume, high reliability and low latency, LDPC code was finally adopted by the 3GPP standard in October 2016 and became the data channel coding scheme of the 5G NR standard.

[0004] The above information disclosed in the background technology section is only used to enhance the understanding of the background technology of the technology described in this article. Therefore, the background technology may contain certain information that does not form the prior art known in this country for those skilled in the art. Summary of the invention

[0005] The main purpose of the present application is to provide a coding method, a coding device, a computer-readable storage medium, a processor and an encoder to solve the problem of time extension of the coding method in the prior art.

[0006] According to one aspect of an embodiment of the present invention, there is provided a coding method, comprising: dividing a data block to obtain a plurality of code blocks, wherein the code length of the code block is less than a predetermined code length; padding the plurality of code blocks to obtain a plurality of code blocks to be encoded, wherein the code length of the code blocks to be encoded is equal to the predetermined code length; performing LDPC encoding on the code blocks to be encoded to obtain a plurality of encoded code blocks, wherein the code rate of the encoded code blocks is equal to a target code rate, wherein the target code rate is greater than or equal to a minimum code rate, and wherein the minimum code rate is equal to a ratio of the predetermined code length to a maximum code length of the encoded code blocks.

[0007] Optionally, LDPC encoding is performed on the code block to be encoded to obtain multiple encoding code blocks, including: generating a target encoding code block based on the code block to be encoded, the target encoding code block is obtained by sequentially splicing a first code block, a second code block and a third code block, the first code block includes the code block to be encoded, and the code length of the target encoding code block is equal to the maximum code length of the encoding code block; calculating the ratio of the code length of the first code block to the target code rate to obtain a first code length, the first code length is the code length of the encoding code block; calculating the second code block according to a parity check matrix; calculating the fourth code block according to the parity check matrix, the fourth code block is composed of a target number of code elements of the third code block, the target number is the difference between the first code length and the second code length, and the second code length is the sum of the code length of the first code block and the code length of the second code block; the first code block, the second code block and the fourth code block are sequentially spliced ​​to obtain the encoding code block.

[0008] Optionally, the parity check matrix is ​​calculated by a basic check matrix and a standard permutation matrix, the basic check matrix includes a first basic check matrix and a second basic check matrix, the parity check matrix corresponding to the first basic check matrix is ​​used to encode the data blocks with the target code rate greater than or equal to 1 / 3, and the parity check matrix corresponding to the second basic check matrix is ​​used to encode the data blocks with the target code rate greater than or equal to 1 / 5.

[0009] Optionally, generating a target encoding code block based on the code block to be encoded includes: when the parity check matrix is ​​calculated by the first basic check matrix and a standard permutation matrix, the first code block is the code block to be encoded; when the parity check matrix is ​​calculated by the second basic check matrix and a standard permutation matrix, the first code block is the code block to be encoded or the first code block consists of the code block to be encoded and multiple 0 code elements.

[0010] Optionally, multiple code blocks are padded to obtain multiple code blocks to be encoded, including: adding a CRC code to each of the code blocks to obtain multiple added code blocks, the code length of the added code blocks is less than or equal to the predetermined code length; padding multiple added code blocks to obtain multiple code blocks to be encoded.

[0011] Optionally, after performing LDPC encoding on the code block to be encoded to obtain a plurality of encoded code blocks, the method further includes: performing bit interleaving on the encoded code blocks to obtain an interleaved bit stream.

[0012] According to another aspect of an embodiment of the present invention, a coding device is also provided, including: a first processing unit, used to divide a data block into multiple code blocks, and the code length of the code block is less than a predetermined code length; a second processing unit, used to fill the multiple code blocks to obtain multiple code blocks to be encoded, and the code length of the code block to be encoded is equal to the predetermined code length; an encoding unit, used to perform LDPC encoding on the code blocks to be encoded to obtain multiple encoded code blocks, and the code rate of the encoded code blocks is equal to the target code rate, the target code rate is greater than or equal to the minimum code rate, and the minimum code rate is equal to the ratio of the predetermined code length to the maximum code length of the encoded code block.

[0013] According to another aspect of the embodiments of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium includes a stored program, wherein the program executes any one of the methods described.

[0014] According to yet another aspect of the embodiments of the present invention, a processor is provided, wherein the processor is used to run a program, wherein any one of the methods is executed when the program is run.

[0015] According to one aspect of an embodiment of the present invention, there is further provided an encoder, comprising an encoding device, wherein the encoding device is used to execute any one of the methods described.

[0016] In an embodiment of the present invention, in the above encoding method, first, the data block is divided into multiple code blocks, and the code length of the above code blocks is less than the predetermined code length; then, the multiple code blocks are padded to obtain multiple code blocks to be encoded, and the code length of the above code blocks to be encoded is equal to the above predetermined code length; finally, LDPC encoding is performed on the above code blocks to be encoded to obtain multiple encoded code blocks, and the code rate of the above encoded code blocks is equal to the target code rate, the above target code rate is greater than or equal to the minimum code rate, and the above minimum code rate is equal to the ratio of the above predetermined code length to the maximum code length of the above encoded code blocks. The method divides and fills a data block to obtain a plurality of to-be-encoded code blocks of predetermined code lengths. When the target code rate is equal to the minimum code rate, the to-be-encoded code blocks are LDPC encoded, and the code length of the encoded code blocks obtained by encoding is equal to the maximum code length, so that the code rate of the encoded code blocks is equal to the target code rate. When the target code rate is greater than the minimum code rate, the to-be-encoded code blocks are LDPC encoded, and the code length of the encoded code blocks obtained by encoding is less than the maximum code length, so that the code rate of the encoded code blocks is equal to the target code rate. Compared with the prior art in which the code length of the encoded code blocks obtained by encoding calculation is equal to the maximum code length and then rate matching is performed, the amount of encoding calculation is reduced, the encoding delay and power consumption are reduced, and the delay problem of the encoding method in the prior art is solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0018] Figure 1 A schematic diagram showing an encoding method according to an embodiment of the present application is shown;

[0019] Figure 2 (a) to (d) show the distribution of cyclic shift coefficients corresponding to the B submatrix according to an embodiment of the present application;

[0020] Figure 3 A schematic diagram of vector multiplication of binary numbers according to an embodiment of the present application is shown;

[0021] Figure 4 A schematic diagram showing an encoding process according to an embodiment of the present application is shown;

[0022] Figure 5 A schematic diagram showing an encoding process according to another embodiment of the present application is shown;

[0023] Figure 6 A schematic diagram of data block segmentation according to an embodiment of the present application is shown;

[0024] Figure 7A schematic diagram of an encoding device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0025] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0026] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0027] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0028] As mentioned in the background technology, the duration of the encoding method in the prior art is long. In order to solve the above problem, in a typical implementation of the present application, a coding method, a coding device, a computer-readable storage medium, a processor and an encoder are provided.

[0029] According to an embodiment of the present application, a coding method is provided.

[0030] Figure 1 is a flow chart of the encoding method according to an embodiment of the present application. Figure 1 As shown, the method comprises the following steps:

[0031] Step S101, dividing a data block into multiple code blocks, wherein the code length of the code blocks is less than a predetermined code length;

[0032] Step S102, padding the plurality of code blocks to obtain a plurality of code blocks to be encoded, wherein the code length of the code blocks to be encoded is equal to the predetermined code length;

[0033] Step S103, performing LDPC encoding on the above-mentioned code block to be encoded to obtain multiple encoded code blocks, the code rate of the above-mentioned encoded code block is equal to the target code rate, the above-mentioned target code rate is greater than or equal to the minimum code rate, and the above-mentioned minimum code rate is equal to the ratio of the above-mentioned predetermined code length to the maximum code length of the above-mentioned encoded code block.

[0034] In the above encoding method, first, the data block is divided into multiple code blocks, and the code length of the above code blocks is less than the predetermined code length; then, the multiple code blocks are padded to obtain multiple code blocks to be encoded, and the code length of the above code blocks to be encoded is equal to the above predetermined code length; finally, LDPC encoding is performed on the above code blocks to be encoded to obtain multiple encoded code blocks, and the code rate of the above encoded code blocks is equal to the target code rate, the above target code rate is greater than or equal to the minimum code rate, and the above minimum code rate is equal to the ratio of the above predetermined code length to the maximum code length of the above encoded code blocks. The method divides and fills a data block to obtain a plurality of to-be-encoded code blocks of predetermined code lengths. When the target code rate is equal to the minimum code rate, the to-be-encoded code blocks are LDPC encoded, and the code length of the encoded code blocks obtained by encoding is equal to the maximum code length, so that the code rate of the encoded code blocks is equal to the target code rate. When the target code rate is greater than the minimum code rate, the to-be-encoded code blocks are LDPC encoded, and the code length of the encoded code blocks obtained by encoding is less than the maximum code length, so that the code rate of the encoded code blocks is equal to the target code rate. Compared with the prior art in which the code length of the encoded code blocks obtained by encoding calculation is equal to the maximum code length and then rate matching is performed, the amount of encoding calculation is reduced, the encoding delay and power consumption are reduced, and the delay problem of the encoding method in the prior art is solved.

[0035] It should be noted that the encoding operation is performed on the check bits to be sent, and the check bits can be continuous or intermittent.

[0036] In actual application, in order to detect errors in the received data blocks at the receiving end, a cyclic redundancy check (CRC) code needs to be added to the transmission block TB; due to the limited length of the channel coding, for LDPC coding, the coding gain brought by codewords exceeding a certain length is not significant, and the 5G standard stipulates that the maximum LDPC code length is 8448 bits, so it is necessary to segment the transmission block to which CRC has been added, and add CRC code to the code block CB obtained after segmentation again, and fill each code block that is less than K=kb*Zc in length; perform LDPC encoding on the code block to be encoded that meets the predetermined code length after filling, and obtain multiple encoded code blocks, so that the length of the encoded code block is 68*Zc or 52*Zc, where Zc is the expansion factor.

[0037] It should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and that, although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0038] In one embodiment of the present application, LDPC encoding is performed on the above-mentioned code block to be encoded to obtain multiple encoding code blocks, including: generating a target encoding code block according to the above-mentioned code block to be encoded, the above-mentioned target encoding code block is obtained by sequentially splicing a first code block, a second code block and a third code block, the above-mentioned first code block includes the above-mentioned code block to be encoded, and the code length of the above-mentioned target encoding code block is equal to the maximum code length of the above-mentioned encoding code block; calculating the ratio of the code length of the above-mentioned first code block to the above-mentioned target code rate to obtain a first code length, the above-mentioned first code length is the code length of the above-mentioned encoding code block, and the above-mentioned second code block is obtained by calculation according to a parity check matrix; obtaining a fourth code block according to the above-mentioned parity check matrix, the above-mentioned fourth code block is composed of a target number of code elements of the above-mentioned third code block, the above-mentioned target number is the difference between the above-mentioned first code length and the second code length, and the above-mentioned second code length is the sum of the code length of the above-mentioned first code block and the code length of the above-mentioned second code block; the above-mentioned first code block, the above-mentioned second code block and the above-mentioned fourth code block are sequentially spliced ​​to obtain the above-mentioned encoding code block. In this scheme, the target number is obtained by the difference between the first code length and the second code length, and then the fourth code block is obtained by the code elements of the target number of third code blocks. The obtained first code block, second code block and fourth code block are spliced ​​to obtain the encoded code block. That is, this scheme implements the non-encoding of check bits that do not need to be transmitted, reduces the computational complexity of the encoding calculation, and further reduces the encoding delay.

[0039] In another embodiment of the present application, the parity check matrix is ​​calculated by a basic check matrix and a standard permutation matrix, and the basic check matrix includes a first basic check matrix BG1 and a second basic check matrix BG2. The parity check matrix corresponding to the first basic check matrix BG1 is used to encode the data blocks whose target code rate is greater than or equal to 1 / 3, and the parity check matrix corresponding to the second basic check matrix BG2 is used to encode the data blocks whose target code rate is greater than or equal to 1 / 5.

[0040] Specifically, the first basic check matrix BG1 and the second basic check matrix BG2 have different numbers of columns. In actual application, the number of columns of the first basic check matrix BG1 may be 68, and the number of columns of the second basic check matrix BG2 may be 52. Figure 4 and Figure 5As shown, the first basic check matrix BG1 and the second basic check matrix BG2 can be divided into six sub-matrices, namely A / B / C / D / 0 / E. In the first basic check matrix BG1, the number of columns of matrix A is 22, and in the second basic check matrix BG2, the number of columns of matrix A is 10.

[0041] In actual application, 5G NR LDPC code uses a quasi-cyclic structure, and its parity check matrix is ​​based on the basic check matrix H given by the 3GPP technical specification. BG Definition, basic check matrix H BG It contains the special structural characteristics of the check matrix and can also be expanded by the factor Z c To construct a larger parity check matrix, the expansion factor is the order of the above standard permutation matrix. Each element in the basic check matrix represents Z c *Z c The zero matrix or the right circular shift Z c *Z c The unit matrix, where the right shift number is given by the shift coefficient table in the 3GPP technical specification. The basic check matrix consists of information bit columns (also called system bit columns), check bit columns and additional check bit columns. Two basic matrices are used, namely the first basic check matrix H BG1 and the second basic check matrix H BG2 , the parity check matrix will generate different parity check matrices through these two basic check matrices), and then combine the expansion factor (Z c The range of Z is 2 to 384). These two parameters can be selected according to the code block size and the code rate. c The design of the value enables QC-LDPC codes to flexibly obtain codewords with different code lengths and different code rates. c The value is selected from Table 1, Z c =a×2 j , where a and j are the factors affecting Z c The coefficient of the value.

[0042] Table 1

[0043] j＝1 j＝2 j＝3 j＝4 j＝5 j＝6 j＝7 a＝2 4 8 16 32 64 128 256 a＝3 6 12 24 48 96 192 384 a＝5 10 20 40 80 160 320 a＝7 14 28 56 112 224 a＝9 18 36 72 144 288 a＝11 22 44 88 176 352 a＝13 26 52 104 208 a＝15 30 60 120 240

[0044] In a specific embodiment of the present application, LDPC coding is a linear block code defined according to a parity check matrix, which satisfies the check relation H*C T= 0, where H is the parity check matrix, which is a sparse matrix, and C is the LDPC codeword of the system code. The parity check matrix is ​​mainly used for encoding. For quasi-cyclic LDPC codes, also known as structured LDPC codes, their parity check matrix can be composed of multiple sub-matrices, each of which is a cyclic shift matrix of an all-zero square matrix or a unit matrix. Furthermore, each parity check matrix H of a quasi-cyclic LDPC code can be composed of a basic check matrix H b (also called shift coefficient matrix) and a standard permutation matrix. b for The standard permutation matrix P is an identity matrix, that is, Parity Check Matrix For example, Get the parity check matrix

[0045] In order to save a large number of cyclic shift XOR calculations in the encoding process, in another embodiment of the present application, a target encoding code block is generated according to the above-mentioned code block to be encoded, including: when the above-mentioned parity check matrix is ​​calculated by the above-mentioned first basic check matrix and the standard permutation matrix, the above-mentioned first code block is the above-mentioned code block to be encoded; when the above-mentioned parity check matrix is ​​calculated by the above-mentioned second basic check matrix and the standard permutation matrix, the above-mentioned first code block is the above-mentioned code block to be encoded or the above-mentioned first code block is composed of the above-mentioned code block to be encoded and multiple 0 code elements.

[0046] Specifically, the target coding code block can be divided into three parts according to the segmentation form of the basic check matrix H, namely the first code block S, the second code block P core , the third code block P i , which can be specifically expressed as C = [SP core P i ], where the number of information bit blocks S is the same as the number of columns of the A and C sub-matrices, and the number of check bit blocks P core and P i The number of blocks is the same as the number of columns of sub-matrices B, D and 0, E respectively.

[0047] For B 4×4 There are four different matrices, as follows Figure 2 (a) Figure 2 (b) Figure 2 (c) and Figure 2As shown in (d), among the 16 cyclic shift coefficient matrices, there are only 4 distributions of cyclic shift coefficients corresponding to the B submatrix, and there are only 4 cases for the cyclic shift coefficient values: -1, 0, 1 and 105, where respectively indicate that the submatrix is ​​a zero matrix, an identity matrix, a permutation matrix obtained by shifting the identity matrix right by 1 bit, and a permutation matrix obtained by shifting the identity matrix right by 105 bits.

[0048] Through the coding characteristics of quasi-cyclic LDPC codes and codeword H*C T =0, we can conclude that:

[0049]

[0050]

[0051] (1) Calculate A*S T

[0052] like Figure 3 As shown, the vector multiplication operation of the binary number can actually be transformed into a row-by-row circular shift XOR operation to further calculate the value of each column vector, and only the positions with a value of 1 in the basic check matrix participate in the operation.

[0053] (2) Calculation

[0054] Depend on

[0055] according to Figure 2 The characteristics of the B submatrix shown can be further deduced

[0056] For Figure 2 (a) shows the cyclic shift diagram:

[0057]

[0058] For Figure 2 (b) shows the cyclic shift graph:

[0059]

[0060] For Figure 2 (c) shows the cyclic shift graph:

[0061]

[0062] For Figure 2 (d) shows the cyclic shift graph:

[0063]

[0064] (3) Calculation

[0065] like Figure 4 As shown in the figure, if the system needs to encode at a code rate of 1 / 3 or 1 / 5, all row blocks of the C and D submatrices need to be cyclically shifted and XORed; when the system only needs to send P1 length check information, The C and D matrices in the formula only need to be encoded to their Mb1 rows. When the system only needs to send the check information of length P2, it only needs to encode and calculate to its Mb2 rows. In this way, if the check bit block part that the system does not need does not need to be encoded, it only needs to calculate the check column block required to be sent by the system, which greatly reduces the coding delay and power consumption. In addition, if Figure 5 As shown, for the encoding of short code blocks, that is, when Kb=6, 8, 9, in addition to the check column block required by the encoding system, the information bit column block (10-Kb) does not need to participate in any calculation, thus saving a large number of cyclic shift XOR calculations.

[0066] In another embodiment of the present application, multiple code blocks are padded to obtain multiple code blocks to be encoded, including: adding CRC code to each of the code blocks to obtain multiple added code blocks, the code length of the added code blocks is less than or equal to the predetermined code length; padding multiple added code blocks to obtain multiple code blocks to be encoded. In this scheme, CRC code is added to each of the code blocks to obtain multiple added code blocks, which ensures that error detection can be performed on each added code block, and the specific position of the added code block with error can be specifically located. Secondly, in this scheme, multiple added code blocks are padded to reach the predetermined code length to obtain multiple code blocks to be encoded, which is convenient for subsequent encoding of the code blocks to be encoded to obtain multiple encoded code blocks, and further the code rate of the encoded code blocks can be made equal to the target code rate.

[0067] Specifically, if Figure 6 As shown, it is a process of dividing a data block into multiple code blocks, and adding CRC codes to the obtained code blocks to obtain multiple added code blocks. CRC codes are added to the obtained multiple code blocks, so that error detection can be performed on each of the obtained added code blocks, and the specific position of the added code block where the error occurs can be further determined. Compared with the prior art of adding CRC codes to the entire data code block, this solution not only realizes error detection on the added code block, but also realizes specific positioning and analysis of the specific position of the added code block, so that the location and cause of the error can be known relatively quickly.

[0068] In order to resist burst errors, in an embodiment of the present application, after performing LDPC encoding on the above-mentioned code blocks to be encoded to obtain multiple encoded code blocks, the above-mentioned method also includes: performing bit interleaving on the above-mentioned encoded code blocks to obtain an interleaved bit stream.

[0069] In a specific embodiment of the present application, after bit interleaving the above-mentioned coded code blocks to obtain an interleaved bit stream, the above-mentioned method further includes: code block cascading, bit scrambling and symbol modulation to map the bit stream to each symbol.

[0070] The embodiment of the present application also provides a coding device. It should be noted that the coding device of the embodiment of the present application can be used to execute the coding method provided by the embodiment of the present application. The coding device provided by the embodiment of the present application is introduced below.

[0071] Figure 7 is a schematic diagram of an encoding device according to an embodiment of the present application. Figure 7 As shown, the device comprises:

[0072] A first processing unit 10 is used to divide the data block into multiple code blocks, wherein the code length of the code block is less than a predetermined code length;

[0073] The second processing unit 20 is used to fill the plurality of the code blocks to obtain a plurality of code blocks to be encoded, wherein the code length of the code blocks to be encoded is equal to the predetermined code length;

[0074] The encoding unit 30 is used to perform LDPC encoding on the above-mentioned code block to be encoded to obtain multiple encoded code blocks, the code rate of the above-mentioned encoded code block is equal to the target code rate, the above-mentioned target code rate is greater than or equal to the minimum code rate, and the above-mentioned minimum code rate is equal to the ratio of the above-mentioned predetermined code length to the maximum code length of the above-mentioned encoded code block.

[0075] In the above-mentioned encoding device, the first processing unit is used to divide the data block into multiple code blocks, and the code length of the above-mentioned code blocks is less than the predetermined code length; the second processing unit is used to fill the multiple code blocks to obtain multiple code blocks to be encoded, and the code length of the above-mentioned code blocks to be encoded is equal to the above-mentioned predetermined code length; the encoding unit is used to perform LDPC encoding on the above-mentioned code blocks to be encoded to obtain multiple encoded code blocks, and the code rate of the above-mentioned encoded code blocks is equal to the target code rate, the above-mentioned target code rate is greater than or equal to the minimum code rate, and the above-mentioned minimum code rate is equal to the ratio of the above-mentioned predetermined code length to the maximum code length of the above-mentioned encoded code block. The device divides and fills the data block to obtain a plurality of to-be-encoded code blocks of predetermined code lengths. When the target code rate is equal to the minimum code rate, the to-be-encoded code blocks are LDPC encoded, and the code length of the encoded code blocks obtained by encoding is equal to the maximum code length, so that the code rate of the encoded code blocks is equal to the target code rate. When the target code rate is greater than the minimum code rate, the to-be-encoded code blocks are LDPC encoded, and the code length of the encoded code blocks obtained by encoding is less than the maximum code length, so that the code rate of the encoded code blocks is equal to the target code rate. Compared with the prior art in which the code length of the encoded code blocks obtained by encoding calculation is equal to the maximum code length and then rate matching is performed, the amount of encoding calculation is reduced, the encoding delay and power consumption are reduced, and the delay problem of the encoding method in the prior art is solved.

[0076] It should be noted that the encoding operation is performed on the check bits to be sent, and the check bits can be continuous or intermittent.

[0077] In actual application, in order to detect errors in the received data blocks at the receiving end, a cyclic redundancy check (CRC) code needs to be added to the transmission block TB; due to the limited length of the channel coding, for LDPC coding, the coding gain brought by codewords exceeding a certain length is not significant, and the 5G standard stipulates that the maximum LDPC code length is 8448 bits, so it is necessary to segment the transmission block to which CRC has been added, and add CRC code to the code block CB obtained after segmentation again, and fill each code block that is less than K=kb*Zc in length; perform LDPC encoding on the code block to be encoded that meets the predetermined code length after filling, and obtain multiple encoded code blocks, so that the length of the encoded code block is 68*Zc or 52*Zc, where Zc is the expansion factor.

[0078] In one embodiment of the present application, the encoding unit includes a generation module, a first calculation module, a second calculation module, a third calculation module and a splicing module, wherein the generation module is used to generate a target encoding code block according to the code block to be encoded, the target encoding code block is obtained by sequentially splicing the first code block, the second code block and the third code block, the first code block includes the code block to be encoded, the code length of the second code block is 4, and the code length of the target encoding code block is equal to the maximum code length of the encoding code block; the first calculation module is used to calculate the ratio of the code length of the first code block to the target code rate, and obtain The first code length, the first code length is the code length of the encoding code block; the second calculation module is used to calculate the second code block according to the parity check matrix; the third calculation module is used to calculate the fourth code block according to the parity check matrix, the fourth code block is composed of a target number of code elements of the third code block, the target number is the difference between the first code length and the second code length, the second code length is the sum of the code length of the first code block and the code length of the second code block; the splicing module is used to sequentially splice the first code block, the second code block and the fourth code block to obtain the encoding code block. In this scheme, the target number is obtained by the difference between the first code length and the second code length, and then the fourth code block is obtained by the code elements of the target number of third code blocks, and the encoding code block is spliced ​​according to the obtained first code block, second code block and fourth code block, that is, this scheme realizes that the check bits that do not need to be transmitted are not encoded, reducing the amount of coding calculation, and further reducing the coding delay.

[0079] In another embodiment of the present application, the parity check matrix is ​​calculated by a basic check matrix and a standard permutation matrix, and the basic check matrix includes a first basic check matrix BG1 and a second basic check matrix BG2. The parity check matrix corresponding to the first basic check matrix BG1 is used to encode the data blocks whose target code rate is greater than or equal to 1 / 3, and the parity check matrix corresponding to the second basic check matrix BG2 is used to encode the data blocks whose target code rate is greater than or equal to 1 / 5.

[0080] Specifically, the first basic check matrix BG1 and the second basic check matrix BG2 have different numbers of columns. In actual application, the number of columns of the first basic check matrix BG1 may be 68, and the number of columns of the second basic check matrix BG2 may be 52. Figure 4 and Figure 5 As shown, the first basic check matrix BG1 and the second basic check matrix BG2 can be divided into six sub-matrices, namely A / B / C / D / 0 / E. In the first basic check matrix BG1, the number of columns of matrix A is 22, and in the second basic check matrix BG2, the number of columns of matrix A is 10.

[0081] In actual application, 5G NR LDPC code uses a quasi-cyclic structure, and its parity check matrix is ​​based on the basic check matrix H given by the 3GPP technical specification. BG Definition, basic check matrix H BG It contains the special structural characteristics of the check matrix and can also be expanded by the factor Z c To construct a larger parity check matrix, the expansion factor is the order of the above standard permutation matrix. Each element in the basic check matrix represents Z c *Z c The zero matrix or the right circular shift Z c *Z c The unit matrix, where the right shift number is given by the shift coefficient table in the 3GPP technical specification. The basic check matrix consists of information bit columns (also called system bit columns), check bit columns and additional check bit columns. Two basic matrices are used, namely the first basic check matrix H BG1 and the second basic check matrix H BG2 , the parity check matrix will generate different parity check matrices through these two basic check matrices), and then combine the expansion factor (Z c The range of Z is 2 to 384). These two parameters can be selected according to the code block size and the code rate. c The design of the value enables QC-LDPC codes to flexibly obtain codewords with different code lengths and different code rates. c The value is selected from Table 1, Z c =a×2 j , where a and j are the factors affecting Z c The coefficient of the value.

[0082] In a specific embodiment of the present application, LDPC coding is a linear block code defined according to a parity check matrix, which satisfies the check relation H*C T = 0, where H is the parity check matrix, which is a sparse matrix, and C is the LDPC codeword of the system code. The parity check matrix is ​​mainly used for encoding. For quasi-cyclic LDPC codes, also known as structured LDPC codes, their parity check matrix can be composed of multiple sub-matrices, each of which is a cyclic shift matrix of an all-zero square matrix or a unit matrix. Furthermore, each parity check matrix H of a quasi-cyclic LDPC code can be composed of a basic check matrix H b (also called shift coefficient matrix) and a standard permutation matrix. b for The standard permutation matrix P is an identity matrix, that is, Parity Check Matrix For example, Get the parity check matrix

[0083] In order to save a large number of cyclic shift XOR calculations in the encoding process, in another embodiment of the present application, the above-mentioned generation module includes a first calculation submodule and a second calculation submodule, wherein the above-mentioned first calculation submodule is used for, when the above-mentioned parity check matrix is ​​calculated by the above-mentioned first basic check matrix and the standard permutation matrix, the above-mentioned first code block is the above-mentioned code block to be encoded; the above-mentioned second calculation submodule is used for, when the above-mentioned parity check matrix is ​​calculated by the above-mentioned second basic check matrix and the standard permutation matrix, the above-mentioned first code block is the above-mentioned code block to be encoded or the above-mentioned first code block is composed of the above-mentioned code block to be encoded and multiple 0 code elements.

[0084] Specifically, the target coding code block can be divided into three parts according to the segmentation form of the basic check matrix H, namely the first code block S, the second code block P core , the third code block P i , which can be specifically expressed as C = [SP core P i ], where the number of information bit blocks S is the same as the number of columns of the A and C sub-matrices, and the number of check bit blocks P core and P i The number of blocks is the same as the number of columns of sub-matrices B, D and 0, E respectively.

[0085] For B 4×4 There are four different matrices, as follows Figure 2 (a) Figure 2 (b) Figure 2 (c) and Figure 2 As shown in (d), among the 16 cyclic shift coefficient matrices, there are only 4 distributions of cyclic shift coefficients corresponding to the B submatrix, and there are only 4 cases for the cyclic shift coefficient values: -1, 0, 1 and 105, where respectively indicate that the submatrix is ​​a zero matrix, an identity matrix, a permutation matrix obtained by shifting the identity matrix right by 1 bit, and a permutation matrix obtained by shifting the identity matrix right by 105 bits.

[0086] Through the coding characteristics of quasi-cyclic LDPC codes and codeword H*C T =0, we can conclude that:

[0087]

[0088]

[0089] (1) Calculate A*S T

[0090] like Figure 3As shown, the vector multiplication operation of the binary number can actually be transformed into a row-by-row circular shift XOR operation to further calculate the value of each column vector, and only the positions with a value of 1 in the basic check matrix participate in the operation.

[0091] (2) Calculation

[0092] Depend on

[0093]

[0094] according to Figure 2 The characteristics of the B submatrix shown can be further deduced

[0095] For Figure 2 (a) shows the cyclic shift diagram:

[0096]

[0097] For Figure 2 (b) shows the cyclic shift graph:

[0098]

[0099] For Figure 2 (c) shows the cyclic shift graph:

[0100]

[0101] For Figure 2 (d) shows the cyclic shift graph:

[0102]

[0103] (3) Calculation

[0104] like Figure 4 As shown in the figure, if the system needs to encode at a code rate of 1 / 3 or 1 / 5, all row blocks of the C and D submatrices need to be cyclically shifted and XORed; when the system only needs to send P1 length check information, The C and D matrices in the formula only need to be encoded to their Mb1 rows. When the system only needs to send the check information of length P2, it only needs to encode and calculate to its Mb2 rows. In this way, if the check bit block part that the system does not need does not need to be encoded, it only needs to calculate the check column block required to be sent by the system, which greatly reduces the coding delay and power consumption. In addition, if Figure 5As shown, for the encoding of short code blocks, that is, when Kb=6, 8, 9, in addition to the check column block required by the encoding system, the information bit column block (10-Kb) does not need to participate in any calculation, thus saving a large number of cyclic shift XOR calculations.

[0105] In another embodiment of the present application, the second processing unit includes an adding module and a filling module, wherein the adding module is used to add a CRC code to each of the above code blocks to obtain a plurality of added code blocks, and the code length of the above added code blocks is less than or equal to the above predetermined code length; the filling module is used to fill the plurality of the above added code blocks to obtain a plurality of the above code blocks to be encoded. In this scheme, a CRC code is added to each of the above code blocks to obtain a plurality of added code blocks, which ensures that errors can be detected for each added code block, and the specific position of the added code block where the error occurs can be specifically located. Secondly, in this scheme, a plurality of added code blocks are filled to reach the predetermined code length to obtain a plurality of code blocks to be encoded, which is convenient for subsequent encoding of the code blocks to be encoded to obtain a plurality of encoded code blocks, and further the code rate of the encoded code blocks can be made equal to the target code rate.

[0106] Specifically, if Figure 6 As shown, it is a process of dividing a data block into multiple code blocks, and adding CRC codes to the obtained code blocks to obtain multiple added code blocks. CRC codes are added to the obtained multiple code blocks, so that error detection can be performed on each of the obtained added code blocks, and the specific position of the added code block where the error occurs can be further determined. Compared with the prior art of adding CRC codes to the entire data code block, this solution not only realizes error detection on the added code block, but also realizes specific positioning and analysis of the specific position of the added code block, so that the location and cause of the error can be known relatively quickly.

[0107] In order to be able to resist burst errors, in one embodiment of the present application, the above-mentioned device also includes a bit interleaving unit, which is used to perform bit interleaving on the above-mentioned coded code blocks after LDPC encoding is performed on the above-mentioned coded code blocks to obtain multiple coded code blocks, so as to obtain an interleaved bit stream.

[0108] In a specific embodiment of the present application, after bit interleaving the above-mentioned coded code blocks to obtain an interleaved bit stream, the above-mentioned method further includes: code block cascading, bit scrambling and symbol modulation to map the bit stream to each symbol.

[0109] The above-mentioned encoding device includes a processor and a memory. The above-mentioned first processing unit, second processing unit and encoding unit, etc. are all stored in the memory as program units, and the processor executes the above-mentioned program units stored in the memory to realize corresponding functions.

[0110] The processor includes a kernel, which retrieves the corresponding program unit from the memory. One or more kernels can be provided, and the problem of time extension of the encoding method in the prior art can be solved by adjusting kernel parameters.

[0111] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip.

[0112] An embodiment of the present invention provides a computer-readable storage medium on which a program is stored. When the program is executed by a processor, the above encoding method is implemented.

[0113] An embodiment of the present invention provides a processor, and the processor is used to run a program, wherein the encoding method is executed when the program is run.

[0114] In a typical embodiment of the present application, an encoder is further provided, including an encoding device, and the encoding device is used to execute any one of the above methods.

[0115] The above-mentioned encoder includes an encoding device, and the above-mentioned encoding device is used for any of the above-mentioned encoding methods. In the above-mentioned encoding method, first, the data block is divided into multiple code blocks, and the code length of the above-mentioned code blocks is less than the predetermined code length; then, the multiple code blocks are padded to obtain multiple code blocks to be encoded, and the code length of the above-mentioned code blocks to be encoded is equal to the above-mentioned predetermined code length; finally, LDPC encoding is performed on the above-mentioned code blocks to be encoded to obtain multiple encoded code blocks, and the code rate of the above-mentioned encoded code blocks is equal to the target code rate, the above-mentioned target code rate is greater than or equal to the minimum code rate, and the above-mentioned minimum code rate is equal to the ratio of the above-mentioned predetermined code length to the maximum code length of the above-mentioned encoded code block. The method divides and fills a data block to obtain a plurality of to-be-encoded code blocks of predetermined code lengths. When the target code rate is equal to the minimum code rate, the to-be-encoded code blocks are LDPC encoded, and the code length of the encoded code blocks obtained by encoding is equal to the maximum code length, so that the code rate of the encoded code blocks is equal to the target code rate. When the target code rate is greater than the minimum code rate, the to-be-encoded code blocks are LDPC encoded, and the code length of the encoded code blocks obtained by encoding is less than the maximum code length, so that the code rate of the encoded code blocks is equal to the target code rate. Compared with the prior art in which the code length of the encoded code blocks obtained by encoding calculation is equal to the maximum code length and then rate matching is performed, the amount of encoding calculation is reduced, the encoding delay and power consumption are reduced, and the delay problem of the encoding method in the prior art is solved.

[0116] An embodiment of the present invention provides a device, the device including a processor, a memory, and a program stored in the memory and executable on the processor, and when the processor executes the program, at least the following steps are implemented:

[0117] Step S101, dividing a data block into multiple code blocks, wherein the code length of the code blocks is less than a predetermined code length;

[0118] Step S102, padding the plurality of code blocks to obtain a plurality of code blocks to be encoded, wherein the code length of the code blocks to be encoded is equal to the predetermined code length;

[0119] Step S103, performing LDPC encoding on the above-mentioned code block to be encoded to obtain multiple encoded code blocks, the code rate of the above-mentioned encoded code block is equal to the target code rate, the above-mentioned target code rate is greater than or equal to the minimum code rate, and the above-mentioned minimum code rate is equal to the ratio of the above-mentioned predetermined code length to the maximum code length of the above-mentioned encoded code block.

[0120] The devices in this article can be servers, PCs, PADs, mobile phones, etc.

[0121] The present application also provides a computer program product, which, when executed on a data processing device, is suitable for executing a program for initializing at least the following method steps:

[0122] Step S101, dividing a data block into multiple code blocks, wherein the code length of the code blocks is less than a predetermined code length;

[0123] Step S102, padding the plurality of code blocks to obtain a plurality of code blocks to be encoded, wherein the code length of the code blocks to be encoded is equal to the predetermined code length;

[0124] Step S103, performing LDPC encoding on the above-mentioned code block to be encoded to obtain multiple encoded code blocks, the code rate of the above-mentioned encoded code block is equal to the target code rate, the above-mentioned target code rate is greater than or equal to the minimum code rate, and the above-mentioned minimum code rate is equal to the ratio of the above-mentioned predetermined code length to the maximum code length of the above-mentioned encoded code block.

[0125] In the above embodiments of the present invention, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0126] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of the above-mentioned units can be a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0127] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0128] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0129] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a computer-readable storage medium, including a number of instructions for a computer device (which can be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the above-mentioned methods of each embodiment of the present invention. The aforementioned computer-readable storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program codes.

[0130] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0131] 1) In the encoding method of the present application, first, the data block is divided into multiple code blocks, and the code length of the above code blocks is less than the predetermined code length; then, the multiple code blocks are padded to obtain multiple code blocks to be encoded, and the code length of the above code blocks to be encoded is equal to the above predetermined code length; finally, LDPC encoding is performed on the above code blocks to be encoded to obtain multiple encoded code blocks, and the code rate of the above encoded code blocks is equal to the target code rate, the above target code rate is greater than or equal to the minimum code rate, and the above minimum code rate is equal to the ratio of the above predetermined code length to the maximum code length of the above encoded code blocks. The method divides and fills a data block to obtain a plurality of to-be-encoded code blocks of predetermined code lengths. When the target code rate is equal to the minimum code rate, the to-be-encoded code blocks are LDPC encoded, and the code length of the encoded code blocks obtained by encoding is equal to the maximum code length, so that the code rate of the encoded code blocks is equal to the target code rate. When the target code rate is greater than the minimum code rate, the to-be-encoded code blocks are LDPC encoded, and the code length of the encoded code blocks obtained by encoding is less than the maximum code length, so that the code rate of the encoded code blocks is equal to the target code rate. Compared with the prior art in which the code length of the encoded code blocks obtained by encoding calculation is equal to the maximum code length and then rate matching is performed, the amount of encoding calculation is reduced, the encoding delay and power consumption are reduced, and the delay problem of the encoding method in the prior art is solved.

[0132] 2) In the encoding device of the present application, the first processing unit is used to divide the data block into multiple code blocks, and the code length of the above code blocks is less than the predetermined code length; the second processing unit is used to fill the multiple code blocks to obtain multiple code blocks to be encoded, and the code length of the above code blocks to be encoded is equal to the above predetermined code length; the encoding unit is used to perform LDPC encoding on the above code blocks to be encoded to obtain multiple encoded code blocks, and the code rate of the above encoded code blocks is equal to the target code rate, the above target code rate is greater than or equal to the minimum code rate, and the above minimum code rate is equal to the ratio of the above predetermined code length to the maximum code length of the above encoded code block. The device divides and fills the data block to obtain a plurality of to-be-encoded code blocks of predetermined code lengths. When the target code rate is equal to the minimum code rate, the to-be-encoded code blocks are LDPC encoded, and the code length of the encoded code blocks obtained by encoding is equal to the maximum code length, so that the code rate of the encoded code blocks is equal to the target code rate. When the target code rate is greater than the minimum code rate, the to-be-encoded code blocks are LDPC encoded, and the code length of the encoded code blocks obtained by encoding is less than the maximum code length, so that the code rate of the encoded code blocks is equal to the target code rate. Compared with the prior art in which the code length of the encoded code blocks obtained by encoding calculation is equal to the maximum code length and then rate matching is performed, the amount of encoding calculation is reduced, the encoding delay and power consumption are reduced, and the delay problem of the encoding method in the prior art is solved.

[0133] 3) The encoder of the present application includes an encoding device, and the encoding device is used for any of the above-mentioned encoding methods. In the above-mentioned encoding methods, first, the data block is divided into multiple code blocks, and the code length of the above-mentioned code blocks is less than the predetermined code length; then, the multiple code blocks are padded to obtain multiple code blocks to be encoded, and the code length of the above-mentioned code blocks to be encoded is equal to the above-mentioned predetermined code length; finally, LDPC encoding is performed on the above-mentioned code blocks to be encoded to obtain multiple encoded code blocks, and the code rate of the above-mentioned encoded code blocks is equal to the target code rate, the above-mentioned target code rate is greater than or equal to the minimum code rate, and the above-mentioned minimum code rate is equal to the ratio of the above-mentioned predetermined code length to the maximum code length of the above-mentioned encoded code block. The method divides and fills a data block to obtain a plurality of to-be-encoded code blocks of predetermined code lengths. When the target code rate is equal to the minimum code rate, the to-be-encoded code blocks are LDPC encoded, and the code length of the encoded code blocks obtained by encoding is equal to the maximum code length, so that the code rate of the encoded code blocks is equal to the target code rate. When the target code rate is greater than the minimum code rate, the to-be-encoded code blocks are LDPC encoded, and the code length of the encoded code blocks obtained by encoding is less than the maximum code length, so that the code rate of the encoded code blocks is equal to the target code rate. Compared with the prior art in which the code length of the encoded code blocks obtained by encoding calculation is equal to the maximum code length and then rate matching is performed, the amount of encoding calculation is reduced, the encoding delay and power consumption are reduced, and the delay problem of the encoding method in the prior art is solved.

[0134] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A coding method, characterized in that: include: Segmenting the data block to obtain a plurality of code blocks, wherein the code length of the code block is less than a predetermined code length; Filling the plurality of code blocks to obtain a plurality of code blocks to be encoded, wherein the code length of the code blocks to be encoded is equal to the predetermined code length; Performing LDPC encoding on the code block to be encoded to obtain multiple encoded code blocks, wherein the code rate of the encoded code block is equal to the target code rate, the target code rate is greater than or equal to the minimum code rate, and the minimum code rate is equal to the ratio of the predetermined code length to the maximum code length of the encoded code block; Performing LDPC encoding on the code block to be encoded to obtain multiple encoding code blocks, including: generating a target encoding code block according to the code block to be encoded, the target encoding code block is obtained by sequentially splicing a first code block, a second code block and a third code block, the first code block includes the code block to be encoded, the second code block and the third code block are check bit blocks, and the code length of the target encoding code block is equal to the maximum code length of the encoding code block; calculating the ratio of the code length of the first code block to the target code rate to obtain a first code length, the first code length is the code length of the encoding code block; calculating the second code block according to a parity check matrix; calculating the fourth code block according to the parity check matrix, the fourth code block is composed of a target number of code elements of the third code block, the target number is the difference between the first code length and the second code length, and the second code length is the sum of the code length of the first code block and the code length of the second code block; sequentially splicing the first code block, the second code block and the fourth code block to obtain the encoding code block.

2. The method according to claim 1, characterized in that The parity check matrix is ​​calculated based on a basic check matrix and a standard permutation matrix, the basic check matrix includes a first basic check matrix and a second basic check matrix, the parity check matrix corresponding to the first basic check matrix is ​​used to encode the data block with the target code rate greater than or equal to 1 / 3, and the parity check matrix corresponding to the second basic check matrix is ​​used to encode the data block with the target code rate greater than or equal to 1 / 5.

3. The method according to claim 2, characterized in that Generating a target encoding code block according to the to-be-encoded code block includes: In a case where the parity check matrix is ​​calculated by the first basic check matrix and a standard permutation matrix, the first code block is the code block to be encoded; In the case where the parity check matrix is ​​calculated using the second basic check matrix and a standard permutation matrix, the first code block is the code block to be encoded or the first code block consists of the code block to be encoded and a plurality of 0 code elements.

4. The method according to any one of claims 1 to 3, characterized in that: Filling the plurality of code blocks to obtain a plurality of code blocks to be encoded includes: Adding a CRC code to each of the code blocks to obtain a plurality of added code blocks, wherein the code length of the added code blocks is less than or equal to the predetermined code length; Filling is performed on a plurality of the added code blocks to obtain a plurality of the to-be-encoded code blocks.

5. The method according to any one of claims 1 to 3, characterized in that: After performing LDPC encoding on the code block to be encoded to obtain a plurality of encoded code blocks, the method further includes: The coded code blocks are bit interleaved to obtain an interleaved bit stream.

6. A coding device, characterized in that: include: A first processing unit, configured to divide the data block into a plurality of code blocks, wherein the code length of the code block is less than a predetermined code length; A second processing unit is used to fill the multiple code blocks to obtain multiple code blocks to be encoded, and the code length of the code blocks to be encoded is equal to the predetermined code length; A coding unit, configured to perform LDPC coding on the code block to be coded to obtain a plurality of coded code blocks, wherein a code rate of the coded code block is equal to a target code rate, the target code rate is greater than or equal to a minimum code rate, and the minimum code rate is equal to a ratio of the predetermined code length to a maximum code length of the coded code block; The encoding unit includes a generation module, a first calculation module, a second calculation module, a third calculation module and a splicing module, wherein the generation module is used to generate a target encoding code block according to the code block to be encoded, the target encoding code block is obtained by sequentially splicing the first code block, the second code block and the third code block, the first code block includes the code block to be encoded, the second code block and the third code block are check bit blocks, and the code length of the target encoding code block is equal to the maximum code length of the encoding code block; the first calculation module is used to calculate the ratio of the code length of the first code block to the target code rate, and obtain a first code length, the first code length is the code length of the encoding code block; the second calculation module is used to calculate the second code block according to the parity check matrix; the third calculation module is used to calculate the fourth code block according to the parity check matrix, the fourth code block is composed of a target number of code elements of the third code block, the target number is the difference between the first code length and the second code length, and the second code length is the sum of the code length of the first code block and the code length of the second code block; the splicing module is used to splice the first code block, the second code block and the fourth code block in sequence to obtain the encoding code block.

7. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored program, wherein the program executes the method of any one of claims 1 to 5.

8. A processor, characterized in that: The processor is used to run a program, wherein the program executes the method according to any one of claims 1 to 5 when running.

9. An encoder, comprising an encoding device, characterized in that: The encoding device is used to execute the method according to any one of claims 1 to 5.

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