Baseband processing unit and random access processing method for indoor small base station

Abstract

The present disclosure proposes a baseband processing unit and a random access processing method for an indoor small base station, which relate to the field of wireless communications. The baseband processing unit of the indoor small base station includes: a hardware acceleration card, which is configured to pre-process the uplink physical random access channel PRACH forwarded by the remote radio unit RRU, remove the cyclic prefix, and perform a fast Fourier transform FFT, and then transmit it to a general processor; a general processor, which is configured to detect the random access preamble code and estimate the time advance of the PRACH channel from the hardware acceleration card. The random access processing of the base station is implemented based on the general processor, which is more flexible and scalable, and solves the limitations of proprietary chips; based on the respective characteristics of the hardware acceleration card and the general processor, the functions are reasonably divided, and the complexity of the base station design is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of wireless communications, and in particular to a baseband processing unit and a random access processing method for an indoor small base station. Background Art

[0002] The 5G (5th Generation) random access process is divided into contention-based random access and non-contention-based random access. Contention-based random access means that when multiple user equipment (UE) sends a preamble to the base station, the base station cannot distinguish which UE sent it, so the UE needs to send a MSG3 (a random access signaling) related to itself to the base station, and the base station can then distinguish which UE sent it. Non-contention-based random access means that the base station specifies a UE to send a message to the base station, the base station allocates resources to the specified UE, and the UE sends the preamble given by the base station.

[0003] The inventors have found that in some related technologies, the random access processing scheme of the base station is implemented based on a baseband proprietary chip, which has poor scalability and a relatively complex design. Summary of the invention

[0004] The disclosed embodiment implements random access processing of the base station based on a general-purpose processor, which is more flexible and scalable and solves the limitations of proprietary chips. Based on the respective characteristics of the hardware acceleration card and the general-purpose processor, the functions are reasonably divided and the complexity of the base station design is reduced.

[0005] The present disclosure provides a baseband processing unit for an indoor small base station, including:

[0006] The hardware acceleration card is configured to pre-process the uplink physical random access channel PRACH channel forwarded by the remote radio unit RRU, remove the cyclic prefix, and perform fast Fourier transform FFT before transmitting it to the general processor;

[0007] The general processor is configured to detect a random access preamble code and estimate a timing advance amount for a PRACH channel from a hardware acceleration card.

[0008] In some embodiments, a general purpose processor is configured to:

[0009] Perform a cross-correlation operation on the PRACH channel from the hardware acceleration card and the logical root sequence to obtain a cross-correlation result;

[0010] Perform inverse fast Fourier transform IFFT on the cross-correlation result to obtain an IFFT result;

[0011] The IFFT results of multiple antennas are combined to obtain a combined result;

[0012] The random access preamble and the time advance are determined by performing peak search on the combined result.

[0013] In some embodiments, the general processor, when performing the combining process, is configured to: accumulate the IFFT results of multiple antennas on all antennas and all symbols to obtain the combining result on the subcarriers.

[0014] In some embodiments, the merging algorithm used by the general processor when performing merging processing is:

[0015]

[0016] Among them, c u (k,l,r) represents the IFFT result based on the logical root sequence u on antenna r, symbol l, and subcarrier k, nAnt represents the maximum number of antennas r, nRepeat represents the maximum number of symbols l, P u (k) represents the combining result based on the logical root sequence u on subcarrier k.

[0017] In some embodiments, the general processor, when determining the random access preamble and the timing advance, is configured to:

[0018] Calculate the noise floor threshold;

[0019] For each zero correlation interval of the logical root sequence, a peak search is performed on the combined result on subcarrier k;

[0020] When the searched peak value is greater than the bottom noise threshold, it is determined that the random access preamble is detected;

[0021] Determine the sequence number of the random access preamble according to the zero correlation interval corresponding to the random access preamble and its length, the logical root and the maximum number of subcarriers k;

[0022] The timing advance is determined according to the zero correlation interval corresponding to the random access preamble code and its length and peak position, the number of IFFT points, and the maximum number of subcarriers k.

[0023] In some embodiments, the general processor, when calculating the noise floor threshold, is configured to:

[0024] The merging result P of the logical root sequence u on subcarrier k based on the number of IFFT points u (k) calculating a first power average value;

[0025] Eliminate each P u (k) a subcarrier whose amplitude is greater than the product of the first power average value and a preset noise threshold;

[0026] Based on the number of IFFT points, the remaining P u (k) Calculating a second power average value, and using the second power average value as a noise floor threshold.

[0027] In some embodiments, performing peak search on the combined result on subcarrier k and detecting a random access preamble code includes:

[0028] For a logical root sequence The combined result P on subcarrier k is u (k), and the noise floor threshold The peak search is performed in the following steps:

[0029]

[0030] For a u value of v, the peak value is obtained It is located in the vth segment;

[0031] When detected When , it is determined that a random access preamble is detected;

[0032] Among them, v represents different zero correlation intervals under the logical root sequence, F overSamp =N IFFT / L RA Represents the oversampling factor, N cS represents the length of the zero correlation interval v, L RA Indicates the maximum number of subcarriers k, max() means taking the maximum value, N IFFT Indicates the number of IFFT points, Indicates rounding down to an integer.

[0033] In some embodiments, the general processor, when determining the sequence number of the random access preamble, is configured to:

[0034] according to Determine the sequence number of the random access preamble,

[0035] Where PreambleIdx represents the sequence number of the random access preamble, nseq represents the logical root, L RA represents the maximum number of subcarriers k, v represents the zero correlation interval corresponding to the random access preamble code, N CS represents the length of the zero correlation interval v, Indicates rounding down to an integer.

[0036] In some embodiments, the general purpose processor, when determining the timing advance, is configured to:

[0037] Determine the timing offset based on the number of IFFT points, the maximum number of subcarriers k, the zero correlation interval corresponding to the random access preamble code, the length of the zero correlation interval and the peak position;

[0038] The time advance is determined based on the timing offset, the subcarrier spacing of the PRACH, the number of IFFT points, and the normalized frequency.

[0039] In some embodiments, Determine timing deviations;

[0040] According to nTa=value_TA / (Δf·N IFFT / f0), determine the time advance;

[0041] Where, value_TA represents the timing deviation, F overSamp Indicates that according to the IFFT point number N IFFT and the maximum number of subcarriers k, v represents the zero correlation interval corresponding to the random access preamble, N cS represents the length of the zero correlation interval v, maxPos represents the peak position, represents the integer rounded down, nTa represents the time advance, Δf represents the subcarrier spacing of PRACH, Δf·N IFFT represents the sampling rate, and f0 represents the normalized frequency.

[0042] In some embodiments, the general processor is configured to: perform amplitude normalization processing on the PRACH channel from the hardware acceleration card before the cross-correlation operation.

[0043] In some embodiments, the general processor, when performing amplitude normalization processing, is configured to:

[0044] Calculate the amplitude mean of the PRACH channel from the hardware accelerator card;

[0045] Determine the amplitude normalization parameter according to the size of the amplitude mean;

[0046] The PRACH channel from the hardware acceleration card is amplitude normalized according to the amplitude normalization parameter.

[0047] In some embodiments, the general processor is further configured to identify a terminal ready to access based on a detected random access preamble code; and control the time when an uplink signal of the terminal arrives at the base station based on an estimated time advance.

[0048] In some embodiments, the hardware acceleration card includes a field programmable gate array FPGA hardware acceleration card.

[0049] The present disclosure provides a random access processing method, including:

[0050] The hardware accelerator card pre-processes the uplink physical random access channel PRACH forwarded by the remote radio unit RRU, removes the cyclic prefix, and performs fast Fourier transform FFT, and then transmits it to the general processor;

[0051] The general processor performs a cross-correlation operation on the PRACH channel from the hardware acceleration card and the logical root sequence to obtain a cross-correlation result;

[0052] The general processor performs inverse fast Fourier transform IFFT on the cross-correlation result to obtain an IFFT result;

[0053] The general processor combines the IFFT results of multiple antennas to obtain a combined result;

[0054] The general processor determines the random access preamble code and the time advance by performing peak search on the combined result.

[0055] In some embodiments, the general processor combines the IFFT results of multiple antennas, including:

[0056] The IFFT results of multiple antennas are accumulated on all antennas and all symbols to obtain the combined results on the subcarriers.

[0057] In some embodiments, the general processor determines a random access preamble and a timing advance, including:

[0058] Calculate the noise floor threshold;

[0059] For each zero correlation interval of the logical root sequence, a peak search is performed on the combined result on subcarrier k;

[0060] When the searched peak value is greater than the bottom noise threshold, it is determined that the random access preamble is detected;

[0061] Determine the sequence number of the random access preamble according to the zero correlation interval corresponding to the random access preamble and its length, the logical root and the maximum number of subcarriers k;

[0062] The timing advance is determined according to the zero correlation interval corresponding to the random access preamble code and its length and peak position, the number of IFFT points, and the maximum number of subcarriers k.

[0063] The embodiments of the present disclosure provide a non-transitory computer-readable storage medium on which a computer program is stored. When the program is executed by a hardware acceleration card and a general-purpose processor, the steps of the random access processing method described in any embodiment are implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] The following is a brief introduction to the drawings required for use in the embodiments or related technical descriptions. The present disclosure can be more clearly understood according to the following detailed description with reference to the drawings.

[0065] Obviously, the drawings described below are only some embodiments of the present disclosure, and a person skilled in the art can obtain other drawings based on these drawings without creative work.

[0066] Figure 1 A schematic diagram of an indoor small base station and its baseband processing unit and remote radio frequency unit according to some embodiments of the present disclosure is shown.

[0067] Figure 2 A flow chart showing a random access processing method for an indoor small base station according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0068] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure.

[0069] Unless otherwise specified, descriptions such as “first” and “second” in the present disclosure are used to distinguish different objects and are not used to indicate meanings such as size or time sequence.

[0070] Figure 1 A schematic diagram of an indoor small base station and its baseband processing unit and remote radio frequency unit according to some embodiments of the present disclosure is shown.

[0071] like Figure 1 As shown, the indoor small base station 10 includes a BBU 110 (Building Baseband Unit) and an RRU 120 (Remote Radio Unit). The signal sent by the terminal is transmitted to the BBU 110 through the RRU 120 for processing.

[0072] BBU110 includes a hardware acceleration card 111 and a general processor 112. The hardware acceleration card 111 mainly unloads some physical layer intensive computing processes, such as physical layer encoding and decoding, FFT (fast Fourier transform), removal of cyclic prefix (CP), etc., but is not limited to the examples given. According to business needs, the hardware acceleration card 111 can be set with one or more blocks, for example, a first hardware acceleration card for encoding and decoding and a second hardware acceleration card for fronthaul processing. The hardware acceleration card 111 can be, for example, an FPGA hardware acceleration card implemented based on a field programmable gate array (Field Programmable Gate Array, FPGA). The general processor 112 mainly completes high-level protocol stack functions such as RRC (Radio Resource Control, Radio Resource Control) / PDCP (Packet Data Convergence Protocol, Packet Data Convergence Protocol) / RLC (Radio Link Control, Radio Link Layer Control Protocol) / MAC (Media Access Control, Media Access Control) and some non-intensive computing physical layer functions. The general processor 112 can be, for example, an X86 general processor.

[0073] The processing speed of the hardware acceleration card 111 is very fast, and some physical layer intensive computing processes can be unloaded, thereby reducing the load of the general processor 112 and improving the performance power consumption ratio of the BBU.

[0074] Combine the following Figure 2 The respective functions of the hardware acceleration card 111 and the general processor 112 of the BBU 110 are described in detail.

[0075] Figure 2 A schematic flow chart of a random access processing method of a base station according to some embodiments of the present disclosure is shown.

[0076] like Figure 2 As shown, the random access processing method of the base station includes: steps 200-250, wherein step 200 is executed by a hardware acceleration card, and steps 210-250 are executed by a general processor.

[0077] In step 200, the hardware acceleration card pre-processes the uplink PRACH (Physical Random Access Channel) forwarded by the RRU, removes the cyclic prefix, and performs a fast Fourier transform (FFT), and then transmits it to the general processor.

[0078] PRACH is the access channel when the terminal initiates a call. After receiving the PRACH response message, the terminal will send an RRC Connection Request message on the PRACH channel according to the information indicated by the base station to establish an RRC connection.

[0079] Then, the general processor detects the random access preamble code and estimates the time advance amount for the PRACH channel from the hardware acceleration card, see steps 210-250 for details.

[0080] In step 210, the general processor performs amplitude normalization processing on the PRACH channel from the hardware acceleration card.

[0081] enter:

[0082] represents the PRACH channel received by the base station on antenna r, symbol l, subcarrier k,

[0083] Output:

[0084] Y(k,l,r) represents the normalized PRACH channel received on antenna r, symbol l, and subcarrier k.

[0085] For details of the normalization processing algorithm, please refer to (1-3).

[0086] (1) Calculate the mean amplitude f of the PRACH channel from the hardware accelerator card using the following formula: MeanAmp

[0087]

[0088] Where nAnt represents the maximum number of antennas r, nRepeat represents the maximum number of symbols l, L RA Indicates the maximum number of subcarriers k.

[0089] (2) According to the size of the amplitude mean, determine the amplitude normalization parameter nBit. The specific formula is as follows:

[0090] like

[0091] (3) The PRACH channel from the hardware acceleration card is amplitude normalized according to the amplitude normalization parameter. The specific formula is as follows:

[0092]

[0093] In step 220, the general processor performs a cross-correlation operation on the PRACH channel and the logical root sequence to obtain a cross-correlation result.

[0094] enter:

[0095] Y(k,l,r) represents the normalized PRACH channel received on antenna r, symbol l, and subcarrier k.

[0096] X u (k) represents a local logical root sequence, such as a local ZC (Zadoff-chu) sequence,

[0097] Among them, the logical root sequence of PRACH uses the ZC sequence as the logical root sequence (hereinafter referred to as the ZC logical root sequence). Since each cell preamble sequence is generated by the ZC logical root sequence through cyclic shift (cyclic shift is also the zero correlation interval configuration, Ncs represents the length of the zero correlation interval), each cell has 64 preamble sequences, and the preamble sequence used by the UE is a cyclic prefix (CP) randomly selected or allocated by the eNB. The random access preamble code preamble is used to identify the UE identity during random access.

[0098] Output:

[0099] C u (k,l,r) represents the cross-correlation result

[0100] The cross-correlation processing algorithm is:

[0101] C u (k,l,r)=conj(Y(k,l,r))·X u (k)

[0102] Among them, conj() represents the cross-correlation operation.

[0103] In step 230, the general processor performs an inverse fast Fourier transform (IFFT) on the cross-correlation result to obtain an IFFT result.

[0104] enter:

[0105] C u (k,l,r), represents the cross-correlation result on antenna r, symbol l, and subcarrier k

[0106] N IFFT , indicating the number of IFFT points, for example 1024

[0107] Output:

[0108] c u (k,l,r), represents the IFFT result on antenna r, symbol l, subcarrier k

[0109] The IFFT processing algorithm is:

[0110] c u (k,l,r)=ifft(C u (k,l,r))

[0111] Among them, ifft() represents IFFT operation.

[0112] In step 240, the general processor performs multi-antenna combining, that is, combines the IFFT results of multiple antennas to obtain a combined result.

[0113] enter:

[0114] c u (k,l,r), represents the IFFT result on antenna r, symbol l, subcarrier k

[0115] Output:

[0116] P u (k) represents the combined result on subcarrier k after multiple antennas are combined

[0117] The specific algorithm is:

[0118]

[0119] Among them, c u (k,l,r) represents the IFFT result on antenna r, symbol l, subcarrier k (based on the logical root sequence u), nAnt represents the maximum number of antennas r, nRepeat represents the maximum number of symbols l, P u (k) represents the combining result on subcarrier k (based on the logical root sequence u).

[0120] In step 250, the general processor determines the random access preamble and the timing advance by performing a peak search on the combined result.

[0121] enter:

[0122] P u (k) represents the combined result on subcarrier k after multiple antennas are combined

[0123] Output:

[0124] PreambleIdx, which indicates the sequence number of the random access preamble code detected by PRACH (Preamble Index),

[0125] nTa represents the estimated timing advance after the PRACH detects the random access preamble. For details on the process of determining the random access preamble and timing advance, please refer to (1-5).

[0126] (1) Calculate the noise floor threshold.

[0127] Based on the number of IFFT points N IFFT , according to the formula For each P u (k) Calculate the first power average meanP u ;

[0128] Eliminate each P u (k) The amplitude is greater than the first power average meanP u and the product of the preset noise threshold fNoiseThreshold (fNoiseThreshold·meanP u ) subcarrier;

[0129] Based on the number of IFFT points, the remaining P u (k) Calculate the second power average value and use the second power average value as the noise floor threshold

[0130] (2) For each zero correlation interval of the logical root sequence, a peak search is performed on the combined result on subcarrier k.

[0131] For a logical root sequence Power value P u (k), noise floor threshold Search for the maximum value (peak value) by traversing the following sections:

[0132]

[0133] Among them, v represents different zero correlation intervals under the logical root sequence, F overSamp =N IFFT / L RA =1024 / L RA Represents the oversampling factor, N CS represents the length of the zero correlation interval v, L RA Indicates the maximum number of subcarriers k.

[0134] For a u value of a certain v, the maximum value is obtained It is located in the vth segment, and the position of the maximum value is set to maxPos.

[0135] (3) When the searched peak value is greater than the noise floor threshold, it is determined that the random access preamble is detected.

[0136] That is, when it is detected When , the random access preamble is considered to be detected.

[0137] (4) Determine the sequence number of the random access preamble according to the zero correlation interval corresponding to the random access preamble and its length, the logical root and the maximum number of subcarriers k.

[0138]

[0139] Where PreambleIdx represents the sequence number of the random access preamble, nseq represents the logical root, L RA represents the maximum number of subcarriers k, v represents the zero correlation interval corresponding to the random access preamble code, N CS represents the length of the zero correlation interval v, Indicates rounding down to an integer.

[0140] (5) Determine the timing advance based on the zero correlation interval corresponding to the random access preamble code and its length and peak position, the number of IFFT points, and the maximum number of subcarriers k.

[0141] In some embodiments, the timing deviation is determined based on the number of IFFT points, the maximum number of subcarriers k, the zero correlation interval corresponding to the random access preamble code, the length of the zero correlation interval and the peak position; the time advance is determined based on the timing deviation, the subcarrier spacing of PRACH, the number of IFFT points and the normalized frequency.

[0142] For example, according to Determine the timing deviation; according to nTa = value_TA / (Δf·N IFFT / f0) to determine the time advance.

[0143] Where, value_TA represents the timing deviation, F overSamp Indicates that according to the IFFT point number N IFFT and the maximum number of subcarriers k L RA The oversampling coefficient is determined, v represents the zero correlation interval corresponding to the random access preamble, N CS represents the length of the zero correlation interval v, maxPos represents the peak position, represents the integer rounded down, nTa represents the time advance, Δf represents the subcarrier spacing of PRACH, Δf·N IFFT represents the sampling rate, and f0 represents the normalized frequency. IFFT For example, it is 1024. For PRACH with Δf=30kHz, the corresponding sampling rate is 30.72MHz. For PRACH with Δf=1.25kHz, the corresponding sampling rate is 1.28MHz. f0 is, for example, 3.84MHz, so that the timing deviation is normalized to 3.84MHz, that is,

[0144] After determining the random access preamble and the time advance, the general processor can identify the terminal ready to access according to the detected random access preamble; and control the time when the uplink signal of the terminal reaches the base station according to the estimated time advance.

[0145] The random access processing of the base station is implemented based on a general-purpose processor, which is more flexible and scalable and solves the limitations of proprietary chips. Based on the respective characteristics of the hardware accelerator card and the general-purpose processor, the functions are reasonably divided and the complexity of the base station design is reduced. The high-performance multi-antenna merging and peak search methods ensure the access check performance.

[0146] In summary, during the random access processing, the general processor 112 is configured to:

[0147] Perform amplitude normalization on the PRACH channel from the hardware accelerator card;

[0148] Perform a cross-correlation operation on the PRACH channel from the hardware acceleration card and the logical root sequence to obtain a cross-correlation result;

[0149] Perform inverse fast Fourier transform IFFT on the cross-correlation result to obtain an IFFT result;

[0150] The IFFT results of multiple antennas are combined to obtain a combined result;

[0151] The random access preamble and the time advance are determined by performing peak search on the combined result.

[0152] The specific implementation methods of the above steps of the general processor 112 are as mentioned above and will not be repeated here.

[0153] Some embodiments of the present disclosure also provide a non-transitory computer-readable storage medium on which a computer program is stored. When the program is executed by a hardware acceleration card and a general-purpose processor, the steps of the random access processing method are implemented.

[0154] Those skilled in the art will appreciate that the embodiments of the present disclosure may be provided as methods, systems, or computer program products. Therefore, the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present disclosure may take the form of a computer program product implemented on one or more non-transient computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer program code.

[0155] The present disclosure is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present disclosure. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0156] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0157] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0158] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A baseband processing unit for an indoor small base station, It is characterized in that include: The hardware acceleration card is configured to pre-process the uplink physical random access channel PRACH channel forwarded by the remote radio unit RRU, remove the cyclic prefix, and perform fast Fourier transform FFT before transmitting it to the general processor; A general purpose processor is configured to detect a random access preamble and estimate a timing advance for a PRACH channel from a hardware acceleration card, including: Perform a cross-correlation operation on the PRACH channel from the hardware acceleration card and the logical root sequence to obtain a cross-correlation result; Perform inverse fast Fourier transform IFFT on the cross-correlation result to obtain an IFFT result; The IFFT results of multiple antennas are combined to obtain a combined result; The random access preamble and the time advance are determined by performing a peak search on the combined result, including: calculating a bottom noise threshold; performing a peak search on the combined result on subcarrier k for each zero correlation interval of the logical root sequence; when the searched peak is greater than the bottom noise threshold, it is determined that the random access preamble is detected; according to the zero correlation interval corresponding to the random access preamble and its length, the logical root and the maximum number of subcarriers k, the sequence number of the random access preamble is determined; according to the zero correlation interval corresponding to the random access preamble and its length and peak position, the number of IFFT points, and the maximum number of subcarriers k, the time advance is determined.

2. The baseband processing unit according to claim 1, It is characterized in that The general processor, when performing the merge process, is configured as follows: The IFFT results of multiple antennas are accumulated on all antennas and all symbols to obtain the combined results on the subcarriers.

3. The baseband processing unit according to claim 2, It is characterized in that The merging algorithm used by the general processor during merging is: Among them, c u (k,l,r) represents the IFFT result based on the logical root sequence u on antenna r, symbol l, and subcarrier k, nAnt represents the maximum number of antennas r, nRepeat represents the maximum number of symbols l, P u (k) represents the combining result based on the logical root sequence u on subcarrier k.

4. The baseband processing unit according to claim 1, It is characterized in that The general purpose processor, when calculating the noise floor threshold, is configured as follows: The merging result P of the logical root sequence u on subcarrier k based on the number of IFFT points u (k) calculating a first power average value; Eliminate each P u (k) a subcarrier whose amplitude is greater than the product of the first power average value and a preset noise threshold; Based on the number of IFFT points, the remaining P u (k) Calculating a second power average value, and using the second power average value as a noise floor threshold.

5. The baseband processing unit according to claim 1, It is characterized in that Performing peak search on the combined result on subcarrier k and detecting a random access preamble code includes: For a logical root sequence The combined result P on subcarrier k is u (k), and the noise floor threshold According to the following segment n 0 ,n 1 ,…,n max v Traverse to search for peaks: For a u value of v, the peak value is obtained It is located in the vth segment; When detected When , it is determined that a random access preamble is detected; Among them, v represents different zero correlation intervals under the logical root sequence, F overSamp =N IFFT / L RA Represents the oversampling factor, N CS represents the length of the zero correlation interval v, L RA Indicates the maximum number of subcarriers k, max() means taking the maximum value, N IFFT Indicates the number of IFFT points, Indicates rounding down to an integer.

6. The baseband processing unit according to claim 1, It is characterized in that The general processor, when determining the sequence number of the random access preamble, is configured to: according to Determine the sequence number of the random access preamble, Where PreambleIdx represents the sequence number of the random access preamble, nseq represents the logical root, L RA represents the maximum number of subcarriers k, v represents the zero correlation interval corresponding to the random access preamble code, N CS represents the length of the zero correlation interval v, Indicates rounding down to an integer.

7. The baseband processing unit according to claim 1, It is characterized in that The general purpose processor, when determining the timing advance, is configured to: Determine the timing offset based on the number of IFFT points, the maximum number of subcarriers k, the zero correlation interval corresponding to the random access preamble code, the length of the zero correlation interval and the peak position; The time advance is determined based on the timing offset, the subcarrier spacing of the PRACH, the number of IFFT points, and the normalized frequency.

8. The baseband processing unit according to claim 7, It is characterized in that according to Determine timing deviations; According to nTa=value_TA / (Δf·N IFFT / f 0 ), determine the time advance; Where, value_TA represents the timing deviation, F overSamp Indicates that according to the IFFT point number N IFFT and the maximum number of subcarriers k, v represents the zero correlation interval corresponding to the random access preamble, N CS represents the length of the zero correlation interval v, max Pos represents the peak position, represents the integer rounded down, nTa represents the time advance, Δf represents the subcarrier spacing of PRACH, Δf·N IFFT represents the sampling rate, f 0 represents the normalized frequency.

9. The baseband processing unit according to claim 1, It is characterized in that A general purpose processor, configured as: Before the cross-correlation operation, the PRACH channel from the hardware acceleration card is amplitude normalized.

10. The baseband processing unit according to claim 9, It is characterized in that The general purpose processor, when performing amplitude normalization processing, is configured as follows: Calculate the amplitude mean of the PRACH channel from the hardware accelerator card; Determine the amplitude normalization parameter according to the size of the amplitude mean; The PRACH channel from the hardware acceleration card is amplitude normalized according to the amplitude normalization parameter.

11. The baseband processing unit according to claim 1, It is characterized in that The general processor is further configured to identify a terminal ready to access according to the detected random access preamble code; and to control the time when the uplink signal of the terminal arrives at the base station according to the estimated time advance.

12. The baseband processing unit according to claim 1, It is characterized in that The hardware acceleration card includes a field programmable gate array FPGA hardware acceleration card.

13. A random access processing method, It is characterized in that include: The hardware accelerator card pre-processes the uplink physical random access channel PRACH forwarded by the remote radio unit RRU, removes the cyclic prefix, and performs fast Fourier transform FFT, and then transmits it to the general processor; The general processor performs a cross-correlation operation on the PRACH channel from the hardware acceleration card and the logical root sequence to obtain a cross-correlation result; The general processor performs inverse fast Fourier transform IFFT on the cross-correlation result to obtain an IFFT result; The general processor combines the IFFT results of multiple antennas to obtain a combined result; The general processor determines the random access preamble and the time advance by performing a peak search on the combined result, including: calculating the bottom noise threshold; performing a peak search on the combined result on the subcarrier k for each zero correlation interval of the logical root sequence; when the searched peak is greater than the bottom noise threshold, it is determined that the random access preamble is detected; according to the zero correlation interval corresponding to the random access preamble and its length, the logical root and the maximum number of subcarriers k, the sequence number of the random access preamble is determined; according to the zero correlation interval corresponding to the random access preamble and its length and peak position, the number of IFFT points, and the maximum number of subcarriers k, the time advance is determined.

14. The method according to claim 13, It is characterized in that The general processor combines the IFFT results of multiple antennas, including: The IFFT results of multiple antennas are accumulated on all antennas and all symbols to obtain the combined results on the subcarriers.

15. A non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a hardware acceleration card and a general-purpose processor, implements the steps of the random access processing method described in any one of claims 13 to 14.

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