Cryptographic architecture for cipher permutation

Abstract

Cryptographic methods and systems are described. Certain examples relate to performing cryptographic operations involving cryptographic permutations. The methods and systems can be used to provide cryptographic functions such as hashing, encryption, decryption, and random number generation. In one example, a cryptographic architecture is provided. The cryptographic architecture has a processor interface that includes a set of cryptographic registers, where the processor interface is accessible by at least one processing unit. The cryptographic architecture also has a cryptographic permutation unit that includes circuitry for performing cryptographic permutations using data stored within the set of cryptographic registers. In an example, the at least one processing unit instructs the cryptographic permutation and uses the processor interface to access a result of the cryptographic permutation.

Description

Technical Field

[0001] The present invention relates to a cryptographic architecture and a method for performing cryptographic operations. In particular, the present invention relates to cryptographic operations involving cryptographic permutations. Certain examples described herein can be used within a computing device to perform cryptographic operations. Background Art

[0002] Recently, the number of devices connected to computer networks has exploded. For example, internet connectivity is expanding from computing devices such as desktop and laptop computers to embedded systems in everyday items such as motor vehicles, light bulbs, refrigerators, medical devices, thermostats, and monitoring systems. Telecommunications links allow many low-cost computing devices to report sensor data and / or be controlled worldwide. One problem facing these connected devices is that they are often vulnerable to attack and malicious control. For example, hundreds or thousands of embedded devices could be compromised by a malicious party and used to perform a distributed denial of service attack. In many cases, control of these devices can be easily gained due to poor or limited implementation of cryptographic protocols. As the number and popularity of these connected devices continue to grow, ensuring their security becomes an unresolved issue.

[0003] Another consideration in ensuring the security of connected computing devices is the potential for future attacks using quantum computing. For many years, quantum computers were primarily theoretical. However, research and implementation of quantum computers is rapidly advancing. Quantum computers with 50 and 72 qubits are currently available, and many research groups are actively working on machines with even higher qubits. Given the potential future reality of quantum computing, recent work has demonstrated that many well-known public-key cryptosystems can be cracked by sufficiently powerful quantum computers.

[0004] A challenge in implementing cryptographic functions, especially those that are “post-quantum” secure, is that many of these functions are resource intensive. For example, many cryptographic functions involve complex mathematical functions using values ​​with long bit lengths. These typically consume a large number of processor cycles and are difficult to implement in low-resource embedded devices. Additionally, as end-to-end encryption of both data and communications becomes commonplace, these cryptographic functions must be repeatedly executed at high speeds. To be secure is to be slow.

[0005] US 9,772,845 B2 describes a device for processing the KECCAK secure hash algorithm. In the device of US 9,772,845 B2, an instruction decoder receives an instruction for processing a KECCAK state cube representing data representing a KECCAK state of the KECCAK hash algorithm. The instruction instructs the KECCAK state cube to be partitioned into a plurality of sub-cubes, each of which is stored in a plurality of registers. An execution unit coupled to the instruction decoder executes the KECCAK hash algorithm in a vectorized manner on the plurality of sub-cubes stored in the plurality of registers. The device of US 9,772,845 B2 is a processor such as a Complex Instruction Set Computing (CISC) or Reduced Instruction Set Computing (RISC) processor. The method described in US 9,772,845 B2 can be implemented by the processor. The method can be implemented using eight instructions per round of the KECCAK algorithm, where each round is performed on a slice (sub-cube) of the total data.

[0006] It would be desirable to provide efficient implementations of cryptographic operations. For example, it would be desirable to provide implementations that can be used within low-resource embedded systems and / or in high-speed data processing operations while providing resistance to attacks in a post-quantum environment. Summary of the Invention

[0007] Various aspects of the present invention are set out in the accompanying independent claims. Certain variations of the invention are then set out in the accompanying dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Examples of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0009] Figure 1 is a schematic diagram illustrating a cryptographic architecture according to an example;

[0010] Figure 2 is a schematic diagram illustrating registers of a processor interface according to an example;

[0011] Figure 3 is a schematic diagram illustrating a first set of cryptographic registers for a processor interface according to an example;

[0012] Figure 4 is a schematic diagram illustrating a second set of cryptographic registers for a processor interface according to an example;

[0013] Figure 5 is a schematic diagram illustrating a password permutation unit according to an example;

[0014] Figure 6 is a schematic diagram illustrating a set of control registers for a processor interface according to an example;

[0015] Figure 7 is a flowchart illustrating a method of performing a cryptographic operation according to an example; and

[0016] Figure 8A and Figure 8B are flowcharts illustrating first and second sequences of operations performed by a cryptographic architecture and a processing unit, respectively, according to an example. DETAILED DESCRIPTION

[0017] Certain examples described herein provide a cryptographic architecture that allows a processing unit to efficiently perform cryptographic permutations. The cryptographic architecture provides a processor interface that enables the processing unit to efficiently communicate with a cryptographic permutation unit to perform cryptographic permutations. As such, the processing unit can efficiently offload the computation of permutations to a specialized module and then access the results of the permutations via the processor interface. The cryptographic architecture can provide atomic low-level operations that allow fast computation of many high-level cryptographic functions, including those that are "post-quantum" secure. The cryptographic architecture can perform fast cryptographic primitive functions on behalf of a processor or microprocessor, thus providing benefits for both low-power embedded devices and high-throughput server devices.

[0018] Figure 1 An example 100 of a cryptographic architecture 110 is shown. In Figure 1 the cryptographic architecture 110 includes a processor interface 120 that enables the cryptographic architecture 110 to communicate with a processing unit 130. The processing unit 130 is shown in a dotted outline because it can not form a part of the cryptographic architecture 110. The cryptographic architecture 110 also includes a cryptographic permutation unit 140. The cryptographic permutation unit 140 includes circuitry for performing cryptographic permutations. As Figure 1 shown, in use, the processing unit 130 instructs a cryptographic permutation and accesses the results of the cryptographic permutation using the processor interface 120.

[0019] In one example, the processor interface 120 includes a set of cryptographic registers. The processing unit 130 has access to the cryptographic registers, e.g., certain cryptographic registers can be read and / or written by the processing unit 130. In use, the processing unit 130 can access the results of a cryptographic permutation as performed by the cryptographic permutation unit 140 via the set of cryptographic registers (i.e., using data stored within the set of cryptographic registers). The set of cryptographic registers can be used to exchange data and control information between the cryptographic permutation unit 140 and the processing unit 130. The cryptographic registers can be accessed as one or more memory-mapped registers and as part of a named single instruction multiple data (SIMD) or vector register file of the processing unit 130.

[0020] In some examples, the processing unit 130 includes a microprocessor having one or more processing cores, e.g., the processing unit 130 can be a processing unit for an embedded device. In other examples, the processing unit can include a central processing unit of a computing device having one or more processing cores, e.g., the processing unit 130 can be a processing unit for a mobile computing device, a desktop computer, and / or a server computing device.

[0021] The cryptographic architecture 110 can be implemented in a variety of different ways (and combinations of approaches are possible). In one case, the cryptographic architecture 110 can be implemented using one or more application specific integrated circuits (ASICs). In another case, the cryptographic architecture 110 can be implemented using one or more field programmable gate arrays (FPGAs). In yet another case, the cryptographic architecture 110 can be implemented using firmware for the processing unit 130. In some cases, different components of the cryptographic architecture 110 can be implemented using a combination of two or more of ASICs, FPGAs, and firmware instructions. In one case, the functionality of the cryptographic architecture 110 can be provided via one or more of microcode and firmware updates. In such a case, the code can need to be authenticated to ensure security. The cryptographic rekey unit 140 can be implemented in a similar manner.

[0022] In one example, one or more of the cryptographic architecture 110 and the cryptographic rekey unit 140 can be provided (e.g., packaged) as a discrete unit. For example, the discrete unit can be a standalone secure microcontroller (e.g., provided as a smart card, a universal serial bus - USB - device, and / or a radio frequency identification - RFID - device), a cryptographic co-processor or accelerator, a cryptographic trusted platform module (TPM) or hardware security module (HSM). The discrete unit can be coupled to the processing unit 130 and / or co-located on a circuit board via one or more communication buses or interfaces. Thus, the cryptographic architecture 110 can be provided as a single chip that is easily added to a computing board for a variety of computing devices.

[0023] Figure 2 The processor interface 120 is shown with the cryptographic registers including a first set of data registers 210 and a second set of control registers 220. The cryptographic rekey unit 140 is able to read data and / or write data to both sets of registers 210, 220. Likewise, the processing unit 130 is also communicatively coupled to the cryptographic registers and is able to read data and / or write data to registers within the first set 210 and the second set 220. The first set of registers 210 and the second set of registers 220 thus provide an interface between the processing unit 130 and the cryptographic rekey unit 140.

[0024] In one case, the cryptographic registers of the processor interface 120 may be memory mapped to the address space of the processing unit 130. This may be implemented directly, for example via a bus of the processing unit 130 and / or via a memory management unit (MMU). Different cryptographic registers may be accessed in different ways if desired. If a given cryptographic register is memory mapped, a read or write by the processing unit 130 to a particular address in the memory may be mapped as a read or write to the given cryptographic register (or a portion of the register). In a reduced instruction set computing (RISC) instruction set architecture (ISA), such as RISC-V, the cryptographic registers of the processor interface 120 may be implemented as one or more control and status registers (CSRs) and / or one or more vector extensions, in which case the cryptographic registers may be considered as one or more vector registers.

[0025] In some examples, processor interface 120 can be implemented using one or more auxiliary processor interface mechanisms such as processor interrupts, direct memory access (DMA), and ISA extensions. For example, processor interface 120 can enable cryptographic substitution unit 140 to invoke an interrupt on processing unit 130 and / or perform DMA operations on a bus associated with processing unit 130 (e.g., a bus of processing unit 130 or a bus to which processing unit 130 is coupled). Alternatively or additionally, control interactions performed through processor interface 120 can be implemented as instruction set architecture extensions.

[0026] In some examples, a command for performing a particular cryptographic permutation operation can be encoded as a single machine code instruction, for example, a single instruction executed by processing unit 130 to perform the cryptographic permutation. For example, a single machine code instruction can activate cryptographic permutation unit 140 via processor interface 120, which performs the permutation and returns the result to processing unit 130 via processor interface 120. In one embodiment, cryptographic permutation unit 140 can set a control flag within second set of control registers 220, which processing unit 130 can check to determine when the cryptographic permutation is complete, at which point the result of the cryptographic permutation can be read by processing unit 130 from first set of data registers 210. In one embodiment, cryptographic permutation unit 140 can trigger an interrupt received by processing unit 130 via processor interface 120 to indicate that the cryptographic permutation has completed. Upon receiving the interrupt, processing unit 130 can again access the result of the cryptographic permutation from first set of data registers 210. Using ISA extensions to implement control interactions with processor interface 120 can provide a way to allow cryptographic permutations to be encoded as a single machine code instruction for processing unit 130.

[0027] In certain examples, the cipher permutation unit 140 performs a cipher permutation on data stored within at least one of the cipher registers (e.g., one of the first set of data registers 210). In one case, the cipher permutation unit 140 performs the cipher permutation in accordance with control data stored within the second set of control registers 220. The cipher permutation can involve one or more operations performed on a cipher state. The cipher state can comprise a set of bits, e.g., a sequence of 256, 512, or 1600 binary values. The cipher permutation can be used to update the cipher state. The update of the cipher state can then provide a framework for various cryptographic functions such as hash, encryption and decryption functions, and digital generators. In cases where a cipher permutation is performed on a set of bits of size b (e.g., 300, 512, or 1600 bits), the processor interface 120 can include a plurality of cipher registers of length b bits. In certain cases, data can be loaded into and out of the cipher registers in words of length w (e.g., where w < b), where w can correspond to the word length of the processing unit 130.

[0028] In one case, the cipher permutation unit 140 implements a cipher permutation that provides a “pseudo-random function” over a block of data. Multiple “rounds” can be performed on the cipher permutation, where each round or set of rounds also constitutes a cipher permutation. The cipher permutation can be a keyless permutation, e.g., can not involve a cryptographic key. For example, the cipher permutation can be different from a block cipher in that it is not controlled by an explicit secret encryption key (although a portion of the permutation state can be designated as a secret “capacity”). Also, unlike a block cipher, the inverse of the permutation is rarely needed to be computed. Each round can be similar to the other rounds. In certain cases, rounds can be distinguished via the use of round constants and / or domain separator parameters. A round constant can be a number of bits that varies across rounds. Using different round constants can help to “separate” rounds by cipher means. A domain separator parameter can also comprise a number of bits and can be used in a similar manner to round constants to separate different domains of use (e.g., encryption versus decryption or hash versus random number generation). Round constants can be used with or independent of the domain separator parameter. Further details of an exemplary cipher permutation are described in UK patent application 1903674.8, which is incorporated by reference herein.

[0029] The cryptographic permutation unit 140 can be configured to perform many different cryptographic permutations. For example, a set of FPGAs can be programmed for a specific use case, and / or the cryptographic permutations can be defined in updateable firmware. As an example, the cryptographic permutation unit 140 can be configured to perform KECCAK-p permutations, for example, as described in Federal Information Processing Standard (FIPS) 202 (or Secure Hash Algorithm 3 - "SHA-3" - Standard) - "SHA-3 Standard: Permutation-Based Hash and Extendable-Output Functions" published by the National Institute of Standards and Technology (NIST) in FIPS PUB 202, August 2015, which is incorporated herein by reference. As described in Section 3 of the FIPS 202 standard, each round of cryptographic permutation can include a combination of five individual (permutation) steps: theta: θ(A), rho: ρ(A), pi: π(A), chi: χ(A), and iotaι(A,i r ). The final step uses the round constant parameter i r Therefore, the composite round function in this standard can be defined as:

[0030] Rnd(A,i r )=ι(χ(π(ρ(θ(A)))),i r ).

[0031] In this example, the cryptographic permutation unit 140 may be configured to execute the composite round function -Rnd, for example, for one round or for multiple rounds. When the size of the permutation input A is 1600 bits, these round functions (with a specific round constant i r ) constitutes KECCAK-p [1600,24]. This then provides the basic building block for the SHA-3 / SHAKE hash function as described in the FIPS 202 standard. It also provides the basic building block for many other derivation primitives. In addition to KECCAK-p, other examples of cryptographic permutations include those by Christoph Dobraunig, Maria Eichlseder, Florian Mendel, and Martin The 320-bit permutation of ASCON, described in "Ascon v1.2," published in Proposal to NIST LWC standardization effort, March 2019, and the 512-bit SNEIK permutation described in "SNEIKEN and SNEIKHA: The SNEIK Family of Lightweight Cryptographic Algorithms," by Markku-Juhani O. Saarinen, published in Proposal to NIST LWC standardization effort, March 2019, both of which are incorporated herein by reference.

[0032] Figure 3 An example of a set of password registers 300 that may form part of the processor interface 120 is shown. In this example, the set of password registers 300 forms Figure 2 The first set of data registers 210 is shown as part of the first set of data registers, but in other cases may form part of a single common set of data and control registers. Figure 3 In FIG, the set of cryptographic registers 300 includes a permutation state register 310 for storing a permutation state (S); a permutation input register 320 for storing permutation input data (X); and a permutation output register 330 for storing output data (O). Each of these registers may be b bits long (or capable of storing b bits). In this example, the permutation input register 320 is writable by the processing unit 130, while the permutation output register 330 is readable by the processing unit 130. The processing unit 130 can therefore instruct the loading of data for cryptographic permutation into the permutation input register 320 and also instruct the loading of data resulting from the cryptographic permutation from the permutation output register 330.

[0033] exist Figure 3 In the embodiment of the present invention, the cryptographic permutation unit 140 is capable of reading data from the permutation state register 310 and writing data to the permutation state register 310. For example, the cryptographic permutation unit 140 can read the current permutation state value (e.g., with b bits) from the permutation state register 310 before cryptographic permutation, and then write the updated permutation state value (e.g., after the cryptographic permutation of the state) back to the permutation state register 310. In other cases, the input state value and the output state value can be read from and written to different registers. The permutation state register 310 may not be visible to the processing unit 130 (e.g., not readable or writable). If the permutation state register 310 is not visible, this can improve security (because the state cannot be directly manipulated by the processing unit 130) and encapsulate functionality in a manner that simplifies the application of cryptographic permutation (e.g., the manufacturer of the processing unit 130 does not need to know how to perform the permutation on the state).

[0034] exist Figure 3 In the embodiment, the cryptographic permutation unit 140 can read data from the permutation input register 320. The data read from the permutation input register 320 can be combined with the permutation state read from the permutation state register 310. In one embodiment, the data from the permutation input register 320 can be combined with the permutation state read from the permutation state register 310 using an XOR operation. The cryptographic permutation unit 140 can perform cryptographic permutation on the combined result. Figure 3 , cryptographic permutation unit 140 can write data to permutation output register 330. The data may include the output of a cryptographic permutation, for example, as performed as described above.

[0035] Figure 4 Another example of a set of password registers 400 is shown. Figure 4 The example extends Figure 3 For example, more functionality may be provided where more functionality is desired. The set of cryptographic registers 400 includes a permute state register 310, a permute input register 320, and a permute output register 330 (S, X, and O, respectively). These may be provided by analogy to Figure 3 The example operates as follows.

[0036] exist Figure 4 In the embodiment, the set of cryptographic registers 400 further includes a mask input register 410 for storing an input mask (M) and a combination output register 420 for storing a result (Y) of combining the data in the permute state register 310 with the data in the permute input register 320. In one embodiment, the combination output register 420 includes an XOR output register, for example, where the combination is an XOR operation. Figure 4 , mask input register 410 is writable by processing unit 130, and combined output register 420 is readable by processing unit 130. Cryptographic permutation unit 140 can read data from mask input register 410 and use the data to perform a masking operation, for example, as part of or prior to cryptographic permutation. Cryptographic permutation unit 140 can also write the combined output to combined output register 420; processing unit 130 can then read the combined output from combined output register 420; processing unit 130 can use the combined output, along with permutation output register 330, in a higher-level cryptographic operation, for example.

[0037] In one example, for example, Figure 3 or Figure 4The cryptographic architecture 110 of the components recited in one or more of further includes circuitry for applying an input XOR operation. For example, the circuitry may receive data derived from the permuted input data from the permuted input register 320 and data derived from the permuted state from the permuted state register 310, and apply the input XOR operation to the data.

[0038] In one case, the circuitry may apply an input XOR operation to the permuted input data and the permuted state, and may write the result of the input XOR operation to combinational output register 420. In another case, the circuitry may apply the input XOR operation to the permuted input data and a modified version of the permuted state; in this case, the circuitry for applying the input XOR operation may be communicatively coupled to or form part of cryptographic permutation unit 140. In the latter case, the circuitry may provide the result of the input XOR operation to cryptographic permutation unit 140 so that cryptographic permutation can be performed on the result. In some examples, two sets of circuitry may be used to provide each use case.

[0039] In one example, for example, Figure 3 or Figure 4 The cryptographic architecture 110 of the components recited in one or more of the above further includes a permutation masking circuit to apply a masking operation to the permutation state, for example, as read from the permutation state register 310. This can be one embodiment of the above-described circuit for applying an XOR operation. The permutation masking circuit can be communicatively coupled to the mask input register 410 and the permutation state register 310. The masking operation can apply the mask from the mask input register 410 to the permutation state. In one embodiment, the mask can be applied using an AND operation.

[0040] Figure 5 An exemplary embodiment 500 of the above-described circuit is shown. Figure 5 In the example of , the circuit is implemented as part of the password replacement unit 140; in other examples, the circuit can be implemented outside the password replacement unit 140, for example, between the data register 210 and the password replacement unit 140. Similar functionality and connections apply in both cases. Figure 5The permutation state register 310-A, permutation input register 320, and mask input register 410 are shown as being communicatively coupled to the cryptographic permutation unit 140 as inputs. In this example, the cryptographic permutation unit 140 also outputs data to the permutation state register 310-B, the permutation output register 330, and the combined output register 420. The permutation state register is shown with dashed lines as component 310-B because it can be the same component as 310-A; however, the operation of the cryptographic permutation unit 140 is more easily understood by representing these components separately. For example, in one embodiment, the cryptographic permutation unit 140 can output an updated permutation state that can be written to the permutation state register, effectively overwriting the previously accessed permutation state as input. In other embodiments, different registers or different portions of a common register can alternatively be used to store the input permutation state and the output permutation state.

[0041] The cryptographic permutation unit 140 includes a first XOR circuit 510, an AND circuit 520, a second XOR circuit 530, and a permutation circuit 540. The first XOR circuit 510 may implement one instance of a circuit to apply an input XOR operation as described above; the AND circuit 520 may implement a permutation masking circuit as described above; and the second XOR circuit 530 may implement an input application circuit as described above (or another instance of the circuit to apply an input XOR operation). Figure 5 In , black circles show communicative coupling; connected crosses without black circles are not communicatively coupled. Figure 5In particular embodiments, the first XOR circuit 510 is communicatively coupled to the permutation state register 310-A and the permutation input register 320. The first XOR circuit 510 applies a logical XOR operation and provides an output to the combined output register 420. The AND circuit 520 applies a logical AND operation to data read from the mask input register 410 (i.e., a mask) and data read from the permutation state register 310-A (i.e., a permutation state). The AND circuit 520 is communicatively coupled to the second XOR circuit 530. The second XOR circuit 530 applies a logical XOR operation to data read from the permutation input register 320 (e.g., an XOR input) and the output of the AND circuit 520 (e.g., a modified or masked permutation state). The second XOR circuit 530 is communicatively coupled to the permutation circuit 540. The permutation circuit 540 is configured to apply a cryptographic permutation to the output of the second XOR circuit 530 and provide a result of the cryptographic permutation to the permutation state register 310-B and the permutation output register 330. The processing unit 130 can read the result of the cryptographic permutation from the permutation output register 330. The permutation state initially stored in the permutation state register 310-A can be overwritten by the result (e.g., the permutation state register 310-B can be the same register storing different values S’ at different points in time). In one case, the result of the cryptographic permutation can be copied to each of the permutation state register 310-A and the permutation output register 330.

[0042] Figure 5 The exemplary embodiment 500 performs a number of operations that can be described using vector notation. For example, the data within the permutation state register 310 at the beginning of a cryptographic permutation can be referred to as a vector S - start state. The data within the permutation state register 310 after a cryptographic permutation can be referred to as a vector S’ - updated state. The state can have b bits as described above. The data within the permutation input register 320 can be referred to as a vector X, while the data within the mask input register 410 can be referred to as a vector M. The logical AND and XOR operations can operate on vectors having b bits (e.g., vectors having a width equal to the entire width of the permutation state). This can allow for fast computation, as the state does not need to be broken into sub-vectors to perform the cryptographic permutation. If the size of each register (e.g., available memory) is greater than b (e.g., a value selected to cover a large class of cryptographic operations), a subset of the b bits (e.g., the first or last b bits) can be accessed in any one particular operation. Each vector having b bits can be a sequence of bits, each bit having a value of 0 or 1.

[0043] With the above notation in mind, Figure 5 The operations of the cryptographic permutation unit 140 in can be summarized as:

[0044] Y = S XOR X

[0045] O=S'=Perm((S AND M)XOR X)

[0046] Therefore, in the update operation, S = S'. In other words, the permutation state S is first XORed with the input X, and the output is then written to Y. In this example, the permutation state S is also masked by M, and the result is also XORed with the input X and cryptographically permuted using Perm(). The resulting new permutation state S' is written to the permutation output O. For the next operation, the permutation state S is set to S = S'.

[0047] In some examples, the permutation state can be internally divided into multiple parts. These parts can include a predefined number of bits. In one case, the permutation state is divided into a set of "confidential" c bits called "capacity" and a set of "common" r bits called "rate", where b=r+c. During cryptographic operations, the processing unit 130 can only access (e.g., interact with) the "rate" bits. For example, only the "rate" bits can be read and / or only written to keep the capacity bits unchanged. The values ​​of b, r, and c may affect the mask selection during encryption and decryption operations and can be configured according to the implementation specification. The "capacity" bits can be associated with the security of the scheme, while the "rate" bits can be associated with the processing speed. For example, making c larger can improve the security of the scheme, while making r smaller can increase the speed of processing.

[0048] The processing unit 130 can use the cryptographic architecture 110 in a variety of different ways. In one embodiment, the processing unit 130 can use the cryptographic architecture 110 to perform one or more of the following cryptographic operations: an "absorb" cryptographic operation for mixing input data with a permutation state; a "squeeze" cryptographic operation for using the permutation state to obtain an output; an "encrypt" cryptographic operation for encrypting input data using the permutation state; and a "decrypt" cryptographic operation for decrypting input data using the permutation state. The "absorb" and "squeeze" operations can be used, for example, for cryptographic hashing. For example, the "encrypt" and "decrypt" operations can be used to construct authenticated encryption and decryption patterns. Examples of these cryptographic operations and how they can use the cryptographic architecture 110 are set forth below.

[0049] In the "absorb" operation, input data is mixed with the permutation state. The input data may include data from the permutation input register 320. The absorb operation may be used to initialize the permutation state or to directly operate on the permutation. The absorb operation may follow the instructions above with reference to Figure 5 The operation of the password replacement unit 140 is described as follows:

[0050] S'=Perm((S AND M)XOR X)

[0051] S=S'

[0052] In this exemplary operation, the permutation state S is first masked by the mask input M (e.g., the contents of the mask input register 410). An XOR operation is then performed between the result and the permutation input X (e.g., the contents of the permutation input register 320). This forms the input to the cryptographic permutation. The output is written back to the permutation state register 310. In one embodiment, the Perm() function may include a KECCAK-p Rnd operation that is performed as an atomic operation. In this case, multiple iterations of the KECCAK-p Rnd operation may be performed as part of a cryptographic permutation, where the permutation is performed by the cryptographic permutation unit 140 as a discrete single operation.

[0053] In one operation case, the mask input M may be set to zero, ie, M=0 b (a vector of 'b' zero bits), which yields in operation:

[0054] S'=Perm(X)

[0055] This can be used to initialize the system or set confidentiality keys and perform other functions. In another operation, the mask input M can be set to 1, that is, M=1 b (a vector of "b" 1-bits), which results in the "sponge" absorption operation:

[0056] S'=Perm(S XOR X)

[0057] By configuring the bits of the mask input M, different covering combinations can be performed. This can also be used to construct secure hashes.

[0058] In a "squeeze" operation, the output can be extracted from the permuted state. For example, if the input permuted state is S and the output permuted state is S', then:

[0059] O=S'=Perm(S)

[0060] S=S'

[0061] In a "squeeze" operation, the permutation state S is cryptographically permuted directly and the result is written back to the permutation state register 310, which now has the new value S'. The output can also be written to O, from which the processing unit 130 can read it. In a hash operation, a portion of the output O, including the r "rate" bits, can be used by the processing unit 130 as the hash operation output. It can also be seen how the "squeeze" operation is equivalent to "absorb", where M = 1 b And X=0 b .

[0062] The "encrypt" operation can be thought of as "absorb," where X represents the data to be encrypted (i.e., plaintext data) written by processing unit 130 to permute input register 320, and after the operation the output state O is copied to permute output register 330, where processing unit 130 reads the "ciphertext" from permute output register 330:

[0063] O=S'=Perm((S AND M)XOR X)

[0064] S=S'

[0065] In this operation, M can be set to M=1 b , X has the role of plaintext, while O represents the ciphertext. Likewise, processing unit 130 may read and / or use only a portion of X and O, for example, r "rate" bits. c "capacity" may be ignored by processing unit 130.

[0066] The "decryption" operation can be considered the inverse of the "encryption" operation. In this case, X (e.g., the contents of the permutation input register 320) can be considered the ciphertext and Y forms the decrypted plaintext (e.g., read from the combined output register 420). In this case:

[0067] Y=S XOR X

[0068] O=S'=Perm((S AND M)XOR X)

[0069] S=S'

[0070] For example, if we consider r “rate” bits as the left part of the permutation state S, and c “capacity” bits as the right part of the permutation state S, then we can set M to M=1. r 0 c In this case, the ciphertext X is overwritten with the permuted state S because the left r bits of X are assumed to be zero. The processing unit 130 can read the corresponding plaintext by taking the right r bits of Y.

[0071] In the examples described herein, the cryptographic registers may be arranged in w-bit words, where the size of w is determined by the architecture of the processing unit 130. For example, w may be 32 for a system with a 32-bit data path, or w=64 for a system with a 64-bit data path. If the inputs and outputs of the cryptographic permutations are b bits (e.g., b=1600 for KECCAK-p and SHA-3), the processing unit 130 may access the registers as a set of n=b / w words. For example, the permutation state S' (e.g., copied to the permutation output register 330) may be accessed as 50 words on a 32-bit system. However, the cryptographic architecture 110 is configured such that the cryptographic permutation unit 140 may access the contents of a complete register within a single cycle. This arrangement may significantly speed up data processing. For example, the data registers 210 (comprising Figure 3 and Figure 4 The registers (such as those shown in ) may each be b bits in size (or capable of storing b bits).

[0072] Figure 6 Another example of a set of password registers 600 is shown. In this example, a set of control registers 220 is shown. These registers may be provided as well as Figure 3 or Figure 4 The data register 210 is shown in one of FIG. Figure 6 An example with seven control registers 220 is shown; different examples and implementations may use a different number of control registers or divide a single register into multiple sections, depending on requirements. Figure 6 , the control registers 220 include: an identifier (ID) register 610; a start (GO) register 620; a ready (RDY) register 630; a set of round registers 640, 650, 660; and an interrupt (IRQ) control register 670.

[0073] The identifier register 610 is writable by the processing unit 130 and stores an identifier of the cryptographic operation to be performed. For example, the identifier register 610 may store one or more domain separator parameters as described above. The value of the identifier may be used to configure the cryptographic permutation according to a particular cryptographic operation (e.g., by ensuring that different values ​​written to the identifier register 610 produce different outputs, such as those read from the permutation output register 330).

[0074] The start register 620 may be written to by the processing unit 130 and store a start (or restart) flag for a cryptographic operation. For example, the start register 620 may store a binary flag having values ​​0 and 1, where a value of 1 indicates that the cryptographic substitution unit 140 is about to begin a cryptographic operation (e.g., by performing a cryptographic substitution as described above). The start register 620 may default to 0 and may be written to (e.g., set to 1) by the processing unit 130 to instruct the cryptographic architecture 110 (and / or the cryptographic substitution unit 140) to perform a cryptographic operation on behalf of the processing unit 130.

[0075] Ready register 630 can be read by processing unit 130 and stores a ready flag, which indicates that cryptographic architecture 110 (and / or cryptographic permutation unit 140) is ready to begin another cryptographic operation and / or that the result of a cryptographic permutation is ready to be read by processing unit 130. Like the start flag, the ready flag can be a binary flag, where a value of 0 indicates that cryptographic architecture 110 is not ready (e.g., in use or busy) and a value of 1 indicates that cryptographic architecture 110 is ready to begin a cryptographic operation. Ready register 630 can be used in a computing device having multiple processing units (e.g., a multi-core processor or microprocessor), where each of the multiple processing units can access cryptographic architecture 110, for example, where each is communicatively coupled to processor interface 120. This may be the case where processor interface 120 is coupled to a system bus that also couples the multiple processing units. In the case where ready register 630 is used to indicate that the result of a cryptographic operation is ready to be read from data register 210, a value of 1 can indicate to processing unit 130 that the result of the cryptographic permutation is available from permutation output register 330, while a value of 0 can indicate that the operation is still in progress.

[0076] The set of round registers 640, 650, 660 can be written by the processing unit 130 and store one or more flags related to the cryptographic permutation round. Figure 6 In

[0065] , there are three round registers: a start (BEG) round register 640, an end (END) round register 650, and a round data (RND) register 660. The start round register 640 and the end round register 650 are writable by the processing unit 130 to store the start round (the first round to be processed) and the end round (the last round to be processed), respectively. The start round and the end round can be indicated by integer values. The processing unit 130 may or may not write to or access the round data register 660. In the case where the round data register 660 stores a round count to track the current round (e.g., as an integer value), the processing unit 130 may not access the round data register 660. In another case, the round data register 660 may store a round constant indicating the number of rounds to be executed. Different implementations are possible depending on the requirements.

[0077] The interrupt control register 670 can be written by the processing unit 130 and stores a flag indicating whether the interrupt is enabled or disabled. For example, the interrupt control register 670 can store a binary flag, where 0 indicates that the interrupt is disabled and 1 indicates that the interrupt is enabled. In this example, an interrupt refers to an interruption of a series of instructions being executed by the interrupt handling unit 130 of the processing unit 130. If the interrupt is enabled, it can be used to indicate that a cryptographic operation (including cryptographic permutation) has been completed and / or that the cryptographic architecture 110 is ready to process input (for example, if the cryptographic architecture is already in use by another processing unit). The processing unit 130 can set whether to use interrupts based on the current device configuration and / or for a specific cryptographic operation. If the interrupt is not used (for example, the flag is set to 0), the processing unit 130 can instead poll the ready register 630 to determine whether an event has occurred.

[0078] Figure 6 The exemplary set of cryptographic registers 600 in thus enables a processing unit (or multiple processing units) to control the operation of the cryptographic architecture 110 and the cryptographic permutation unit 140. Using a unified and common processor interface 120 for control and data can help simplify the integration of the cryptographic architecture 110. It also enables a single coupling to a larger computing device, for example, the cryptographic architecture 110 can be easily added to the motherboard or control board of a larger computing device. Although the set of cryptographic registers 600 in Figure 6 , but some or all of the contents of these registers may instead be grouped as fields in one or more control registers (e.g., the binary flags described above may comprise different bits of an 8-bit register).

[0079] Figure 7 、 Figure 8A and Figure 8B Some methods of controlling cryptographic architectures, such as Figures 1 to 6 The cryptographic architecture may be controlled to perform cryptographic operations, for example, at least one processing unit may control the cryptographic architecture via a processor interface. In some cases, the cryptographic architecture may be used in a manner that facilitates input preparation and allows output offloading to occur concurrently with permutation computations.

[0080] Figure 7 A method 700 of performing cryptographic operations according to an example is shown. The method 700 may be performed by, for example Figure 1 In one embodiment, the method 700 may be performed by a cryptographic architecture such as the cryptographic architecture 110 of FIG. Figures 1 to 6 The password replacement unit 140 shown in FIG is executed.

[0081] The method begins at block 710, which includes receiving an instruction from a processing unit to perform a cryptographic operation. This may include Figure 1 The processor interface 120 receives a signal from the processing unit 130. In one embodiment, the password replacement unit 140 can monitor Figure 6 , and block 710 may include loading a value from the start register 620 and determining whether the value indicates a positive start signal (eg, a value of 1).

[0082] At block 720, a permutation state is loaded from one of a set of cryptographic registers. This may include the cryptographic permutation unit 140 loading data from the permutation state register 310, such as Figures 3 to 5 The processing unit cannot access the replacement state.

[0083] At block 730, cryptographic permutation is performed on data derived from the permuted state. The data may include the permuted state itself, or Figure 5 As shown in , before performing the cryptographic permutation, a number of logical operations may be applied to the permuted state. Block 730 may be performed by Figures 1 to 6 The cryptographic replacement unit 140 uses data stored in the cryptographic registers of the processor interface 120 to perform. Block 730 may include reading data from a plurality of data registers 210 within the processor interface 120, such as Figure 5 As shown in .

[0084] At block 740, method 700 includes storing the output of the cryptographic permutation in one of the set of cryptographic registers. For example, this may include copying the output of the cryptographic permutation to permutation output register 330. It may also include storing the same output in permutation status register 310. Cryptographic permutation unit 140 may perform read / write operations on data register 210.

[0085] At block 750, the method 700 includes indicating to the processing unit that the replacement is complete. The processing unit can then, for example, Figure 1 The processor interface 120 of the cryptographic permutation unit 140 accesses the output of the cryptographic permutation from the set of cryptographic registers. In one embodiment, block 750 may include the cryptographic permutation unit 140 sending an interrupt to the processing unit (e.g., if interrupts are enabled). Alternatively or in addition, block 750 may include writing a flag value (e.g., a value of 1) to the ready register 630. The processing unit may read the result of the cryptographic permutation from the set of cryptographic registers (e.g., from the permutation output register 420).

[0086] In one case, the method may include indicating via one of the set of control registers that the cryptographic permutation unit is ready to begin processing. For example, this may be accomplished by Figure 6In an example, the operations of the processing unit and the cryptographic substitution unit 140 may be synchronized based on one or more of an interrupt and a state of one of the set of control registers, for example, the start of a process flow may be synchronized based on one or more of these.

[0087] In one embodiment, the method may include loading the round count from a round control register such as the round data register 660 by the cryptographic replacement unit. The round count may be used in the cryptographic replacement, for example as a round constant input. After the cryptographic replacement, the round count in the round control register may be incremented. The loading, using, and incrementing operations may be based on the round control register and the end control register (such as Figure 6 The comparison is repeated based on the end round register 650 in the .

[0088] In one case, the method may include loading a permutation input from a permutation input register, such as permutation input register 320. Masked input data may then be loaded from a mask input register, such as mask input register 410. In this case, performing the cryptographic permutation at block 730 may include updating a permutation state in the permutation register by the cryptographic permutation unit by performing an XOR operation based on the permutation input data and a result of an AND operation performed on the masked input data and the permutation state. In this case, block 740 may include loading the updated permutation state into a permutation state register (e.g., Figure 3 and Figure 4 For example, this may include the following: Figure 5 The operations performed by the arrangement shown in .

[0089] Figure 8A and Figure 8B Shows such as Figure 1 Two exemplary operating modes 800 of a cryptographic module such as the cryptographic architecture 110 (eg, implemented by the cryptographic permutation unit 140 ) are shown. Figure 8A and Figure 8B The left side 805 shows the Figures 1 to 6 The operations performed by the password replacement unit 140 and other password modules. Figure 8A and Figure 8B The right side 810 shows that the Figure 1 The corresponding operations performed by the processing unit 130 and other processing units when executing the control program. Figure 8A and Figure 8B The two sides show how the operations of the cryptographic module and the processing unit can be synchronized.

[0090] The left side operation 805 begins when the ready (RDY) flag is set at box 815 to indicate that the cryptographic module is ready to perform a cryptographic operation. This can be performed via an interrupt and / or via the cryptographic module setting a ready register (such as ready register 630) to have a specific value (e.g., 1). In some cases, setting the ready flag to 1 can also trigger a processing unit interrupt, thereby notifying the processing unit that the cryptographic module is ready. In other cases, the processing unit can periodically read the ready register to look for a specific value (e.g., 1) or a change in value (e.g., from 0 to 1). Synchronization based on the ready flag value is shown via arrow 840, where an interface register provided by, for example, the processor interface 120 is shown as 845. Figure 8A At block 855 in , the processing unit receives an interrupt based on the ready flag value (eg, indicating that the ready flag has a value of 1, which indicates that the cryptographic module is ready for processing). Figure 8A The case where interrupts are enabled is shown. Figure 8B An alternative case is shown where interrupts are not enabled; Figure 8B In block 890 , the processing unit monitors the value of the ready flag (eg, by periodically polling the ready register) and begins operation when the value is set to one.

[0091] Once the ready flag is set to 1 and the cryptographic module is ready to execute processing at block 815, the cryptographic module proceeds to block 820, where the cryptographic module waits for the start flag to be set to indicate that a new cryptographic operation is to be executed (e.g., indicated by the start flag being set to 1). Block 820 may include the cryptographic permutation unit 140 monitoring the value stored in the start register 620, such as Figure 6 shown.

[0092] When the password module is waiting for the start signal, the processing unit Figure 8A Block 855 in (e.g., indicating an interrupt of Ready=1) or Figure 8B After one of the blocks 890 in the cryptographic module (e.g., the processing unit reads the value of the ready register 630 and determines that it is 1), processing of the old output of the cryptographic module begins at block 860. For example, when the ready flag is considered to be 1, the processing unit may begin a new operation and read the contents of one or more of the permuted output and the combined output. This latter operation may include reading the values ​​stored in the permuted output register 330 and the combined output register 420, respectively.

[0093] After block 860, the processing unit performs a check at block 865 to determine if there is more data to process. As described in more detail below, for a new cryptographic operation, the value read at block 860 can be ignored and more data will be processed. If the processing unit is following a previously indicated cryptographic operation, for example, where the result is now ready, there may be no further data to process. If there is more data to process, the method proceeds to block 870, where the processing unit prepares new input values. This can include writing new values ​​for the permutation input (X) and / or mask input (M) to the permutation input register 320 and the mask input register 410, respectively. Once the new values ​​are written, the start flag is set to 1 to initiate a new cryptographic permutation. Similarly, for example, as part of a write cycle, writing the new value and the value 1 to the start register 620 can be performed simultaneously. The design of the processor interface 120 facilitates this operation.

[0094] If the processing unit initially sets the start flag, for example, at block 870, the cryptographic module proceeds from block 820 to block 825. This may be performed in parallel with one or more of blocks 860, 865, and 870 within the processing unit program flow. At block 825, the cryptographic module performs initialization operations. This may include atomic operations, for example, multiple different events may occur simultaneously as a single operation over at least one clock cycle of the cryptographic module. Block 825 may include one or more of the following operations: setting the start flag to 0 (to indicate that processing has begun); setting the ready flag to 0 (to indicate that the cryptographic module cannot process further cryptographic requests at this time); setting the permutation output (O) to the current permutation state (S); performing an XOR operation on the permutation input (X) and the permutation state (S) to set the value of the combined output (Y); loading the permutation state (S) as S = ((S AND M) XOR X); and setting the round count flag to the round start flag. Thus, block 825 may include storing the value 0 in the start register 620 and the ready register 630; copying the contents of the permute state register 310 to the permute output register 330; storing the output of the first XOR circuit 510 in the combinational output register 420; loading the value of the permute state into temporary storage as the output of the second XOR circuit 530; and copying the value of the start round register 640 to the round data register 660. These components of the cryptographic architecture are configured so that the operations of block 825 can be performed in parallel. This enables them to be performed as atomic operations and significantly increases the speed of cryptographic operations.

[0095] After initialization at block 825, the cryptographic module performs an iteration (i.e., a round) of the cryptographic permutation at block 830. This may include activating the permutation circuit 540 using the value of the initialized permutation state (S) loaded into (temporary memory) at block 825. The permutation circuit 540 may also access a round count or constant stored using the round data register 660 (e.g., S=Round(S, RND), as referenced above when discussing the KECCAK-p implementation). In some cases, the permutation circuit 540 may also access a domain separation parameter stored in the identifier register 610. The initialized permutation state (S), the round count or constant, and the domain separation parameter may be provided as inputs to the permutation round (e.g., S=Round(S, RND, ID)). As part of block 830, the value of the round count may be incremented within the round data register 660 (e.g., RND=RND+1).

[0096] At block 835, in the left processing flow 805, a check is made to determine if the round count is less than the end round value (eg, RND <END?)。这可以包括将轮数据寄存器660和结束轮寄存器650中的整数值进行比较。如果轮计数小于结束轮值,则可以重复框830。如果轮计数不小于结束轮值(例如,现在等于在框830处的最后一次递增之后的结束轮值),则密码置换完成。所述方法进行到框815,其中就绪标志被设置为1,其指示置换的结果已就绪,并且密码模块已准备好执行进一步的密码操作。所述方法然后再次进行到框820,其中密码模块等待处理单元将起始标志设置为1。

[0097] exist Figure 8AIn block 870, after processing the input, the processing unit's process flow ends at block 875. The processing unit can thus execute different (e.g., unrelated) instructions while waiting for an interrupt to arrive indicating that the result of the cryptographic operation is ready. In this way, the processing unit can be efficiently utilized. When the cryptographic module executes block 815, for example, by storing a 1 in the ready register 630 via the cryptographic permute unit 140, this indicates that the result of the cryptographic operation is ready, and the processing unit begins another process flow at block 855. The processing unit then processes the output at block 860, which may involve reading the values ​​stored in the permutation output register 330 and the combined output register 420. The result in the combined output register 420 may have been set by a previous execution of block 825, and the result in the permutation output register 330 may have been stored as part of the iteration at block 830 (e.g., O=S'=Perm((SAND M) XOR X)). Once the processing unit has read the output at block 860, a check is performed at block 865. If the cryptographic operation is complete (e.g., the result in the permute output register 330 is the desired result), the processing unit ends its processing at block 875. If there are additional cryptographic operations to be performed, block 870 is executed again and the process is repeated. In one embodiment, new values ​​can be written to the permute input register 320 and the mask input register 410 while the previous iteration is still being performed at block 830.

[0098] Figure 8B A similar process is shown when interrupts are not enabled or configured. In this case, after block 870, the processing unit returns to block 890 and waits for the ready flag to change state to indicate that the result of the cryptographic operation is ready. The processing unit is not required to execute block 890, but can execute it intermittently as part of a monitoring or polling process.

[0099] Certain examples described herein provide a cryptographic architecture and methods for operating such an architecture that efficiently interface a cryptographic permutation unit with a processing unit such as a microprocessor. Certain examples described herein provide cryptographic methods that can be suitable for implementation on low-resource microcontrollers and embedded devices and are suitable for implementing high-speed secure data processing. The described cryptographic architecture is independent of the type of processing unit used, and a processor interface allows different processing units to be coupled to the cryptographic permutation unit, wherein options for different control programs are available through a common set of control registers. The cryptographic architecture can be implemented using memory mapping and / or other methods, thereby providing simple or transparent data access for different types of processing units. The described method can provide tight coupling of keyless cryptographic permutation with a processor core via memory-mapped registers or vector registers and instructions, wherein the processor interface provides a buffer architecture to reduce power consumption and idle cycles.

[0100] Certain examples described herein can be implemented as ISA extensions, for example, to various processing units. The examples can directly and / or indirectly support secure implementations of quantum-resistant symmetric and asymmetric cryptography. The processor interfaces described herein can be controlled via the bus architecture of the processing unit or via other input / output mechanisms. Certain examples can be configured to provide constant-time and emission-protected binary algorithms.

[0101] Certain examples described herein may be used to enable efficient hardware and / or software implementations of advanced algorithms that use cryptographic permutations as “building blocks” for the advanced algorithms. Examples of algorithms that can benefit from this efficient software-hardware co-design include: cryptographic hash functions and message digests (e.g., the SHA3 and SHAKE standards discussed previously, SNEIKHA that forms part of the SNEIK method described previously, and Ascon hash from the ASCON method described previously); SHA3 derivative functions, such as message authentication codes (MACs) (e.g., as described in “SHA-3 Derived Functions: cSHAKE, KMAC, TupleHash, and ParallelHash,” published by John Kelsey, Shu-Jen Chang, and Ray Perlner in NIST Special Publication 800-185, National Institute of Standards and Technology (NIST), December 2016, which is incorporated herein by reference); authenticated encryption of associated data (AEAD) based on cryptographic permutations (e.g., SNEIKEN and Ascon-AEAD, as described in the SNEIK and ASCON methods described previously and by Guido Bertoni, Joan Daemen, Seth Hoffert, Peeters, Gilles Van Assche, and Ronny Van Keer, “CAESAR submission: Keyak v2” by Keccak Team, September 2016, which is incorporated herein by reference); pseudorandom number generation (PRNG) and key derivation function (KDF) structures based on cryptographic permutations; cipher modes based on cryptographic primitives, such as those described in Guido Bertoni, Joan Daemen, Seth Hoffert, Peeters, Gilles Van Assche, and Ronny Van Keer, “Farfalle: parallel permutation-based cryptography,” IACR Cryptology ePrint Archive: Report 2016 / 1188, December 2016, and Guido Bertoni, Joan Daemen, Peeters, Gilles Van Assche, Ronny Van Keer and Viguier, “Kangaroo Twelve: fast hashing based on Keccak-p (Kangaroo Twelve: Fast Hashing Based on Keccak-p), both of which are incorporated herein by reference; traditional public-key cryptographic algorithms such as Rivest-Shamir-Adleman (RSA) and the Elliptic Curve Digital Signature Algorithm (ECDSA), which use permutation-based primitives as building blocks (e.g., as described in FIPS Standard 186-4); and many post-quantum public-key cryptographic algorithms that use cryptographic permutations as building blocks (e.g., BIKE, “Classic McEliece”, Dilithium, Falcon, FrodoKEM, GeMMS, Kyber, Luov, MQDSS, NewHope, NTRU, NTS-KEM, Picnic, qTESLA, Round5, Saber, Sphincs+, and ThreeBears, as described in “Post-Quantum Cryptography: Round 5, 2019, published by the NIST Information Technology Laboratory,” March 2019. 2 Submissions (Post-Quantum Cryptography: Round 2 Submissions),” which is also incorporated herein by reference.

[0102] Although some examples refer to accessing data within a register and reading and / or writing data from such register, it will be understood that in fact, intermediate data storage devices and / or data structures may be used in certain embodiments, and references to "data in..." may also apply to "data derived from...", such as data generated from one or more intermediate processes in addition to those described. References to XOR and AND refer to logical operations that perform logical "exclusive OR" and logical "AND" operations, respectively. It will also be understood that references to circuits coupled to certain components may alternatively be implemented as functionality within the components, such as via executed firmware code and / or dedicated hardware circuitry. The "circuits" described herein may be implemented in hardware, such as using digital logic gates or programmable gates of an FPGA, and / or as computer program code loaded from a memory and executed by a processor such as a microprocessor. Certain system components and methods described herein may be implemented by computer program code (such as firmware or an instruction set) that may be stored on a non-transitory storage medium such as a read-only updateable firmware memory.

[0103] The above examples should be understood as illustrative. Further examples are contemplated. For example, the specific values ​​discussed herein are based on test examples and may vary depending on the implementation (e.g., depending on the microcontroller specification and type, safety requirements, and other factors). Although certain components of each example have been described separately, it should be understood that the functionality described with reference to one example may be suitable for implementation in another example, and certain components may be omitted depending on the implementation. It should be understood that any feature described with respect to any example may be used alone, or in combination with the other features described, and may also be used in combination with one or more features of any other example, or in combination with any combination of any other example. For example, the features described with respect to the system components may also be suitable for execution as part of the described method. In addition, equivalents and modifications not described above may also be adopted without departing from the scope of the invention as defined in the appended claims.

Claims

1. A cryptographic architecture comprising: a processor interface, the processor interface including a set of cryptographic registers, the processor interface being accessible by at least one processing unit; as well as a cryptographic substitution unit comprising circuitry for performing cryptographic substitution using data stored in the set of cryptographic registers, wherein the at least one processing unit instructs the cryptographic architecture to perform the cryptographic permutation and accesses a result of the cryptographic permutation using the processor interface, The password register group includes: a permutation status register for storing a permutation status; a permutation input register for storing permutation input data, the permutation input register being writable by the at least one processing unit; a permutation output register for storing output data, the permutation output register being readable by the at least one processing unit; a mask input register for storing an input mask, the mask input register being writable by the at least one processing unit; a permutation mask circuit communicatively coupled to the mask input register and the permutation status register to apply an AND operation to data derived from the input mask and data derived from the permutation data; An input application circuit is communicatively coupled to the permutation mask circuit and the permutation input register to apply an XOR operation to data derived from the permutation mask circuit and data derived from the permutation input data, the input application circuit being configured to provide output data to the cryptographic permutation unit.

2. The cryptographic architecture of claim 1 , wherein the cryptographic architecture is configured to perform the cryptographic permutation based on a single machine code instruction executed by the at least one processing unit.

3. The cryptographic architecture of claim 2, wherein the single machine code instruction is implemented as an instruction set architecture (ISA) extension.

4. The cryptographic architecture of claim 1 , wherein the set of cryptographic registers comprises a register configured to store at least b Multiple registers of bits, where b is the size of the bits to permute the input.

5. The cryptographic architecture of claim 1, wherein the cryptographic permutation unit is configured to perform KECCAK-p permutation.

6. The cryptographic architecture of claim 1, wherein the cryptographic permutation unit is configured to perform a keyless permutation comprising multiple rounds.

7. The cryptographic architecture of claim 1 , wherein the cryptographic architecture is configured to perform one or more of the following: Absorption cryptographic operations, which are used to mix input data with a permuted state; a squeeze cipher operation for obtaining an output using the permuted state; an encryption cipher operation for encrypting input data using the permuted state; and A decryption cipher operation is used to decrypt input data using the permuted state.

8. The cryptographic architecture of claim 1 , comprising: circuitry for applying an input XOR operation applied to data derived from the permute input data in the permute input register and data derived from the permute state in the permute state register, Wherein the circuit for applying an XOR operation on the inputs is communicatively coupled to an XOR output register, the XOR output register for storing an output of the circuit for applying the XOR operation on the inputs.

9. The cryptographic architecture of claim 8, wherein after the cryptographic permutation is performed by the cryptographic permutation unit, an output of the cryptographic permutation unit is copied to the permutation state register.

10. The cryptographic architecture of claim 1, wherein the set of cryptographic registers comprises one or more control registers accessible to the at least one processing unit.

11. The cryptographic architecture of claim 10 , wherein the one or more control registers include one or more of: an identifier register writable by the at least one processing unit to store an identifier of a cryptographic operation to be performed; a start register, to which the at least one processing unit can write to store a start flag of the cryptographic operation; a ready register readable by the at least one processing unit to store a ready flag indicating that the cryptographic architecture is ready to begin another cryptographic operation; one or more round registers, writable by the at least one processing unit to store one or more flags associated with a round of cryptographic permutation; as well as An interrupt control register is written by the at least one processing unit to control an interrupt to the at least one processing unit.

12. The cryptographic architecture of claim 1, wherein the cryptographic architecture is configured to perform cryptographic permutations on a SHA-3 function.

13. A method for performing a cryptographic operation, the method being performed by the cryptographic architecture according to claim 1, the method comprising: receiving, at the cryptographic substitution unit, from the processing unit, an instruction for performing the cryptographic operation; The password replacement unit loads a replacement state from a replacement state register; The password replacement unit loads replacement input data from the replacement input register; The password replacement unit loads mask input data from the mask input register; updating, by the cryptographic permutation unit, the permutation states in the permutation state registers of a set of cryptographic registers by performing an XOR operation based on the permutation input data and a result of an AND operation performed on the mask input data and the permutation state to generate updated data, performing password replacement on the updated data by the password replacement unit; The password replacement unit stores the output of the password replacement in the replacement status register; and Completion of the cryptographic permutation is indicated by the cryptographic permutation unit to the processing unit, wherein the processing unit accesses the output of the cryptographic permutation from the set of cryptographic registers.

14. The method according to claim 13, comprising: Indicates via one of a set of control registers that the cryptographic permutation unit is ready to begin processing, Wherein operations of the processing unit and the cryptographic permutation unit are synchronized based on one or more of an interrupt and a status of one of the set of control registers.

15. The method according to claim 14, comprising: The output of the cryptographic permutation is read by the processing unit from the set of cryptographic registers.

16. The method according to claim 15, comprising: The password replacement unit loads a round count from a round control register; using the round count in the password replacement by the password replacement unit; as well as incrementing the round count in the round control register, The load, use, and increment operations are repeated based on a comparison of the round control register with an end control register.

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