Erasure Verification Method, Erasure Method and Decoding Circuit for Small Capacity Storage Array

Abstract

The present invention relates to the technical field of semiconductor integrated circuits, and specifically discloses an erasure verification method, an erasure method, and a decoding circuit for a small-capacity storage array. Among them, the erasure verification method includes the following steps: establishing a mapping relationship, which is used to map the processing operation of a word line address that does not exist in the small-capacity storage array to the processing operation of the real word line address of the small-capacity storage array; performing erasure verification on the small-capacity storage array according to the mapping relationship; by establishing the mapping relationship between the word line address that does not exist in the small-capacity storage array and the real word line address of the small-capacity storage array, when performing erasure verification on the small-capacity storage array, all the traversed addresses have corresponding real word line addresses, that is, there are corresponding actually existing storage units, so that the erasure verification step can be smoothly executed.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor integrated circuits, and in particular, to an erasure verification method, an erasure method, and a decoding circuit for a small-capacity storage array. Background Art

[0002] A traditional word line decoder decodes an n-bit address into 2 n word lines.

[0003] In actual requirements, there is also a situation where the number of word lines corresponding to the storage array capacity is between 2 n and 2 n-1 For example, 12 * 32 bits (48 bytes). This storage array has 12 word lines, which is between 8 and 16. It is still necessary to set a 4-bit word line address for decoding. However, if all four-bit word line decoding is used, 2 4 A total of 16 four-input AND gates are required for decoding. The extra 4 word lines will introduce other problems. For example, during erasure verification, the word line address will traverse from 0000 to 1111. When the word line address traverses to 1100, there is no word line corresponding to the address in the storage cell array, that is, there is no corresponding storage cell, which will prevent the comparison of the threshold voltages of the storage cells at addresses 1100 - 1111 with the verification voltage during the verification step, resulting in the erasure verification step never passing.

[0004] In response to the above problems, there is currently no effective technical solution. Summary of the Invention

[0005] The purpose of the present application is to provide an erasure verification method, an erasure method, and a decoding circuit for a small-capacity storage array, so that the small-capacity storage array can perform erasure verification smoothly.

[0006] In a first aspect, the present application provides an erasure verification method for a small-capacity storage array, which is used to verify the threshold voltage of a storage cell. The erasure verification method includes the following steps:

[0007] Establish a mapping relationship, which is used to map the processing operation of a word line address that does not exist in the small-capacity storage array to the processing operation of the actual word line address of the small-capacity storage array;

[0008] Perform erasure verification on the small-capacity storage array according to the mapping relationship.

[0009] An erasure verification method for a small-capacity storage array of the present application, by establishing a mapping relationship between the word line addresses that do not exist in the small-capacity storage array and the real word line addresses of the small-capacity storage array, when performing erasure verification on the small-capacity storage array, all the addresses traversed have corresponding real word line addresses, that is, there are corresponding actually existing storage units, so that the erasure verification steps can be smoothly executed.

[0010] In a second aspect, the present application also provides an erasure method for a small-capacity storage array, for erasing the storage array, the erasure method includes the following steps:

[0011] Establish a mapping relationship, which is used to map the processing operation on the word line address that does not exist in the small-capacity storage array to the processing operation on the real word line address of the small-capacity storage array;

[0012] Perform erasure verification on the small-capacity storage array according to the mapping relationship;

[0013] If the erasure verification fails, perform pre-programming processing on the small-capacity storage array;

[0014] Perform an erasure operation on the small-capacity storage array so that the small-capacity storage array passes the erasure verification.

[0015] An erasure method for a small-capacity storage array of the present application, by establishing a mapping relationship between the word line addresses that do not exist in the small-capacity storage array and the real word line addresses of the small-capacity storage array, when performing erasure verification on the small-capacity storage array, all the addresses traversed have corresponding real word line addresses, that is, there are corresponding actually existing storage units, so that the erasure verification steps can be smoothly executed, and further the erasure process of the entire storage array can be smoothly completed.

[0016] In the erasure method of the small-capacity storage array described above, the pre-programming processing is performed under the condition of canceling the mapping relationship.

[0017] In the erasure method of this example, the pre-programming processing is performed under the condition of canceling the mapping relationship, that is, the real word line addresses of the storage array are traversed and the corresponding storage units are pre-programmed, and there are no corresponding storage units for the word line addresses that do not exist in the small-capacity storage array, and traversing this part of the addresses will not affect the storage units corresponding to the real word line addresses.

[0018] In the erasure method of the small-capacity storage array described above, the step of performing an erasure operation on the small-capacity storage array so that the small-capacity storage array passes the erasure verification includes:

[0019] Perform a first erasure operation and a first light programming operation on the small-capacity storage array so that the small-capacity storage array passes the erasure verification of the first verification voltage;

[0020] Perform a second light programming operation on the small-capacity storage array so that the small-capacity storage array passes the erasure verification of the second verification voltage.

[0021] The erasure method of a small-capacity storage array, wherein the first light programming operation and the second light programming operation are performed under the cancellation of the mapping relationship.

[0022] In the erasure method of this example, the first light programming operation and the second light programming operation are performed under the cancellation of the mapping relationship, so that there are no corresponding storage cells for the word line addresses that do not exist in the small-capacity storage array. Therefore, in one light programming operation, the storage cells corresponding to the real word line addresses will not be reprogrammed repeatedly.

[0023] In a third aspect, the present application also provides a decoding circuit for a small-capacity storage array, which is used for word line decoding of storage cells. The decoding circuit includes:

[0024] A plurality of first word line decoders, which are used for decoding partial real word line addresses of the small-capacity storage array, and the output ends of the first word line decoders are connected to the partial real word line addresses;

[0025] A plurality of mapping circuits, which are used for decoding word line addresses that do not exist in the small-capacity storage array and for decoding the remaining real word line addresses of the small-capacity storage array, and mapping the word line addresses that do not exist in the small-capacity storage array to the remaining real word line addresses;

[0026] Both the first word line decoder and the mapping circuit are connected to the same address line for word line decoding.

[0027] The decoding circuit of a small-capacity storage array of the present application uses a mapping circuit to establish mapping discrimination, maps the word line addresses that do not exist in the small-capacity storage array to the remaining real word line addresses, so that when performing erasure verification on the small-capacity storage array, all the traversed addresses have corresponding real word line addresses, that is, there are corresponding real existing storage cells, so that the erasure verification steps can be smoothly executed, and further the erasure process of the entire storage array can be successfully completed.

[0028] The decoding circuit of a small-capacity storage array, wherein the mapping circuit includes:

[0029] A second word line decoder, which is used for decoding the remaining real word line addresses;

[0030] A virtual word line decoder for decoding the word line addresses that do not exist in the small-capacity storage array;

[0031] A first mapper for mapping the word line addresses that do not exist in the small-capacity storage array to the remaining real word line addresses.

[0032] In the decoding circuit of this example, the first mapper can map the operations originally performed on the word line addresses that do not exist in the small-capacity storage array to the operations on the remaining real word line addresses, and can also keep the operations originally performed on the remaining real word line addresses as the operations on the remaining real word line addresses.

[0033] The decoding circuit of a small-capacity storage array, wherein the first mapper includes:

[0034] A first NAND gate, one input terminal of the first NAND gate is connected to the first programming signal terminal;

[0035] A first OR gate, one input terminal of the first OR gate is connected to the output terminal of one of the second word line decoders;

[0036] A first AND gate, two input terminals of the first AND gate are respectively connected to the output terminal of the first NAND gate and the output terminal of the first OR gate, and the output terminal of the first AND gate is connected to one of the remaining real word line addresses;

[0037] The output terminal of one of the virtual word line decoders is connected to the other input terminal of the first NAND gate and the other input terminal of the first OR gate.

[0038] In the decoding circuit of this example, the first mapper establishes a mapping relationship between the virtual word line decoder and the second word line decoder by setting the first NAND gate, the first OR gate and the first AND gate, and at the same time uses the first NAND gate to obtain the programming status signal, so that the decoding circuit of the present application can establish and cancel the mapping relationship according to the programming status signal.

[0039] The decoding circuit of a small-capacity storage array, wherein when the first word line decoder is a four-bit word line decoder, the mapping circuit includes:

[0040] A third word line decoder, the third word line decoder is a two-bit word line decoder for decoding the leftmost bit level and the rightmost bit level corresponding to the four-bit word line decoder to obtain a decoding result;

[0041] A second mapper for decoding the remaining two bit levels corresponding to the four-bit word line decoder, and mapping the word line addresses that do not exist in the small-capacity storage array to the remaining real word line addresses according to the decoding result.

[0042] The decoding circuit of a small-capacity storage array, wherein the second mapper includes:

[0043] A second OR gate, the two input terminals of the second OR gate are used to respectively obtain the remaining two-bit levels;

[0044] A second AND gate, one input terminal of the second AND gate is connected to the output terminal of the second OR gate, and the other input terminal is used to obtain the leftmost bit level;

[0045] A second NAND gate, the two input terminals of the second NAND gate are respectively connected to the output terminal of the second AND gate and the second programming signal terminal;

[0046] A third AND gate, the two input terminals of the third AND gate are respectively connected to the output terminal of the second NAND gate and the output terminal of the third word line decoder, and the output terminal of the third AND gate is connected to one of the remaining true word line addresses.

[0047] In the decoding circuit of this example, the second mapper establishes a mapping relationship by setting a second OR gate, a second AND gate, a second NAND gate, and a third AND gate. At the same time, the second NAND gate is used to obtain the programming status signal, so that the decoding circuit of the embodiment of the present application can establish and cancel the mapping relationship according to the programming status signal.

[0048] As can be seen from the above, the present application provides an erasure verification method, an erasure method, and a decoding circuit for a small-capacity storage array. Among them, the erasure verification method establishes a mapping relationship between the word line addresses that do not exist in the small-capacity storage array and the true word line addresses of the small-capacity storage array, so that when performing erasure verification on the small-capacity storage array, all the traversed addresses have corresponding true word line addresses, that is, there are corresponding actually existing storage units, so that the erasure verification steps can be smoothly executed. Description of the Drawings

[0049] Figure 1 It is a flowchart of an erasure verification method for a small-capacity storage array provided by an embodiment of the present application.

[0050] Figure 2 It is a flowchart of an erasure method for a small-capacity storage array provided by an embodiment of the present application.

[0051] Figure 3 It is a schematic structural diagram of Embodiment 1 of a decoding circuit for a small-capacity storage array provided by an embodiment of the present application.

[0052] Figure 4 It is a schematic structural diagram of Embodiment 2 of a decoding circuit for a small-capacity storage array provided by an embodiment of the present application.

[0053] Label description: 100, first word line decoder; 200, second word line decoder; 301, first NAND gate; 302, first OR gate; 303, first AND gate; 401, third word line decoder; 402, second OR gate; 403, second AND gate; 404, second NAND gate; 405, third AND gate; 500, virtual word line decoder. Specific implementation manner

[0054] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and illustrated herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the present application to be protected, but only represents the selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative efforts belong to the scope of protection of the present application.

[0055] It should be noted that similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of the present application, the terms "first", "second", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0056] The traditional word line decoder decodes an n-bit address into 2 n word lines. A small-capacity storage array refers to a storage array with fewer storage units, generally referring to a storage array with a storage capacity of less than 1 kb; in actual needs, there is also a situation where the number of word lines corresponding to the storage array capacity is between 2 n-1 and 2 n . Taking n = 4 as an example, for a storage array with the number of word lines being 9 - 15 (between 2 3 and 2 4 ), it is still necessary to set a 4-bit word line address for decoding. However, if all four-bit word line decoding is adopted, 2 4A total of 16 four-input AND gates are used for decoding. Correspondingly, there will be 7 to 1 extra word line addresses. Using the memory array in the normal way will introduce other problems. For example, taking a memory array with a capacity of 12 * 32 bits (48 bytes) as an example, this memory array has 12 word lines. Setting 4-bit word line addresses for decoding will result in 4 extra word line addresses. During the erase verification, the word line addresses will traverse from 0000 to 1111. When the word line address traverses to 1100, there is no word line in the memory cell array corresponding to the address, that is, there is no corresponding memory cell, which will make it impossible to compare the threshold voltages of the memory cells at addresses 1100 - 1111 with the verification voltage during the verification step, resulting in the erase verification step never passing.

[0057] In a first aspect, please refer to Figure 1 , Figure 1 which is an erase verification method for a small-capacity memory array in some embodiments of the present application, used to verify the threshold voltage of memory cells. The erase verification method includes the following steps:

[0058] A1. Establish a mapping relationship, which is used to map the processing operations on the word line addresses that do not exist in the small-capacity memory array to the processing operations on the real word line addresses of the small-capacity memory array;

[0059] Specifically, the word line addresses that do not exist in the small-capacity memory array are the high-order word line addresses without corresponding real word line addresses in the memory array, and the real word line addresses are the word line addresses that exist in the small-capacity memory array. For example, for a four-bit binary address corresponding to 0000 - 1111 (corresponding to word lines <0> - <15>), the addresses included in this small-capacity memory array are 0000 - 1001 (corresponding to word lines <0> - <9>), then the real word line addresses are 0000 - 1001, and the word line addresses that do not exist in this small-capacity memory array are the addresses other than 0000 - 1001. Since the four-bit binary address only involves 0000 - 1111, the word line addresses that do not exist in this small-capacity memory array are 1010 - 1111 (corresponding to word lines <10> - <15>).

[0060] More specifically, after establishing the mapping relationship, all the processing operations performed on the word line addresses that do not exist in the small-capacity memory array in the mapping relationship are mapped to the processing operations performed on the corresponding real word line addresses of the small-capacity memory array in the mapping relationship. For example, if the mapping relationship between address 1111 and address 1001 is established, the processing operation command executed on address 1111 will be mapped to the processing operation command executed on address 1001.

[0061] More specifically, the mapping relationship does not affect the pointing of the real word line address itself. That is, after establishing the mapping relationship, the processing operation on the real word line address of the small-capacity storage array in the mapping relationship is the normal processing operation on the real word line address of the small-capacity storage array.

[0062] A2. Perform an erase verification on the small-capacity storage array according to the mapping relationship.

[0063] Specifically, after establishing the mapping relationship, the erase verification performed on the real word line address is still the erase verification on the corresponding real word line address. The erase verification performed on the word line address that does not exist in the small-capacity storage array is the erase verification on the corresponding real word line address under the mapping relationship, so that the erase verification result of the word line address that does not exist in the small-capacity storage array is the erase verification result of the corresponding real word line address under the mapping relationship.

[0064] An erase verification method for a small-capacity storage array according to an embodiment of the present application makes all addresses traversed have corresponding real word line addresses, that is, there are corresponding actually existing storage units, when performing an erase verification on the small-capacity storage array by establishing a mapping relationship between the word line addresses that do not exist in the small-capacity storage array and the real word line addresses of the small-capacity storage array, so that the erase verification step can be smoothly executed.

[0065] In some preferred embodiments, each word line address that does not exist in the small-capacity storage array is mapped to a different real word line address, and the operation performed on each word line address that does not exist in the small-capacity storage array can be mapped to an operation in a different real word line address.

[0066] In other embodiments, the word line addresses that do not exist in the small-capacity storage array can also be mapped to the same real word line address.

[0067] In a second aspect, please refer to Figure 2 , Figure 2 which is an erase method for a small-capacity storage array provided in some embodiments of the present application, used to erase the storage array. The erase method includes the following steps:

[0068] B1. Establish a mapping relationship, where the mapping relationship is used to map the processing operation on the word line address that does not exist in the small-capacity storage array to the processing operation on the real word line address of the small-capacity storage array;

[0069] B2. Perform an erase verification on the small-capacity storage array according to the mapping relationship;

[0070] Specifically, since the mapping relationship is established in step B1, when the small-capacity storage array is subjected to an erase verification in step B2, all the addresses traversed have corresponding real word line addresses, that is, there are corresponding actually existing storage units, so that the erase verification step can be smoothly executed.

[0071] B3. If the erase verification fails, perform a pre-programming process on the small-capacity storage array;

[0072] Specifically, the erase verification generally uses a verification voltage to test the data conditions of the storage units in the storage array. Its purpose is to check whether the threshold voltages of all the storage units in the storage array are lower than the verification voltage, that is, to test whether the data of all the word line addresses in the storage array all show 1 by applying the verification voltage. If the erase verification fails, it indicates that there is a data 0 in the storage array under the verification voltage verification; since step B2 performs the erase verification according to the mapping relationship, the erase verification still traverses all the real word line addresses, and the erase verification fails only when the threshold voltage of the storage unit corresponding to the real word line address is higher than the verification voltage.

[0073] More specifically, if the erase verification passes, it indicates that the threshold voltages of the storage units of the small-capacity storage array are all below the verification voltage.

[0074] More specifically, when the erase verification fails, it indicates that there is at least one storage unit in the storage array whose threshold voltage is higher than the verification voltage. An erase operation needs to be performed to make all the storage units in the erased state. If erased directly, it is easy to cause over-erasure of the storage units that are already in the erased state. Therefore, a pre-programming process needs to be performed on the storage array to keep the threshold voltages of the storage units in the storage array similar, and then all the storage units in the storage array are written with data before erasing.

[0075] B4. Perform an erase operation on the small-capacity storage array so that the small-capacity storage array passes the erase verification.

[0076] Specifically, after the erase operation on the storage array is completed, the small-capacity storage array is subjected to an erase verification again according to the mapping relationship. If the verification still fails, the erase operation is continued until the small-capacity storage array passes the erase verification according to the mapping relationship.

[0077] An erase method for a small-capacity storage array according to an embodiment of the present application, by establishing a mapping relationship between the word line addresses that do not exist in the small-capacity storage array and the real word line addresses of the small-capacity storage array, when the small-capacity storage array is subjected to an erase verification, all the addresses traversed have corresponding real word line addresses, that is, there are corresponding actually existing storage units, so that the erase verification step can be smoothly executed, and further the erase process of the entire storage array can be smoothly completed.

[0078] In some preferred embodiments, the pre-programming process is performed under the unmapped relationship.

[0079] Specifically, in the case where the mapping relationship is established, operations on word line addresses that do not exist in the small-capacity storage array are all mapped to operations on corresponding real word line addresses, and the pre-programming process is a programming operation performed by traversing all word line addresses. If the pre-programming process is performed under the mapping relationship, the real word line addresses with the mapping relationship are programmed at least twice, which will cause a deeper programming degree in a part of the storage array area, still resulting in a wide threshold voltage distribution of the storage array and having a problem of poor consistency. Therefore, in the erasure method of the embodiments of the present application, the pre-programming process is performed under the unmapped relationship, that is, the real word line addresses of the storage array are traversed and the corresponding storage units are pre-programmed, and there are no corresponding storage units for the word line addresses that do not exist in the small-capacity storage array, and traversing this part of the addresses will not affect the storage units corresponding to the real word line addresses.

[0080] In some preferred embodiments, the steps for performing an erasure operation on the small-capacity storage array to enable the small-capacity storage array to pass the erasure verification include:

[0081] B41. Perform a first erasure operation and a first light programming operation on the small-capacity storage array to enable the small-capacity storage array to pass the erasure verification of the first verification voltage;

[0082] Specifically, the first erasure operation is used to reduce the threshold voltage of the storage units of the storage array, and the first light programming operation is used to raise the threshold voltage of the storage units of the storage array, so that the storage units of the storage array have appropriate threshold voltages, that is, below the first verification voltage and prevent there from being storage units with too low threshold voltages.

[0083] B42. Perform a second light programming operation on the small-capacity storage array to enable the small-capacity storage array to pass the erasure verification of the second verification voltage.

[0084] Specifically, the second light programming operation is used to repair the over-erased storage units in the storage array, so that the threshold voltage of the storage array is between the second verification voltage and the first verification voltage, so as to improve the consistency of the threshold voltage of the storage array.

[0085] In some preferred embodiments, step B2 performs the erasure verification using the first verification voltage.

[0086] In some preferred embodiments, if the erasure verification in step B2 passes, perform a second light programming operation on the small-capacity storage array to enable the small-capacity storage array to pass the erasure verification of the second verification voltage, so that the threshold voltage of the storage array is between the second verification voltage and the first verification voltage, so as to improve the consistency of the threshold voltage of the storage array.

[0087] In some preferred embodiments, the first light programming operation and the second light programming operation are performed under an unmapped relationship.

[0088] Specifically, the first light programming operation and the second light programming operation are similar to pre-programming, and both are programming operations on the storage cells corresponding to the word line addresses. If pre-programming is performed under the mapped relationship, the real word line addresses with the mapped relationship that need to perform the first light programming operation or the second light programming operation are programmed at least twice, which will cause a deeper programming degree in a part of the storage array area, resulting in a wider threshold voltage distribution of the storage array and a problem of poor consistency. Therefore, in the erasing method of the embodiments of the present application, the first light programming operation and the second light programming operation are performed under the unmapped relationship, so that the word line addresses that do not exist in the small-capacity storage array do not have corresponding storage cells, so that in a single light programming operation, the storage cells corresponding to the real word line addresses are not repetitively light-programmed.

[0089] For a third aspect, please refer to Figure 3 and Figure 4 , Figure 3 and Figure 4 are a decoding circuit of a small-capacity storage array provided in some embodiments of the present application, used for word line decoding of storage cells. The decoding circuit includes:

[0090] A plurality of first word line decoders 100 are used to decode some real word line addresses of the small-capacity storage array. The output end of the first word line decoder 100 is connected to some real word line addresses;

[0091] A plurality of mapping circuits are used to decode the word line addresses that do not exist in the small-capacity storage array and the remaining real word line addresses of the small-capacity storage array, and map the word line addresses that do not exist in the small-capacity storage array to the remaining real word line addresses;

[0092] Both the first word line decoder and the mapping circuit are connected to the same address line for word line decoding.

[0093] Specifically, both the first word line decoder and the mapping circuit are connected to the same number of address lines. The word line address decoding is determined by distinguishing the high and low levels of the address lines, and then the word line is determined. That is, when the address line completely satisfies the high and low level characteristics, the corresponding first word line decoder or mapping circuit is turned on to determine the word line. Taking a four-bit word line address 0011 as an example, this level characteristic only satisfies the conduction requirement of the first word line decoder corresponding to the word line WL<3>. At this time, only the first word line decoder corresponding to the word line WL<3> is turned on, thus completing the decoding of this word line address. Among them, addrb<0>-addrb<3> in the figure represent that the address lines are at a low level, and addr<0>-addr<3> represent that the address lines are at a high level.

[0094] Specifically, the remaining true word line addresses are the true word line addresses among several divided ones in the small-capacity storage array for establishing mapping relationships; in order to perform erase verification, the number of word line addresses that do not exist in the small-capacity storage array and need to establish mapping relationships is between 2 n -2 n-1 and 2. When n is greater than 2, the number of true word line addresses in the small-capacity storage array is more than the number of word line addresses that do not exist in the small-capacity storage array. Therefore, it is not necessary to use all true word line addresses to establish mapping relationships. Thus, in this embodiment, after removing the remaining true word line addresses used for establishing mapping relationships in the storage array, the remaining partial true word line addresses can be normally decoded. Therefore, the first word line decoder 100 is used for decoding, and the remaining true word line addresses are used for establishing mapping relationships, so the mapping circuit is used for decoding.

[0095] More specifically, since different word line addresses that do not exist in the small-capacity storage array can be mapped to the same true word line address, the number of word line addresses that do not exist in the small-capacity storage array is greater than or equal to the number of the remaining true word line addresses. The number of partial true word line addresses is determined by the number of the remaining true word line addresses, that is, the number of true word line addresses without establishing mapping relationships is calculated and determined by the number of true word line addresses participating in establishing mapping relationships; generally, the number of partial true word line addresses is an integer multiple of the number of bits of the word line decoder. For example, taking a storage array with a capacity of 12 * 32 bits (48 bytes) as an example, there are 12 word lines in this storage array, and 4-bit word line addresses need to be set for decoding. The number of word line addresses that do not exist in the small-capacity storage array is 4. It is necessary to ensure that the number of the remaining true word line addresses is less than or equal to 4, and ensure that the number of partial true word line addresses is an integer multiple of 4. Thus, the number of the remaining true word line addresses can be determined to be 4, and the number of partial true word line addresses is 8.

[0096] Specifically, the first word line decoder 100 is used for decoding a part of the true word line addresses in the storage array, and the mapping circuit is used for decoding the remaining true word line addresses in the storage array and the word line addresses that do not exist in the small-capacity storage array.

[0097] A decoding circuit for a small-capacity storage array according to an embodiment of the present application uses a mapping circuit to establish mapping discrimination, maps the word line addresses that do not exist in the small-capacity storage array to the remaining true word line addresses, so that when performing erase verification on the small-capacity storage array, all traversed addresses have corresponding true word line addresses, that is, there are corresponding actually existing storage units, thereby enabling the erase verification step to be smoothly executed, and further enabling the erase process of the entire storage array to be successfully completed.

[0098] In some preferred embodiments, the mapping circuit includes:

[0099] The second word line decoder 200 is configured to decode the remaining real word line addresses;

[0100] The virtual word line decoder 500 is configured to decode the word line addresses that do not exist in the small-capacity storage array;

[0101] The first mapper is configured to map the word line addresses that do not exist in the small-capacity storage array to the remaining real word line addresses.

[0102] Specifically, the output ends of the second word line decoder 200 and the virtual word line decoder 500 are both connected to the input end of the first mapper.

[0103] Specifically, the first mapper is configured to obtain the decoding results of the second word line decoder 200 and the virtual word line decoder 500. When the second word line decoder 200 or the virtual word line decoder 500 decodes successfully, the first mapper will output the decoding result of the remaining real word line address correspondingly; for example: the second word line decoder 200 is configured to decode word line <11>, and the virtual word line decoder 500 is configured to decode word line <15>. The first mapper is configured to map word line <15> to <11>. Therefore, when the decoder for decoding word line <11> decodes successfully, the first mapper outputs the decoding result of word line <11>, and when the virtual word line decoder 500 for decoding word line <15> decodes successfully, the first mapper also outputs the decoding result of word line <11>, thus realizing the mapping from word line <15> to word line <11>.

[0104] More specifically, the first mapper can map the operations originally performed on the word line addresses that do not exist in the small-capacity storage array to the operations performed on the remaining real word line addresses, and can also keep the operations originally performed on the remaining real word line addresses as the operations performed on the remaining real word line addresses.

[0105] In some preferred embodiments, the first mapper includes:

[0106] The first NAND gate 301, one input end of the first NAND gate 301 is connected to the first programming signal end;

[0107] The first OR gate 302, one input end of the first OR gate 302 is connected to the output end of a second word line decoder 200;

[0108] The first AND gate 303, the two input ends of the first AND gate 303 are respectively connected to the output end of the first NAND gate 301 and the output end of the first OR gate 302, and the output end of the first AND gate 303 is connected to a remaining real word line address;

[0109] The output end of a virtual word line decoder 500 is connected to the other input end of the first NAND gate 301 and the other input end of the first OR gate 302.

[0110] Specifically, the first programming signal terminal is used to obtain a programming status signal. For example, if the programming status signal is program_flag, when program_flag is 1, it indicates that the memory array is performing a programming operation (including pre-programming processing, first light programming operation, second light programming operation). When program_flag is 0, it indicates that the memory array is performing an operation other than the programming operation, such as an erase operation, an erase verification operation, etc.

[0111] More specifically, when program_flag is 0, the output result of the first NAND gate 301 is necessarily 1, thereby starting the mapping relationship. When program_flag is 1 and the virtual word line decoder 500 successfully decodes and outputs 1, the output result of the first NAND gate 301 is 0 and no mapping occurs. Therefore, the decoding circuit of the embodiment of the present application can automatically establish and cancel the mapping relationship according to the programming status.

[0112] More specifically, the first mapper sets up a mapping relationship between the virtual word line decoder 500 and the second word line decoder 200 by using the first NAND gate 301, the first OR gate 302, and the first AND gate 303. At the same time, the first NAND gate 301 is used to obtain the programming status signal, so that the decoding circuit of the embodiment of the present application can establish and cancel the mapping relationship according to the programming status signal.

[0113] In some preferred embodiments, when the first word line decoder 100 is a four-bit word line decoder, the mapping circuit includes:

[0114] A third word line decoder 401, which is a two-bit word line decoder, is used to decode the leftmost level and the rightmost level corresponding to the four-bit word line decoder to obtain a decoding result;

[0115] A second mapper, which is used to decode the remaining two levels corresponding to the four-bit word line decoder, and map the word line address that does not exist in the small-capacity memory array to the remaining real word line address according to the decoding result.

[0116] Specifically, the second mapper is used to analyze the decoding result according to the four levels of the four-bit word line decoder, establish a mapping relationship between a word line address that does not exist in the small-capacity memory array and a real word line address, that is, combine at least two decoding results and output them as one decoding result. For example, map the decoding result of the address 1010 to the decoding result of the address 1000, that is, map the original <10> result of the word line to the word line <8>. That is, the second mapper decodes according to the decoding results of the leftmost level and the rightmost level by the third word line decoder 401 and the remaining two levels, and outputs the word line <8> as the decoding result when the word line addresses are 1010 and 1000.

[0117] In some preferred embodiments, the second mapper includes:

[0118] A second OR gate 402, the two input terminals of the second OR gate 402 are respectively used to obtain the remaining two-bit levels;

[0119] A second AND gate 403, one input terminal of the second AND gate 403 is connected to the output terminal of the second OR gate 402, and the other input terminal is used to obtain the leftmost bit level;

[0120] A second NAND gate 404, the two input terminals of the second NAND gate 404 are respectively connected to the output terminal of the second AND gate 403 and the second programming signal terminal;

[0121] A third AND gate 405, the two input terminals of the third AND gate 405 are respectively connected to the output terminal of the second NAND gate 404 and the output terminal of the third word line decoder 401, and the output terminal of the third AND gate 405 is connected to a remaining real word line address.

[0122] Specifically, the second programming signal terminal is used to obtain a programming status signal. For example, if the programming status signal is program_state, when program_state is 1, it indicates that the memory array is performing a programming operation (including pre-programming processing, first light programming operation, second light programming operation). When program_state is 0, it indicates that the memory array is performing an operation other than the programming operation, such as an erase operation, an erase verification operation, etc.

[0123] More specifically, when program_state is 0, the output result of the second NAND gate 404 must be 1, thereby starting the mapping relationship. When program_state is 1, only when the second OR gate 402 outputs 1 and the second AND gate 403 also outputs 1, the output result of the second NAND gate 404 is 0, and no mapping will occur. It only needs to be ensured that when the second OR gate 402 outputs 1, the levels of its two input terminals are different from the levels corresponding to the real address to be mapped to avoid mapping the word line address that does not exist in the small-capacity memory array to the real word line address; therefore, the decoding circuit of the embodiment of the present application can automatically establish and cancel the mapping relationship according to the programming status.

[0124] More specifically, the second mapper establishes a mapping relationship by setting the second OR gate 402, the second AND gate 403, the second NAND gate 404, and the third AND gate 405, and at the same time uses the second NAND gate 404 to obtain the programming status signal, so that the decoding circuit of the embodiment of the present application can establish and cancel the mapping relationship according to the programming status signal.

[0125] Embodiment 1

[0126] When decoding a 12 * 32 - bit (48 - byte) storage array, there are 12 word lines in this storage array, so 4 - bit word - line addresses need to be set.

[0127] During the erase verification operation, the storage array has word lines WL<0> - WL<11> and does not have word lines WL<12> - WL<15>. It cannot fully correspond to the word - line addresses 0000 - 1111. Generally, the erase verification will not pass. Therefore, the decoding circuit as shown in Figure 3 is used to decode this storage array. Among them, Figure 3 on the right side, 8 four - input AND gates are used as the first word - line decoder 100 to decode word lines WL<0> - WL<7>, corresponding to word - line addresses 0000 - 0111; 4 four - input AND gates are used as the second word - line decoder 200 to output WL_1<8> - WL_1<11>; 4 four - input AND gates are used as the virtual word - line decoder 500 to output WL_1<12> - WL_1<15>; 4 first mappers composed of the first NAND gate 301, the first OR gate 302, and the first AND gate 303 are used to output WL<8> - WL<11>, where program_flag is the programming status signal.

[0128] Analysis shows that regardless of the programming status signal program_flag, addresses 0000 - 1011 can be successfully decoded into WL<0> - WL<11>.

[0129] When the programming status signal program_flag is 0, the decoding of addresses 1100 - 1111 is as follows:

[0130] Table 1 Decoding table of addresses 1100 - 1111 when the programming status signal program_flag = 0

[0131]

[0132] Among them, Addr is the word - line address. When the programming status signal program_flag is 0, the word lines WL_1<12> - WL_1<15> output by the virtual word - line decoder 500 will be mapped to word lines WL<8> - WL<11>.

[0133] Therefore, as can be seen from the above table, in the non - programming state, the word - line decoding results corresponding to the word - line addresses that do not exist in the small - capacity storage array can be mapped to the word - line decoding results corresponding to the real word - line addresses, enabling the erase verification to proceed smoothly.

[0134] When the programming status signal program_flag is 1, the decoding of addresses 1100 - 1111 is as follows:

[0135] Table 2 Decoding table for addresses 1100 - 1111 when the programming status signal program_flag = 1

[0136]

[0137] Among them, when the programming status signal program_flag is 1, there is no corresponding mapped object for the word lines WL_1<12> - WL_1<15> output by the virtual word line decoder 500.

[0138] Therefore, as can be seen from the above table, in the programming state, there is no demapping relationship for the word line addresses that do not exist in the small-capacity storage array, and there is no corresponding word line, so that the programming operation will not be repeated on the real word lines.

[0139] Embodiment 2

[0140] When decoding a 10 * 32 bits (40 bytes) storage array, there are 10 word lines in this storage array, so 4-bit word line addresses need to be set.

[0141] During the erase verification operation, this storage array has word lines WL<0> - WL<9>, and there are no word lines WL<10> - WL<15>, which cannot fully correspond to the word line addresses 0000 - 1111. Generally, the erase verification will not pass, so the decoding circuit shown in Figure 4 is used to decode this storage array; among them, Figure 4On the right side of the middle, 8 four-input AND gates are used as the first word line decoder 100 to decode word lines WL<0>-WL<7>, and the corresponding word line addresses are 0000-0111; 2 two-input AND gates are used as the third word line decoder 401, and the third word line decoder 401 is used to decode the leftmost bit level and the rightmost bit level. The leftmost bit level can be used to judge the word line address, and it passes only when the leftmost bit level is high (when the leftmost bit level is high, it corresponds to word line addresses 1000-1111). The rightmost bit level is used to distribute the word line addresses to the corresponding third word line decoders 401 for decoding. Thus, the addresses can be alternately distinguished according to the ascending order of the addresses, and corresponding word line ready signals WL_pre<9> and WL_pre<8> are generated; a second mapper composed of a second OR gate 402, a second AND gate 403, a second NAND gate 404, and a third AND gate 405 is adopted; the word line ready signals WL_pre<9> and WL_pre<8> (the two signals are integrated and abbreviated as WL_pre<9:8>) are both connected to the third AND gate in the second mapper. The second mapper determines whether the word line address is a real word line address through the second OR gate 402 and the second AND gate 403 (the addresses connected to the third word line decoder 401 include 1000-1111, so the real addresses judged by the second mapper are 1000 and 1001), and then maps the corresponding word line addresses combined with WL_pre<9> and WL_pre<8> to WL <9> and WL <8>; among them, program_state is the programming state signal.

[0142] Analysis shows that regardless of the programming state signal program_state, addresses 0000-1001 can be successfully decoded into WL<0>-WL<9>.

[0143] When the programming state signal program_state is 0, the decoding conditions of addresses 1010-1111 are as follows:

[0144] Table 3 Decoding table of addresses 1010-1111 when the programming state signal program_state = 0

[0145]

[0146] Among them, Addr is the word line address. When the programming state signal program_flag is 0, the word line addresses 1010-1111 alternately output word lines WL<8> and WL<9>.

[0147] Therefore, as can be seen from the above table, in the non-programming state, the word line decoding results corresponding to the word line addresses that do not exist in the small-capacity storage array cannot be mapped to the word line decoding results corresponding to the real word line addresses, enabling the erase verification to proceed smoothly.

[0148] When the programming status signal program_state is 1, the decoding of addresses 1010 - 1111 is as follows:

[0149] Table 4 Decoding Table of Addresses 1010 - 1111 When the Programming Status Signal program_state = 1

[0150]

[0151] Among them, when the programming status signal program_flag is 1, there is no corresponding mapped object for the word line addresses 1010 - 1111.

[0152] Therefore, as can be seen from the above table, in the programming state, there is no unmapping relationship for the word line addresses that do not exist in the small - capacity storage array, and there is no corresponding word line, so that the programming operation will not be repeated on the real word lines.

[0153] In summary, the embodiments of the present application provide an erasure verification method, an erasure method, and a decoding circuit for a small - capacity storage array. Among them, the erasure verification method makes all the addresses traversed have corresponding real word line addresses, that is, there are corresponding real - existing storage units, by establishing a mapping relationship between the word line addresses that do not exist in the small - capacity storage array and the real word line addresses of the small - capacity storage array, so that the erasure verification steps can be smoothly executed.

[0154] In the embodiments provided by the present application, it should be understood that the disclosed circuit and method can be implemented in other ways. The circuit embodiments described above are only illustrative. For example, the division of the units is only a logical function division, and there can be other division methods in actual implementation. Also, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection between each other can be through some communication interfaces, and the indirect coupling or communication connection of the circuit or unit can be in an electrical, mechanical or other forms.

[0155] In addition, the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0156] Furthermore, in each embodiment of the present application, the functional modules can be integrated together to form an independent part, or each module can exist alone, or two or more modules can be integrated to form an independent part.

[0157] In this document, relational terms such as first and second are used solely to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0158] The above description is only for the embodiments of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A decoding circuit for a small-capacity storage array, used for word line decoding of storage cells, characterized in that, The small-capacity storage array refers to a storage array with a storage capacity of less than 1 kb. The decoding circuit includes: A plurality of first word line decoders for decoding part of the real word line addresses of the small-capacity storage array. The output ends of the first word line decoders are connected to the part of the real word line addresses; A plurality of mapping circuits for decoding the word line addresses that do not exist in the small-capacity storage array and for decoding the remaining real word line addresses of the small-capacity storage array, and mapping the word line addresses that do not exist in the small-capacity storage array to the remaining real word line addresses; Both the first word line decoder and the mapping circuit are connected to the same address line for word line decoding.

2. The decoding circuit of a small-capacity storage array according to claim 1, characterized in that, The mapping circuit includes: A second word line decoder for decoding the remaining real word line addresses; A virtual word line decoder for decoding the word line addresses that do not exist in the small-capacity storage array; A first mapper for mapping the word line addresses that do not exist in the small-capacity storage array to the remaining real word line addresses.

3. The decoding circuit of a small-capacity storage array according to claim 2, characterized in that, The first mapper includes: A first NAND gate, one input end of the first NAND gate is connected to the first programming signal end; A first OR gate, one input end of the first OR gate is connected to the output end of one of the second word line decoders; A first AND gate, two input ends of the first AND gate are respectively connected to the output end of the first NAND gate and the output end of the first OR gate, and the output end of the first AND gate is connected to one of the remaining real word line addresses; The output end of one of the virtual word line decoders is connected to the other input end of the first NAND gate and the other input end of the first OR gate.

4. The decoding circuit of a small-capacity storage array according to claim 1, characterized in that, When the first word line decoder is a four-bit word line decoder, the mapping circuit includes: A third word line decoder, which is a two-bit word line decoder, for decoding the leftmost level and the rightmost level corresponding to the four-bit word line decoder to obtain a decoding result; A second mapper for decoding the remaining two levels corresponding to the four-bit word line decoder and mapping the word line addresses that do not exist in the small-capacity storage array to the remaining real word line addresses according to the decoding result.

5. The decoding circuit of a small-capacity storage array according to claim 4, characterized in that, The second mapper includes: A second OR gate, two input ends of the second OR gate are respectively used to obtain the remaining two levels; A second AND gate, one input end of the second AND gate is connected to the output end of the second OR gate, and the other input end is used to obtain the leftmost level; A second NAND gate, two input ends of the second NAND gate are respectively connected to the output end of the second AND gate and the second programming signal end; A third AND gate, two input ends of the third AND gate are respectively connected to the output end of the second NAND gate and the output end of the third word line decoder, and the output end of the third AND gate is connected to one of the remaining real word line addresses.

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