Thin film transistor substrate and method for manufacturing thin film transistor substrate

Abstract

The present invention relates to a thin film transistor substrate and a method for manufacturing a thin film transistor substrate. A first thin film transistor includes a polysilicon film. A second thin film transistor includes an oxide semiconductor film. A first insulating film is located above the polysilicon film and the oxide semiconductor film. The first insulating film is in contact with the oxide semiconductor film and covers at least a portion of the polysilicon film and at least a portion of the oxide semiconductor film. The second insulating film is located above the first insulating film and includes a higher concentration of hydrogen than the hydrogen concentration of the first insulating film. The first insulating film includes a first portion and a second portion. The first portion includes a portion covering at least a portion of the polysilicon film. The second portion includes a portion covering at least a portion of the oxide semiconductor film. The first portion is thinner than the second portion.

Description

Technical Field

[0001] The invention relates to a thin film transistor substrate. Background Art

[0002] The technology of incorporating a low-temperature polysilicon thin film transistor (LTPS TFT) and an oxide semiconductor TFT into one pixel circuit has been put into practical use. This technology is referred to as a hybrid TFT display (HTD) technology in this specification. The HTD technology incorporates a low-temperature polysilicon TFT with high mobility and an oxide semiconductor TFT that generates a small leakage current into a pixel circuit to achieve higher display quality and lower power consumption. Summary of the invention

[0003] Low-temperature polysilicon TFTs and oxide semiconductor TFTs have different requirements for hydrogen. Specifically, low-temperature polysilicon requires more hydrogen, while oxide semiconductors should contain less hydrogen. Therefore, a technology is needed to meet these different requirements for hydrogen of low-temperature polysilicon TFTs and oxide semiconductor TFTs to obtain circuits with better characteristics.

[0004] One aspect of the present invention is a thin film transistor substrate, comprising: an insulating substrate; a first thin film transistor, the first thin film transistor being disposed on the insulating substrate and comprising a polysilicon film as an active film; a second thin film transistor, the second thin film transistor being disposed on the insulating substrate and comprising an oxide semiconductor film as an active film located above the polysilicon film; a first insulating film, the first insulating film being located above the polysilicon film and the oxide semiconductor film, the first insulating film being in contact with the oxide semiconductor film and covering at least a portion of the polysilicon film and at least a portion of the oxide semiconductor film when viewed in a plane; and a second insulating film, the second insulating film being located above the first insulating film, and the second insulating film being covered at least a portion of the polysilicon film and at least a portion of the oxide semiconductor film when viewed in a plane and containing a higher hydrogen concentration than the hydrogen concentration in the first insulating film. The first insulating film comprises a first portion and a second portion. The first portion comprises a portion covering at least a portion of the polysilicon thin film, the second portion comprises a portion covering at least a portion of the oxide semiconductor film, and the first portion is thinner than the second portion.

[0005] One aspect of the present invention is a method for manufacturing a thin film transistor substrate, comprising: forming a polysilicon film as an active film of a first thin film transistor on an insulating substrate; after forming the polysilicon film, forming an oxide semiconductor film as an active film of a second thin film transistor on a layer above the polysilicon film; after forming the oxide semiconductor film, forming a first insulating film on a layer above the oxide semiconductor film; and after forming the first insulating film, forming a second insulating film on a layer above the first insulating film, the second insulating film containing a higher hydrogen concentration than the hydrogen concentration in the first insulating film, wherein the first insulating film is in contact with the oxide semiconductor film and covers at least a portion of the polysilicon film and at least a portion of the oxide semiconductor film when viewed in a planar manner, wherein the first insulating film includes a first portion and a second portion, wherein the first portion includes a portion covering at least a portion of the polysilicon film, wherein the second portion includes a portion covering at least a portion of the oxide semiconductor film, wherein the second insulating film covers at least a portion of the polysilicon film and at least a portion of the oxide semiconductor film when viewed in a planar manner, and wherein forming the first insulating film includes etching the first insulating film so that the first portion is thinner than the second portion.

[0006] An aspect of the present invention improves characteristics of a circuit including a polysilicon thin film transistor and an oxide semiconductor thin film transistor.

[0007] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of a structural example of an OLED display device;

[0009] Figure 2A An example of the structure of a pixel circuit is shown;

[0010] Figure 2B Another structural example of a pixel circuit is shown;

[0011] Figure 2C Another structural example of a pixel circuit is shown;

[0012] Figure 3 The cross-sectional structure of a portion of a thin film transistor substrate is schematically shown;

[0013] Figure 4 An example of a planar structure of a portion of a thin film transistor substrate is schematically shown;

[0014] Figure 5 Another example of a planar structure of a portion of a thin film transistor substrate is schematically shown;

[0015] Fig. 6Ais a schematic diagram for explaining a method for manufacturing a thin film transistor substrate;

[0016] Figure 6B is a schematic diagram for explaining a method for manufacturing a thin film transistor substrate;

[0017] Figure 6C is a schematic diagram for explaining a method for manufacturing a thin film transistor substrate;

[0018] Fig.6D is a schematic diagram for explaining a method for manufacturing a thin film transistor substrate;

[0019] Fig. 6E is a schematic diagram for explaining a method for manufacturing a thin film transistor substrate;

[0020] Fig. 6F is a schematic diagram for explaining a method for manufacturing a thin film transistor substrate;

[0021] Figure 7 The cross-sectional structure of a portion of a thin film transistor substrate in another structural example is schematically shown;

[0022] Figure 8 The cross-sectional structure of a portion of a thin film transistor substrate in another structural example is schematically shown;

[0023] Fig. 9 A structural example of a shift register circuit in still another structural example is shown;

[0024] Fig.10 The cross-sectional structure of a portion of a thin film transistor substrate in another structural example is schematically shown;

[0025] Fig.11 The cross-sectional structure of a portion of a thin film transistor substrate in another structural example is schematically shown;

[0026] Fig.12 The cross-sectional structure of a portion of a thin film transistor substrate in another structural example is schematically shown;

[0027] Fig.13 A structural example of a sensor circuit in still another structural example is shown; and

[0028] Fig.14 The cross-sectional structure of a portion of a thin film transistor substrate in still another structural example is schematically shown. DETAILED DESCRIPTION

[0029] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that the above embodiments are only examples for implementing the present invention and are not intended to limit the technical scope of the present invention. Common elements in the accompanying drawings are represented by the same reference numerals, and some elements in the accompanying drawings are enlarged in size or shape to clearly understand the description.

[0030] summary

[0031] The following description uses an organic light emitting diode (OLED) display device as an example of a device including a thin film transistor substrate. The OLED display device in the present invention includes a low temperature polysilicon thin film transistor (LTPS TFT) and an oxide semiconductor TFT in a pixel circuit and / or a peripheral circuit. Since the oxide semiconductor TFT generates a small leakage current, it can be used, for example, as a switching transistor connected to a storage capacitor for maintaining the gate potential of a driving transistor of the pixel circuit. A low temperature polysilicon TFT with high mobility can be used, for example, as a driving transistor. The structure of the present invention is applicable to devices other than display devices.

[0032] Low-temperature polysilicon and oxide semiconductors have different requirements for hydrogen. When oxide semiconductors are reduced by hydrogen, excess carriers are generated. Therefore, it is important that oxide semiconductors contain less hydrogen. From this point of view, it is important that the hydrogen concentration in the insulating film in contact with the oxide semiconductor film is low.

[0033] On the other hand, low-temperature polysilicon requires a large amount of hydrogen to terminate dangling bonds at grain boundaries. A low-temperature polysilicon TFT including a low-temperature polysilicon film lacking hydrogen deteriorates in TFT characteristics such as hysteresis; it affects the display quality of an OLED display device. In addition, it may reduce mobility, thereby weakening the driving capability of circuits such as gate drivers.

[0034] Typical hydrogenation of low-temperature polysilicon supplies hydrogen to low-temperature polysilicon by diffusing hydrogen in an insulating film including a large amount of hydrogen. Typically, the manufacture of a circuit including a low-temperature polysilicon TFT and an oxide semiconductor TFT prepares a low-temperature polysilicon film before an oxide semiconductor film. In order to obtain an oxide semiconductor containing less hydrogen, the insulating film in contact with the oxide semiconductor and the insulating film located above these films are made of a low-hydrogen insulating material such as SiOx. Therefore, the amount of hydrogen supplied to the low-temperature polysilicon becomes less.

[0035] Meanwhile, during the process of manufacturing oxide semiconductor TFTs, hydrogen in low-temperature polysilicon escapes. For example, the process of manufacturing oxide semiconductor TFTs includes multiple anneals. For highly reliable oxide semiconductor TFTs, a temperature of 300°C to 400°C is required. This high-temperature annealing removes hydrogen from low-temperature polysilicon.

[0036] As described above, low-temperature polysilicon TFTs are limited by oxide semiconductor TFTs. When a low-hydrogen insulating film such as a SiOx film is used to obtain an oxide semiconductor film containing less hydrogen, the amount of hydrogen supplied to the low-temperature polysilicon film may be insufficient. The process of manufacturing oxide semiconductor TFTs can further reduce the hydrogen in the low-temperature polysilicon. For these reasons, a structure and manufacturing process are needed to prevent hydrogen deficiency in low-temperature polysilicon TFTs.

[0037] The thin film transistor substrate in the embodiment of the present specification includes a low-temperature polysilicon film and an oxide semiconductor film disposed above the low-temperature polysilicon film. The thin film transistor substrate also includes a low-hydrogen insulating film disposed above and in contact with the oxide semiconductor film and a high-hydrogen insulating film disposed above the low-hydrogen insulating film. The low-hydrogen insulating film above the low-temperature polysilicon film is thinner than the low-hydrogen insulating film above the oxide semiconductor film. This structure reduces the degradation of the characteristics of the oxide semiconductor film, but increases the hydrogen supplied from the high-hydrogen insulating film to the low-temperature polysilicon film to alleviate the hydrogen deficiency in the low-temperature polysilicon film.

[0038] Implementation Method 1

[0039] Structure of display device

[0040] Figure 1 An example of the structure of an OLED display device 1 is schematically shown. The OLED display device 1 includes a thin film transistor (TFT) substrate 10 on which an organic light emitting element (OLED element) and a pixel circuit are manufactured and a thin film encapsulation (TFE) 20 for encapsulating the organic light emitting element. The thin film encapsulation 20 is a structural encapsulation unit. Another example of a structural encapsulation unit includes an encapsulation substrate for encapsulating the organic light emitting element and an adhesive (glass frit sealant) for bonding the TFT substrate 10 to the encapsulation substrate. For example, the space between the TFT substrate 10 and the encapsulation substrate is filled with dry nitrogen.

[0041] A scanning driver 31, a light emitting driver 32, a protection circuit 33, a driver IC 34, and a demultiplexer 36 are provided around the cathode electrode region 14 outside the display region 25 of the TFT substrate 10. The driver IC 34 is connected to an external device via a flexible printed circuit (FPC) 35.

[0042] The scanning driver 31 drives the scanning lines on the TFT substrate 10. The light emission driver 32 drives the light emission control lines to control the light emission period of the pixels. For example, the driver IC 34 is mounted with an anisotropic conductive film (ACF).

[0043] The protection circuit 33 protects the elements in the pixel circuit from being damaged by electrostatic discharge. The driver IC 34 supplies power and timing signals (control signals) to the scan driver 31 and the light emitting driver 32 , and further supplies power and data signals to the demultiplexer 36 .

[0044] The demultiplexer 36 sequentially outputs the output of one pin of the driver IC 34 to d data lines (d is an integer greater than 1). The demultiplexer 36 changes the output data line of the data signal from the driver IC 34 d times in each scanning period to drive the data lines d times the output pin of the driver IC 34. These scanning driver 31, light emitting driver 32, protection circuit 33 and demultiplexer 36 are peripheral circuits made on the TFT substrate 10.

[0045] Pixel circuit structure

[0046] A plurality of pixel circuits are formed on the TFT substrate 10 to control current supplied to anodes of sub-pixels (also simply referred to as pixels). Figure 2A An example of the structure of a pixel circuit is shown. Each pixel circuit includes a driving transistor T1, a selection transistor T2, a light emitting transistor T3 and a storage capacitor C1. The pixel circuit controls the light emission of the OLED element E1. The transistor is a TFT. Transistors other than the driving transistor T1 are switching transistors.

[0047] The selection transistor T2 is a switch for selecting a sub-pixel. The selection transistor T2 is an n-channel oxide semiconductor TFT, and its gate terminal is connected to the scanning line 16. Its source terminal is connected to the data line 15. Its drain terminal is connected to the gate terminal of the driving transistor T1.

[0048] The driving transistor T1 is a transistor (driving TFT) for driving the OLED element E1. The driving transistor T1 is a p-channel low-temperature polysilicon TFT, and its gate terminal is connected to the drain terminal of the selection transistor T2. The source terminal of the driving transistor T1 is connected to the power supply line (Vdd) 18. Its drain terminal is connected to the source terminal of the light-emitting transistor T3. The storage capacitor C1 is provided between the gate terminal and the source terminal of the driving transistor T1.

[0049] The light emitting transistor T3 is a switch for controlling the supply / stop of the driving current to the OLED element E1. The light emitting transistor T3 is an n-channel oxide semiconductor TFT, and its gate is connected to the light emitting control line 17. The source terminal of the light emitting transistor T3 is connected to the drain terminal of the driving transistor T1. The drain terminal of the light emitting transistor T3 is connected to the OLED element E1.

[0050] Next, the operation of the pixel circuit is described. The scan driver 31 outputs a selection pulse to the scan line 16, turning on the selection transistor T2. The data voltage supplied from the driver IC 34 through the data line 15 is stored in the storage capacitor C1. The storage capacitor C1 holds the stored voltage during a frame period. The conductance of the drive transistor T1 changes in an analog manner according to the stored voltage, so that the drive transistor T1 supplies a forward bias current corresponding to the light emission level to the OLED element E1.

[0051] The light emitting transistor T3 is located on the supply path of the driving current. The light emitting driver 32 outputs a control signal to the light emitting control line 17 to control the on / off of the light emitting transistor T3. When the light emitting transistor T3 is turned on, the driving current is supplied to the OLED element E1. When the light emitting transistor T3 is turned off, the supply is stopped. The lighting period (duty cycle) in one frame period can be controlled by controlling the on / off of the transistor T3.

[0052] Figure 2B Another structural example of a pixel circuit is shown. The pixel circuit includes a reset transistor T4 instead of Figure 2A The light emitting transistor T3 in the OLED element E1 is provided. The reset transistor T4 is an n-channel oxide semiconductor TFT. The reset transistor T4 controls the electrical connection between the reference voltage supply line 11 and the anode of the OLED element E1. The control is performed according to a reset control signal supplied from the reset control line 19 to the gate terminal of the reset transistor T4. The reset transistor T4 can be used for various purposes.

[0053] Figure 2C Another structural example of a pixel circuit is shown. The pixel circuit includes n-channel transistors T1 to T6. The gate terminal of the selection transistor T2 is supplied with a Vscan2 signal. The storage capacitor C1 is supplied with a data voltage through the selection transistor T2. The gates of the transistors T4 and T6 are supplied with a Vscan1 signal.

[0054] Transistors T4 and T6 supply Vref to the anode of OLED element E1 to set a threshold voltage for storage capacitor C1. Gates of transistors T3 and T5 are supplied with signals Vem1 and Vem2, respectively, to control the light emission of OLED element E1. Transistors other than driving transistor T1 are switching transistors.

[0055] The driving transistor T1 may be a low-temperature polysilicon TFT, the transistor T6 may be an oxide semiconductor TFT, and the other transistors may be a low-temperature polysilicon TFT or an oxide semiconductor TFT. Figure 2A , Figure 2B and Figure 2C The circuit configuration in is an example; the pixel circuit may have a different circuit configuration.

[0056] The above-mentioned pixel circuit includes a low-temperature polysilicon TFT and an oxide semiconductor TFT. The configuration described in this specification improves the characteristics of the low-temperature polysilicon TFT and the oxide semiconductor TFT.

[0057] Structure of thin film transistor substrate

[0058] Hereinafter, a structure example of a thin film transistor substrate including a low temperature polysilicon TFT and an oxide semiconductor TFT is described. The oxide semiconductor may be indium gallium zinc oxide (IGZO). The structure described in this specification is applicable to elements made of other oxide semiconductors.

[0059] Figure 3 The cross-sectional structure of a part of the thin film transistor substrate is schematically shown. The low temperature polysilicon TFT 141, the oxide semiconductor TFT 143 and the storage capacitor 145 are fabricated on the insulating substrate 101. Further, the anode electrode 162 of the OLED element is connected to the source / drain electrode 130 of the low temperature polysilicon TFT 141. Figure 3 Other components of the OLED component are omitted.

[0060] The low temperature polysilicon TFT 141 includes a low temperature polysilicon film 103, a gate electrode 123, a gate insulating film between the gate electrode 123 and the low temperature polysilicon film 103, and source / drain electrodes 129 and 130. The gate insulating film is a part of a gate insulating (GI) film 111.

[0061] The oxide semiconductor TFT 143 includes an oxide semiconductor film 109 , a gate electrode 125 , a gate insulating film 114 between the gate electrode 125 and the oxide semiconductor film 109 , and source / drain electrodes 126 and 127 .

[0062] The storage capacitor 145 includes a first electrode 124 as a lower electrode, a second electrode 128 as an upper electrode, and an insulating film sandwiched between the first electrode 124 and the second electrode 128. The insulating film has a stacked structure; a portion of the insulating films 112, 113, and 115 are stacked. The first electrode 124 is connected to the source / drain electrode 127 of the oxide semiconductor TFT 143. The second electrode 128 is connected to the source / drain electrode 129 of the low-temperature polysilicon TFT 141.

[0063] In the following, the components of the thin film transistor substrate are described in accordance with Figure 3101 is a flexible or inflexible substrate made of resin or glass. The low-temperature polysilicon film 103 is an active film; it includes a channel and a low-resistance region sandwiching the channel in a planar direction. The channel is made of low-temperature polysilicon (high-resistance low-temperature polysilicon) whose resistance is not reduced. The low-resistance region is composed of low-temperature polysilicon whose resistance is reduced by doping with high-concentration impurities; they are connected to the source / drain electrodes 129 and 130.

[0064] The low temperature polysilicon film 103 is included in the low temperature polysilicon layer. The low temperature polysilicon layer includes the low temperature polysilicon films of a plurality of low temperature polysilicon TFTs. Figure 3 The low-temperature polysilicon film 103 in the example is in contact with the insulating substrate 101, but another insulating layer such as a silicon nitride layer may be provided therebetween.

[0065] The gate insulating film 111 is provided to cover the low-temperature polysilicon film 103. The gate insulating film 111 may be made of silicon oxide (SiOx). The gate insulating film of the low-temperature polysilicon TFT 141 is a part of the gate insulating film 111; it is located between the gate electrode 123 and the polysilicon film 103 in the stacking direction. The gate insulating film is in contact with the polysilicon film 103 and the gate electrode 123. The gate insulating film 111 may be composed of multiple layers.

[0066] The gate electrode 123 is disposed above the gate insulating film 111. The gate electrode 123 is made of metal and is included in the first metal layer. The material of the first metal layer can be selected arbitrarily; for example, Mo, W, Nb, or Al can be used. Figure 3 The low-temperature polysilicon TFT 141 in the example has a top gate structure, but the low-temperature polysilicon TFT 141 may have a bottom gate structure.

[0067] The first electrode 124 of the storage capacitor 145 is disposed over the gate insulating film 111. The first electrode 124 is included in the same first metal layer including the gate electrode 123 and is made of the same material as the gate electrode 123.

[0068] An interlayer insulating film (ILD) 112 is provided to cover the gate electrode 123, the first electrode 124, and the gate insulating film 111. The interlayer insulating film 112 may be a silicon oxide film or a silicon nitride (SiNx) film. Another interlayer insulating film 113 is placed over the interlayer insulating film 112. The interlayer insulating film 113 is a low-hydrogen insulating film such as a silicon oxide film.

[0069] The oxide semiconductor film 109 is disposed above the interlayer insulating film 113 and in contact with the interlayer insulating film 113. The oxide semiconductor film 109 is an active film; it includes a channel and a low resistance region sandwiching the channel in a planar direction. The low resistance region is made of IGZO with reduced resistance. The source / drain electrodes 126 and 127 are connected to the low resistance region. The oxide semiconductor film 109 is included in the oxide semiconductor layer. The oxide semiconductor layer includes oxide semiconductor films of a plurality of oxide semiconductor TFTs.

[0070] The gate insulating film 114 and the gate electrode 125 are placed above the channel of the oxide semiconductor film 109. The channel of the oxide semiconductor film 109, the gate insulating film 114, and the gate electrode 125 are placed in order from the bottom (from the side close to the insulating substrate 101); the gate insulating film 114 is in contact with the channel of the oxide semiconductor film 109 and the gate electrode 125.

[0071] The gate insulating film 114 may be made of silicon oxide. The gate electrode 125 is made of metal and is included in the second metal layer. The gate electrode 125 may be made of the same material as the gate electrode 123 of the low temperature polysilicon TFT 141. Figure 3 The oxide semiconductor TFT 143 in the example has a top gate structure, but the oxide semiconductor TFT 143 may have a bottom gate structure.

[0072] The interlayer insulating film 115 is provided to cover the oxide semiconductor film 109, the gate insulating film 114, and the gate electrode 125. The interlayer insulating film 115 covers a portion of the interlayer insulating film 113. The interlayer insulating film 115 contacts the oxide semiconductor film 109. The entire oxide semiconductor film 109 is covered by the interlayer insulating film 113 therebelow and the interlayer insulating film 115 thereover.

[0073] The interlayer insulating film 115 is a low-hydrogen insulating film such as a silicon oxide film. The hydrogen concentration in the low-hydrogen interlayer insulating films 113 and 115 may be at most 1E21 atoms / cm 3 . The low hydrogen insulating film can be made of silicon oxide prepared by plasma enhanced chemical vapor deposition (PECVD) or silicon nitride prepared from a hydrogen-free material. In addition, an AlOx film prepared by atomic layer deposition (ALD) or a TaOx film prepared by sputtering can also be used. Since the interlayer insulating films 113 and 115 in contact with the oxide semiconductor film 109 are low hydrogen insulators, they prevent the increase of carriers due to the supplied hydrogen.

[0074] The interlayer insulating film 115 has different thicknesses depending on the position. Specifically, when viewed in the stacking direction (planar view), the portion covering the low-temperature polysilicon film 103 is thinner than the portion covering the oxide semiconductor film 109. The portion sandwiched between the two electrodes 124 and 128 of the storage capacitor 145 is equal to or smaller than the portion covering the oxide semiconductor film 109.

[0075] Figure 3 The interlayer insulating film 115 in the structural example has a thick portion (second portion) 131 and a thin portion (first portion) 132. The thick portion 131 covers the oxide semiconductor film 109. The thin portion 132 covers the low-temperature polysilicon film 103. The thin portion 132 is partially included in the storage capacitor 145. The portion included in the storage capacitor 145 has the same thickness as the portion covering the low-temperature polysilicon film 103. The influence of the interlayer insulating film 115 of different thicknesses will be described below.

[0076] The source / drain electrodes 126 and 127 of the oxide semiconductor TFT 143 and the source / drain electrodes 129 and 130 of the low-temperature polysilicon TFT 141 are disposed above the interlayer insulating film 115. Further, the second electrode 128 of the storage capacitor 145 is disposed above the interlayer insulating film 115. The source / drain electrodes 126, 127, 129 and 130 and the second electrode 128 are included in the third metal layer and they are made of the same material. The material of the third metal layer can be selected as needed; for example, Al or Ti can be used.

[0077] The source / drain electrodes 126 and 127 of the oxide semiconductor TFT 143 are provided above the thick portion 131 of the interlayer insulating film 115. The source / drain electrodes 126 of the oxide semiconductor TFT 143 are in contact with a low resistance region of the oxide semiconductor film 109 through a contact hole opened through the interlayer insulating film 115.

[0078] The source / drain electrode 127 contacts another low resistance region of the oxide semiconductor film 109 through a contact hole opened through the interlayer insulating film 115. The source / drain electrode 127 also contacts the first electrode 124 of the storage capacitor 145 through a contact hole opened through the interlayer insulating films 115, 113, and 112.

[0079] The source / drain electrodes 129 and 130 of the low-temperature polysilicon TFT 141 are disposed above the thin portion 132 of the interlayer insulating film 115. The source / drain electrodes 129 and 130 of the low-temperature polysilicon TFT 141 are in contact with the low-resistance region of the low-temperature polysilicon film 103 through contact holes opened through the interlayer insulating films 115, 113, and 112 and the gate insulating film 111.

[0080] The second electrode 128 of the storage capacitor 145 is connected to the source / drain electrodes 129 of the low-temperature polysilicon TFT 141. An insulating film having a stacked structure composed of parts of the interlayer insulating films 112, 113, and 115 is located in a region where the second electrode 128 and the first electrode 124 are opposed to each other (their overlapping region in a plan view).

[0081] A passivation film (PAS) 116 is provided to cover the source / drain electrodes 126, 127, 129, and 130 and the second electrode 128. The passivation film 116 contacts and covers a portion of the interlayer insulating film 115. The passivation film 116 is separated from the oxide semiconductor film 109 by the interlayer insulating film 115. The interlayer insulating film 115 and the passivation film 116 are a first insulating film and a second insulating film, respectively.

[0082] The passivation film 116 is a high-hydrogen insulating film such as a silicon nitride film. The hydrogen concentration in the passivation film 116 is higher than the hydrogen concentration in the interlayer insulating films 113 and 115. The hydrogen concentration in the passivation film 116 may be at least 2E21 atoms / cm 3 .

[0083] When the passivation film 116 is being formed or is subsequently annealed, the passivation film 116 supplies hydrogen to the low temperature polysilicon film 103. The supplied hydrogen terminates dangling bonds at the grain boundaries of the low temperature polysilicon film 103. The low temperature polysilicon film 103 achieves desired characteristics by hydrogen supplied from the passivation film 116.

[0084] As described above, the portion of the interlayer insulating film 115 covering the low-temperature polysilicon film 103 is thinner than the portion covering the oxide semiconductor film 109. This structure allows the high-hydrogen passivation film 116 to be closer to the low-temperature polysilicon film 103. The thick portion 131 of the low-hydrogen interlayer insulating film 115 serves as a barrier film for hydrogen of the oxide semiconductor film 109.

[0085] Due to such a difference in thickness of the interlayer insulating film 115 , the passivation film 116 can effectively supply hydrogen to the low-temperature polysilicon film 103 , and further reduce the influence of hydrogen from the passivation film 116 on the oxide semiconductor film 109 to achieve characteristics required for the oxide semiconductor film 109 .

[0086] As described above, the portion of the interlayer insulating film 115 included in the storage capacitor 145 is as thin as the portion covering the low-temperature polysilicon film 103. This structure provides a higher capacitance for the storage capacitor 145. The portion of the interlayer insulating film 115 included in the storage capacitor 145 may be thinner than the portion covering the low-temperature polysilicon film 103, or thinner than the portion covering the oxide semiconductor film 109 but thicker than the portion covering the low-temperature polysilicon film 103. The portion of the interlayer insulating film 115 included in the storage capacitor 145 may be as thick as the portion covering the oxide semiconductor film 109. The storage capacitor 145 may include portions of the interlayer insulating film 115 having different thicknesses.

[0087] An insulating planarization film (PLN) 161 is disposed on the passivation film 116. The planarization film 161 may be made of an organic material. An anode electrode 162 is disposed above the planarization film 161. The anode electrode 162 contacts the source / drain electrode 130 of the low-temperature polysilicon TFT 141 through contact holes in the planarization film 161 and the passivation film 116.

[0088] The anode electrode 162 may include, for example, a transparent film of ITO or IZO, a reflective film made of a metal such as Ag, Mg, Al, Pt, or Mo or an alloy containing such a metal, and another transparent film as described above. This three-layer structure of the anode electrode 162 is only an example; the anode electrode 162 may have a two-layer structure.

[0089] Above the anode electrode 162, an insulating pixel defining layer (PDL) 163 is provided to separate the OLED elements. The pixel defining layer 163 may be made of an organic material. The OLED element is provided in the opening of the pixel defining layer 163. An organic light emitting film, not shown, is provided above the anode electrode 162. The organic light emitting film is composed of, for example, a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer in sequence from the bottom. The stacked structure of the organic light emitting film is determined according to the design.

[0090] In addition, a cathode electrode not shown is disposed above the organic light emitting film. The cathode electrode transmits a portion of visible light from the organic light emitting film. The stack of the anode electrode 162, the organic light emitting film and the cathode electrode disposed in the opening of the pixel defining layer 163 corresponds to an OLED element.

[0091] exist Figure 3 In the illustrated structural example, when viewed in a plan view, the thick portion 131 of the interlayer insulating film 115 covers the entire oxide semiconductor film 109. This structure effectively prevents degradation of the characteristics of the oxide semiconductor film 109. In another example, the thick portion 131 of the interlayer insulating film 115 may cover only a portion of the oxide semiconductor film 109.

[0092] exist Figure 3 In the illustrated structural example, when viewed in plan, the thin portion 132 of the interlayer insulating film 115 covers the entire low-temperature polysilicon film 103. This structure effectively prevents hydrogen deficiency in the low-temperature polysilicon film 103. In another example, the thin portion 132 of the interlayer insulating film 115 may cover only a portion of the low-temperature polysilicon film 103.

[0093] Figure 4 An example of a planar structure of a portion of a thin film transistor substrate is schematically shown. Figure 4 In the embodiment, the data line 151 extends vertically, and the scan line 152 extends horizontally. The gate electrode 125 ( Figure 4 ) is part of scan line 152.

[0094] exist Figure 4 , the thin portion 132 of the interlayer insulating film 115 is surrounded by a dotted line, and all around it is the thick portion 131 of the interlayer insulating film 115. When viewed in a plan view, the thin portion 132 overlaps the entire low-temperature polysilicon TFT 141 including the low-temperature polysilicon film 103. The thin portion 132 further occupies the entire region where the two electrodes 124 and 128 of the storage capacitor 145 are opposed to each other. When viewed in a plan view, the thick portion 131 overlaps the entire oxide semiconductor TFT 143 including the oxide semiconductor film 109.

[0095] exist Figure 4 In the structural example, the area occupied by the thick portion 131 is larger than the area occupied by the thin portion 132. More specifically, only the area overlapping the low-temperature polysilicon TFT 141 and the storage capacitor 145 and its adjacent area are included in the thin portion 132, and the other area is included in the thick portion 131.

[0096] Figure 5 Another example of a planar structure of a portion of a thin film transistor substrate is schematically shown. Figure 4 Unlike the structural example of FIG. 1 , the area occupied by the thin portion 132 is larger than the area occupied by the thick portion 131. More specifically, only the area overlapping with the oxide semiconductor TFT 143 and its adjacent area are included in the thick portion 131, and the other area is included in the thin portion 132. For example, such a structure can be adopted in a thin film transistor substrate including fewer oxide semiconductor TFTs than low-temperature polysilicon TFTs.

[0097] Manufacturing method

[0098] Reference 6A to 6F describe Figure 3 The manufacturing method of the structure shown in FIG. Fig. 6AAs shown, the manufacturing method forms a low-temperature polysilicon film 103 on an insulating substrate 101. Specifically, the manufacturing method deposits amorphous silicon on the insulating substrate 101 by PECVD, and crystallizes the amorphous silicon by excimer laser annealing to form a low-temperature polysilicon film. The manufacturing method patterns the low-temperature polysilicon film by photolithography to form an island-shaped polysilicon film 103.

[0099] Next, the manufacturing method forms a gate insulating film 111 by, for example, PECVD. Further, the manufacturing method forms a first metal layer by sputtering and patterns the first metal layer by photolithography to form a gate electrode 123 and a first electrode 124. In addition, the manufacturing method uses the gate electrode 123 as a mask to implant impurities into the low-temperature polysilicon film 103 to prepare a low-resistance region.

[0100] Next, the manufacturing method forms the interlayer insulating film 112 by PECVD, and further forms the low-hydrogen interlayer insulating film 113 by PECVD. Next, the manufacturing method forms an oxide semiconductor layer on the low-hydrogen interlayer insulating film 113 by sputtering, and patterns the oxide semiconductor layer by photolithography. Thus, the oxide semiconductor film 109 is formed.

[0101] Next, refer to Figure 6B The manufacturing method forms an insulating film including a gate insulating film 114 by PECVD. Further, the manufacturing method forms a second metal layer by sputtering and patterns the second metal layer by photolithography to form a gate electrode 125.

[0102] Next, the manufacturing method patterns the insulating film using the gate electrode 125 as a mask to form the gate insulating film 114. In another example, the manufacturing method patterns the insulating film together with the gate electrode 125 by photolithography and etching. In addition, the manufacturing method reduces the resistance of the end region of the oxide semiconductor film 109 by using the gate electrode 125 as a mask. By exposing the oxide semiconductor film 109 in the region not covered by the gate electrode 125 to He plasma, the resistance can be reduced. Next, the manufacturing method forms an interlayer insulating film 115 by PECVD. The interlayer insulating film 115 contacts and covers the oxide semiconductor film 109 in the portion not covered by the gate electrode 125. The interlayer insulating film 115 is a low hydrogen insulating film such as a silicon oxide film formed by PECVD or a silicon nitride film formed by PECVD of a hydrogen-free material.

[0103] Next, refer to Figure 6C , the manufacturing method etches the interlayer insulating film 115 by photolithography to form the thin portion 132. The remaining unetched portion of the interlayer insulating film 115 is the thick portion 131. Wet etching or dry etching may be employed.

[0104] Next, refer to Fig.6D The manufacturing method opens a contact hole in the stacked insulating film by anisotropic etching. Further, the manufacturing method forms a third metal layer by sputtering and patterns the third metal layer by photolithography. For example, the third metal layer may have a multilayer structure of Ti / Al / Ti. The source / drain electrodes 126, 127, 129 and 130 and the second electrode 128 are patterned. Further, data lines and power lines are formed together.

[0105] The source / drain electrode 126 is connected to the oxide semiconductor film 109 through a contact hole opened through the interlayer insulating film 115. The source / drain electrode 127 is connected to the oxide semiconductor film 109 and the first electrode 124 through an interconnector provided in the contact hole. The source / drain electrodes 129 and 130 are connected to the low-temperature polysilicon film 103 through the interconnector provided in the contact hole.

[0106] Next, refer to Fig. 6E The manufacturing method forms a passivation film 116 by PECVD. The passivation film 116 is a high-hydrogen insulating film, such as a silicon nitride film made of a hydrogen-containing material by PECVD. After forming the passivation film 116, the manufacturing method performs annealing. Annealing allows the passivation film 116 to effectively supply hydrogen to the low-temperature polysilicon film 103.

[0107] Next, refer to Fig. 6F The manufacturing method deposits a photosensitive organic material on the entire substrate to form a planarization film 161 and opens a contact hole for connecting the anode electrode 162 to the source / drain electrode 130 by photolithography. The manufacturing method forms the anode electrode 162 on the planarization film 161 having the contact hole by sputtering and patterning. Next, the manufacturing method deposits a photosensitive organic resin film by spin coating and patterns the photosensitive organic resin film to form a pixel defining layer 163.

[0108] Although not shown in the figure, the manufacturing method forms an organic light-emitting film on the anode electrode 162 after forming the pixel defining layer 163. The organic light-emitting film is formed by depositing an organic light-emitting material by vapor deposition at a position corresponding to the pixel through a metal mask. The manufacturing method further deposits a metal material for a cathode electrode. The metal material deposited on the organic light-emitting film of a sub-pixel is used as the cathode electrode of the sub-pixel in the opening area of ​​the pixel defining layer 163.

[0109] Other Implementations

[0110] Figure 7 The cross-sectional structure of a portion of a thin film transistor substrate in another structural example is schematically shown. Figure 3 The structural example shown is different from the structural example. This structural example includes a high hydrogen passivation film 119 to replace Figure 3 The high hydrogen passivation film 116 in the structural example. The structural example also includes a low hydrogen passivation film 118 between the high hydrogen passivation film 119 and the low hydrogen interlayer insulating film 115. The high hydrogen passivation film 119 and the low hydrogen passivation film 118 are examples of the second insulating film and the third insulating film, respectively.

[0111] like Figure 7 As shown, the passivation film 118 is in contact with the passivation film 119 and the interlayer insulating film 115. The passivation film 118 is provided to cover the source / drain electrodes 126, 127, 129 and 130 and the second electrode 128. The passivation film 118 contacts and covers a portion of the interlayer insulating film 115. The passivation film 118 is an insulating film with low hydrogen; it can be made of a material that can be used for the interlayer insulating film 115.

[0112] The interlayer insulating film 118 has different thicknesses depending on the position. Specifically, when viewed in the stacking direction (planar view), the portion covering the low-temperature polysilicon film 103 is thinner than the portion covering the oxide semiconductor film 109 . Figure 7 The passivation film 118 in the structural example has a thick portion (fourth portion) 134 and a thin portion (third portion) 135 .

[0113] The thick portion 134 covers the oxide semiconductor film 109. The thin portion 135 covers the low-temperature polysilicon film 103. The passivation film 118 can be formed by PECVD, and the thick portion 134 and the thin portion 135 are formed by etching, similarly to the interlayer insulating film 115.

[0114] The passivation film 119 is disposed on the passivation film 118. The layers above the passivation film 119 are Figure 3 The passivation film 119 is separated from the oxide semiconductor film 109 by the low-hydrogen interlayer insulating film 115 and the low-hydrogen passivation film 118. The passivation film 119 is a high-hydrogen insulating film; it can be made of Figure 3 The hydrogen concentration in the passivation film 119 can be made of the same material and the same process as in the structure example. Figure 3 The hydrogen concentration in the passivation film 116 in the structural examples is the same.

[0115] The thin film transistor substrate is manufactured by forming the interlayer insulating film 115 below and then forming the passivation film 118. After forming the passivation film 118, the manufacturing method forms the passivation film 119 on the passivation film 118. After forming the passivation film 119, annealing is performed.

[0116] When the passivation film 119 is being formed or is subsequently annealed, the passivation film 119 supplies hydrogen to the low temperature polysilicon film 103. The supplied hydrogen terminates dangling bonds at the grain boundaries of the low temperature polysilicon film 103. The low temperature polysilicon film 103 obtains desired characteristics by the hydrogen supplied from the passivation film 119.

[0117] As described above, the portions of the interlayer insulating film 115 and the passivation film 118 covering the low-temperature polysilicon film 103 are thinner than the portions covering the oxide semiconductor film 109. This structure allows the high-hydrogen passivation film 119 to be closer to the low-temperature polysilicon film 103. The thick portion 131 of the low-hydrogen interlayer insulating film 115 and the thick portion 134 of the passivation film 118 serve as a barrier film for hydrogen of the oxide semiconductor film 109.

[0118] Due to this difference in thickness between the interlayer insulating film 115 and the passivation film 118 , the passivation film 119 can effectively supply hydrogen to the low-temperature polysilicon film 103 and further reduce the influence of hydrogen from the passivation film 119 on the oxide semiconductor film 109 to achieve the characteristics required of the oxide semiconductor film 109 .

[0119] exist Figure 7 In the illustrated structural example, the thick portion 134 of the passivation film 118 covers the entire oxide semiconductor film 109 in plan view. This structure effectively prevents degradation of the characteristics of the oxide semiconductor film 109. In another example, the thick portion 134 of the passivation film 118 may cover only a portion of the oxide semiconductor film 109.

[0120] exist Figure 7 In the illustrated structural example, the thin portion 135 of the passivation film 118 covers the entire low-temperature polysilicon film 103 when viewed in plan. This structure effectively prevents hydrogen deficiency in the low-temperature polysilicon film 103. In another example, the thin portion 135 of the passivation film 118 may cover only a portion of the low-temperature polysilicon film 103.

[0121] Figure 8 The cross-sectional structure of a portion of a thin film transistor substrate in another structural example is schematically shown. Figure 7 The structural examples shown are different. Figure 8 The example structure shown is Figure 7 In addition to the illustrated structural example, a third electrode 139 included in the storage capacitor 145 is included. The third electrode 139 is located above the second electrode 128.

[0122] The third electrode 139 is disposed above the passivation film 119 and in contact with the passivation film 119. The third electrode 139 is opposite to the second electrode 128 in the stacking direction; a stack of a portion of the passivation film 119 and a portion of the passivation film 118 is sandwiched therebetween. The third electrode 139 is connected to the first electrode 124 through a contact hole opened through the passivation films 118 and 119 and the source / drain electrode 127 of the oxide semiconductor TFT 143. The first electrode 124 and the third electrode 139 are at the same potential. Due to the third electrode 139, the storage capacitor 145 obtains a higher capacitance.

[0123] exist Figure 8 In the structural example of FIG. 1 , a portion of the thin portion 135 of the passivation film 118 is located between the second electrode 128 and the third electrode 139. This structure increases the capacitance of the storage capacitor 145. Figure 8 In the structural example of FIG. 1 , a portion of the thick portion 134 and a portion of the thin portion 135 of the passivation film 118 are located between the second electrode 128 and the third electrode 139 .

[0124] The thinnest portion of the passivation film 118 located between the second electrode 128 and the third electrode 139 may be thinner than the portion covering the low-temperature polysilicon film 103, or thinner than the portion covering the oxide semiconductor film 109 but thicker than the portion covering the low-temperature polysilicon film 103. The portion of the passivation film 118 located between the second electrode 128 and the third electrode 139 may be as thick as the portion covering the oxide semiconductor film 109.

[0125] The manufacturing of the thin film transistor substrate forms the third electrode 139 after forming the passivation film 119 thereunder. Specifically, after opening contact holes in the passivation films 119 and 118 by anisotropic etching, the manufacturing method forms a metal film by sputtering and patterns the metal film by photolithography to form the third electrode 139. The third electrode 139 may be made of the same material as the second electrode 128 or the first electrode 124 and have the same structure as the second electrode 128 or the first electrode 124.

[0126] Next, we will describe Figure 3 The structural example in the display area shown in FIG. is applied to an example of a peripheral circuit. The peripheral circuits are arranged outside (periphery) of the display area where the light emitting elements are arranged, and they transmit signals for controlling the light emitting elements. The peripheral circuit 37 may be a scan driver 31, a light emitting driver 32, a protection circuit 33, or a demultiplexer 36. The peripheral circuit 37 is made on the TFT substrate 10.

[0127] Fig. 9 An example of a shift register circuit included in a scan driver circuit is shown. The shift register circuit includes transistors T11 to T19 and storage capacitors C11 and C12. Potential VGH is a high power supply potential, and potential VGL is a low power supply potential. Signal ST is a start pulse or an output from a previous stage. Signal OUT1 is an output. Signal OUT2 is a feedback signal from a next stage. Signal RST is a reset signal. Signal CK is a clock signal, and signal XCK is an inverted clock signal.

[0128] exist Fig. 9In the circuit shown, transistors T16 to T19 are connected to the output terminal OUT1 of the signal. Since the output terminal OUT1 of the signal is connected to the pixel in the display area, it has a large load capacity. Therefore, transistors T16 to T19 are required to have high driving capabilities. Therefore, low-temperature polysilicon TFTs with high mobility can be used for transistors T16 to T19. On the other hand, transistors T11 to T15 connected to the gate of transistor T16 are required to generate less leakage current to maintain the gate potential of transistor T16. Therefore, oxide semiconductor TFTs can be used for transistors T11 to T15.

[0129] Fig.10 The cross-sectional structure of a portion of the thin film transistor substrate in this structural example is schematically shown. Figure 3 The structural example shown is different in that it includes a peripheral circuit 37. The peripheral circuit includes a low-temperature polysilicon TFT 142 and an oxide semiconductor TFT 144. The low-temperature polysilicon TFT 142 includes a low-temperature polysilicon film 104, a gate electrode 150, and source / drain electrodes 173 and 174. The oxide semiconductor TFT 144 includes an oxide semiconductor film 110, a gate electrode 136, and source / drain electrodes 171 and 172.

[0130] The portion of the interlayer insulating film 115 in the peripheral circuit 37 covering the low-temperature polysilicon film 104 is thinner than the portion covering the oxide semiconductor film 110. This structure allows the high-hydrogen passivation film 116 to be closer to the low-temperature polysilicon film 104. The thick portion 131 of the low-hydrogen interlayer insulating film 115 serves as a barrier film for hydrogen of the oxide semiconductor film 110.

[0131] Due to such a difference in thickness of the interlayer insulating film 115 , the passivation film 116 can effectively supply hydrogen to the low-temperature polysilicon film 104 , thereby further reducing the influence of hydrogen from the passivation film 116 on the oxide semiconductor film 110 to achieve the characteristics required of the oxide semiconductor film 110 .

[0132] Hydrogen efficiently supplied from the passivation film 116 to the low temperature polysilicon film 104 enables the low temperature polysilicon TFT in the peripheral circuit 37 to have characteristics required for higher driving capability. As a result, the peripheral circuit 37 can have a narrower width and achieve high-speed driving.

[0133] Fig.11 The cross-sectional structure of a portion of a thin film transistor substrate in another structural example is schematically shown. This example is a structure of a thin film transistor substrate applied to a liquid crystal display device. Fig.10 The differences in the structures shown are examples. Fig.11The structure example includes an oxide semiconductor TFT 143 in the display region 25. The oxide semiconductor TFT 143 drives liquid crystal (not shown) using charges stored in a storage capacitor insulating film 177 between a pixel electrode 176 and a common electrode 178. In addition, a light shielding layer 175 is provided below the oxide semiconductor film 109 of the oxide semiconductor TFT 143.

[0134] exist Fig.11 In the structural example of , the portion of the interlayer insulating film 115 covering the low-temperature polysilicon film 104 in the peripheral circuit is thinner than the portion covering the oxide semiconductor films 109 and 110. Therefore, the passivation film 116 can effectively supply hydrogen to the low-temperature polysilicon film 104, and further reduce the influence of hydrogen from the passivation film 116 on the oxide semiconductor films 109 and 110, so as to achieve the characteristics required by the oxide semiconductor films 109 and 110.

[0135] Hydrogen efficiently supplied from the passivation film 116 to the low-temperature polysilicon film 104 enables the low-temperature polysilicon TFT 142 in the peripheral circuit 37 to have a desired characteristic of higher driving capability. As a result, the peripheral circuit 37 can have a narrower width and achieve high-speed driving. This structural example can include a low-temperature polysilicon TFT in the display area 25.

[0136] Fig.12 The cross-sectional structure of a portion of a thin film transistor substrate in another structural example is schematically shown. This example is a structure of a thin film transistor substrate applied to a Micro-LED display device. Fig.10 The structural examples shown are different. Fig.12 The structure example includes Fig.10 In addition to the structural example of , it also includes bumps 180 and 181, a micro LED 182, an anode electrode 183 of the micro LED 182, and a cathode electrode 184 of the micro LED 182. The anode electrode 183 of the micro LED 182 is connected to the anode electrode 162 through the bump 180. The cathode electrode 184 of the micro LED 182 is connected to the common electrode 185 through the bump 181. The bump can be a solder bump (Ag / Sn) or made of Au or Cu.

[0137] Fig.12 Examples of Figure 2A , Figure 2B or Figure 2C A pixel circuit in the micro LED 182. A low-temperature polysilicon TFT 141 having high mobility can be used as a driving transistor of the micro LED 182. An oxide semiconductor TFT 143 generating a small leakage current can be used as a switching transistor connected to a storage capacitor 145 for maintaining a gate potential of the driving transistor.

[0138] exist Fig.12 In the structural example, the portion of the interlayer insulating film 115 in the display region 25 and the peripheral circuit 37 covering the low-temperature polysilicon films 103 and 104 is thinner than the portion covering the oxide semiconductor films 109 and 110. Therefore, the passivation film 116 can effectively supply hydrogen to the low-temperature polysilicon films 103 and 104, and further reduce the influence of hydrogen from the passivation film 116 on the oxide semiconductor films 109 and 110, so as to achieve the characteristics required by the oxide semiconductor films 109 and 110.

[0139] Hydrogen efficiently supplied from the passivation film 116 to the low temperature polysilicon films 103 and 104 enables the low temperature polysilicon TFTs 141 and 142 to have desired characteristics of higher driving capability. As a result, the peripheral circuit 37 can have a narrower width and achieve high-speed driving.

[0140] Next, an example in which the thin film transistor substrate of the present invention is applied to a sensor array in which sensors such as photodiodes are arranged is described. Fig.13 2 is an equivalent circuit diagram of a unit pixel of a sensor array. The equivalent circuit includes transistors T21 to T25 and a diode D1. During the period when transistors T24 and T25 are in a conductive state according to the COLUMN PULSE n signal and the LINE PULSE m signal, transistor T23 outputs the voltage of diode D1 to the COMMON OUTPUT line 201. That is, the signal is amplified and buffered by transistor T23 before being output.

[0141] Therefore, noise is difficult to mix on the output line, thereby obtaining a high S / N ratio. In this circuit, a low-temperature polysilicon TFT having high mobility can be used for transistors T23, T24, and T25 on a path that outputs the voltage of the diode D1 to the COMMON OUTPUT line 201. On the other hand, the transistors T21 and T22 can adopt oxide semiconductor TFTs that generate a small leakage current in order to accurately maintain the voltage of the diode D1.

[0142] Fig.14 The cross-sectional structure of a portion of the thin film transistor substrate in this structural example is schematically shown. Fig.10 The structural examples shown are different. Fig.14 The structure example includes Fig.10 In addition to the structure of FIG. 1 , the photodiode 190, the protective film 186, the cathode electrode 184, the common electrode 185 and the contact hole 187 are also included. One end of the photodiode 190 is connected to the anode electrode 162. The other end of the photodiode 190 is connected to the cathode electrode 184 through the contact hole 187, and is further connected to the common electrode 185.

[0143] exist Fig.14 In the structural example of , the portion of the interlayer insulating film 115 in the sensor array region 26 and the peripheral circuit 37 covering the low-temperature polysilicon films 103 and 104 is thinner than the portion covering the oxide semiconductor films 109 and 110. Therefore, the passivation film 116 can effectively supply hydrogen to the low-temperature polysilicon films 103 and 104, and further reduce the influence of hydrogen from the passivation film 116 on the oxide semiconductor films 109 and 110 to obtain the desired characteristics of the oxide semiconductor films 109 and 109. Therefore, the unexpected change in the voltage of the diode D1 is reduced to achieve a high S / N ratio.

[0144] The hydrogen efficiently supplied from the passivation film 116 to the low temperature polysilicon films 103 and 104 enables the low temperature polysilicon TFTs 141 and 142 to have the desired characteristics of higher driving capability. As a result, the voltage signal of the diode D1 is amplified to achieve a high S / N ratio. In addition, the peripheral circuit 37 can have a narrower width and achieve high-speed driving.

[0145] As described above, the embodiments of the present invention have been described; however, the present invention is not limited to the aforementioned embodiments. Those skilled in the art can easily modify, add or convert the various elements in the above embodiments within the scope of the present invention. A part of the structure of one embodiment can be replaced with the structure of another embodiment, or the structure of one embodiment can be incorporated into the structure of another embodiment.

Claims

1. A thin film transistor substrate, comprising: Insulating substrate; a first thin film transistor, the first thin film transistor being provided on the insulating substrate and including a polysilicon film as an active film; a second thin film transistor provided on the insulating substrate and including an oxide semiconductor film as an active film located above the polysilicon film; a first insulating film located above the polysilicon film and the oxide semiconductor film, the first insulating film being in contact with the oxide semiconductor film and covering at least a portion of the polysilicon film and at least a portion of the oxide semiconductor film when viewed in a stacking direction; as well as a second insulating film which is located above the first insulating film and covers the at least a portion of the polysilicon film and the at least a portion of the oxide semiconductor film when viewed in the stacking direction and contains hydrogen at a higher concentration than the hydrogen concentration in the first insulating film, The first insulating film includes a first portion and a second portion. wherein the first portion includes a portion covering the at least a portion of the polysilicon film, wherein the second portion includes a portion covering the at least a portion of the oxide semiconductor film, and Wherein, the first portion is thinner than the second portion.

2. The thin film transistor substrate according to claim 1, further comprising: a first electrode; as well as a second electrode located above the first electrode, The first portion includes a portion sandwiched between the first electrode and the second electrode.

3. The thin film transistor substrate according to claim 1, wherein: The second insulating film is in contact with the first insulating film.

4. The thin film transistor substrate according to claim 1, further comprising a third insulating film located between the first insulating film and the second insulating film, in, The hydrogen concentration in the third insulating film is lower than the hydrogen concentration in the second insulating film, The third insulating film includes a third portion and a fourth portion. wherein the third portion includes a portion covering the at least a portion of the polysilicon film, wherein the fourth portion includes a portion covering the at least a portion of the oxide semiconductor film, and Wherein, the third portion is thinner than the fourth portion.

5. The thin film transistor substrate according to claim 4, further comprising: a first electrode; a second electrode located above the first electrode; as well as a third electrode located above the second electrode, wherein the first portion includes a portion sandwiched between the first electrode and the second electrode, and The third portion includes a portion sandwiched between the second electrode and the third electrode.

6. The thin film transistor substrate according to claim 1, further comprising a light emitting element on the insulating substrate, in, The first thin film transistor and the second thin film transistor are included in a pixel circuit configured to control light emission of the light emitting element, wherein the first thin film transistor is a driving thin film transistor configured to supply current to the light emitting element, and Wherein, the second thin film transistor is a switching transistor.

7. The thin film transistor substrate according to claim 6, in, The pixel circuit includes a storage capacitor configured to hold a gate potential of the driving thin film transistor, The storage capacitor includes a first electrode and a second electrode located above the first electrode, and The first portion includes a portion sandwiched between the first electrode and the second electrode.

8. The thin film transistor substrate according to claim 6, further comprising: a display region in which a plurality of light emitting elements including the light emitting element are arranged on the insulating substrate; as well as a peripheral circuit, the peripheral circuit being disposed on the insulating substrate, the peripheral circuit being located outside the display area and being configured to transmit a signal, the signal being configured to control each of the plurality of light emitting elements, Wherein, the peripheral circuit includes another first thin film transistor.

9. The thin film transistor substrate according to claim 1, further comprising: a display area, in which a plurality of pixel electrodes and a common electrode are arranged on the insulating substrate; as well as a peripheral circuit, the peripheral circuit being disposed on the insulating substrate, the peripheral circuit being located outside the display area and being configured to transmit a signal, the signal being configured to control a charge to be stored between each pixel electrode of the plurality of pixel electrodes and the common electrode, wherein the second thin film transistor in the display area is a thin film transistor configured to supply charges to one pixel electrode among the plurality of pixel electrodes, and Wherein, the peripheral circuit includes the first thin film transistor.

10. The thin film transistor substrate according to claim 1, further comprising: a display area, in which a plurality of pixel electrodes and a common electrode are arranged on the insulating substrate; as well as a peripheral circuit, the peripheral circuit being disposed on the insulating substrate, the peripheral circuit being located outside the display area and being configured to transmit a signal, the signal being configured to control a charge to be stored between each pixel electrode of the plurality of pixel electrodes and the common electrode, wherein the first thin film transistor in the display area is a thin film transistor configured to supply charges to one pixel electrode among the plurality of pixel electrodes, and Wherein, the peripheral circuit includes another first thin film transistor and the second thin film transistor.

11. The thin film transistor substrate according to claim 6, wherein: The light emitting element is a micro LED.

12. The thin film transistor substrate according to claim 1, further comprising: a sensor array region in which a plurality of sensor elements are arranged on the insulating substrate; as well as a peripheral circuit, the peripheral circuit being disposed on the insulating substrate, the peripheral circuit being located outside the sensor array region and being configured to transmit a signal, the signal being configured to control the plurality of sensor elements, wherein the first thin film transistor and the second thin film transistor are included in a sensor circuit configured to control one sensor element among the plurality of sensor elements, and Wherein, the peripheral circuit includes another first thin film transistor.

13. A method for manufacturing a thin film transistor substrate, comprising: forming a polysilicon film as an active film of a first thin film transistor on an insulating substrate; After forming the polysilicon film, forming an oxide semiconductor film as an active film of a second thin film transistor on a layer above the polysilicon film on the insulating substrate; After forming the oxide semiconductor film, forming a first insulating film on a layer above the oxide semiconductor film; as well as After forming the first insulating film, forming a second insulating film on a layer above the first insulating film, the second insulating film containing hydrogen at a higher concentration than the hydrogen concentration in the first insulating film, wherein the first insulating film is in contact with the oxide semiconductor film and covers at least a portion of the polysilicon film and at least a portion of the oxide semiconductor film when viewed in a stacking direction, The first insulating film includes a first portion and a second portion. wherein the first portion includes a portion covering the at least a portion of the polysilicon film, wherein the second portion includes a portion covering the at least a portion of the oxide semiconductor film, wherein the second insulating film covers the at least a portion of the polysilicon film and the at least a portion of the oxide semiconductor film when viewed in the stacking direction, and Here, forming the first insulating film includes etching the first insulating film so that the first portion is thinner than the second portion.

14. The method according to claim 13, further comprising: before forming the first insulating film, forming a first electrode on a layer below the first insulating film; as well as After forming the first insulating film, forming a second electrode on a layer above the first insulating film, The first portion includes a portion sandwiched between the first electrode and the second electrode.

15. The method according to claim 13, further comprising, after forming the first insulating film, forming a third insulating film on a layer above the first insulating film, in, The forming of the second insulating film is to form the second insulating film on a layer above the third insulating film after forming the third insulating film. wherein the hydrogen concentration in the third insulating film is lower than the hydrogen concentration in the second insulating film, The third insulating film includes a third portion and a fourth portion. wherein the third portion includes a portion covering the at least a portion of the polysilicon film, wherein the fourth portion includes a portion covering the at least a portion of the oxide semiconductor film, and Here, forming the third insulating film includes etching the third insulating film so that the third portion is thinner than the fourth portion.

16. The method according to claim 15, further comprising: before forming the first insulating film, forming a first electrode on a layer below the first insulating film; after forming the first insulating film and before forming the second insulating film, forming a second electrode on a layer above the first insulating film; as well as After forming the second insulating film, forming a third electrode on a layer above the second insulating film, wherein the first portion includes a portion sandwiched between the first electrode and the second electrode, and The third portion includes a portion sandwiched between the second electrode and the third electrode. 17 . The method according to claim 13 , further comprising performing annealing after forming the second insulating film.

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