A method for manufacturing super junction trench gate MOS

Abstract

The invention provides a manufacturing method of a super junction trench gate MOS, comprising the following steps: forming an N-type drift region by epitaxy on a highly doped N-type substrate; performing high-energy P-type implantation on the N-type drift region to form a P-type implantation region at the bottom of the N-type drift region; forming a trench at the top of the N-type drift region, and forming a trench gate dielectric layer on the inner wall of the trench; filling the trench gate polysilicon layer in the trench; then implanting on both sides of the trench to form a P-type body region; performing N-type heavy doping implantation above the P-type body regions on both sides of the trench to form an N-type heavy doping region; and activating impurities in the N-type heavy doping region through a thermal process; then performing selective implantation on the N-type drift region and the P-type body region to form a P-pillar region; forming contact holes on both sides of the N-type heavy doping region; performing P-type heavy doping implantation on the P-type body region below the contact hole to form a P-type heavy doping region through thermal diffusion, and activating impurities in the P-pillar region at the same time; forming an insulating dielectric layer on the trench gate polysilicon layer, and then covering the metal layer to form a source-drain metal layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a super junction trench gate MOS. Background Art

[0002] Trench gate MOSFET devices are widely used in power conversion circuits and are often used in power switching devices. The on-resistance Rsp and breakdown voltage BV of the trench gate are one of its important parameter indicators. To obtain a higher breakdown voltage and lower R sp It can improve the competitiveness of products. In order to improve the on-resistance of medium and high voltage (50-200V) trench gate, the concept of super junction-trench gate was proposed, as shown in the figure above.

[0003] Taking the N-channel trench gate as an example, in order to improve the characteristics of the super junction-trench gate device, the bottom of the P-pillar used to assist the depletion of the drift region will be as close to the highly doped substrate as possible, which can increase the concentration of the entire epitaxial layer.

[0004] However, due to the limitation of Boron injection energy, the P-pillar formed by injection is restricted to the process conditions where the Boron energy is greater than 3000KeV. In particular, for the requirement of BV>80V (epitaxial layer Epi thickness>5um), the Boron injection energy must be greater than 2500KeV to make the bottom as close as possible to the highly doped substrate. Therefore, the process difficulty of realizing medium and high voltage super junction-trench gate devices with BV>80V is increased only by injecting P-pillar. Summary of the invention

[0005] In view of the shortcomings of the prior art described above, an object of the present invention is to provide a method for manufacturing a super junction trench gate MOS, which is used to solve the problem of complex process of medium and high voltage super junction trench gate MOSFET in which the P-type injection region is depleted in the N-type drift region formed by selective high-energy injection in the prior art.

[0006] To achieve the above-mentioned and other related purposes, the present invention provides a method for manufacturing a super junction trench gate MOS, which at least comprises:

[0007] Step 1: epitaxially forming an N-type drift region on a highly doped N-type substrate;

[0008] Step 2: Perform high-energy P-type implantation on the N-type drift region to form a P-type implantation region at the bottom of the N-type drift region;

[0009] Step 3, forming a trench on the top of the N-type drift region, forming a trench gate dielectric layer on the inner wall of the trench; filling the trench gate polysilicon layer in the trench; and then implanting a P-type body region on both sides of the trench;

[0010] Step 4: performing N-type heavy doping implantation above the P-type body region on both sides of the trench to form an N-type heavy doping region; and activating the impurities in the N-type heavy doping region through a thermal process; and then performing selective implantation in the N-type drift region and the P-type body region to form a P-pillar region;

[0011] Step 5, forming contact holes on both sides of the N-type heavily doped region;

[0012] Step 6: Perform P-type heavy doping injection on the P-type body region below the contact hole to form a P-type heavy doping region through thermal diffusion, and activate impurities in the P-pillar region at the same time;

[0013] Step seven: forming an insulating dielectric layer on the trench gate polysilicon layer, and then covering it with a metal layer to form a source and drain metal layer.

[0014] The present invention also provides another method for manufacturing a super junction trench gate MOS, which at least comprises:

[0015] Step 1: epitaxially forming an N-type drift region on a highly doped N-type substrate;

[0016] Step 2: forming a trench on the top of the N-type drift region, forming a trench gate dielectric layer on the inner wall of the trench; filling the trench gate polysilicon layer in the trench; and then implanting a P-type body region on both sides of the trench;

[0017] Step 3: Perform high-energy P-type implantation on the N-type drift region to form a P-type implantation region at the bottom of the N-type drift region;

[0018] Step 4: performing N-type heavy doping implantation above the P-type body region on both sides of the trench to form an N-type heavy doping region; and activating the impurities in the N-type heavy doping region through a thermal process; and then performing selective implantation in the N-type drift region and the P-type body region to form a P-pillar region;

[0019] Step 5, forming contact holes on both sides of the N-type heavily doped region;

[0020] Step 6: Perform P-type heavy doping injection on the P-type body region below the contact hole to form a P-type heavy doping region through thermal diffusion, and activate impurities in the P-pillar region at the same time;

[0021] Step seven: forming an insulating dielectric layer on the trench gate polysilicon layer, and then covering it with a metal layer to form a source and drain metal layer.

[0022] The present invention also provides another method for manufacturing a super junction trench gate MOS, which at least comprises:

[0023] Step 1: epitaxially forming an N-type drift region on a highly doped N-type substrate;

[0024] Step 2: forming a trench on the top of the N-type drift region, forming a trench gate dielectric layer on the inner wall of the trench; filling the trench gate polysilicon layer in the trench; and then implanting a P-type body region on both sides of the trench;

[0025] Step 3, performing N-type heavy doping implantation above the P-type body region on both sides of the trench to form an N-type heavily doped region; and activating the impurities in the N-type heavily doped region through a thermal process; and then performing selective implantation in the N-type drift region and the P-type body region to form a P-pillar region;

[0026] Step 4: Perform high-energy P-type implantation on the N-type drift region to form a P-type implantation region at the bottom of the N-type drift region;

[0027] Step 5, forming contact holes on both sides of the N-type heavily doped region;

[0028] Step 6: Perform P-type heavy doping injection on the P-type body region below the contact hole to form a P-type heavy doping region through thermal diffusion, and activate impurities in the P-pillar region at the same time;

[0029] Step seven: forming an insulating dielectric layer on the trench gate polysilicon layer, and then covering it with a metal layer to form a source and drain metal layer.

[0030] Preferably, the concentration range of the N-type drift region is 5e15-1e17cm ^-3 .

[0031] Preferably, the ions used for high-energy P-type implantation into the N-type drift region are boron ions.

[0032] Preferably, the P-type implant is a global implant and does not require photoresist.

[0033] Preferably, the P-type injection region 113 is a location for high-energy P-type injection, but the injection of the P-type injection region 113 does not completely compensate the N-type drift region 102 , so that the net doping of the P-type injection region 113 is still N-type.

[0034] Preferably, the P-pillar region is formed by selective implantation using a photoresist or a hard dielectric layer as a barrier layer.

[0035] Preferably, the P-pillar region is a P-type implantation region that assists in depletion of the N-type drift region, and the implantation energy is less than 2500 KeV.

[0036] Preferably, the contact hole is formed by photolithography.

[0037] Preferably, the remaining photoresist after the contact hole is formed by photolithography is injected with adhesive to form the P-type heavily doped region.

[0038] As described above, the manufacturing method of the super junction trench gate MOS of the present invention has the following beneficial effects: the method of the present invention splits the multiple P-Pillar injections in the medium and high voltage super junction trench gate MOSFET into multiple times, wherein the injection with energy less than 2500KeV adopts selective injection, i.e. local injection, but the required photoresist thickness can be thinned; and the injection greater than 2500KeV adopts global injection, i.e. the whole wafer is injected, and no photoresist is required. The local P-Pillar formed by the Boron injection less than 2500KeV assists in depleting the upper end of the epitaxial layer (with a relatively large concentration), while the net doping concentration of the lower end of the epitaxial layer is reduced due to the high-energy P-type global injection, and can be depleted without the P-pillar, so the bottom end of the locally injected P-pillar only needs to be as close as possible to the top of the N-type drift region with a relatively low net doping concentration. Since the injection energy of the P-pillar requiring photoresist is reduced, i.e. the thickness of the photoresist is thinned, the process difficulty is reduced. In addition, due to the greatly reduced energy of the P-Pillar, the miniaturization capability of the process can be further improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a schematic diagram showing the structure of forming an N-type drift region and a P-type injection region on a highly doped N-type substrate in the present invention;

[0040] Figure 2 It is a schematic diagram showing the structure of forming a trench gate dielectric layer, a trench gate polysilicon layer and a P-type body region in the present invention;

[0041] Figure 3 It is a schematic diagram showing the structure of forming an N-type heavily doped region and a P-pillar region in the present invention;

[0042] Figure 4 It is a schematic diagram showing the structure of forming a contact hole and a P-type heavily doped region in the present invention;

[0043] Figure 5 It is a schematic diagram of the structure after the insulating dielectric layer and the source-drain metal layer are formed in the present invention;

[0044] Figure 6 Shown is a comparison diagram of the id-vd relationship curves of the conventional trench gate MOS and the trench gate MOS of the present invention;

[0045] Figure 7 Shown is a comparison diagram of the relationship between vd and breakdown voltage of the conventional trench gate MOS and the trench gate MOS of the present invention. DETAILED DESCRIPTION

[0046] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0047] See also Figures 1 to 7 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0048] Embodiment 1

[0049] The present invention provides a method for manufacturing a super junction trench gate MOS, such as Figures 1 to 4 As shown, Figure 1 It is a schematic diagram showing the structure of forming an N-type drift region and a P-type injection region on a highly doped N-type substrate in the present invention; Figure 2 It is a schematic diagram showing the structure of forming a trench gate dielectric layer, a trench gate polysilicon layer and a P-type body region in the present invention; Figure 3 It is a schematic diagram showing the structure of forming an N-type heavily doped region and a P-pillar region in the present invention; Figure 4 It is a schematic diagram showing the structure of forming a contact hole and a P-type heavily doped region in the present invention; Figure 5 It is a schematic diagram of the structure after the insulating dielectric layer and the source-drain metal layer are formed in the present invention.

[0050] The method of this embodiment at least includes:

[0051] Step 1: epitaxially forming an N-type drift region 102 on a highly doped N-type substrate 101;

[0052] In the present invention, the concentration range of the N-type drift region 102 in step 1 of this embodiment is 5e15-1e17cm ^-3 .

[0053] Step 2: Perform high-energy P-type implantation on the N-type drift region 102 to form a P-type implantation region 113 at the bottom of the N-type drift region 102;

[0054] Furthermore, in the present invention, the ions used for high-energy P-type implantation into the N-type drift region 102 in step 2 of this embodiment are boron ions.

[0055] Furthermore, in the present invention, the P-type implantation in step 2 of this embodiment is a global implantation and does not require photoresist.

[0056] The present invention further states that the P-type injection region 113 of this embodiment is a location for high-energy P-type injection, but the injection of the P-type injection region 113 does not completely compensate the N-type drift region 102, so that the net doping of the P-type injection region 113 is still N-type. In other words, the P-type injection region 113 is a location for high-energy P-type injection, but the net doping of the P-type injection region 113 is still N-type, that is, the injection of 113 does not completely compensate the N-type drift region 102 to form a net doped P-type region.

[0057] Step 3: forming a trench on the top of the N-type drift region 102, forming a trench gate dielectric layer 104 on the inner wall of the trench; filling the trench with a trench gate polysilicon layer 105; and then implanting a P-type body region 106 on both sides of the trench;

[0058] Step 4: Perform N-type heavy doping implantation on the P-type body region 106 on both sides of the trench to form an N-type heavy doping region 108; and activate the impurities in the N-type heavy doping region 108 through a thermal process; and then perform selective implantation on the N-type drift region 102 and the P-type body region 106 to form a P-pillar region 103;

[0059] According to the present invention, in step 4 of this embodiment, the P-pillar region 103 is formed by selectively implanting a photoresist or a hard dielectric layer as a barrier layer.

[0060] In the present invention, the P-pillar region 103 in step 4 of this embodiment is a P-type implantation region that assists in depleting the N-type drift region, and the implantation energy is less than 2500 KeV.

[0061] Step 5: forming contact holes 109 on both sides of the N-type heavily doped region 108;

[0062] Furthermore, in the present invention, the contact hole 109 is formed in step five of this embodiment by photolithography.

[0063] Step 6: Perform P-type heavy doping injection on the P-type body region 106 below the contact hole 109 to form a P-type heavy doping region 107 through thermal diffusion, and activate impurities in the P-pillar region 103 at the same time;

[0064] The present invention further includes that in step six of this embodiment, the remaining photoresist after the contact hole is formed by photolithography is injected with adhesive to form the P-type heavily doped region 107 .

[0065] Step seven: forming an insulating dielectric layer 110 on the trench gate polysilicon layer 105 , and then covering it with a metal layer to form a source-drain metal layer 111 .

[0066] Embodiment 2

[0067] The present invention provides another method for manufacturing a super junction trench gate MOS, such as Figures 1 to 4 As shown, Figure 1 It is a schematic diagram showing the structure of forming an N-type drift region and a P-type injection region on a highly doped N-type substrate in the present invention; Figure 2 It is a schematic diagram showing the structure of forming a trench gate dielectric layer, a trench gate polysilicon layer and a P-type body region in the present invention; Figure 3 It is a schematic diagram showing the structure of forming an N-type heavily doped region and a P-pillar region in the present invention; Figure 4 It is a schematic diagram showing the structure of forming a contact hole and a P-type heavily doped region in the present invention; Figure 5 It is a schematic diagram of the structure after the insulating dielectric layer and the source-drain metal layer are formed in the present invention.

[0068] The method of this embodiment at least includes:

[0069] Step 1: epitaxially forming an N-type drift region 102 on a highly doped N-type substrate 101;

[0070] In the present invention, the concentration range of the N-type drift region 102 in step 1 of this embodiment is 5e15-1e17cm ^-3 .

[0071] Step 2: forming a trench on the top of the N-type drift region 102, forming a trench gate dielectric layer 104 on the inner wall of the trench; filling the trench with a trench gate polysilicon layer 105; and then implanting a P-type body region 106 on both sides of the trench;

[0072] Step three, high-energy P-type implantation is performed on the N-type drift region 102 to form a P-type implantation region 113 at the bottom of the N-type drift region 102; further, in the present invention, the ions implanted into the N-type drift region 102 in step three of this embodiment are boron ions.

[0073] The present invention further comprises that the P-type implantation in step three of this embodiment is a global implantation and does not require photoresist.

[0074] The present invention further provides that the P-type injection region 113 of this embodiment is a location for high-energy P-type injection, but the injection of the P-type injection region 113 does not completely compensate the N-type drift region 102, so that the net doping of the P-type injection region 113 is still N-type. In other words, the P-type injection region 113 is a location for high-energy P-type injection, but the net doping of the P-type injection region 113 is still N-type, that is, the injection of the P-type injection region 113 does not completely compensate the N-type drift region 102 to form a net-doped P-type region.

[0075] Step 4: Perform N-type heavy doping implantation on the P-type body region 106 on both sides of the trench to form an N-type heavy doping region 108; and activate the impurities in the N-type heavy doping region 108 through a thermal process; and then perform selective implantation on the N-type drift region 102 and the P-type body region 106 to form a P-pillar region 103;

[0076] According to the present invention, in step 4 of this embodiment, the P-pillar region 103 is formed by selectively implanting a photoresist or a hard dielectric layer as a barrier layer.

[0077] In the present invention, the P-pillar region 103 in step 4 of this embodiment is a P-type implantation region that assists in depleting the N-type drift region, and the implantation energy is less than 2500 KeV.

[0078] Step 5: forming contact holes 109 on both sides of the N-type heavily doped region 108;

[0079] Furthermore, in the present invention, the contact hole 109 is formed in step five of this embodiment by photolithography.

[0080] Step 6: Perform P-type heavy doping injection on the P-type body region 106 below the contact hole 109 to form a P-type heavy doping region 107 through thermal diffusion, and activate impurities in the P-pillar region 103 at the same time;

[0081] The present invention further includes that in step six of this embodiment, the remaining photoresist after the contact hole is formed by photolithography is injected with adhesive to form the P-type heavily doped region 107 .

[0082] Step seven: forming an insulating dielectric layer 110 on the trench gate polysilicon layer 105 , and then covering it with a metal layer to form a source-drain metal layer 111 .

[0083] Embodiment 3

[0084] The present invention provides another method for manufacturing a super junction trench gate MOS, such as Figures 1 to 4 As shown, Figure 1 It is a schematic diagram showing the structure of forming an N-type drift region and a P-type injection region on a highly doped N-type substrate in the present invention; Figure 2 It is a schematic diagram showing the structure of forming a trench gate dielectric layer, a trench gate polysilicon layer and a P-type body region in the present invention; Figure 3 It is a schematic diagram showing the structure of forming an N-type heavily doped region and a P-pillar region in the present invention; Figure 4 It is a schematic diagram showing the structure of forming a contact hole and a P-type heavily doped region in the present invention; Figure 5 It is a schematic diagram showing the structure after the insulating dielectric layer and the source-drain metal layer are formed in the present invention.

[0085] The method of this embodiment at least includes:

[0086] Step 1: epitaxially forming an N-type drift region 102 on a highly doped N-type substrate 101;

[0087] In the present invention, the concentration range of the N-type drift region 102 in step 1 of this embodiment is 5e15-1e17cm ^-3 .

[0088] Step 2: forming a trench on the top of the N-type drift region 102, forming a trench gate dielectric layer 104 on the inner wall of the trench; filling the trench with a trench gate polysilicon layer 105; and then implanting a P-type body region 106 on both sides of the trench;

[0089] Step 3: Perform N-type heavy doping implantation on the P-type body region 106 on both sides of the trench to form an N-type heavy doping region 108; and activate the impurities in the N-type heavy doping region 108 through a thermal process; and then perform selective implantation on the N-type drift region 102 and the P-type body region 106 to form a P-pillar region 103;

[0090] According to the present invention, in step three of this embodiment, the P-pillar region 103 is formed by selectively implanting a photoresist or a hard dielectric layer as a barrier layer.

[0091] In the present invention, the P-pillar region 103 in step three of this embodiment is a P-type implantation region that assists in depleting the N-type drift region, and the implantation energy is less than 2500 KeV.

[0092] Step 4: Perform high-energy P-type implantation on the N-type drift region 102 to form a P-type implantation region 113 at the bottom of the N-type drift region 102; (In the present invention, the ions that perform high-energy P-type implantation on the N-type drift region 102 in step 4 of this embodiment are boron ions.

[0093] Furthermore, in the present invention, the P-type implantation in step 2 of this embodiment is a global implantation and does not require photoresist.

[0094] The present invention further states that the P-type injection region 113 of this embodiment is a location for high-energy P-type injection, but the injection of the P-type injection region 113 does not completely compensate the N-type drift region 102, so that the net doping of the P-type injection region 113 is still N-type. In other words, the P-type injection region 113 is a location for high-energy P-type injection, but the net doping of 113 is still N-type, that is, the injection of 113 does not completely compensate the N-type drift region 102 to form a net-doped P-type region.

[0095] Step 5: forming contact holes 109 on both sides of the N-type heavily doped region 108;

[0096] Furthermore, in the present invention, the contact hole 109 is formed in step five of this embodiment by photolithography.

[0097] Step 6: Perform P-type heavy doping injection on the P-type body region 106 below the contact hole 109 to form a P-type heavy doping region 107 through thermal diffusion, and activate impurities in the P-pillar region 103 at the same time;

[0098] The present invention further includes that in step six of this embodiment, the remaining photoresist after the contact hole is formed by photolithography is injected with adhesive to form the P-type heavily doped region 107 .

[0099] Step seven: forming an insulating dielectric layer 110 on the trench gate polysilicon layer 105 , and then covering it with a metal layer to form a source-drain metal layer 111 .

[0100] like Figure 6 and Figure 7 As shown, Figure 6 It shows a comparison diagram of the Id-Vg relationship curves of the conventional trench gate MOS and the trench gate MOS of the present invention; Figure 7 It shows a comparison diagram of the breakdown voltage Id-Vg curves of the conventional trench gate MOS and the trench gate MOS of the present invention.

[0101] It can be seen that compared with the traditional trench gate MOSFET (Trench Gate, TGMOSFET) structure, although the BV of the super junction trench gate MOSFET (Super Junction Trench Gate, SJ-TGMOSFET) is reduced by 7V, R sp / I dLin It is reduced / increased by 49.1% (@Vg=10V), thus greatly improving the overall performance of the device. At the same time, due to the reduction of P-pillar injection energy, the difficulty of the manufacturing process is greatly reduced.

[0102] In summary, the method of the present invention splits multiple P-Pillar injections in medium and high voltage super junction-trench gate MOSFET into multiple times, wherein the injection with energy less than 2500KeV adopts selective injection, i.e. local injection, but the required photoresist thickness can be thinned; and the injection with energy greater than 2500KeV adopts global injection, i.e. the whole wafer is injected without photoresist. The local P-Pillar formed by Boron injection less than 2500KeV assists in depleting the upper end of the epitaxial layer (with a relatively high concentration), while the net doping concentration of the lower end of the epitaxial layer is reduced due to the high-energy P-type global injection, and can be depleted without P-pillar, so the bottom end of the locally injected P-pillar only needs to be as close as possible to the top of the N-type drift region with a lower net doping concentration. Since the injection energy of the P-pillar requiring photoresist is reduced, the thickness of the photoresist is thinned, and the process difficulty is reduced. In addition, due to the greatly reduced energy of the P-Pillar, the miniaturization capability of the process can be further improved. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0103] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a super junction trench gate MOS, characterized in that: At least: Step 1: epitaxially forming an N-type drift region on a highly doped N-type substrate; Step 2: Perform high-energy P-type implantation on the N-type drift region to form a P-type implantation region at the bottom of the N-type drift region; Step 3, forming a trench on the top of the N-type drift region, forming a trench gate dielectric layer on the inner wall of the trench; filling the trench gate polysilicon layer in the trench; and then implanting a P-type body region on both sides of the trench; Step 4: performing N-type heavy doping implantation above the P-type body region on both sides of the trench to form an N-type heavy doping region; and activating the impurities in the N-type heavy doping region through a thermal process; and then performing selective implantation in the N-type drift region and the P-type body region to form a P-pillar region; Step 5, forming contact holes on both sides of the N-type heavily doped region; Step 6: Perform P-type heavy doping injection on the P-type body region below the contact hole to form a P-type heavy doping region through thermal diffusion, and activate impurities in the P-pillar region at the same time; Step seven: forming an insulating dielectric layer on the trench gate polysilicon layer, and then covering it with a metal layer to form a source and drain metal layer.

2. The method for manufacturing a super junction trench gate MOS according to claim 1, characterized in that: The concentration range of the N-type drift region in step 1 is 5e15~1e17cm ^-3 .

3. The method for manufacturing a super junction trench gate MOS according to claim 1, characterized in that: In step 2, the ions used for high-energy P-type implantation into the N-type drift region are boron ions.

4. The method for manufacturing a super junction trench gate MOS according to claim 1, characterized in that: The P-type injection region in step 2 is the location of high-energy P-type injection, but the injection of the P-type injection region does not completely compensate the N-type drift region, so that the net doping of the P-type injection region is still N-type.

5. The method for manufacturing a super junction trench gate MOS according to claim 3, characterized in that: The P-type implantation in step 2 is a global implantation and does not require photoresist.

6. The method for manufacturing a super junction trench gate MOS according to claim 3, characterized in that: In step 4, the P-pillar region is formed by selective implantation using a photoresist or a hard dielectric layer as a barrier layer.

7. The method for manufacturing a super junction trench gate MOS according to claim 6, characterized in that: The P-pillar region in step 4 is a P-type implantation region that assists the depletion of the N-type drift region, and the implantation energy is less than 2500 KeV.

8. The method for manufacturing a super junction trench gate MOS according to claim 6, characterized in that: The contact hole is formed in step five by photolithography.

9. The method for manufacturing a super junction trench gate MOS according to claim 6, characterized in that: In step six, the remaining photoresist after the contact hole is formed by photolithography is injected with adhesive to form the P-type heavily doped region.

10. A method for manufacturing a super junction trench gate MOS, characterized in that: At least: Step 1: epitaxially forming an N-type drift region on a highly doped N-type substrate; Step 2: forming a trench on the top of the N-type drift region, forming a trench gate dielectric layer on the inner wall of the trench; filling the trench gate polysilicon layer in the trench; and then implanting a P-type body region on both sides of the trench; Step 3: Perform high-energy P-type implantation on the N-type drift region to form a P-type implantation region at the bottom of the N-type drift region; Step 4: performing N-type heavy doping implantation above the P-type body region on both sides of the trench to form an N-type heavy doping region; and activating the impurities in the N-type heavy doping region through a thermal process; and then performing selective implantation in the N-type drift region and the P-type body region to form a P-pillar region; Step 5, forming contact holes on both sides of the N-type heavily doped region; Step 6: Perform P-type heavy doping injection on the P-type body region below the contact hole to form a P-type heavy doping region through thermal diffusion, and activate impurities in the P-pillar region at the same time; Step seven: forming an insulating dielectric layer on the trench gate polysilicon layer, and then covering it with a metal layer to form a source and drain metal layer.

11. The method for manufacturing a super junction trench gate MOS according to claim 9, characterized in that: The concentration range of the N-type drift region in step 1 is 5e15~1e17cm ^-3 .

12. The method for manufacturing a super junction trench gate MOS according to claim 9, characterized in that: In step 3, the ions used for high-energy P-type implantation into the N-type drift region are boron ions.

13. The method for manufacturing a super junction trench gate MOS according to claim 11, characterized in that: The P-type implantation in step three is a global implantation and does not require photoresist.

14. The method for manufacturing a super junction trench gate MOS according to claim 10, characterized in that: The P-type injection region in step three is the location of high-energy P-type injection, but the injection of the P-type injection region does not completely compensate the N-type drift region, so that the net doping of the P-type injection region is still N-type.

15. The method for manufacturing a super junction trench gate MOS according to claim 11, characterized in that: In step 4, the P-pillar region is formed by selective implantation using a photoresist or a hard dielectric layer as a barrier layer.

16. The method for manufacturing a super junction trench gate MOS according to claim 15, characterized in that: The P-pillar region in step 4 is a P-type implantation region that assists the depletion of the N-type drift region, and the implantation energy is less than 2500 KeV.

17. The method for manufacturing a super junction trench gate MOS according to claim 15, characterized in that: The contact hole is formed in step five by photolithography.

18. The method for manufacturing a super junction trench gate MOS according to claim 15, characterized in that: In step six, the remaining photoresist after the contact hole is formed by photolithography is injected with adhesive to form the P-type heavily doped region.

19. A method for manufacturing a super junction trench gate MOS, characterized in that: At least: Step 1: epitaxially forming an N-type drift region on a highly doped N-type substrate; Step 2: forming a trench on the top of the N-type drift region, forming a trench gate dielectric layer on the inner wall of the trench; filling the trench gate polysilicon layer in the trench; and then implanting a P-type body region on both sides of the trench; Step 3, performing N-type heavy doping implantation above the P-type body region on both sides of the trench to form an N-type heavily doped region; and activating the impurities in the N-type heavily doped region through a thermal process; and then performing selective implantation in the N-type drift region and the P-type body region to form a P-pillar region; Step 4: Perform high-energy P-type implantation on the N-type drift region to form a P-type implantation region at the bottom of the N-type drift region; Step 5, forming contact holes on both sides of the N-type heavily doped region; Step 6: Perform P-type heavy doping injection on the P-type body region below the contact hole to form a P-type heavy doping region through thermal diffusion, and activate impurities in the P-pillar region at the same time; Step seven: forming an insulating dielectric layer on the trench gate polysilicon layer, and then covering it with a metal layer to form a source and drain metal layer.

20. The method for manufacturing a super junction trench gate MOS according to claim 17, characterized in that: The concentration range of the N-type drift region in step 1 is 5e15~1e17cm ^-3 .

21. The method for manufacturing a super junction trench gate MOS according to claim 17, characterized in that: In step 4, the ions used for high-energy P-type implantation into the N-type drift region are boron ions.

22. The method for manufacturing a super junction trench gate MOS according to claim 19, characterized in that: The P-type implantation in step 4 is a global implantation and does not require photoresist.

23. The method for manufacturing a super junction trench gate MOS according to claim 19, characterized in that: The P-type injection region in step 4 is the location of high-energy P-type injection, but the injection of the P-type injection region does not completely compensate the N-type drift region, so that the net doping of the P-type injection region is still N-type.

24. The method for manufacturing a super junction trench gate MOS according to claim 21, characterized in that: In step three, the P-pillar region is formed by selective implantation using a photoresist or a hard dielectric layer as a barrier layer.

25. The method for manufacturing a super junction trench gate MOS according to claim 24, characterized in that: The P-pillar region in step three is a P-type implantation region that assists the depletion of the N-type drift region, and the implantation energy is less than 2500 KeV.

26. The method for manufacturing a super junction trench gate MOS according to claim 24, characterized in that: The contact hole is formed in step five by photolithography.

27. The method for manufacturing a super junction trench gate MOS according to claim 24, characterized in that: In step six, the remaining photoresist after the contact hole is formed by photolithography is injected with adhesive to form the P-type heavily doped region.

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