Semiconductor test chip and manufacturing method thereof

Abstract

A semiconductor test chip for wire bonding reliability testing of semiconductor components, comprising a semiconductor substrate and at least one test chip disposed on the semiconductor substrate. The at least one test chip has a top surface opposite to the semiconductor substrate and at least one electrical connection pad exposed outward from the top surface. The electrical connection pad has a metal layer and a metal compound layer formed on at least a part of the surface of the metal layer. Wherein, the metal compound layer includes metal oxide, and the thickness of the metal compound layer is between 2 nm and 50 nm. In addition, the present invention also provides a manufacturing method of the semiconductor test chip at the same time. By at least one of the composition, thickness and pattern of the metal compound layer, the surface state of the electrical connection pad of the semiconductor component, or the oxidation and corrosion damage conditions in different environments are simulated, so as to accelerate the reaction during the reliability test using the semiconductor test chip, and reduce the time of the reliability test.

Description

Technical Field

[0001] The present invention relates to a semiconductor chip and a manufacturing method thereof, and particularly to a semiconductor test chip for wire bonding reliability testing and a manufacturing method thereof. Background Art

[0002] With the demand for thinner, lighter, shorter, and smaller electronic products and the development of semiconductor technology, the size of semiconductor chips has become increasingly miniaturized. Among them, wire bonding is an important technology that enables the external electrical connection of miniaturized semiconductor chips. Therefore, how to ensure the reliability of wire bonding of semiconductor chips is an important issue that relevant industries actively pay attention to.

[0003] The metal layer used for wire bonding in semiconductor chips is generally composed of aluminum or copper. However, since aluminum or copper is easily oxidized and easily adsorbs foreign ions in the external environment, during the process of wire bonding and packaging a metal layer with a surface oxidized or adsorbed with foreign ions (such as chloride ions, nitrogen ions, etc.) to form a semiconductor component for use, due to the metal oxides and foreign ions adsorbed on the metal layer will affect the surface properties of the metal layer, or further cause corrosion of the metal layer, or generate intermetallic compounds that affect the adhesion between the wire bonding metal and the metal layer, etc., the wire bonding will peel off or fall off during the use of the semiconductor component, which has an adverse effect on the reliability of the component.

[0004] Therefore, in order to ensure the reliability and yield of the chip, the wire bonding reliability test of the semiconductor component is generally carried out before packaging. However, since the reliability test needs to simulate different environmental conditions and requires a long time for testing, the test is extremely time-consuming. Summary of the Invention

[0005] An object of the present invention is to provide a semiconductor test chip for wire bonding reliability testing of semiconductor components.

[0006] The semiconductor test chip of the present invention includes a semiconductor substrate and at least one test chip.

[0007] The at least one test chip is disposed on the semiconductor substrate, including a top surface opposite to the semiconductor substrate, and at least one electrical connection pad exposed outward from the top surface. The electrical connection pad includes a metal layer and a metal compound layer formed on at least a part of the surface of the metal layer by atomic deposition.

[0008] Preferably, in the semiconductor test chip of the present invention, the metal compound layer includes at least one of a halogen-containing metal compound, a nitrogen-containing metal compound, and an oxygen-containing metal compound.

[0009] Preferably, in the semiconductor test chip of the present invention, the thickness of the metal compound layer is between 2 nm and 50 nm.

[0010] Preferably, for the semiconductor test chip of the present invention, the at least one test chip further includes a test circuit for external electrical connection of the at least one test chip.

[0011] Preferably, for the semiconductor test chip of the present invention, the semiconductor test chip includes a plurality of test chips arrayed on the semiconductor substrate, wherein each test chip further includes a test circuit, and the test chips can be electrically connected by means of the test circuit.

[0012] Preferably, for the semiconductor test chip of the present invention, each test chip further has a redistribution line located above the test circuit and electrically connected to the test circuit, and a dielectric layer covering the redistribution line and having at least one opening, and each electrical connection pad is electrically connected to the redistribution line and is externally exposed from a corresponding one of the openings.

[0013] Preferably, for the semiconductor test chip of the present invention, the metal layer is electrically connected to the test circuit, and the metal compound layer completely covers the surface of the metal layer.

[0014] Preferably, for the semiconductor test chip of the present invention, the metal layer is electrically connected to the test circuit, and the metal compound layer partially covers the surface of the electrical connection pad.

[0015] Preferably, for the semiconductor test chip of the present invention, the metal compound layer further extends to cover the dielectric layer.

[0016] Another object of the present invention is to provide a method for manufacturing a semiconductor test chip for use in testing the wire bonding reliability of semiconductor components.

[0017] The method for manufacturing a semiconductor test chip of the present invention includes the following steps:

[0018] Provide a semiconductor component semi-finished product, the semiconductor component semi-finished product having a semiconductor substrate and at least one chip disposed on the semiconductor substrate, the at least one chip having a test circuit, and at least one metal layer electrically connected to the test circuit and externally exposed from the top surface of the at least one chip.

[0019] Use an atomic deposition method to deposit a metal compound layer on at least a part of the surface of the at least one metal layer to obtain the semiconductor test chip.

[0020] Preferably, for the method for manufacturing a semiconductor test chip of the present invention, the material of the metal compound layer includes at least one of metal oxides, halogen-containing metal compounds, nitrogen-containing metal compounds, and oxygen-containing metal compounds.

[0021] Preferably, in the method for manufacturing a semiconductor test chip according to the present invention, the thickness of the metal compound layer ranges from 2 nm to 50 nm.

[0022] Preferably, in the method for manufacturing a semiconductor test chip according to the present invention, the semiconductor component semi-finished product has a plurality of chips arrayed on the semiconductor substrate, each chip has a test circuit, and the chips can be electrically connected by means of the test circuit.

[0023] Preferably, in the method for manufacturing a semiconductor test chip according to the present invention, each chip further has a redistribution line located above the test circuit and electrically connected to the test circuit, and a dielectric layer covering the redistribution line and having at least one opening, and the electrical connection pads are electrically connected to the redistribution line and are respectively exposed to the outside through the corresponding openings.

[0024] The beneficial effect of the present invention is that by forming a metal compound layer including metal oxide on at least part of the surface of the electrical connection pads for external electrical connection of the semiconductor test chip, when performing a wire bonding reliability test using the semiconductor test chip, the surface state of the electrical connection pads of the semiconductor component, such as roughness, oxidation state, etc., and / or the oxidation and corrosion damage conditions in different environments can be simulated through at least one of the composition, thickness, and pattern of the metal compound layer, so as to accelerate the reaction during the reliability test using the semiconductor test chip and reduce the time for the reliability test. Description of the Drawings

[0025] Figure 1 is a top view schematic diagram of an embodiment of the semiconductor test chip of the present invention;

[0026] Figure 2 is a cross-sectional structural schematic diagram of one of the test chips of this embodiment;

[0027] Figure 3 is a partial cross-sectional structural schematic diagram of the electrical connection pad of this embodiment;

[0028] Figure 4 is a TEM diagram showing the formation of a metal compound layer on a metal layer. Detailed Embodiments

[0029] The present invention will be described in detail below with reference to the drawings and embodiments.

[0030] It should be noted that the drawings of the present invention only show the structural and / or positional relative relationship between components, and are not directly related to the actual sizes of the components.

[0031] The semiconductor test chip of the present invention is used for wire bonding reliability tests.

[0032] Refer toFigure 1 , 2 An embodiment of the semiconductor test chip includes a semiconductor substrate 2 and several test chips 3.

[0033] The semiconductor substrate 2 can be selected from silicon, compound semiconductors such as silicon carbide (SiC), or group III-IV semiconductors such as gallium arsenide (GaAs) and indium phosphide (InP), or group II-VI semiconductor materials such as zinc oxide (ZnO) and cadmium telluride (CdTe).

[0034] The test chips 3 are arranged on the semiconductor substrate 2 in an array arrangement. Each test chip 3 has a top surface opposite to the semiconductor substrate 2, a test circuit 31, a redistribution line 32 located above the test circuit 31 and electrically connected to the test circuit 31, a dielectric layer 33 covering the redistribution line 32 and having at least one opening 331, and electrical connection pads 34 respectively connected to the redistribution line 32 and exposed to the outside through a corresponding one of the openings 331 of the dielectric layer 33.

[0035] Specifically, the test circuit 31 has a plurality of dielectric insulating layers 311, metal wiring layers 312, and conductive vias 313 that are alternately stacked on the semiconductor substrate 2. The conductive vias 313 penetrate through the dielectric insulating layers 311 to electrically connect the metal wiring layers 312 in different ways, so as to form different conduction loops. Among them, in order to simulate the circuit of a general functional chip, the number of layers, thickness, and electrical connection relationship of the dielectric insulating layer 311 and the metal wiring layer 312 of the test circuit 31 can also completely simulate the circuit structure of the functional chip. In this way, the circuit test results of the test chip 3 can be fed back to the fully functional chip to correspondingly adjust the circuit design of the functional chip. The aforementioned dielectric insulating layer 311 can be selected from silicon dioxide, silicon nitride, silicon oxynitride, or polymer materials, and the metal wiring layer 312 and the conductive vias 313 can be respectively selected from conductive materials such as tungsten, aluminum, copper, aluminum alloy, or copper alloy. Since the related manufacturing processes and materials used for the test circuit 31 are well known to those skilled in the semiconductor technology field, no further elaboration will be provided.

[0036] The redistribution line 32 is disposed above the test circuit 31 and electrically connected to the test circuit 31. The dielectric layer 33 covers the redistribution line 32 and has a plurality of openings 331 that can expose the redistribution line 32. Among them, the redistribution line 32 is selected from conductive materials such as tungsten, aluminum, copper, aluminum alloy, or copper alloy, and the dielectric layer 33 can be selected from silicon dioxide, silicon nitride, silicon oxynitride, or polymer materials.

[0037] The electrical connection pads 34 are connected to the surface of the redistribution line 32 exposed from the opening 331 and are respectively exposed to the outside through the corresponding openings 331, for subsequent wire bonding, solder formation, or copper bump formation, so that the metal wiring layers 312 are connected in series to form at least one independent conductive loop. Specifically, each electrical connection pad 34 has a metal layer 341 connected to the surface of the redistribution line 32 exposed from the opening 331, and a metal compound layer 342 formed on at least a part of the surface of the metal layer 341. The metal layer 341 is made of materials such as aluminum, aluminum alloy, copper, or copper alloy. The material of the metal compound layer 342 includes metal oxides, and at least one of halogen-containing metal compounds, nitrogen-containing metal compounds, and oxygen-containing metal compounds.

[0038] In some embodiments, the thickness of the metal compound layer 342 is between 2 nm and 50 nm. Preferably, the thickness of the metal compound layer 342 is greater than 5 nm.

[0039] In some embodiments, the thickness of the metal compound layer 342 is between 10 nm and 50 nm.

[0040] It should be noted that since the metal compound layer 342 is composed of at least one of metal oxides, halogen-containing compounds, nitrogen-containing compounds, and oxygen-containing compounds, it will affect the electrical properties of the electrical connection pad 34. Therefore, depending on the test requirements and purposes of the semiconductor test chip, through the composition and distribution pattern of the metal compound layer 342 (for example, it can be controlled that the metal compound layer 342 selectively covers the surface of the metal layer 341 completely or partially. For example, refer to Figure 2 、 Figure 3 , Figure 2 so that the metal compound layer 342 completely covers the surface of the metal layer 341 and the thickness is between 2 nm and 50 nm; Figure 3 so that the metal compound layer 342 covers a part of the surface of the metal layer 341 in a patterned manner and the thickness is between 2 nm and 50 nm), the electrical connection pad 34 can be controlled to have surfaces with different electrical properties and roughness, so as to be more suitable for simulating test conditions of different wire bonding reliabilities. In addition, it should be further noted that in actual implementation, the metal compound layer 342 can also cover a part of the surface of the metal layer 341 in an irregular manner, or can be further extended to cover the dielectric layer 33 as required, not limited to the Figure 2 、 3 shown structure

[0041] Generally speaking, the metal compound layer 342 formed on the surface of the metal layer 341 will not only cause changes in electrical properties, but also cause changes in surface roughness and surface chemical properties, which will affect the adhesion and bonding strength of subsequent wire bonding, soldering or copper bumps to the electrical connection pad 34. However, because the thickness of general native metal oxides is extremely thin (<5 nm), when wire bonding is performed on a chip with an electrical connection pad having an extremely thin metal oxide on its surface and a reliability evaluation test of the wire bonding is carried out, a relatively long detection time is required to measure the influence of the metal oxide on the wire bonding. Therefore, in the present invention, by controlling the composition, distribution and thickness of the metal compound layer 342, the original surface properties and roughness of the electrical connection pad 34 are controlled, and a test chip 3 with electrical connection pads 34 having different surface chemical / electrical properties and roughness conditions can be provided for wire bonding reliability tests under different conditions, and the reaction of the semiconductor test chip during the reliability test can be induced and accelerated, thereby effectively reducing the reliability test time.

[0042] Specifically, the aforementioned metal compound layer 342 can be formed on the surface of the metal layer 341 by atomic layer deposition (ALD) on a chip disposed on the semiconductor substrate and having the test circuit 31, the redistribution line 32, the dielectric layer 33, and the metal layer exposed from the opening 331 of the dielectric layer 33, so as to more precisely control the thickness and pattern of the metal compound layer 342 and thus control the surface roughness of the electrical connection pad 34.

[0043] It should be further noted that since the adhesion of the wire bond / solder ball / copper bump to the electrical connection pad 34 is affected not only by the surface roughness of the electrical connection pad 34 but also by the chemical properties of the connection interface between the wire bond / solder ball / copper pillar and the electrical connection pad 34, in addition to metal oxides, the metal compound layer 342 of the present invention may further include one of the compounds in Group A. The compounds in Group A are formed by the reaction of the metal layer 341 with non-metal elements (such as halogens, nitrogen, oxygen), and include: halogen-containing compounds, nitrogen-containing compounds, and oxygen-containing compounds. By changing the composition of the metal compound layer 342, in addition to the change in surface roughness, the surface of the electrical connection pad 34 can also simulate the oxidation and corrosion damage conditions of the electrical connection pad 34 in different environments through the change in surface chemical properties, so that when the reliability test of the semiconductor test chip is carried out, the induced reaction can be accelerated to reduce the reliability test time.

[0044] In some embodiments, when the metal layer 341 is made of aluminum (Al), the metal oxide of the metal compound layer 342 is aluminum oxide (Al2O3), and the halogen-containing compound can be [AlF6] 3- , or AlF3, and the nitrogen-containing compound can be aluminum nitride (AlN).

[0045] In some other embodiments, the metal layer 341 is made of copper (Cu), the metal oxides of the metal compound layer 342 are copper oxide (CuO) and / or cuprous oxide (Cu2O), and the halogen-containing compound may be CuCl x .

[0046] It should be noted again that the test chip 3 can subsequently form solder bumps on its electrical connection pads 34, and electrically connect the solder bumps of one electrical connection pad 34 to the solder bumps of other electrical connection pads 34; or use wire bonding to electrically connect different electrical connection pads 34 to each other, so that the multiple independent circuits of the test circuit 31 of the test chip 3 are electrically conductive, or different test chips 3 can be connected in series to form a daisy chain. Since the test chips 3 are distributed in an array on the semiconductor substrate 2, during use, they can be cut according to the required number of test chips 3 and electrical connection states (as shown by the dotted line), making them easier to use. Figure 1 as shown by the dotted line), making them easier to use.

[0047] Refer to Figure 4 , Figure 4 is a TEM photo of a metal compound layer 342 containing aluminum oxide formed on a metal layer 341 made of Al. Among them, Figure 4 (b) is Figure 4 a partial enlarged view of (a), Figure 4 (c) is the metal compound layer 342 containing aluminum oxide and a fluorine-containing compound. It can be seen from Figure 4 that by using the thickness of the metal compound layer 342, the surface roughness of the electrical connection pad 34 can be controlled, and by cooperating with the chemical composition change of the metal compound layer 342, test chips 3 with different surface roughnesses and chemical energy states can be obtained, which can then be used for reliability evaluation tests to evaluate the influence of different roughnesses and different surface energy states on wire bonding.

[0048] In summary, the present invention forms a metal compound layer 342 on the surface of the metal layer 341, which contains at least one of metal oxides, or may further contain a halogen-containing compound, a nitrogen-containing compound, and an oxygen-containing compound obtained by reacting different non-metal elements with the metal of the metal layer 341. This allows the surface properties of the electrical connection pad 34 to simulate the surface roughness, oxidation, and corrosion damage conditions of the electrical connection pad 34 on the semiconductor chip in different environments through the metal compound layer 342. Thus, in the reliability test, it can simulate the possible states of abnormal wire bonding reliability on the metal layer surface during the semiconductor component manufacturing process, accelerate the induction reaction, reduce the time of the reliability test, and assist the R & D personnel to grasp the problems in real time and shorten the R & D time. Therefore, the purpose of the present invention can indeed be achieved.

Claims

1. A semiconductor test chip for wire bonding reliability testing of semiconductor components, comprising: a semiconductor substrate; and at least one test chip disposed on the semiconductor substrate, characterized in that: the at least one test chip includes: the top surface of the semiconductor substrate facing in the reverse direction; and at least one electrical connection pad, exposed to the outside from the top surface, and including a metal layer, and a metal compound layer formed on at least a part of the surface of the metal layer by atomic deposition, and the metal compound layer includes at least one of a halogen-containing metal compound and an oxygen-containing metal compound.

2. The semiconductor test chip according to claim 1, wherein: The thickness of the metal compound layer is between 2 nm and 50 nm.

3. The semiconductor test chip according to claim 1, characterized in that: The at least one test chip further includes a test circuit for electrically connecting the at least one test chip to the outside.

4. The semiconductor test chip according to claim 1, characterized in that: The semiconductor test chip includes a plurality of test chips arrayed on the semiconductor substrate. Among them, each test chip further includes a test circuit, and the test chips can be electrically connected by the test circuit.

5. The semiconductor test chip according to claim 4, wherein: Each test chip further has a redistribution line located above the test circuit and electrically connected to the test circuit, and a dielectric layer covering the redistribution line and having at least one opening. Each electrical connection pad is electrically connected to the redistribution line and is exposed to the outside from a corresponding one of the openings.

6. The semiconductor test chip according to claim 4, wherein: The metal layer is electrically connected to the test circuit, and the metal compound layer completely covers the surface of the metal layer.

7. The semiconductor test chip according to claim 4, wherein: The metal layer is electrically connected to the test circuit, and the metal compound layer partially covers the surface of the electrical connection pad.

8. The semiconductor test chip according to claim 6 or 7, characterized in that: Each test chip further has a redistribution line located above the test circuit and electrically connected to the test circuit, and a dielectric layer covering the redistribution line and having at least one opening. The metal compound layer further extends to cover the dielectric layer.

9. A method for fabricating a semiconductor test chip, characterized in that: including: providing a semiconductor component semi-finished product, the semiconductor component semi-finished product having a semiconductor substrate and at least one chip disposed on the semiconductor substrate, the at least one chip having a test circuit, and at least one metal layer electrically connected to the test circuit and exposed to the outside from the top surface of the at least one chip; and using atomic deposition to deposit and form a metal compound layer on at least a part of the surface of the at least one metal layer, thereby manufacturing the semiconductor test chip, and the material of the metal compound layer includes at least one of a halogen-containing metal compound and an oxygen-containing metal compound.

10. The method for fabricating a semiconductor test chip according to claim 9, wherein: The thickness of the metal compound layer is between 2 nm and 50 nm.

11. The method for manufacturing a semiconductor test chip according to claim 9, wherein: The semiconductor component semi-finished product has a plurality of chips arrayed on the semiconductor substrate. Each chip has a test circuit, and the chips can be electrically connected by the test circuit.

12. The method for fabricating a semiconductor test chip according to claim 11, wherein: Each chip further has a redistribution line located above the test circuit and electrically connected to the test circuit, and a dielectric layer covering the redistribution line and having at least one opening. The electrical connection pads are electrically connected to the redistribution line and are respectively exposed to the outside from the corresponding openings.

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