A FPGA heat dissipation device based on thermoelectric cooling sheet and heat dissipation method thereof

Abstract

The invention discloses an FPGA heat dissipation device based on a thermoelectric cooling sheet and a heat dissipation method thereof, belonging to the technical field of FPGA chip heat dissipation, and solving the problems of heat saturation and high power consumption when the thermoelectric cooling sheet is used for FPGA chip heat dissipation. The invention provides a FPGA chip heat dissipation device based on a thermoelectric cooling sheet and a heat dissipation method thereof, belonging to the technical field of FPGA chip heat dissipation, and solving the problems of heat saturation and high power consumption when the thermoelectric cooling sheet is used for FPGA chip heat dissipation. The invention provides a FPGA chip heat dissipation device based on a thermoelectric cooling sheet and a heat dissipation method thereof, belonging to the technical field of FPGA chip heat dissipation, and solving the problems of heat saturation and high power consumption when the thermoelectric cooling sheet is used for FPGA chip heat dissipation. The invention provides a FPGA chip heat dissipation device based on a thermoelectric cooling sheet and a thermoelectric cooling sheet ...

Description

Technical Field

[0001] The present invention belongs to the technical field of FPGA chip heat dissipation, and relates to an FPGA heat dissipation device based on a thermoelectric cooling sheet and a heat dissipation method thereof, which is suitable for heat dissipation of high heat flux density components on circuit boards with high integration density, large heat generation and compact structure, such as FPGA signal processing boards. Background Art

[0002] With the rise and rapid development of industries such as 5G / 6G communications, lidar, big data centers, artificial intelligence technology, and edge computing, the use value of high-end FPGAs is becoming more and more obvious. FPGAs have the following four main advantages: ① Greater parallelism. FPGAs can enable multiple modules to calculate independently at the same time, can realize different logical functions, and are not limited to executing the same function at the same time, and can enable the same task to be executed at different times at the same time; ② Software-definable. Within the scope of resources allowed, users can define their own logic circuits and functions as needed; ③ Functional reconfiguration. The logic inside the FPGA can be changed as needed, reducing development costs and achieving high input-output ratio. With the development of Moore's Law, the level of integrated circuit technology is moving towards smaller process technology and multi-functional heterogeneous integration. The process technology of FPGA chips is becoming more and more advanced, and the functions are becoming more and more powerful. For example, Xilinx, the leader in FPGA, launched the Virtex-7FPGA based on the 28nm semiconductor process in 2012, integrating hundreds of millions of transistors. The FPGA launched in 2020 is based on the 7nm process, integrating tens of billions of transistors, with more logic resources, interfaces, hard-core IP, DSP resources and higher bandwidth.

[0003] The digital signal processing system is based on FPGA, and is composed of different types of chips such as digital-to-analog / analog-to-digital conversion chips, clocks, drivers, storage, interfaces and power supplies. This system is suitable for many signal processing systems because of its configurable software functions, high flexibility and strong processing capabilities. At the same time, electronic information equipment in the post-Moore era shows a strong characteristic of "integration-integration-reintegration". The demand for high integration, miniaturization and lightweight in various applications is increasing rapidly. The electrical, magnetic, optical, mechanical and thermal coupling of the system is becoming more and more close. The performance degradation caused by the comprehensive factors caused by the high power consumption of the system is increasing. The high power consumption of the system has gradually become the main problem in the field of electronic packaging. For example, the static power consumption of Virtex-7 FPGA after power-on is about 25W. When its resource utilization rate reaches 75%, its power consumption can reach about 50W. Now many users want to maximize the use of FPGA resources, and the power consumption will increase further. Excessive power consumption will significantly increase the chip temperature. Excessive temperature will cause the chip to run slower and unstable, until the chip fails physically.

[0004] At present, the main way to solve the heat dissipation problem is air cooling, which has the characteristics of simple structure, low price, safety and reliability, and mature technology. However, with the rapid development of miniaturization, its heat dissipation capacity has been difficult to match the heat dissipation requirements of today's high heat flux density packaged devices. For example, after the FPGA chip is powered on, when the fan is working, it is sometimes necessary to stop the FPGA. In addition, fan cooling also has limitations such as noise and fan life.

[0005] Liquid cooling has a higher heat dissipation capacity than air cooling, and its physical forms are also more developed. For example, heat pipes are widely used for chassis heat dissipation and large system heat dissipation, and have strong heat dissipation capacity. However, heat pipes will have reduced heat transfer performance after a period of use due to problems such as manufacturing materials, processes, and cleanliness inside the pipe. In addition, for packaging-level and chip-level heat dissipation, heat pipes are relatively large, which is not conducive to the trend of miniaturization and high integration.

[0006] Embedded microfluidic heat dissipation technology based on liquid cooling is an option for efficient heat dissipation at ultra-high heat flux density, and is also suitable for microsystem-level and chip-level heat dissipation. However, there are still many technical bottlenecks in microfluidic heat dissipation technology that need to be resolved: ① The small scale is easily blocked by particles, and there is currently no good solution; ② The system liquid supply device is too large, and the liquid cooling source needs to be miniaturized; ③ The antifreeze has a large flow resistance at low temperatures and is corrosive to metals, so the problems of drag reduction and solution replacement need to be solved; ④ Silicon-based microfluidics have strong heat dissipation capabilities, but are brittle and have poor structural reliability.

[0007] Thermoelectric cooling technology is based on thermoelectric semiconductor solid materials. After the thermoelectric cooling sheet is powered, it can cool the cold end close to the chip, thereby increasing the heat transfer temperature difference, improving the heat flux density of heat dissipation, and achieving stable and effective temperature control in a small area. Thermoelectric components made of thermoelectric materials also have the advantages of no need for transmission parts, no noise, no emissions, stable and reliable, and easy to miniaturize. However, the cooling efficiency of thermoelectric cooling sheets is currently lower than that of traditional air cooling and liquid cooling, and thermoelectric cooling technology is an active scattering technology that requires electrical energy. Therefore, more electrical energy is required while cooling the chip. In addition, the thermal resistance of the thermoelectric cooling sheet itself is very large. After the cooling capacity of the thermoelectric cooling sheet is saturated, it is equivalent to an insulating material and cannot transfer heat to the heat sink. This is also a potential risk when using thermoelectric cooling sheets. Summary of the invention

[0008] The purpose of the present invention is to design an FPGA heat dissipation device based on a thermoelectric cooling sheet and a heat dissipation method thereof to solve the problems of heat saturation and high power consumption when the thermoelectric cooling sheet is used for FPGA chip heat dissipation.

[0009] The present invention solves the above technical problems through the following technical solutions:

[0010] A FPGA heat dissipation device based on a thermoelectric cooling sheet comprises: an FPGA chip (1), a flat heat sink (2), four thermoelectric cooling sheets (3), a heat dissipation fin (4), a driver (6), a transistor Q1, a DC power supply (7), a pull-up resistor R1, and a pull-down resistor R2; the control end of the FPGA chip (1) is connected to the input end of the driver (6), the output end of the driver (6) is connected to the base of the transistor Q1, one end of the pull-up resistor R1 is connected to the DC power supply (7), and the other end is connected to the collector of the transistor Q1; one end of the pull-down resistor R2 is grounded, and the other end is connected to the emitter of the transistor Q1. The positive electrodes of the power input terminals of the four thermoelectric cooling sheets (3) are all connected to the emitter of the transistor Q1, and the negative electrodes of the power input terminals are grounded; the flat heat sink (2) is tightly attached to the FPGA chip (1) through thermal conductive silicone grease, the four thermoelectric cooling sheets (3) are tightly attached to the four corners of the flat heat sink (2) through thermal conductive silicone grease, and the heat sink fins (4) are tightly attached to the upper surfaces of the thermoelectric cooling sheets (3) and the flat heat sink (2) through thermal conductive silicone grease; there are two heat dissipation paths of the device: FPGA chip → flat heat sink → thermoelectric cooling sheet → heat sink fins; FPGA → flat heat sink → heat sink fins;

[0011] When the temperature T of the FPGA chip (1) is lower than the threshold temperature Tc, the control end of the FPGA chip (1) is in a low level state, the transistor Q1 is not enabled, the collector and emitter of the transistor Q1 are not conducting, and the thermoelectric cooling sheet (3) does not work. At this time, heat is dissipated according to the path: FPGA chip → flat heat sink → thermoelectric cooling sheet → heat sink fin;

[0012] When the temperature T of the FPGA chip (1) exceeds the threshold temperature Tc, the control end of the FPGA chip (1) is converted to a high level state, the transistor Q1 is enabled, the transistor Q1 works in the on state, and the thermoelectric cooling plate (3) starts cooling. At this time, according to the path: FPGA chip → flat heat sink → thermoelectric cooling plate → heat sink fin, and the path: FPGA → flat heat sink → heat sink fin, heat is dissipated simultaneously, and the temperature of the FPGA chip (1) is reduced to below the threshold temperature Tc.

[0013] The present invention places a flat heat sink in close contact with an FPGA chip, distributes four thermoelectric cooling sheets at the four corners of the flat heat sink and places them in close contact, the thermoelectric cooling sheet and the power supply are respectively connected to the emitter and collector of the transistor, the FPGA chip control signal is connected to the base of the transistor, and according to the temperature of the FPGA chip, the control port of the FPGA chip generates an enable signal to control the on and off of the transistor, thereby realizing adaptive control of the thermoelectric cooling sheet and working according to two different heat dissipation paths, thereby avoiding the problems of heat saturation and high power consumption of the thermoelectric cooling sheet.

[0014] The FPGA heat dissipation device further comprises: a fan, which is arranged above the heat dissipation fins (4) and is used to dissipate the heat gathered on the heat dissipation fins (4) to the external environment.

[0015] The model of the FPGA chip (1) is Virtex-7 FPGA.

[0016] The model of the driver (6) is SN74AVC4T245 or SM16245.

[0017] A heat dissipation method using the FPGA heat dissipation device includes the following situations:

[0018] When the temperature T of the FPGA chip (1) is lower than the threshold temperature Tc, the control end of the FPGA chip (1) is in a low level state, the transistor Q1 is not enabled, the collector and emitter of the transistor Q1 are not conducting, and the thermoelectric cooling sheet (3) does not work. At this time, heat is dissipated according to the path: FPGA chip → flat heat sink → thermoelectric cooling sheet → heat sink fin;

[0019] When the temperature T of the FPGA chip (1) exceeds the threshold temperature Tc, the control end of the FPGA chip (1) is converted to a high level state, the transistor Q1 is enabled, the transistor Q1 works in the on state, and the thermoelectric cooling plate (3) starts cooling. At this time, according to the path: FPGA chip → flat heat sink → thermoelectric cooling plate → heat sink fin, and the path: FPGA → flat heat sink → heat sink fin, heat is dissipated simultaneously, and the temperature of the FPGA chip (1) is reduced to below the threshold temperature Tc.

[0020] The advantages of the present invention are:

[0021] The present invention places a flat heat sink in close contact with an FPGA chip, distributes four thermoelectric cooling sheets at the four corners of the flat heat sink and places them in close contact, the thermoelectric cooling sheet and the power supply are respectively connected to the emitter and collector of the transistor, the FPGA chip control signal is connected to the base of the transistor, and according to the temperature of the FPGA chip, the control port of the FPGA chip generates an enable signal to control the on and off of the transistor, so as to realize the adaptive control of the thermoelectric cooling sheet, work according to two different heat dissipation paths, and avoid the problems of heat saturation and high power consumption of the thermoelectric cooling sheet. The heat dissipation device of the present invention is simple and low in cost. Compared with the existing refrigeration device, the temperature control is more accurate and flexible, more efficient and lower in power consumption, and the heat dissipation method also presents the characteristics of digitization and intelligence, which can meet the trend of industrial equipment to continuously develop towards digitization, softwareization and intelligence. Therefore, the present invention is of great significance to the application of FPGA chip heat dissipation and FPGA signal processing board. The present invention utilizes the flexibly definable function feature of FPGA to make the thermoelectric cooling chip work more flexibly and adaptively, thereby avoiding excessive power consumption of the cooling itself and deterioration of the device's own performance when used for a long time, thereby improving the heat dissipation efficiency; at the same time, the potential risk of heat saturation is considered in advance, so that the passive heat dissipation path of conductive heat dissipation is always unobstructed, avoiding heat dissipation problems caused by inherent defects of thermoelectric cooling chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of the working principle of the FPGA heat dissipation device according to an embodiment of the present invention;

[0023] Figure 2 A schematic diagram of the heat dissipation structure arrangement on the FPGA chip according to an embodiment of the present invention;

[0024] Figure 3 Schematic diagram of the distribution of thermoelectric cooling sheets on the upper surface of a flat heat sink according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in combination with the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] The technical solution of the present invention is further described below in conjunction with the accompanying drawings and specific embodiments:

[0027] Embodiment 1

[0028] like Figure 1-2As shown, an FPGA heat dissipation device based on a thermoelectric cooling sheet comprises: an FPGA chip 1, a flat heat sink 2, four thermoelectric cooling sheets 3, a heat sink fin 4, a driver 6, a transistor Q1, a DC power supply 7, a pull-up resistor R1, and a pull-down resistor R2; the control end of the FPGA chip 1 is connected to the input end of the driver 6, the output end of the driver 6 is connected to the base of the transistor Q1, one end of the pull-up resistor R1 is connected to the DC power supply 7, and the other end is connected to the collector of the transistor Q1, one end of the pull-down resistor R2 is grounded, and the other end is connected to the emitter of the transistor Q1, and the positive poles of the power input ends of the four thermoelectric cooling sheets 3 are all connected to the emitter of the transistor Q1, and the negative pole of the power input end is grounded.

[0029] like Figure 2 As shown, the flat heat sink 2 is closely attached to the FPGA chip 1 through thermal grease. Figure 3 As shown, the four thermoelectric cooling sheets 3 are respectively attached to the four corners of the flat heat sink 2 through thermal grease, and the heat sink fins 4 are tightly attached to the upper surfaces of the thermoelectric cooling sheets 3 and the flat heat sink 2 through thermal grease.

[0030] The flat heat sink 2 first conducts the heat generated by the FPGA chip 1 to the end away from the FPGA chip 1, and then dissipates the heat on the flat heat sink 2 to the environment through the heat sink fins 4. At the same time, the thermoelectric cooling sheet 3 cools the flat heat sink 2 and the FPGA chip 1 to increase the heat transfer temperature difference. The heat absorbed by the thermoelectric cooling sheet 3 in the process of cooling the flat heat sink 2 and the FPGA chip 1 is dissipated to the environment by the heat sink fins 4; that is, according to different cooling modes, there are two heat dissipation paths:

[0031] ①FPGA chip → flat heat sink → thermoelectric cooling sheet → heat sink fin;

[0032] ②FPGA→flat heat sink→heat sink fins;

[0033] These two different paths transfer heat to the heat sink fins and dissipate the heat to the external environment through forced convection by the fan.

[0034] Since the thermoelectric material used in the thermoelectric cooling sheet 3 is prone to heat accumulation due to excessive thermal resistance, causing damage to the FPGA chip 1, the present embodiment uses the flat heat sink 2 to conduct the heat of the FPGA chip 1, avoiding direct contact between the thermoelectric cooling sheet 3 and the FPGA chip 1, preventing heat saturation, and improving safety. The use of heat dissipation fins 4 can greatly increase the heat dissipation area and more efficiently dissipate the heat of the thermoelectric cooling sheet 3 and the flat heat sink 2.

[0035] The FPGA chip 1 is a system on chip (SOC). The model of the FPGA chip 1 is Virtex-7 FPGA, with a size of 45mm×45mm×5mm, and internally integrates a temperature sensor, a 12-bit high-precision analog-to-digital converter, a logic unit, a storage unit, etc.; the size of a single thermoelectric cooling sheet 3 is 15mm×15mm×2mm;

[0036] The driver 6 is used to match the level output by the IO pin of the FPGA chip 1 with the driving voltage of the transistor Q1, so that the FPGA chip 1 can stably and continuously drive the transistor Q1, while protecting the pin of the FPGA chip 1. The model of the driver 6 can be SN74AVC4T245 or SM16245.

[0037] This embodiment can utilize the flexible definition of FPGA functions, call the XADC IP core of FPGA, and perform simple programming to realize the reading and heat dissipation control of the chip temperature. By comparing the real-time read chip temperature with the preset threshold temperature in programming, the IO port of FPGA generates an enable signal, and the signal control pin of FPGA is connected to the base of the switch transistor, so that the power supply of the thermoelectric cooling sheet is turned on and off according to the programmed program, thereby realizing adaptive intelligent control of the thermoelectric cooling sheet. The power supply of the thermoelectric cooling sheet 3 is directly provided by the existing DC power supply 7 on the printed circuit board where the FPGA chip 1 is located. The power supply voltage range is adjustable, the current size meets the cooling capacity requirements of the thermoelectric cooling sheet 3, and the power supply output ripple performance meets the normal working requirements of the thermoelectric cooling sheet.

[0038] After the temperature sensor integrated inside FPGA chip 1 reads the temperature, the obtained temperature signal is an analog signal, which is converted into a digital signal by the internal high-precision analog-to-digital converter (ADC) and stored in the register. The value of the register in the FPGA is a 16-bit digital code, in which only the upper 12 bits represent the temperature, and the lower 4 bits are invalid. After obtaining the valid temperature value of the upper 12 bits, the value must be converted into Celsius temperature. The conversion formula is:

[0039]

[0040] By creating a project in Vivado software, writing a program, setting the threshold Tc for the cooling plate to start working, setting the real-time monitoring temperature T to compare with the threshold temperature Tc, making the FPGA generate an enable signal, and giving play to the role of software-defined functions, the cooling parameters can be flexibly configured on demand; the details are as follows:

[0041] (1) When the temperature T of the FPGA chip 1 is lower than the threshold temperature Tc, the control end of the FPGA chip 1 is in a low level state, the transistor Q1 is not enabled, the collector and emitter of the transistor Q1 are not conducting, and the thermoelectric cooling sheet 3 does not work. At this time, the heat of the FPGA chip 1 is dissipated along the path: FPGA chip → flat heat sink → thermoelectric cooling sheet → heat sink fin;

[0042] (2) When the temperature T of FPGA chip 1 exceeds the threshold temperature Tc, the control end of FPGA chip 1 is converted to a high level state, transistor Q1 is enabled, transistor Q1 works in the on state, and the thermoelectric cooling sheet 3 starts to cool. At this time, the heat of FPGA chip 1 follows the path: FPGA chip → flat heat sink → thermoelectric cooling sheet → cooling fin and the path: FPGA → flat heat sink → cooling fin, and dissipates heat at the same time, quickly reducing the temperature of FPGA chip 1 to below the threshold temperature Tc.

[0043] The enable signal of the FPGA chip 1 is controlled to meet the requirements of adaptive control. Since the operation of the thermoelectric cooling sheet 3 is intelligently controlled, the power consumption of the thermoelectric cooling sheet is greatly reduced, thereby reducing the heat dissipation pressure of the system. In addition, when the thermoelectric cooling sheet 3 works for a long time, the conversion efficiency of the material itself will gradually deteriorate due to the temperature rise, so that heat gradually accumulates until saturation occurs. The working mode of the present invention avoids the occurrence of such danger and improves the safety of the system.

[0044] The present invention aims to realize adaptive intelligent heat dissipation in a high-density integrated digital signal processing system, significantly improve heat dissipation efficiency, reduce system total power consumption, and enhance system safety and reliability. By placing a flat heat sink in close contact with an FPGA chip, the heat of the chip is transferred; then four thermoelectric cooling sheets are distributed at the four corners of the flat heat sink and placed closely, the thermoelectric cooling sheet and its power supply are respectively connected to the emitter and collector of a transistor, the FPGA end control signal is connected to the base of the transistor, and the functions of the FPGA can be flexibly defined. By calling the XADC IP core inside the FPGA chip, simple programming is performed to realize the reading and heat dissipation control of the chip temperature, and by comparing the real-time read chip temperature with the preset threshold temperature in programming, the IO port of the FPGA generates an enable signal, and the signal control pin of the FPGA is connected to the base of the transistor, so that the power supply of the thermoelectric cooling sheet is turned on and off according to the programmed program, thereby realizing adaptive intelligent control of the thermoelectric cooling sheet.

[0045] The hot end of the thermoelectric cooling plate and the surface of the flat heat sink are closely mounted with heat dissipation fins. The heat will eventually converge to the heat dissipation fins along the two different paths of FPGA chip → flat heat sink → thermoelectric cooling plate → heat dissipation fins and FPGA → flat heat sink → heat dissipation fins, and the heat will be dissipated to the external environment by forced convection. The FPGA chip can directly power the cooling plate, and it only needs to integrate the triode and the driver on the basis of the FPGA signal processing board. The device is simple and easy to integrate; the heat dissipation device of the present invention is more accurate and flexible in temperature control, higher efficiency and lower power consumption compared to the existing refrigeration device, so that the heat dissipation is gradually digitized and intelligent, so as to meet the trend of industrial equipment to develop towards digitization, software and intelligence. Therefore, the present invention is of great significance to the application of FPGA chip heat dissipation and FPGA signal processing board. The method of the present invention is universal, and can achieve high-efficiency heat dissipation in the system architecture integrated with ZYNQ and ARM core, and can realize the controllable adaptive adjustment of chip temperature through computer code, improve the heat dissipation efficiency, and avoid the problems of high power consumption and heat accumulation of thermoelectric cooling plate.

[0046] The allowable shell temperature of FPGA is 100℃. When the resource utilization rate is high, it is difficult for conventional heat sink + air cooling to dissipate heat. At this time, the XADC IP core inside the FPGA is used to monitor and read the real-time temperature. The real-time temperature will be compared with the threshold temperature Tc set when writing the program. If it is greater than or equal to this temperature, the FPGA will generate a high-level signal, which will be converted into the conduction voltage of the switching transistor through the driver, so that the transistor is turned on, and the thermoelectric cooling chip starts to work, quickly cooling and increasing heat dissipation. However, the power consumption of the thermoelectric cooling chip is large, which will cause the power consumption of the entire system to be large for a long time, increasing the heat dissipation pressure of the system; at the same time, the efficiency of the thermoelectric cooling chip itself will decrease due to heat accumulation. When the heat accumulates to saturation, the thermoelectric chip itself is equivalent to an insulating material, which hinders the heat conduction of the chip to the outside. Therefore, after the thermoelectric cooling chip reduces the heat, and if the FPGA is not always working under high load, the heat can be dissipated by means of heat sink + air cooling. Therefore, the cooling chips are distributed at the four corners of the chip, and the other uncovered parts are directly removed by heat sink fins. This can effectively achieve an adaptive mode in which lower heat is derived from the FPGA-flat heat sink-heat sink path, and higher heat is derived from the FPGA-flat heat sink-thermoelectric cooling chip-heat sink and the former combined. It is worth mentioning that the power supply of the FPGA-based signal processing system can directly power the cooling chip. It only needs to integrate the transistor and FPGA output terminal driver on the basis of the FPGA signal processing board. The device is simple and easy to integrate.

[0047] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An FPGA heat dissipation device based on a thermoelectric cooling sheet, characterized in that: include: FPGA chip (1), a flat heat sink (2), four thermoelectric cooling sheets (3), heat sink fins (4), a driver (6), a transistor Q1, a DC power supply (7), a pull-up resistor R1, and a pull-down resistor R2; the control end of the FPGA chip (1) is connected to the input end of the driver (6), the output end of the driver (6) is connected to the base of the transistor Q1, one end of the pull-up resistor R1 is connected to the DC power supply (7), and the other end is connected to the collector of the transistor Q1, one end of the pull-down resistor R2 is grounded, and the other end is connected to the emitter of the transistor Q1, the four thermoelectric cooling sheets (3) are connected to the DC power supply (7), and the other end is connected to the emitter of the transistor Q1. The positive pole of the power input terminal of the sheet (3) is connected to the emitter of the transistor Q1, and the negative pole of the power input terminal is grounded; the flat heat sink (2) is closely attached to the FPGA chip (1) through thermal conductive silicone grease, the four thermoelectric cooling sheets (3) are closely attached to the four corners of the flat heat sink (2) through thermal conductive silicone grease, and the heat dissipation fins (4) are closely attached to the upper surfaces of the thermoelectric cooling sheets (3) and the flat heat sink (2) through thermal conductive silicone grease; there are two heat dissipation paths of the device: FPGA chip → flat heat sink → thermoelectric cooling sheet → heat dissipation fins; FPGA → flat heat sink → heat dissipation fins; When the temperature T of the FPGA chip (1) is lower than the threshold temperature Tc, the control end of the FPGA chip (1) is in a low level state, the transistor Q1 is not enabled, the collector and emitter of the transistor Q1 are not conducting, and the thermoelectric cooling sheet (3) does not work. At this time, heat is dissipated according to the path: FPGA chip → flat heat sink → thermoelectric cooling sheet → heat sink fin; When the temperature T of the FPGA chip (1) exceeds the threshold temperature Tc, the control end of the FPGA chip (1) is converted to a high level state, the transistor Q1 is enabled, the transistor Q1 works in the on state, and the thermoelectric cooling plate (3) starts cooling. At this time, according to the path: FPGA chip → flat heat sink → thermoelectric cooling plate → heat sink fin, and the path: FPGA → flat heat sink → heat sink fin, heat is dissipated simultaneously, and the temperature of the FPGA chip (1) is reduced to below the threshold temperature Tc.

2. The FPGA heat dissipation device according to claim 1, characterized in that: Also includes: A fan is arranged above the heat dissipation fins (4) and is used to dissipate the heat gathered on the heat dissipation fins (4) to the external environment.

3. The FPGA heat dissipation device according to claim 1, characterized in that: The model of the FPGA chip (1) is Virtex-7 FPGA.

4. The FPGA heat dissipation device according to claim 1, characterized in that: The model of the driver (6) is SN74AVC4T245 or SM16245.

5. A heat dissipation method using the FPGA heat dissipation device according to any one of claims 1 to 4, characterized in that: This includes the following situations: When the temperature T of the FPGA chip (1) is lower than the threshold temperature Tc, the control end of the FPGA chip (1) is in a low level state, the transistor Q1 is not enabled, the collector and emitter of the transistor Q1 are not conducting, and the thermoelectric cooling sheet (3) does not work. At this time, heat is dissipated according to the path: FPGA chip → flat heat sink → thermoelectric cooling sheet → heat sink fin; When the temperature T of the FPGA chip (1) exceeds the threshold temperature Tc, the control end of the FPGA chip (1) is converted to a high level state, the transistor Q1 is enabled, the transistor Q1 works in the on state, and the thermoelectric cooling plate (3) starts cooling. At this time, according to the path: FPGA chip → flat heat sink → thermoelectric cooling plate → heat sink fin, and the path: FPGA → flat heat sink → heat sink fin, heat is dissipated simultaneously, and the temperature of the FPGA chip (1) is reduced to below the threshold temperature Tc.

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