Semiconductor device module comprising vertical metal contacts and method of manufacturing the same

Abstract

A semiconductor device module (100) comprises a package carrier (10) comprising an opening (10A), wherein a semiconductor package (20) is arranged in the opening (10A), the semiconductor package comprising a semiconductor die (22), an encapsulant (23) and a first vertical contact (24), wherein the encapsulant (23) at least partially covers the semiconductor die (22), and the first vertical contact (24) is connected to the semiconductor die (22) and at least partially extends through the encapsulant (23), and a first external metal contact layer (40) electrically connected to the first vertical contact (24).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device module comprising an embedded semiconductor die and vertical metal contacts for electrically connecting contact pads of the semiconductor die with an external metal contact layer. BACKGROUND

[0002] In the past years, a lot of activities have been performed regarding embedding of passive components and active semiconductor dies into PCB or package carrier systems. Some low voltage use cases have found their way into production, as embedding offers additional value compared to module or discrete package solutions, such as compactness (power density), short lead lengths leading to much lower parasitic inductances, good thermal management and significantly improved power cycling capability. These advantages are also attractive for power supply applications with high voltages up to 1200 V and especially for fast switching applications > 20 kHz. However, when considering how chip embedding is currently done, some existing blockages have to be solved first, as in the future peak voltages of 1700 V, 2000 V or even higher are to be considered.

[0003] Current chip embedding processes do not meet the requirements for high voltage applications. The breakdown voltage, halogen impurity level and overall reliability of the PCB material currently used for chip embedding are not suitable for 600 V devices. Moreover, the isolation distance between the wiring layers on the chip edge and the module top is limited and typically at maximum 50-100 pm.

[0004] For these and other reasons, the present disclosure is needed. SUMMARY

[0005] A first aspect of the present disclosure relates to a semiconductor device module comprising a package carrier comprising an opening, wherein a semiconductor package is arranged in the opening, the semiconductor package comprising a semiconductor die, a sealing agent and first vertical contacts, wherein the sealing agent at least partially covers the semiconductor die and the first vertical contacts are connected to the semiconductor die and at least partially extend through the sealing agent; and a first external metal contact layer electrically connected to the first vertical contacts.

[0006] A second aspect of the present disclosure relates to a method for manufacturing a semiconductor device module, the method comprising manufacturing a semiconductor die package by providing a semiconductor die, connecting first vertical contacts to the semiconductor die, at least partially covering the semiconductor die with a sealing agent such that the first vertical contacts at least partially extend through the sealing agent; providing a package carrier comprising an opening; placing the semiconductor die package in the opening; and electrically connecting a first external metal contact layer to the first vertical contacts. BRIEF DESCRIPTION OF DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and, together with the description, serve to explain principles of embodiments. Other embodiments and many of the intended advantages of the embodiments will be readily appreciated as they become better understood by reference to the following detailed description, when considered in connection with the accompanying drawings.

[0008] Elements in the figures are not necessarily to scale. Like reference numerals in different figures refer to like parts throughout.

[0009] Figure 1 A schematic cross-sectional side view of an example of a semiconductor device module is shown, which comprises an external metal contact layer only on one of the two main faces of the module, and wherein the die carrier comprises a recess.

[0010] Figure 2 A schematic cross-sectional side view of an example of a semiconductor device module is shown, which comprises an external metal contact layer only on one of the two main faces of the module, and wherein the die carrier does not comprise a recess. In addition to this, the encapsulant is only provided in the central region and does not extend to the sidewalls of the opening of the package carrier, such that the sidewalls of the die carrier are not covered by the encapsulant.

[0011] Figure 3 A schematic cross-sectional side view of an example of a semiconductor device module is shown, which comprises an external metal contact layer on both main faces of the module.

[0012] Figure 4 A flow chart of an exemplary method for manufacturing a semiconductor device module is shown.

[0013] Figures 5A to 5E A schematic cross-sectional side view is shown for illustrating an exemplary method for manufacturing a semiconductor device module as shown in Figure 1 wherein Figure 5D An enlarged portion of the schematic cross-sectional side view shows a cross-sectional view of a via drilled in the uppermost seed layer and the lamination layer.

[0014] Figures 6A to 6C A schematic cross-sectional side view is shown for illustrating an exemplary method for manufacturing a semiconductor device module as shown in Figure 3

[0015] Figures 7A to 7D A schematic cross-sectional side view is shown for illustrating different methods of drilling a hole in the lamination layer or the encapsulant, such as mechanical drilling within the lamination layer (A), mechanical drilling through the lamination layer and into the package layer (B), creating a large area opening by plasma etching or water blasting (C), and drilling by laser drilling (D). ​DETAILED DESCRIPTION

[0016] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration specific embodiments in which the disclosure can be practiced. In this regard, directional terminology, such as "top," "bottom," "front," "back," "leading," "trailing," etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims.

[0017] It is to be understood that the features of the various example embodiments described herein can be combined with each other, unless specifically stated otherwise.

[0018] As employed in this specification, the terms "joined," "attached," "connected," "coupled," and / or "electrically connected / electrically coupled" do not necessarily mean that elements or layers must directly contact one another; an intervening element or layer can be provided between the elements that are "joined," "attached," "connected," "coupled," and / or "electrically connected / electrically coupled," respectively. However, according to the present disclosure, the aforementioned terms can optionally also have the specific meaning that the elements or layers are in direct contact with one another, i.e., no intervening element or layer is provided between the elements that are "joined," "attached," "connected," "coupled," and / or "electrically connected / electrically coupled," respectively.

[0019] Further, the word "over" as used herein in relation to a component, element, or material layer formed "over" or "on" a surface means that the component, element, or material layer is "indirectly over" (e.g., placed, formed, deposited, etc.) the implied surface with one or more additional components, elements, or layers arranged between the implied surface and the component, element, or material layer. However, the word "over" as used herein in relation to a component, element, or material layer formed "over" or "on" a surface optionally also has the specific meaning of the component, element, or material layer being "directly over" (e.g., placed, formed, deposited, etc.) the implied surface, e.g., in direct contact with the implied surface.

[0020] DETAILED DESCRIPTION

[0021] Figure 1 A schematic cross-sectional side view of an exemplary semiconductor device module is shown.

[0022] More specifically, Figure 1A semiconductor device module 100 is shown, which comprises a package carrier 10 essentially consisting of a polymer layer, in particular an FR4 layer, which has an opening or recess 10A. In the opening 10A, a die carrier 21 is arranged, wherein the die carrier 21 comprises a recessed area 21A in which a semiconductor die 22 is disposed, such that the sidewalls of the semiconductor die 22 are spaced apart from the inner sidewalls of the recessed area 21A. The die carrier 21 and the semiconductor die 22 are partially embedded by a sealant 23, such that the upper main face and the sidewalls of the die carrier 21 are covered by the sealant 23 and the recessed area 21A is also filled by the sealant 23, such that the intermediate space between the sidewalls of the semiconductor die 22 and the inner walls of the recessed area 21A is filled by the sealant 23. The die carrier 21, the semiconductor die 22 and the sealant form a semiconductor die package 20. In the manufacturing process of the semiconductor device module, the semiconductor die package 20 can first be formed and then placed into the opening portion 10A of the package carrier 10. The manufacturing process of the semiconductor die package 20 will be described in more detail later.

[0023] The package carrier 10 shall generally be adapted to accommodate and support the semiconductor die package 20 in the opening 10A of the package carrier 10. In particular, the package carrier 10 can be one or more of an insulation layer, a laminate layer, an FR4 layer, a ceramic layer, a glass layer, a metal layer, in particular a Cu or Al layer, a printed circuit board, or any combination of these layers.

[0024] The semiconductor die 22 comprises a first upper main face and a second lower main face opposite to the first surface, on the first upper main face a first contact pad 22A is disposed, on the second lower main face a second contact pad 22B is disposed. A third contact pad 22C is disposed on the first main face. The semiconductor die 22 is attached with its second contact pad 22B to the bottom of the recessed area 21A of the die carrier 21. The first, second and third contact pads 22A to 22C can be source, drain and gate contact pads of an IGBT semiconductor die 22.

[0025] More generally, the semiconductor die 22 can be one or more of a vertical transistor die, a MOSFET die, an IGBT die, a SiC-MOS die, a Cool-MOS die or a S-FET die. Furthermore, the semiconductor die 22 can be made of Si or of a wide bandgap semiconductor material such as SiC or GaN.

[0026] The semiconductor device module 100 further comprises a polymer layer 30 which can substantially completely cover the package carrier 10, meaning that the polymer layer 30 comprises a first horizontal upper layer 30A, a second horizontal lower layer 30B and left and right vertical layers 30C between the first and second layers 30A, 30B which can have the form of a continuous ring around the open area 10A of the package carrier 10. The polymer layer 30 can be formed by lamination, which will be explained later.

[0027] The electrical connections to the contact pads will be described in more detail below, while the manufacturing of these electrical connections will be described in more detail later.

[0028] One essential feature of the present disclosure is the use of metal contacts as part of the electrical connections. In particular, the semiconductor die package 20 comprises a first plurality of vertical contacts 24 connected to the source pads 22A. The vertical contacts 24 can have an elongated linear shape and extend in vertical direction through the encapsulant 23. They extend at least to the upper main face of the encapsulant 23, or they can also extend beyond the upper main face of the encapsulant 23. The first vertical contacts 24 can be made of Cu and they can be attached to the source pads 22A by stud bumping. The source pads 22A can also be divided into a plurality of small sub-pads (not shown in the figures) and each of the sub-pads can be connected with one or more of the first vertical contacts 24.

[0029] Furthermore, the semiconductor die package 20 can comprise a second plurality of vertical contacts 25 which are connected to the upper surface of the die carrier 21 so that they are electrically connected with the drain pads 22B. As Figure 1 shown, the vertical contacts 25 can be attached on opposite sides of the upper surface of the die carrier 21 across the open area 10A of the package carrier 10.

[0030] Furthermore, the semiconductor die package 20 can comprise a third single vertical contact 26 connected to the gate pad 22C of the semiconductor die 22. Even more contact pads and corresponding vertical contacts can be provided to implement sensing functions for similar temperature or current sensing functions or even other functions.

[0031] With regard to the dimensions of the vertical contacts 24, 25, 26, the length of the vertical contacts 24, 25, 26 is in the range of 30 pm to 1 mm, more specifically in the range of 50 pm to 500 pm, more specifically in the range of 100 pm to 300 pm. The thickness or lateral diameter of the vertical contacts 24, 25 and 26 is in the range of 20 pm to 150 pm, more specifically in the range of 50 pm to 100 pm.

[0032] To further electrically connect the vertical contacts 24, 25 and 26, via connections 30A.1 are formed in the first upper polymer layer 30A by first forming a via 30A_1 and then filling the via with a metallic material. The via connections 30A.1 are formed in the first polymer layer 30A such that they extend to the vertical contacts 24, 25 and 26. Different methods for forming vias will be given later. As Figure 1 As can be seen in Fig. 1, it is not necessary to form a via connection 30A.1 to any of the vertical contacts 24 and 25, so some of the vertical contacts 24 and 25 can be left unconnected.

[0033] The via connections 30A.1 can be filled with a metal, such as Cu, by electroplating, and then the external metal contact layers 40, 41, 42 can be applied to the via connections 30A.1. As Figure 1 As can be seen in Fig. 1, the first external metal area 40 can be electrically connected with the source pad 22A, the second external metal area 41 can be electrically connected with the drain pad 22B, and the third external metal contact layer 42 can be electrically connected with the gate pad 22C.

[0034] As Figure 1 As can be seen in Fig. 1, the external metal contact layers 40, 41 and 42 are only provided on one of the main faces of the semiconductor device module 100. The second plurality of vertical contacts 25 can be connected with two different external metal contact layers 41.

[0035] One specific advantage of the present disclosure is that it allows to reduce the parasitic inductance of the electrical connections to the range of 1 nH to 10 nH, more specifically to the range of 1 nH to 5 nH, more specifically to the range of 1 nH to 2 nH.

[0036] One further advantage of the present disclosure relates to the manufacturing process which will be described later. Specifically, the manufacturing process comprises independently pre-manufacturing one or more semiconductor die packages and then placing the pre-manufactured semiconductor die packages into one or more openings of a package carrier. This has several advantages, including the possibility to test the functionality of the one or more semiconductor die packages and to place them into the openings of the package carrier only after a positive test. This is especially important for high voltage semiconductor transistor devices. Furthermore, when pre-fabricating the semiconductor die packages, they can be constructed in an optimal way with respect to the interaction between the encapsulant and the semiconductor die, the adhesion between the encapsulant and the semiconductor die and the optimal electrical isolation with respect to high voltages.

[0037] Another advantage of the present disclosure is that it allows for a very small manufacturing area of the gate pad 22C. Due to the stud-bonding process and depending on the length of the vertical contacts 24, 25 and 26 as described above, the gate pad area can be reduced to the range of 300 pm x 300 pm to 400 pm x 400 pm. In case the contact diameter is 30 pm, even a gate area in the range of 50 pm x 50 pm to 100 pm x 100 pm should be possible. The same applies to the area of additional pads, e.g. temperature or current sense pads.

[0038] In Figure 1 In the example shown, the carrier 21 consists of a metal block similar to a part of a leadframe and the carrier comprises a recessed area. The carrier can also not comprise a recessed area and the semiconductor die will be placed on a planar upper surface of the carrier. Further, the carrier can also comprise a Direct Copper Bonding (DCB), Active Metal Brazing (AMB) or Isolated Metal Substrate (IMS) or even other carrier systems, e.g. leadframe or laminate based carrier systems.

[0039] The encapsulant 23 can consist of a conventional molding compound, e.g. a resin material, in particular an epoxy resin material. Further, the encapsulant 23 can be applied in different aggregated states, e.g. in liquid form, in small balls or in pellets. Further, the encapsulant 23 can be made of a thermally conductive material to allow for an efficient heat dissipation to an external metal heat sink. The material of the encapsulant 23 can in particular comprise a resin, like an epoxy resin material, filled with thermally conductive particles, e.g. made of AI2O3, BN, AIN, Si3N4, diamond or any other thermally conductive particles. The encapsulant 23 can also be made of a platable molding compound.

[0040] It should also be noted that the semiconductor die package 20 can be manufactured such that the lateral dimensions of the die carrier 21 correspond to or are only slightly smaller than the lateral dimensions of the opening 10A such that the sidewalls of the die carrier 21 are in direct contact with the sidewalls of the opening 10A. This will be explained in more detail below with respect to Figure 2 a specific example thereof is shown and described.

[0041] The present disclosure also relates to a system module, wherein two or more semiconductor device modules are integrated in a package carrier such as Figure 1 a B6 half-bridge, an H-bridge, an anti-parallel free-wheeling diode and / or one or more of a parallel connection between any switching components, an SR topology, a buck-boost converter, a DC / DC converter or an AC switch.

[0042] Furthermore, other electrical or electronic devices can be integrated with the semiconductor device module, such as gate drivers, controllers, sensors, connection devices (Bluetooth or WiFi devices), passive devices, etc. Such devices can be embedded in the package carrier in the same way as the semiconductor die, or they can be placed on the outer surface of the package carrier.

[0043] Figure 2 A schematic cross-sectional side view of an example of a semiconductor device module is shown, in which the Figure 1 In contrast, the die carrier does not comprise a recess. In addition to this, the sidewalls of the die carrier are not covered by the sealing agent, and the sealing agent is only provided in the central region without extending to the sidewalls of the opening of the package carrier.

[0044] More specifically, Figure 2 A semiconductor device module 200 similar to the semiconductor device module 100 of Figure 1 is shown, thereby employing most of the reference numerals of the semiconductor device module 100 of Figure 1 The semiconductor device module 200 of Figure 2 comprises a semiconductor die package 20. In contrast to Figure 1 the semiconductor die package 20 comprises a die carrier 21, which does not comprise a recessed region such as the recessed region 21A of the die carrier 21 shown in Figure 1 Instead, the semiconductor die package 20 is configured such that the semiconductor die 22 is placed on the planar upper main surface of the die carrier 21. Therefore, the second plurality of vertical metal contacts 25 has to be formed much longer than those shown in Figure 1

[0045] As previously described in connection with Figure 1 in the example of Figure 2 the semiconductor die package 20 can also be manufactured such that the lateral dimension of the die carrier 21 corresponds to or is only slightly smaller than the lateral dimension of the opening 10A, such that the sidewalls of the die carrier 21 are in direct contact with the sidewalls of the opening 10A. In contrast to Figure 1 Another modification in contrast to

[0046] It should be added that further embodiments can be formed by modifying the embodiment of Figure 1 in only one aspect, such as omitting the recess 21A only and retaining the lateral extension of the sealing agent 23, or retaining the recess 21A and modifying the lateral extension of the sealing agent 23.

[0047] Figure 3 A further example of a semiconductor device module is shown. ​

[0048] More specifically, according to Figure 3 the structure of the semiconductor device module 300 is similar to Figure 1 the structure of the semiconductor device module 100. The semiconductor device module 300 is shown in an inverted manner compared to Figure 1 and 2 and comprises: a package carrier 110 comprising an opening or recess 110A; a semiconductor die package 120 comprising a die carrier 121, a semiconductor die 122, a first plurality of vertical contacts 124, a second plurality of vertical contacts 125, a single vertical contact 126, and a sealing agent 123; and a lamination layer 130; and first, second, third, fourth, and fifth external electrical contact layers 140, 141, 142, 143, 144. The properties of these elements are similar to the properties of the semiconductor device module 100 of Figure 1 and will not be repeated here.

[0049] A further difference compared to the semiconductor device module 100 of Figure 1 is that the lamination layer 130 is only applied on one of the main surfaces of the package carrier 110, namely on the upper main surface in Figure 3 and thus comprises only one first horizontal upper layer 130A and left and right vertical layers 130C which can have the form of continuous rings around the opening area 110A of the package carrier 110.

[0050] A further difference compared to the semiconductor device module 100 of Figure 1 concerns the electrical connection of the drain pads 122B. Similar to Figure 1 , the drain pads 122B are connected with the die carrier 121 and the die carrier 121 is connected with the second plurality of vertical contacts 125 which are connected with the second external metal area 141. However, in addition to the way the drain pads 122B are connected, the backside of the die carrier 121 is also connected with a metal layer 145 and this metal layer 145 is then connected with both external metal contact layers 143 and 144. This semiconductor device module 300 presents a greater flexibility in connecting it to external electronic devices.

[0051] It should be added that the semiconductor device module 300 can also be constructed such that the semiconductor die package 120 comprises a die carrier 121 which does not comprise a recessed area but the semiconductor die 122 is placed on the planar upper main surface of the die carrier 121. As mentioned in connection with Figure 2 , the second plurality of vertical metal contacts 25 has to be formed much longer than those shown in Figure 3 as they have to reach from the main lower surface of the sealing agent 123 up to the lower main face of the die carrier 121.

[0052] Figure 4 A flow chart illustrating an exemplary method for manufacturing a semiconductor device module is shown.

[0053] The method 400 for manufacturing a semiconductor device module comprises 310 manufacturing a semiconductor die package by providing a semiconductor die, connecting a first vertical contact to the semiconductor die, embedding the semiconductor die at least partially by a sealing agent such that the vertical contact extends at least partially through the sealing agent; providing 320 a package carrier comprising an opening; placing 330 the semiconductor die package in the opening; and 340 electrically connecting a first external metal contact layer to the first plurality of vertical contacts.

[0054] According to Figure 4 An example of the method 400, connecting a vertical contact to a contact pad of the semiconductor die comprises a stud bumping.

[0055] According to Figure 4 An example of the method 400, manufacturing a semiconductor die package further comprises providing a die carrier and disposing the semiconductor die on the die carrier.

[0056] According to Figure 4 An example of the method 400, embedding the semiconductor die by a sealing agent comprises compression molding or transfer molding. According to Figure 4 Another example of the method 300, embedding the semiconductor die by a sealing agent comprises film assisted molding. In this way, the molding can be performed such that the vertical contact extends up to the upper surface of the sealing agent and is exposed to the outside. As an alternative, also a normal molding without film assistance can be performed and then the sealing agent is removed from above until the vertical contact is reached. The removal of the sealing agent can be performed by any kind of trimming process, e.g. laser ablation, etching, water jet blasting, etc.

[0057] Further embodiments of the method 400 can be formed by adding the aspects or features described above in connection with the semiconductor device module according to the first aspect.

[0058] Figures 5A to 5E A schematic cross-sectional side view is shown for illustrating an exemplary method for manufacturing a semiconductor device module as shown in Figure 1

[0059] Figure 5A ​A metal die carrier 21, which can be made of Cu or a Cu alloy, is shown. The die carrier 21 can have a quadratic ground shape and can have a recessed area 21A, which can be formed within an upper main face of the die carrier 21 and which has an equal distance to the side edges of the die carrier 21. A semiconductor die 22, in particular an IGBT die, comprises an emitter contact pad 22A, a collector contact pad 22B and a gate contact pad 22C and the semiconductor die 22 is inserted into the recessed area 21A by connecting the recessed area 21A with the collector contact pad 22B of the semiconductor die 22 to the bottom face of the recessed area 21A. Then, a first plurality of vertical contacts 25 is connected to the emitter contact pad 22A, a second plurality of vertical contacts is connected to the upper surface of the die carrier 21 and a single vertical contact 26 is connected to the gate contact pad 22C. The vertical contacts 24, 25 and 26 can be connected to the respective contact pads by stud bumping.

[0060] Figure 5B A finished semiconductor die package 20 is shown after applying an encapsulant onto the die carrier 21 and the semiconductor die 22 in such a way that the lower main surface of the die carrier 21 is not covered by the encapsulant 23. The applying of the encapsulant 23 can be done, for example, by liquid compression molding. The molding process can be performed in such a way that the vertical contacts 24, 25 and 26 are exposed to the outside. This can be achieved by performing film assisted molding or by ordinary molding and / or subsequently removing the encapsulant from above by any kind of trimming as described before until the upper tops of the vertical contacts are reached. However, it is also possible to apply the encapsulant 23 in such a way that the vertical contacts 24, 25 and 26 are not exposed to the outside.

[0061] Figure 5C An intermediate product is shown after placing the semiconductor die package 20 into the opening 10A of the package carrier 10 and, thereafter, applying the lamination layer 30 onto the package carrier 10, thereby creating the lamination layers 30A, 30B and 30C as described above. The vertical lamination layer 30C is created by the lamination material flowing into the intermediate space between the side walls of the semiconductor die package 20 and the inner side walls of the opening area 10A of the package carrier 10. Furthermore, a metal seed layer 35 is deposited onto the lamination layers 30A and 30B by, for example, sputtering. It is also possible to provide the seed layer 35 on the lamination layer 30 before applying the lamination layer 30 onto the package carrier 10.

[0062] Figure 5D An intermediate product is shown after forming a via 30A_1 in the upper lamination layer 30A and the covering seed layer 35. Forming the via 30A_1 can be done by mechanical drilling, laser drilling or plasma etching. In Figure 5DOn the right-hand side, a partial enlarged view shows a cross-section through one of the through-holes 30A_1. The through-holes 30A_1 are formed such that they reach the upper tops of the vertical contacts 24, 25 and 26. They can have a depth in the range from 50 pm to 500 pm, in particular in the range from 100 pm to 300 pm, and a width in the range from 50 pm to 500 pm, with 80 pm to 150 pm being most likely in the case of a layer thickness of 50 mm to 500 pm. The dimensions of the through-holes 30A_1 can be approximately the same as the thickness of the insulating layer. It can also be seen that the through-holes 30A_1 are not formed above each of the contacts 24 and 25. The through-holes 30A_1 can have a larger diameter than the vertical contacts 24, 25 and 26.

[0063] Figure 5E A semiconductor device module after formation of the external metal contact layers is shown. Before this can be done, a seed layer has to be deposited into the through-holes 30A_1 by sputtering or electroless plating. The through-holes 30A_1 are filled by electroplating a metal material, in particular Cu or a Cu alloy, and thereby form the electrical through-connections 30A.1. Thereafter, a further electroplating of Cu or a Cu alloy is performed to create a first external metal contact layer 40 connected with the first plurality of vertical contacts 24, a second external metal area 41 connected with the second plurality of vertical contacts 25, and a third external metal contact layer 42 connected with the single vertical contact 26.

[0064] Figures 6A to 6C A schematic cross-sectional side view is shown for illustrating the manufacturing Figure 3 of the semiconductor device module shown.

[0065] Figure 6A A situation is shown immediately before placing the semiconductor die package 120 into the open area 110A of the package carrier 110. Before this, an adhesive foil 160 is attached to the lower surface of the package carrier 110. The semiconductor die package 120 comprises a die carrier 121, a semiconductor die 122, an encapsulant 123, a first plurality of vertical contacts 124, a second plurality of vertical contacts 125, and a single vertical contact 126. In conjunction with Figure 3 The structure of the semiconductor die package 120 is described in more detail.

[0066] After placing the semiconductor die package 120 into the open area 110A of the package carrier 110, a polymer layer 130 is laminated onto the upper surface of the package carrier 110 such that the polymer material also flows into the intermediate space between the side of the semiconductor die package 120 and the inner wall of the open area 110A of the package carrier 110.

[0067] Figure 6BAn intermediate product is shown after removal of portions of the lamination layer 130A that cover most of the area of the back surface of the die carrier 121. Removal of portions of the polymer layer 130A can be performed by mechanical drilling or etching.

[0068] Figure 6C A semiconductor device module is shown after formation of the external metal contact layers. Prior to this can be done, a seed layer has to be deposited onto the area. Thereafter, electroplating of copper or a copper alloy is performed to create a first external metal contact layer 140 connected with the first plurality of vertical contacts 124, a second external metal contact layer 141 connected with the second plurality of vertical contacts 125, a third external metal contact layer 142 connected with the single vertical contact 26, and a fourth external metal contact layer 143 connected with the back surface of the die carrier 121. Finally, an insulating layer 170 is deposited on the central portion of the fourth external metal contact layer 143. It should be added that either of the second external metal layer 141 or the fourth external metal layer 143 can be present. Thus, also any of these can be omitted.

[0069] Figures 7A to 7D A schematic cross-sectional side view is shown to illustrate different methods of drilling into a lamination polymer layer.

[0070] Figure 7A And 7B An example of mechanical drilling is shown.

[0071] According to Figure 7A the example, the vertical contacts extend beyond the upper surface of the encapsulant, so that the hole 230A_1 has to be drilled into the overlying seed layer and only into the polymer layer 230 until the top end of the vertical contact is reached.

[0072] According to Figure 7B the example, the vertical contacts extend exactly to the upper surface of the encapsulant 323, so that the hole 330A_1 has to be drilled into the polymer layer 330 and partially into the encapsulant 323 to ensure reliable electrical connection of the subsequently plated metal with the vertical contacts.

[0073] Figure 7C And 7D An example of another drilling method is shown.

[0074] According to Figure 7C the example, the vertical contacts extend exactly to the upper surface of the encapsulant 423. In this example, a large area opening 430A_1 is created in the polymer layer 430, which extends over the entire area above the plurality of vertical contacts. The opening 430A_1 can be formed by plasma etching or water blasting.

[0075] According to Figure 7DIn the example of FIG. 5A, the vertical contacts extend precisely to the upper surface of the encapsulant. Prior to lamination of the polymer layer 530, a seed layer is formed on the upper surface of the encapsulant 523 such that the seed layer is connected with the plurality of vertical contacts. Thereafter, the polymer layer 530 is laminated, followed by deposition of another seed layer on the upper surface of the polymer layer 530. Thereafter, holes 530A_1 are formed in the polymer layer 530 by laser drilling.

[0076] Example

[0077] The present disclosure is described in the following detailed examples.

[0078] Example 1 is a semiconductor device module comprising: a package carrier comprising an opening, wherein a semiconductor package is disposed in the opening, the semiconductor package comprising a semiconductor die, an encapsulant, and a first vertical contact, wherein the encapsulant at least partially covers the semiconductor die and the first vertical contact is connected to the semiconductor die; and a first external metal contact layer electrically connected to the first vertical contact.

[0079] Example 2 is the semiconductor device module of Example 1, wherein the vertical contact at least partially extends through the encapsulant.

[0080] Example 3 is the semiconductor device module of Example 1 or 2, further comprising a die carrier disposed in the opening of the package carrier, the semiconductor die being disposed on the die carrier.

[0081] Example 4 is the semiconductor device module of any of the preceding examples, wherein the semiconductor die comprises a first major face and a second major face opposite the first major face, the first contact pad being disposed on the first major face, the semiconductor die further comprising a second contact pad on the second major face.

[0082] Example 5 is the semiconductor device module of any of the preceding examples, wherein the semiconductor die is a power semiconductor transistor die.

[0083] Example 6 is the semiconductor device module of any of the preceding examples, wherein the vertical contact is in the form of a vertical pin or a vertical wire.

[0084] Example 7 is the semiconductor device module of any of Examples 4 to 6, further comprising a second vertical contact connected with the second contact pad and extending through the encapsulant.

[0085] Example 8 is the semiconductor device module of Example 7, further comprising a second external metal contact layer electrically connected to the second vertical contact.

[0086] Example 9 is the semiconductor device module of any one of examples 4-8, wherein the semiconductor die is a semiconductor transistor die, and the first contact pad is a source contact pad, and the second contact pad is a drain contact pad.

[0087] Example 10 is the semiconductor device module of any one of examples 4-9, the semiconductor die further comprising a third contact pad disposed on the first major face, the third contact pad being a gate contact pad of the semiconductor transistor die.

[0088] Example 11 is the semiconductor device module of example 10, further comprising a single vertical contact connected to the third contact pad and extending through the encapsulant.

[0089] Example 12 is the semiconductor device module of example 11, further comprising a third external metal contact layer electrically connected to the single vertical contact.

[0090] Example 13 is the semiconductor device module of example 11 or 12, wherein the first and second vertical contacts and the single vertical contact have a length in a range of 30 pm to 1 mm.

[0091] Example 14 is the semiconductor device module of any one of examples 11-13, wherein the vertical contacts and the single vertical contact have a diameter in a range of 20 pm to 150 pm.

[0092] Example 15 is the semiconductor device module of any one of the preceding examples, further comprising a lamination layer at least partially covering the package carrier and the semiconductor die package.

[0093] Example 16 is the semiconductor device module of example 15, wherein the lamination layer comprises a via connection connected between the first external metal layer and the first vertical contact, wherein the via connection has a larger lateral dimension than the first vertical contact.

[0094] Example 17 is a method for manufacturing a semiconductor device module, the method comprising manufacturing a semiconductor die package by providing a semiconductor die, connecting a first vertical contact to a contact pad, at least partially covering the semiconductor die with an encapsulant; providing a package carrier comprising an opening; placing the semiconductor die package in the opening; and electrically connecting a first external metal contact layer to the first vertical contact.

[0095] Example 18 is the method of example 17, wherein the vertical contact at least partially extends through the encapsulant.

[0096] Example 19 is the method of example 17 or 18, wherein connecting the vertical contact comprises stud bumping.

[0097] Example 20 is the method of any one of Examples 17-19, wherein fabricating the semiconductor die package further comprises providing a die carrier and disposing the semiconductor die on the die carrier.

[0098] Example 21 is the method of any one of Examples 15-17, wherein embedding the semiconductor die with the encapsulant comprises one or more of transfer molding, compression molding, or film assisted molding.

[0099] In addition, although a particular feature or aspect of an embodiment of the disclosure can have been disclosed with respect to only one of several implementations, such feature or aspect can be combined with one or more other features or aspects of the other implementations as can be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms "including", "includes", "having", "has", "earns", "containing", "contains" or variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprising". Moreover, unless specifically stated to the contrary, it is intended that the embodiments of the disclosure can be implemented in either hardware or software, or a combination of both hardware and software. Further, the term "exemplary" is used herein merely for the purpose of illustration and is not intended to imply that any feature, or aspect, or embodiment is superior or better than any other. Also, it is to be understood that the features and / or elements of the present disclosure can be implemented in various discrete components or in combination with other components in a partially integrated circuit or in a fully integrated circuit.

[0100] Although specific embodiments have been illustrated and described herein, it will be appreciated that various alterations and / or modifications can be made to the illustrated and described specific embodiments without departing from the scope of the present disclosure. The application is intended to cover any alternatives, modifications, or equivalents of the specific embodiments discussed herein. Thus, the present disclosure is intended to be limited only by the claims and their equivalents.

Claims

1. A semiconductor device module (100), comprising: - a package carrier (10) comprising an opening (10A), wherein a semiconductor die package (20) is arranged in the opening (10A), the semiconductor die package (20) comprising: a semiconductor die (22) comprising a first contact pad (22A), a second contact pad (22B) and a third contact pad (22C), a sealing agent (23), a plurality of first vertical contacts (24), a plurality of second vertical contacts (25), and a single vertical contact (26), wherein the sealing agent (23) at least partially covers the semiconductor die (22), and the plurality of first vertical contacts (24), the plurality of second vertical contacts (25) and the single vertical contact (26) are connected to the first contact pad (22A), the second contact pad (22B) and the third contact pad (22C) of the semiconductor die (22), respectively, by a stud bumping; and - a first external metal contact layer (40) electrically connected to the plurality of first vertical contacts (24), wherein the plurality of first vertical contacts (24), the plurality of second vertical contacts (25) and the single vertical contact (26) are in the form of vertical pins or vertical wires, the vertical pins or vertical wires comprising a diameter in the range of 20 pm to 150 pm, and a length of the plurality of first vertical contacts (24), the plurality of second vertical contacts (25) and the single vertical contact (26) is in the range of 30 pm to 1 mm.

2. The semiconductor device module (100) according to claim 1, wherein the plurality of first vertical contacts (24) at least partially extend through the sealing agent (23).

3. The semiconductor device module (100) according to claim 1, further comprising: - a die carrier (21) arranged in the opening (10A) of the package carrier (10), the semiconductor die (22) being arranged on the die carrier (21).

4. The semiconductor device module (100) according to claim 1, wherein the semiconductor die (22) comprises a first main face and a second main face opposite to the first main face, the first contact pad (22A) being arranged on the first main face and the second contact pad (22B) being arranged on the second main face.

5. The semiconductor device module (100) according to claim 3, wherein the plurality of second vertical contacts (25) are attached on opposite sides of an upper surface of the die carrier (21) across the opening (10A) of the package carrier (10).

6. The semiconductor device module (100) according to claim 1, wherein the plurality of second vertical contacts (25) extend through the sealing agent (23).

7. The semiconductor device module (100) according to claim 1, further comprising: - a second external metal contact layer (41) electrically connected to the plurality of second vertical contacts (25).

8. The semiconductor device module (100) according to any one of claims 1-7, wherein The semiconductor die (22) is a semiconductor transistor die, and the first contact pad (22A) is a source contact pad, and the second contact pad (22B) is a drain contact pad.

9. The semiconductor device module (100) according to claim 4, wherein The third contact pad (22C) is provided on the first main face, and the third contact pad (22C) is a gate contact pad of the semiconductor transistor die (22).

10. The semiconductor device module (100) according to any one of claims 1-7, and 9, wherein The single vertical contact (26) extends through the encapsulant (23).

11. The semiconductor device module (100) according to any one of claims 1-7, and 9, further comprising: - a third external metal contact layer (42) electrically connected to the single vertical contact (26).

12. The semiconductor device module (100) according to any one of claims 1-7, and 9, wherein The first contact pad (22A) is a source pad or an emitter pad.

13. The semiconductor device module (100) according to claim 12, wherein The source pad is divided into a plurality of sub-pads, and each of the plurality of sub-pads of the source pad is connected with one or more of the plurality of first vertical contacts (24).

14. The semiconductor device module (100) according to any one of claims 1-7, 9, and 13, further comprising: a lamination layer (30) at least partially covering the package carrier (10) and the semiconductor die package (20).

15. The semiconductor device module (100) according to claim 14, wherein The lamination layer (30) comprises via connections (30A.1) between the first external metal layer (40) and the first vertical contacts (24), wherein the via connections (30A.1) have a larger lateral dimension than the first vertical contacts (24).

16. A method (400) for manufacturing a semiconductor device module, the method comprising: - manufacturing a semiconductor die package (310) by providing a semiconductor die comprising a first contact pad, a second contact pad, and a third contact pad, connecting a plurality of first vertical contacts (24), a plurality of second vertical contacts (25), and a single vertical contact (26) to the first contact pad (22A), the second contact pad (22B), and the third contact pad (22C) of the semiconductor die (22), respectively, by stud-bonding, and at least partially covering the semiconductor die with an encapsulant; - providing a package carrier comprising an opening (320); - placing the semiconductor die package in the opening (330); and - electrically connecting a first external metal contact layer to the plurality of first vertical contacts (340), wherein the plurality of first vertical contacts (24), the plurality of second vertical contacts (25), and the single vertical contact (26) are in the form of vertical pins or vertical wires comprising a diameter in the range of 20 pm to 150 pm, and The length of the plurality of first vertical contacts (24), the plurality of second vertical contacts (25), and the single vertical contact (26) is in a range of 30 pm to 1 mm.

17. The method of claim 16, wherein, The plurality of first vertical contacts extend at least partially through the encapsulant.

18. The method of claim 16, wherein, The first contact pad (22A) is a source pad or an emitter pad.

19. The method of claim 18, wherein, The source pad is divided into a plurality of sub-pads, and each of the plurality of sub-pads of the source pad is connected with one or more of the plurality of first vertical contacts (24).

20. The method of any one of claims 16 to 19, wherein, Fabricating the semiconductor die package further comprises providing a die carrier and disposing the semiconductor die on the die carrier.

21. The method of any one of claims 16 to 19, wherein, At least partially covering the semiconductor die with the encapsulant comprises one or more of transfer molding, compression molding, or film assisted molding.

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