Manufacturing methods and structures for improving gate coupling ratio in NORD flash
By forming a structure in NORD flash that encloses the outer wall of the floating gate with the control gate, the problem of low gate coupling ratio is solved, device performance is improved and the flash memory cell area is reduced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUA HONG SEMICON WUXI LTD
- Filing Date
- 2021-12-16
- Publication Date
- 2026-06-02
AI Technical Summary
In the existing technology, the gate coupling of NORD flash is relatively low, and it is difficult to effectively improve it by increasing the overlap area between the floating gate and the control gate surface.
By depositing and etching a multilayer structure on a semiconductor substrate, an outer wall is formed that encloses the floating gate with the control gate, increasing the overlap area between the floating gate and the control gate. A self-aligned etching process is then used to form the NORD flash structure.
It increases the gate coupling ratio of NORD flash, enhances device performance, and reduces the area of flash memory cells, without being limited by photolithography processes.
Smart Images
Figure CN114284277B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, specifically to a manufacturing method and structure for improving the gate coupling ratio of NORD flash. Background Technology
[0002] In flash memory devices, two gates are typically provided in a stacked configuration: a floating gate, formed of polysilicon, for storing charge, and a control gate for controlling information access. The floating gate is generally located below the control gate, with a dielectric layer (typically an oxide / nitride / oxide insulating stack) between the control gate and the floating gate. The floating gate is named for its floating state, meaning it does not require connection to external circuitry, while the control gate does. Furthermore, source and drain regions are positioned on the semiconductor substrate on either side of the gate.
[0003] The semiconductor market trend is towards manufacturing devices with smaller size, lower operating voltage, lower price, and higher speed. One of the key characteristics of flash memory devices is the gate coupling ratio between the floating gate and the control gate, which affects the operating voltage and device speed. The gate coupling ratio is defined as the ratio of the induced voltage at the floating gate to the applied voltage at the control gate. Generally, increasing the gate coupling ratio reduces the operating voltage while simultaneously increasing device speed. Increasing the gate coupling ratio includes: increasing the surface overlap area between the floating gate and the control gate, reducing the dielectric layer thickness between the floating gate and the control gate, and increasing the dielectric constant of the dielectric layer between the floating gate and the control gate.
[0004] When considering increasing the surface overlap area between the floating gate and the control gate as a method to increase the gate coupling ratio, the surface overlap area between the floating gate and the control gate is generally limited, and the gate coupling ratio is only about 60%. Therefore, there is an urgent need to improve the process method that can increase the surface overlap area between the floating gate and the control gate, thereby improving the gate coupling ratio. Summary of the Invention
[0005] This application provides a NORD flash device and a method for manufacturing the same, in order to solve the problem of low coupling rate of NORD flash in related technologies.
[0006] On one hand, this application provides a method for manufacturing NORD flash to improve the gate coupling ratio, including:
[0007] Step 1: Sequentially deposit a gate oxide layer and a floating gate polysilicon layer on a semiconductor substrate, and etch away part of the floating gate polysilicon layer to expose the gate oxide layer;
[0008] Step 2: Sequentially deposit a dielectric layer, a control gate polysilicon layer, and a first silicon nitride layer on the remaining floating gate polysilicon layer and the exposed gate oxide layer;
[0009] Step 3: Etch away the first silicon nitride layer in the cell area to form word lines in the cell area;
[0010] Step 4: Deposit a second silicon nitride layer on the cell region and the remaining first silicon nitride layer;
[0011] Step 5: Remove the second silicon nitride layer and the remaining first silicon nitride layer, and use the cell region unit as a self-aligned etching mask to complete the etching of the exposed control gate polysilicon layer and the dielectric layer below it.
[0012] Alternatively, in step five, phosphoric acid is used to remove the second silicon nitride layer and the remaining first silicon nitride layer.
[0013] Alternatively, in step three, the first silicon nitride layer in the cell region can be removed by dry etching.
[0014] Optionally, the dielectric layer includes an ONO, which comprises, from bottom to top, a silicon dioxide layer, a silicon nitride layer, and a silicon dioxide layer.
[0015] Alternatively, the manufacturing method for improving the gate coupling ratio of the NORD flash can be further improved, and can be used in processes including but not limited to 55nm NORD flash.
[0016] To address the aforementioned technical problems, this invention provides a NORD flash structure with improved gate coupling ratio, manufactured by any one of the NORD flash manufacturing methods for improved gate coupling ratio described above. The NORD flash structure with improved gate coupling ratio includes: a semiconductor substrate; a gate oxide layer formed on a cell region of the semiconductor substrate, a word line formed on the gate oxide layer, and a floating gate, a dielectric layer, a control gate, and a sidewall structure formed sequentially from bottom to top on both sides of the word line, wherein the control gate surrounds the outer sidewall of the floating gate.
[0017] Furthermore, the control gate covers 1 / 3 of the outer wall of the floating gate.
[0018] The technical solution of this application has at least the following advantages:
[0019] In the traditional NORD flash structure, the control gate is located above the floating gate. However, in the NORD flash structure with improved gate coupling ratio provided in this application, the control gate can be coupled and controlled not only through the upper part of the floating gate, but also through the sidewall region of the floating gate. Therefore, the gate coupling ratio of the device is increased compared to the traditional structure. Attached Figure Description
[0020] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0021] Figure 1 This is a schematic flowchart of a manufacturing method for improving the gate coupling ratio of a NORD flash according to an exemplary embodiment of this application;
[0022] Figure 2a A schematic cross-sectional view of the NORD flash structure after step one in the manufacturing method for improving the gate coupling ratio of NORD flash.
[0023] Figure 2b A schematic cross-sectional view of the NORD flash structure after step two in the manufacturing method for improving the gate coupling ratio of NORD flash.
[0024] Figure 2c A schematic cross-sectional view of the NORD flash structure after step three in the manufacturing method for improving the gate coupling ratio of NORD flash.
[0025] Figure 2d A schematic cross-sectional view of the NORD flash structure after step four in the manufacturing method for improving the gate coupling ratio of NORD flash.
[0026] Figure 2e A schematic cross-sectional view of the NORD flash structure after step five in the manufacturing method for increasing the gate coupling ratio of NORD flash. Detailed Implementation
[0027] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0028] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0029] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0030] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0031] Figure 1 This is a schematic flowchart illustrating the steps of a manufacturing method for improving the gate coupling ratio of a NORD flash according to an exemplary embodiment of this application. (Refer to...) Figure 1 A method for manufacturing a NORD flash to improve the gate coupling ratio, comprising:
[0032] S11. Sequentially deposit a gate oxide layer and a floating gate polysilicon layer on a semiconductor substrate, and etch away part of the floating gate polysilicon layer to expose the gate oxide layer.
[0033] S12. A dielectric layer, a control gate polysilicon layer, and a first silicon nitride layer are sequentially deposited on the remaining floating gate polysilicon layer and the exposed gate oxide layer.
[0034] S13. Etch away the first silicon nitride layer in the cell region to form word lines in the cell region;
[0035] S14. Deposit a second silicon nitride layer on the cell region and the remaining first silicon nitride layer;
[0036] S15. Remove the second silicon nitride layer and the remaining first silicon nitride layer, and complete the etching of the exposed control gate polysilicon layer and the dielectric layer below it.
[0037] To more intuitively reveal the technical features of this invention and highlight its beneficial effects, the working principle of the manufacturing method for improving the gate coupling ratio of NORD flash according to this invention is explained in conjunction with specific embodiments. In the specific embodiments, the formation processes, methods, structural properties, dimensions, etc., of each functional layer are merely examples and should not be considered as limitations on the technical solution of this invention. Conventional processes, methods, and materials used in the field will not be elaborated upon.
[0038] Figure 2a A schematic cross-sectional view of the NORD flash structure after step one in the manufacturing method for increasing the gate coupling ratio of NORD flash. (Refer to...) Figure 2a A gate oxide layer 201, a floating gate polysilicon layer 202, and a silicon nitride layer are sequentially deposited on a silicon substrate 200. The floating gate polysilicon layer 202, which will be used to form the floating gate, is grown by chemical vapor deposition. The silicon nitride layer is used as an etching mask for etching the floating gate polysilicon layer 202. After etching the floating gate polysilicon layer 202, the silicon nitride layer is removed. The etched floating gate polysilicon layer initially defines the range of the cell region. Each cell region unit is separated by the exposed gate oxide layer 201.
[0039] Figure 2b A schematic cross-sectional view of the NORD flash structure after step two in the manufacturing method for increasing the gate coupling ratio of NORD flash. (Refer to...) Figure 2b A dielectric layer 203, a control gate polysilicon layer 204, and a first silicon nitride layer 205 are sequentially deposited on the remaining floating gate polysilicon layer 202 and the exposed gate oxide layer 201. The dielectric layer 203 comprises ONO, which, from bottom to top, comprises a silicon dioxide layer, a silicon nitride layer, and another silicon dioxide layer. In this embodiment of the invention, the thickness of the first silicon nitride layer 205 is 2000 angstroms.
[0040] Figure 2c A schematic cross-sectional view of the NORD flash structure after step three in the manufacturing method for increasing the gate coupling ratio of NORD flash. (Refer to...) Figure 2c The first silicon nitride layer 205 in the cell region is removed by etching with an etching mask. A first sidewall 208 is formed on the control gate polysilicon layer 204, and a second sidewall 209 is formed, which is located between the word line and the control gate and the floating gate, forming the word line 206. Figure 2d A schematic cross-sectional view of the NORD flash structure after step four in the manufacturing method for increasing the gate coupling ratio of NORD flash. (Refer to...) Figure 2dA second silicon nitride layer 207 is deposited on the cell region and the remaining first silicon nitride layer. The purpose of depositing the second silicon nitride layer 207 is to avoid affecting the structure of the cell region during the etching process of the logic region.
[0041] Figure 2e A schematic cross-sectional view of the NORD flash structure after step five in the manufacturing method for increasing the gate coupling ratio of NORD flash. (Refer to...) Figure 2e The second silicon nitride layer 207 and the remaining first silicon nitride layer 205 are removed using phosphoric acid wet etching, and the exposed control gate polysilicon layer 204 and the underlying dielectric layer 203 are etched. Since the control gate polysilicon layer 204 in the cell region is longer than the floating gate 2021, the outer wall of the floating gate 2021 is wrapped by the etched control gate 2041, increasing the area of overlap between the surface of the floating gate 2021 and the control gate 2041, further increasing the gate coupling ratio of the device.
[0042] In summary, in the embodiments of this application, the NORD flash structure formed by the self-aligned process in the manufacturing method of increasing the gate coupling ratio of NORD flash not only etches until the outer wall of the control gate wraps around the floating gate, increasing the area of overlap between the floating gate surface and the control gate, thus further increasing the gate coupling ratio of the device, but also further reduces the area of the flash memory cell through the self-aligned process, while not being limited by the photolithography process.
[0043] Alternatively, the NORD flash manufacturing method described in the above embodiments can be used for processes including but not limited to 55nm NORD flash.
[0044] The present invention also provides a NORD flash structure for improving the gate coupling ratio, which is manufactured by the manufacturing method for improving the gate coupling ratio of NORD flash described in the above embodiments, with reference to... Figure 2e A NORD flash structure for improving gate coupling ratio includes: a silicon substrate 200; a gate oxide layer 201 formed on a cell region of the silicon substrate 200, a word line 206 formed on the gate oxide layer 201, and a floating gate 2021, a dielectric layer 203, a control gate 2041, and a sidewall 208 structure formed sequentially from bottom to top on both sides of the word line 206, wherein the control gate 2041 surrounds the outer sidewall of the floating gate 2021. Preferably, the control gate surrounds 1 / 3 of the outer sidewall of the floating gate.
[0045] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A method for manufacturing a NORD flash to improve the gate coupling ratio, characterized in that, include: Step 1: Sequentially deposit a gate oxide layer and a floating gate polysilicon layer on a semiconductor substrate, and etch away part of the floating gate polysilicon layer to expose the gate oxide layer; Step 2: Sequentially deposit a dielectric layer, a control gate polysilicon layer, and a first silicon nitride layer on the remaining floating gate polysilicon layer and the exposed gate oxide layer; the dielectric layer and the control gate polysilicon layer sequentially wrap around the sidewalls and the top surface of the floating gate polysilicon layer; Step 3: Etch away the first silicon nitride layer in the cell area to form word lines in the cell area; Step 4: Deposit a second silicon nitride layer on the cell region and the remaining first silicon nitride layer; Step 5: Remove the second silicon nitride layer and the remaining first silicon nitride layer, and complete the etching of the exposed control gate polysilicon layer and the dielectric layer below it.
2. The manufacturing method for improving the gate coupling ratio of NORD flash according to claim 1, characterized in that, In step five, phosphoric acid is used to remove the second silicon nitride layer and the remaining first silicon nitride layer.
3. The manufacturing method for improving the gate coupling ratio of NORD flash according to claim 1, characterized in that, In step three, the first silicon nitride layer in the cell region is removed by dry etching.
4. The manufacturing method for improving the gate coupling ratio of NORD flash according to claim 1, characterized in that, The dielectric layer includes an ONO layer, which, from bottom to top, comprises a silicon dioxide layer, a silicon nitride layer, and a silicon dioxide layer.
5. The manufacturing method for improving the gate coupling ratio of NORD flash according to claim 1, characterized in that, It can be used in processes including but not limited to 55nm NORD flash.