Phase change memory (PCM) including pads to reduce drag drift.

Abstract

This disclosure relates to a phase change memory (PCM) including a pad to reduce drag drift. A phase change memory (PCM) device includes: a dielectric layer; a bottom electrode disposed in the dielectric layer; a pad material disposed on the bottom electrode; a phase change material disposed on the pad material; and a top electrode disposed on the phase change material and in the dielectric layer.

Description

Background Technology

[0001] This invention relates to memory devices, and more particularly to improved phase-change memory (PCM) devices.

[0002] Neuromorphic engineering (also known as neuromorphic computing) is a concept that describes the use of very large-scale integrated (VLSI) systems containing electronic analog circuitry to simulate the neurobiological architectures present in the nervous system.

[0003] The application of these neurobiological architectures to machine learning can be accelerated by using analog chips incorporating phase-change memory (PCM). PCMs are based on chalcogenide glass materials that, when a suitable current is applied, change their phase from crystalline to amorphous and back again. Each phase has a different resistance level that is stable until the phase is changed. The maximum and minimum resistance levels in a PCM device are based on binary one or zero values.

[0004] PCM devices are non-volatile and have access latency at the DRAM level, making them examples of memory-class storage. Intel-Micron 3D XPoint technology is a PCM-based binary memory. PCMs can be programmed to change their resistance states between maximum and minimum resistance states depending on the ratio of the present amorphous to crystalline phases, thus providing simulated states for neuromorphic computation. Summary of the Invention

[0005] According to an embodiment of the present invention, a phase change memory (PCM) device includes: a dielectric layer; a bottom electrode disposed in the dielectric layer; a pad material disposed on the bottom electrode; a phase change material disposed on the pad material; and a top electrode disposed on the phase change material and in the dielectric layer.

[0006] According to some embodiments, a method of manufacturing a phase-change memory (PCM) device includes: providing a substrate; forming a first structure including a first dielectric layer and a bottom electrode, wherein the bottom electrode is disposed in the first dielectric layer and the bottom electrode and the first dielectric layer are disposed on the substrate; forming a pad material disposed on the bottom electrode and in a second dielectric layer; forming a phase-change material on the pad material and in a third dielectric layer; and forming a top electrode disposed on the phase-change material and in a fourth dielectric layer.

[0007] According to some embodiments, a phase change memory (PCM) device includes: a dielectric layer; a first electrode disposed on a first side of the dielectric layer; a second electrode disposed on a second side of the dielectric layer, opposite to the first electrode; a phase change material disposed on the dielectric layer, the first electrode, and the second electrode; and a pad material disposed on the phase change material.

[0008] As used herein, "facilitating" an action includes performing an action, making an action easier, assisting in performing an action, or causing an action to be performed. Therefore, by way of example and not limitation, an instruction executing on one processor can facilitate an action performed by instructions executing on a remote processor by sending appropriate data or commands to cause or assist in the execution of that action. To avoid confusion, where the actor facilitates the action by actions other than performing the action, the action is still performed by some entity or combination of entities.

[0009] One or more embodiments of the present invention, or elements thereof, can be implemented in the form of a computer program product comprising a computer-readable storage medium having computer-usable program code for performing the indicated method steps. Furthermore, one or more embodiments of the present invention, or elements thereof, can be implemented in the form of a system (or apparatus) comprising a memory and at least one processor coupled to the memory and operable to perform exemplary method steps. Further, in another aspect, one or more embodiments of the present invention, or elements thereof, can be implemented in the form of means for performing one or more of the method steps described herein; the apparatus may include: (i) a hardware module, (ii) a software module stored in a computer-readable storage medium (or multiple such media) and implemented on a hardware processor, or (iii) a combination of (i) and (ii); any one of (i)-(iii) implements the specific techniques set forth herein.

[0010] The technology of this invention can provide substantial and beneficial technical effects. For example, one or more embodiments can provide:

[0011] Reduced resistance drift in PCM devices; and

[0012] Reduce the programming current in the device.

[0013] These and other features and advantages of the invention will become apparent from the following detailed description of illustrative embodiments of the invention, which are read in conjunction with the accompanying drawings. Attached Figure Description

[0014] Preferred embodiments of the present invention will now be described in more detail with reference to the accompanying drawings:

[0015] Figure 1 This is an exemplary PCM cross-point memory and neuron morphology computation cross array according to some embodiments of the present invention;

[0016] Figure 2 It is a PCM unit comprising a pad formed of conductive oxide according to some embodiments of the present invention;

[0017] Figure 3 It is a PCM unit comprising a pad formed of metal and conductive oxide according to some embodiments of the present invention;

[0018] Figure 4 It is a PCM unit comprising a pad formed of metal, according to some embodiments of the present invention;

[0019] Figure 5 This is a graph showing the resistance of different pads over time according to some embodiments of the present invention.

[0020] Figure 6 This is a flowchart of a method for manufacturing a PCM device according to some embodiments of the present invention;

[0021] Figure 7 It is a PCM unit configured as a bridging unit according to some embodiments of the present invention; and

[0022] Figure 8 It is a PCM unit configured as a defined unit according to some embodiments of the present invention. Detailed Implementation

[0023] This application will now be described in more detail with reference to the following discussion and the accompanying drawings. It should be noted that the drawings are provided for illustrative purposes only, and therefore are not drawn to scale. It should also be noted that identical and corresponding elements are indicated by the same reference numerals.

[0024] In the following description, numerous specific details, such as particular structures, components, materials, dimensions, processing steps, and techniques, are set forth in order to provide an understanding of different embodiments of this application. However, those skilled in the art will recognize that different embodiments of this application can be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail to avoid obscuring this application.

[0025] Back-end process (BEOL) compatible phase-change memory (PCM), crosspoint memory, and neuromorphic computing cross arrays (see...) Figure 1Training of fully connected neural networks can be accelerated by performing computations at the location of the data. Resistance drift is a problem when using phase-change memory (PCM) as analog memory in neuromorphic computing devices. Embodiments of the present invention relate to an improved PCM structure.

[0026] See Figure 1 Device 100 includes bit line 101, PCM 102, pad 103, and word line 104. According to at least one embodiment, PCM 102 sequentially includes a top electrode, a phase change material layer such as GST (germanium-antimony-tellurium or Ge2Sb2Te5), a pad material, and a bottom electrode. According to some embodiments of the invention, the pad material comprises a conductive oxide film (e.g., aluminum (Al)-doped zinc oxide (ZnO, hereinafter AZO)). The pad material can be formed by, for example, by doping ZnO with Al (AZO), indium oxide with tin (ITO), or by doping other metal oxides to create the conductive oxide, or by depositing the conductive oxide.

[0027] According to some embodiments of the invention, the pad acts as an inert capping layer. According to some embodiments of the invention, the pad acts as a thermal barrier that reduces heat loss to the underlying bottom electrode during the electrical programming (amorphization or crystallization) of the PCM. According to one or more embodiments of the invention, ZnO is a semiconductor material, and its resistance can be precisely controlled by Al doping.

[0028] refer to Figure 2 According to some embodiments, PCM 102 includes a top electrode 201 (e.g., formed of a metal or metal nitride (XN, where X can be any transition metal that forms a stable nitride, such as tantalum (Ta), titanium (Ti), or tungsten (W))), a phase change material 202 / 205 (e.g., GST), a conductive oxide pad material 203, and a bottom electrode 204 (e.g., formed of a metal or metal nitride (XN, where X can be any transition metal that forms a stable nitride, such as Ta, Ti, or W)).

[0029] Phase change material 202 / 205 may include a first portion 202 and / or a second portion 205. It should be understood that, considering the ability of GST to influence reversible phase transitions during rapid heating and cooling or slow heating between an amorphous and crystalline state, GST can be used as a memory or a medium for a memory. According to one or more embodiments, the first portion of GST 202 is amorphous GST, while the second portion of GST 205 is crystalline GST. Portion 202 can be electrically programmed to the crystalline state of GST. It should be understood that portions 202 and 205 are the same material, and the presence of portion 202 depends on the state of the device (i.e., if the GST is amorphized to a reset state (high resistance), then portion 202 is present).

[0030] According to some embodiments, PCM 102 is disposed in dielectric layer 206. According to some embodiments, dielectric layer 206 may be silicon dioxide (SiO2), silicon nitride (SiNx), aluminum oxide (Al2O3), etc.

[0031] According to some embodiments, the PCM 102 has a thickness (A-A') of about 20 nanometers (nm) to 100 nm and a lateral dimension (B-B') of about 40 nm to 500 nm, as well as a bottom contact dimension of about 10 nm to 50 nm.

[0032] According to some embodiments, the conductive oxide pad material 203 does not oxidize significantly in air and therefore acts as an inert capping layer. Furthermore, the conductive oxide pad material 203 maintains its resistance even when exposed (e.g., exposed to the environment). According to some embodiments, the pad acts as a thermal barrier between the PCM and the bottom electrode. Within the conductive oxide pad material 203, the layer composed of metal oxides (e.g., InOx, ZnOx) is semiconductor, and its resistance can be precisely controlled by metal doping (e.g., tin (Sn), Al). The conductive oxide pad material 203 can be deposited by atomic layer deposition (ALD) or physical vapor deposition (PVD). According to some embodiments, the conductive oxide pad material 203 has a thickness of about 1-15 nanometers (nm). According to some embodiments, the thickness of the conductive oxide pad is proportionally adjusted to the thickness of the PCM layer to achieve good reversible phase transition characteristics. For example, for Figure 4 and Figure 8 The device, depending on the thickness of the conductive oxide pad, can have a resistivity that is about 0.1 to 10 times that of the PCM crystal resistivity.

[0033] refer to Figure 3 According to some embodiments, PCM 102 includes a top electrode 201, a GST 202 / 205 layer, an Al layer 301 above a conductive oxide pad material 203, and a bottom electrode 204. PCM 102 is disposed in layer 206.

[0034] refer to Figure 4 According to some embodiments, PCM 102 includes a top electrode 201, a GST 202 / 205 layer, an Al layer 401, and a bottom electrode 204. PCM 102 is disposed in layer 206.

[0035] According to some embodiments, the metal liner material 401 may be composed of Al and have a thickness of approximately 10 nanometers (nm). The metal liner material 401 may be deposited by sputtering, evaporation, chemical vapor deposition (CVD), etc. According to some embodiments, after deposition, the metal liner material 401 may be annealed, for example, by forming gas (FG) annealing. Table 1 lists the processes used for conventional control structures. Table 1 further lists exemplary liners and structures according to embodiments of the invention, and their associated average resistance drift upon reset (i.e., upon reset of the PCM). In Table 1, the liners are given at the initial deposition (As-dep) temperature.

[0036] Figure 5 This is a graph 500 showing the resistance of different pads over time according to some embodiments of the present invention. The conventional device 501 with only GST has a higher resistance than the GST with conductive oxide pad 502 or the GST with conductive oxide / Al pad 503.

[0037] Table 1.

[0038]

[0039] See Figure 6 According to some embodiments, a method of manufacturing a PCM device includes: providing at frame 601 a layer including word lines and pads (see...). Figure 1 The intermediate front-end process (FEOL) or BEOL wafer; forming a dielectric layer 206 at frame 602; forming a bottom electrode 204 at frame 603; forming a pad material 203 at frame 604; forming a phase change material 202 / 205 at frame 605; forming a top electrode 201 at frame 606; and integrating the PCM device into the computer device at frame 607 (e.g., including forming a bit line 101).

[0040] As described below, dielectric layer 206 may be formed as one or more layers, wherein the formation of components (e.g., padding material at frame 604) may further include the deposition and patterning of dielectric layers.

[0041] According to one or more embodiments, the bottom electrode 204 is embedded in the dielectric layer 206. Although a single bottom electrode 204 is described and shown, multiple bottom electrodes may be formed in the dielectric layer 206.

[0042] According to some embodiments, the dielectric layer 206 is formed of, for example, SiO2, Si3N4, silicon oxynitride (N2OSi2), silsesquioxane, or carbon-doped oxides (i.e., organosilicones) comprising Si, C, and H atoms. In some embodiments, the dielectric layer 206 is non-porous. In other embodiments, the dielectric layer 206 is porous. In some embodiments, a single dielectric material may be used as the dielectric layer 206. In another embodiment, multiple dielectric materials may be used as the dielectric layer 206.

[0043] According to some embodiments, a dielectric layer 206 is formed on a base substrate (not shown). The base substrate may include semiconductor materials, insulating materials, and / or conductive materials (e.g., word lines). The dielectric layer 206 may be formed using deposition processes including, for example, CVD, plasma-enhanced chemical vapor deposition (PECVD), spin coating, evaporation, chemical solution deposition, etc.

[0044] In some embodiments, a first opening is formed in a dielectric layer 206, and then a bottom electrode 204 is formed within the first opening 603. The first opening can be formed using photolithography and etching. Photolithography includes providing a photoresist material (not shown) on the upper surface of the dielectric layer 206, exposing the photoresist material to a desired radiation pattern, and subsequently developing the exposed photoresist material using a conventional resist developer. Etching is then used to transfer the pattern from the patterned photoresist material to the underlying dielectric layer 206. Etching can include dry etching processes (e.g., reactive ion etching (RIE), ion beam etching, plasma etching, and / or laser ablation) and / or wet chemical etching processes. In one embodiment, RIE is used to provide an opening in the dielectric layer 206. In some embodiments, anisotropic etching is used to provide an opening with vertical sidewalls. In other embodiments, isotropic etching is used to provide an opening with non-vertical (i.e., inclined) sidewalls. After pattern transfer, the photoresist material can be removed using a resist stripping process (e.g., ashing).

[0045] After an opening is formed within the dielectric layer 206, a bottom electrode 204 is formed at frame 603 by depositing a conductive metal material into the opening. According to some embodiments, the conductive metal material providing the bottom electrode 204 is, for example, titanium nitride (TiN), tungsten (W), silver (Ag), gold (Au), aluminum (Al), or a multilayer stack thereof. The conductive metal material can be formed by a deposition process, such as CVD, PECVD, physical vapor deposition (PVD), sputtering, atomic layer deposition (ALD), or electroplating. When the dielectric layer 206 is deposited as multiple layers, a planarization process or an etch-back process can follow the deposition of the conductive metal material providing the bottom electrode 204.

[0046] According to some embodiments, a bottom electrode 204 is formed on the surface of a base substrate (not shown) by depositing a conductive metal material, followed by patterning the deposited conductive metal material through photolithography and etching. A dielectric layer 206 may then be formed by depositing a dielectric material followed by a planarization or etch-back process.

[0047] According to one or more embodiments of the invention, at block 604, a second opening is formed in the dielectric layer 206 (e.g., in a second portion of the dielectric layer 206 formed over the bottom electrode 204), and a pad material 203 is formed in the second opening. According to some embodiments, the pad material 203 can be deposited by atomic layer deposition (ALD) or sputtering. According to at least one embodiment, the pad material 203 is planarized after deposition using process steps similar to those described in conjunction with the bottom electrode 204.

[0048] According to one or more embodiments of the invention, at block 605, a third opening is formed in the dielectric layer 206 (e.g., in a third portion of the dielectric layer 206 formed over the pad material 203), and a phase change material 202 / 205 is formed in the third opening. The phase change material 202 / 205 may include a first portion and / or a second portion of GST 202 / 205. According to at least one embodiment, similar to those described in conjunction with the bottom electrode 204, the phase change material 202 / 205 is planarized after deposition.

[0049] According to one or more embodiments of the present invention, at block 606, a fourth opening is formed in the dielectric layer 206 (e.g., in a third portion of the dielectric layer 206 formed over the phase change material 202 / 205), and a top electrode 201 is formed in the fourth opening. This embodiment includes processing steps for planarizing the top electrode 201, similar to the processing steps described in conjunction with the bottom electrode 204.

[0050] Summary:

[0051] According to an embodiment of the present invention, a phase change memory (PCM) device includes: a dielectric layer 206; a bottom electrode 204 disposed in the dielectric layer; a pad material 203 disposed in the bottom electrode and the dielectric layer; a phase change material 202 / 205 disposed on the pad material and in the dielectric layer; and a top electrode 201 disposed on the phase change material and in the dielectric layer.

[0052] According to some embodiments, a method of manufacturing a phase-change memory (PCM) device includes: providing a substrate 601; forming a first structure 602 / 603 including a first dielectric layer and a bottom electrode, wherein the bottom electrode is disposed in the first dielectric layer and the bottom electrode and the first dielectric layer are disposed on the substrate; forming a pad material 604 disposed on the bottom electrode and in a second dielectric layer; forming a phase-change material 605 on the pad material and in a third dielectric layer; and forming a top electrode 606 disposed on the phase-change material and in a fourth dielectric layer.

[0053] According to one or more embodiments, the PCM device may have a variety of other configurations (see, for example) Figure 7 and Figure 8 For example, according to some embodiments, the PCM device is configured as a bridging unit 700 (see...). Figure 7 The PCM 704 includes a conductive oxide pad material 705 disposed on a thin PCM 704. The PCM 704 is formed on a first metal electrode 701 and a second metal electrode 702, which are separated by an interlayer dielectric (ILD) 703.

[0054] According to some embodiments, the PCM device is configured as a restricted cell device 800 (see [reference]). Figure 8 The device includes a conductive oxide 805 that liner the via 806 formed in the intermediate layer 807 and surrounds the PCM 804. The confined unit includes a top electrode 801 and a bottom electrode 802, each disposed in a dielectric, such as 803. The top electrode 801 is disposed above the via and contacts the upper surfaces of the conductive oxide 805 and the PCM 804. The bottom electrode 802 is disposed below the via and contacts the lower surface of the conductive oxide 805.

[0055] According to some embodiments, the sidewalls of the through-hole 806 may have different configurations, such as vertical sidewalls. According to some embodiments, the gasket 805 may be disposed only on the sidewalls of the through-hole 806, such that the lower surface of the PCM 804 is in direct contact with the top electrode 801 and the bottom electrode 802. According to one or more embodiments, the PCM 804 is separated from one or more of the electrodes 801 to 802 by the gasket 805.

[0056] like Figure 7 and Figure 8 As shown, as described herein, the presence of the amorphous PCM (a-PCM) portion 202 of the PCM depends on the state of the device.

[0057] Summary:

[0058] According to an embodiment of the present invention, a phase change memory (PCM) device 102 includes: a dielectric layer 206; a bottom electrode 204 disposed in the dielectric layer; a pad material 203 disposed on the bottom electrode; a phase change material 205 disposed on the pad material; and a top electrode 201 disposed on the phase change material and in the dielectric layer.

[0059] According to some embodiments, a method of manufacturing a phase-change memory (PCM) device includes: providing a substrate 601; forming a first structure including a first dielectric layer 602 and a bottom electrode 603, wherein the bottom electrode is disposed in the first dielectric layer and the bottom electrode and the first dielectric layer are disposed on the substrate; forming a pad material 604 disposed on the bottom electrode and in a second dielectric layer; forming a phase-change material 605 on the pad material and in a third dielectric layer; and forming a top electrode 606 disposed on the phase-change material and in a fourth dielectric layer.

[0060] According to some embodiments, a phase change memory (PCM) device includes: a dielectric layer 703; a first electrode 701 disposed on a first side of the dielectric layer; a second electrode 702 disposed on a second side of the dielectric layer, opposite to the first electrode; a phase change material 704 disposed on the dielectric layer and on the first and second electrodes; and a pad material 705 disposed on the phase change material.

[0061] It should be understood that the invention will be described in accordance with the given illustrative architecture; however, other architectures, structures, substrate materials, and process features and steps may be modified within the scope of the invention.

[0062] It will also be understood that when a component, such as a layer, region, or substrate, is referred to as being "on" or "above" another component, it may be directly on the other component or there may be intermediate components. Conversely, when a component is referred to as being "directly on" or "directly on" another component, there are no intermediate components. It will also be understood that when a component is referred to as being "connected" or "coupled" to another component, it may be directly connected or coupled to the other component or there may be intermediate components. Conversely, when a component is referred to as being "directly connected" or "directly coupled" to another component, there are no intermediate components.

[0063] This embodiment may include a design for an integrated circuit chip, which can be created using a graphical computer programming language and stored in a computer storage medium (such as a disk, tape, physical hard disk drive, or virtual hard disk drive in a storage access network). If the designer does not manufacture the chip or the photomask used to manufacture the chip, the designer may transfer the resulting design directly or indirectly to such an entity by physical means (e.g., by providing a copy of the storage medium containing the design) or electronically (e.g., via the Internet). The stored design is then converted into a suitable format (e.g., GDSII) for manufacturing the photomask, which typically includes multiple copies of the chip design in question to be formed on a wafer. The photomask is used to define areas of the wafer (and / or layers on it) to be etched or otherwise processed.

[0064] The methods described herein can be used to manufacture integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. In the latter case, the chips are mounted in a single-chip package (such as a plastic carrier with leads attached to a motherboard or other more advanced carrier) or a multi-chip package (such as a ceramic carrier with one or both surface interconnects or buried interconnects). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (such as a motherboard) or (b) a final product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0065] It should also be understood that the material compounds will be described based on the listed elements (e.g., SiGe). These compounds include elements in different proportions within the compound; for example, SiGe includes Si. x Ge 1-x Where x is less than or equal to 1, and so on. Furthermore, other elements may be included in the compound and still function according to the principles of the invention. Compounds with additional elements will be referred to herein as alloys.

[0066] References to the principles of this specification as "one embodiment" or "embodiment" and other variations thereof mean that a particular feature, structure, characteristic, etc., described in connection with that embodiment is included in at least one embodiment of the principles. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout the specification, as well as any other variations, do not necessarily all refer to the same embodiment.

[0067] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. Each block in a flowchart or block diagram may represent a module, segment, or part of an instruction, which includes one or more executable instructions for implementing a specified logical function. In some alternative embodiments, the functions marked in the blocks may occur in a different order than indicated in the figures. For example, depending on the functions involved, two consecutively shown blocks may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. It will also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0068] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms “comprising” and / or “including” are used in this specification, they specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0069] All means or steps in the following claims, plus corresponding structures, materials, actions, and equivalents of the functional elements, are intended to include any structure, material, or action for performing the function in conjunction with other claimed elements as specifically claimed. Descriptions of various embodiments of the invention have been presented for illustrative purposes but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A phase change memory (PCM) device, comprising: a dielectric layer; a bottom electrode disposed in the dielectric layer; a liner material disposed on the bottom electrode, wherein the liner material includes a conductive oxide thin film and a metal layer formed of Al disposed above the conductive oxide thin film; a phase change material disposed on the liner material; and a top electrode disposed on the phase change material and in the dielectric layer.

2. The PCM device of claim 1, wherein the bottom electrode is formed of one of a first metal and a first metal nitride, and the top electrode is formed of one of a second metal and a second metal nitride, wherein the bottom electrode and the top electrode are formed of one of the same material and different materials.

3. The PCM device of claim 1, wherein the liner material and the phase change material are disposed in the dielectric layer.

4. The PCM device of claim 1, wherein the dielectric layer includes a first dielectric layer and a second dielectric layer, and the bottom electrode is formed in the first dielectric layer, and the top electrode is formed in the second dielectric layer, wherein the liner material and the phase change material are disposed in a via formed in an intermediate layer between the first dielectric layer and the second dielectric layer, and further wherein the liner material is in contact with the top electrode and the bottom electrode.

5. The PCM device of claim 1, wherein the conductive oxide thin film is one of Al-doped ZnO (AZO), indium tin oxide (ITO) doped with tin, and a doped metal oxide.

6. The PCM device of claim 1, wherein the dielectric layer includes a plurality of dielectric layers.

7. A method of fabricating a phase change memory (PCM) device, comprising: providing a substrate; forming a first structure including a first dielectric layer and a bottom electrode, wherein the bottom electrode is disposed in the first dielectric layer, and the bottom electrode and the first dielectric layer are disposed on the substrate; forming a liner material disposed on the bottom electrode and in a second dielectric layer; forming a phase change material on the liner material and in a third dielectric layer; and forming a top electrode disposed on the phase change material and in a fourth dielectric layer.

8. The method of claim 7, wherein the bottom electrode is formed of a first metal or metal nitride, and the top electrode is formed of a second metal or metal nitride, wherein the first metal nitride and the second metal nitride are one of the same metal nitride and different metal nitrides.

9. The method of claim 7, wherein the liner material includes a conductive oxide thin film.

10. The method of claim 9, wherein the conductive oxide thin film is one of Al-doped ZnO (AZO), indium tin oxide (ITO) doped with tin, and a doped metal oxide. ​ ​ 11. The method of claim 7, wherein forming the liner material further comprises: forming a conductive oxide thin film on the bottom electrode; and forming a metal layer on the conductive oxide thin film.

12. The method of claim 11, wherein the metal layer is formed of Al.

13. The method of claim 11, wherein the conductive oxide thin film is one of Al-doped ZnO (AZO), indium tin oxide (ITO), and a doped metal oxide.

14. The method of claim 7, wherein the liner material is an Al layer.

15. The method of claim 7, further comprising sequentially depositing and patterning the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer.

16. A phase change memory (PCM) device, comprising: a dielectric layer; a first electrode disposed on a first side of the dielectric layer; a second electrode disposed on a second side of the dielectric layer, opposite the first electrode; a phase change material disposed on the dielectric layer and the first and second electrodes; and a liner material disposed on the phase change material. ​

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