Level Conversion Circuit Based on Logic Process for Flash FPGA

Abstract

The present invention discloses a level conversion circuit based on a logic process for a flash-type FPGA, which relates to the field of flash-type FPGAs. The level conversion circuit performs three-level voltage conversion through three conversion modules. The first-level conversion module is used to convert the first signal in the VDD-GND voltage domain of the input into the second signal in the VP1-GND voltage domain. The intermediate-level conversion module is used to convert the second signal in the VP1-GND voltage domain of the input into the third signal in the VP1-VN voltage domain. The driving-level conversion module is used to convert the third signal in the VP1-VN voltage domain of the input into the driving signal in the VP2-VN voltage domain and output the driven word line, reducing the pressure of each-level conversion, ensuring the ability to drive the next level, improving the conversion speed, and providing a large driving ability in the last level.

Description

Technical Field

[0001] The present invention relates to the field of flash type FPGAs, and in particular to a level conversion circuit based on a logic process for a flash type FPGA. Background Art

[0002] A flash type FPGA is a programmable logic circuit based on flash memory technology. It consists of a programmable routing switch matrix formed by flash memory cells (flash cells). By configuring the flash cells, different flash switch paths are selected, thereby realizing the programmable logic function of the user.

[0003] The flash type FPGA has a fast startup speed, and the circuit can quickly enter the working state after power-on. Therefore, it has become the mainstream of programmable logic devices and is widely used in the fields of signal processing and control. The flash type FPGA provides users with logic with a system equivalent gate count ranging from several hundred thousand to several million gates, with a maximum operating frequency of up to 350 MHz, and a large number of IP cores are provided. The flash type FPGA must be designed and manufactured based on a logic process, rather than being designed and manufactured on a specific process like a flash memory (flash memory).

[0004] The erasing and programming of flash cells require relatively high voltages, and it is necessary to convert the low-voltage (VDD) control logic of the core into the positive high voltage and negative high voltage required for erasing and programming. The logic process line cannot provide devices with various required voltages like the specific process of a flash memory. Therefore, the flash type FPGA must be designed using the breakdown voltage (break-down voltage) of devices based on the logic process. The maximum operating voltage that the logic process can usually provide for devices is 5V, and the break-down voltage is 12V. At the same time, the flash type FPGA is characterized in that the flash cell array is dispersed in small pieces throughout the chip, and the word lines and bit lines have relatively long traces and large loads. In order to ensure the driving of the word lines and bit lines, the sizes of the word lines and bit lines are designed relatively large, which also requires the pre-stage (i.e., the level conversion circuit) of the word lines and bit lines to have relatively large driving and relatively fast conversion speeds. Summary of the Invention

[0005] In view of the above problems and technical requirements, the inventor of the present invention has proposed a level conversion circuit based on a logic process for a flash type FPGA. The technical solution of the present invention is as follows:

[0006] A level conversion circuit based on a logic process for a flash type FPGA, characterized in that the level conversion circuit includes a first-stage conversion module, an intermediate-stage conversion module, and a driving-stage conversion module cascaded in sequence;

[0007] The first-level conversion module is used to convert the first signal in the VDD-GND voltage domain of the input into the second signal in the VP1-GND voltage domain and output it to the intermediate-level conversion module; the intermediate-level conversion module is used to convert the second signal in the VP1-GND voltage domain of the input into the third signal in the VP1-VN voltage domain and output it to the drive-level conversion module; the drive-level conversion module is used to convert the third signal in the VP1-VN voltage domain of the input into the drive signal in the VP2-VN voltage domain and output the word line for driving the flash-type FPGA.

[0008] The control logic process outputs the corresponding voltage combination to complete the erase operation or programming operation of the flash-type FPGA. The voltage combination includes the core low voltage VDD provided by the logic process, the intermediate voltage VP1 provided by the logic process, the drive-level voltage VP2 provided by the logic process, and the negative voltage VN. Among them, GND is the ground voltage, and VP2 ≥ VP1 ≥ VDD.

[0009] A further technical solution thereof is that when performing a programming operation on the flash-type FPGA, the voltage values of the core low voltage VDD, the intermediate voltage VP1, and the drive-level voltage VP2 provided by the control logic process increase in sequence, and the voltage value of the drive-level voltage VP2 is the positive high voltage HV required for programming the flash memory cell. The drive-level conversion module outputs the drive signal in the VP2-VN voltage domain to control the word line to apply the positive high voltage HV to the gate terminal of the flash memory cell to complete the programming operation.

[0010] A further technical solution thereof is that when performing an erase operation on the flash-type FPGA, the voltage values of the intermediate voltage VP1 and the drive-level voltage VP2 provided by the control logic process are equal to the voltage value of the core low voltage VDD. The negative voltage VN provided by the control logic process is the negative high voltage LV required for erasing the flash memory cell. The drive-level conversion module outputs the drive signal in the VP2-VN voltage domain to control the word line to apply the negative high voltage LV to the gate terminal of the flash memory cell to complete the erase operation.

[0011] A further technical solution thereof is that voltage-dividing switching transistors for voltage division are respectively arranged in the intermediate-level conversion module and the drive-level conversion module, and the voltage-dividing switching transistors in the two conversion modules are both controlled by the gate voltage control signal. The gate voltage control signal has different voltage values at different time periods in one working cycle of the level conversion circuit to adjust the state of the voltage-dividing switching transistor and reduce the working duration of the devices in the level conversion circuit under the breakdown voltage.

[0012] A further technical solution is that both the second signal and the third signal are differential signals. In the intermediate-stage conversion module, the sources of PMOS transistors P3, P4, P5, and P6 are connected together and connected to the intermediate voltage VP1. The drain of P4 is connected to the drain of NMOS transistor N3, and the source of N3 is connected to the drain of NMOS transistor N5. The drain of P5 is connected to the drain of NMOS transistor N4, and the source of N4 is connected to the drain of NMOS transistor N6. The sources of N5 and N6 are connected together and connected to the negative voltage VN. The drains of P3, the gate of P4, the drain of P5, and the gate of N5 are all connected together. The drains of P6, the gate of P5, the drain of P4, and the gate of N6 are all connected together. The gates of P3 and P6 are used as a differential pair to obtain the second signal, and the gates of N5 and N6 are used as a differential pair to output the third signal. N3 and N4 are used as voltage-dividing switch transistors in the intermediate-stage conversion module, and the gates of N3 and N4 are connected together and controlled by the gate voltage control signal.

[0013] A further technical solution is that both the third signal and the drive signal are differential signals. In the drive-stage conversion module, the sources of PMOS transistors P7 and P8 are connected together and connected to the drive-stage voltage VP2. The drain of P7 is connected to the gate of P8 and the drain of NMOS transistor N7. The drain of P8 is connected to the gate of P7 and the drain of NMOS transistor N8. The source of N7 is connected to the drain of NMOS transistor N9, and the source of N8 is connected to the drain of NMOS transistor N10. The sources of N9 and N10 are connected together and connected to the negative voltage VN. The gates of N9 and N10 are used as a differential pair to obtain the third signal, and the drains of N7 and N8 are used as a differential pair to output the drive signal. N7 and N8 are used as voltage-dividing switch transistors in the drive-stage conversion module, and the gates of N7 and N8 are connected together and controlled by the gate voltage control signal.

[0014] A further technical solution is that in any working cycle of performing a programming operation or an erasing operation on the flash-type FPGA, the working cycle sequentially includes a level conversion stage and a holding stage. The level conversion stage is used to complete the conversion of signals in different voltage domains, and the holding stage is used to maintain the state of the signals. During the holding stage of the working cycle, the voltage value of the gate voltage control signal is the negative voltage VN. The voltage-dividing switch transistors N3 and N4 in the intermediate-stage conversion module are turned off, and the voltage-dividing switch transistors N7 and N8 in the drive-stage conversion module are turned off. The state of the level conversion circuit is maintained by the voltage of the parasitic capacitance of the circuit without a pull-down drive. The charge existing on the parasitic capacitance holds the data but is less than the breakdown voltage of the device to protect P3, P4, P5, and P6 in the intermediate-stage conversion module, and to protect P7 and P8 in the drive-stage conversion module.

[0015] Among them, the parasitic capacitances in the intermediate-stage conversion module include the parasitic capacitance between P4 and N3 and the parasitic capacitance between P5 and N4 in the intermediate-stage conversion module, and the parasitic capacitances in the driving-stage conversion module include the parasitic capacitance between P7 and N7 and the parasitic capacitance between P8 and N8.

[0016] A further technical solution thereof is that, in any working cycle of performing a programming operation or an erasing operation on the flash type FPGA, during the level conversion stage at the start of the working cycle, the voltage value of the gate voltage control signal is equal to the intermediate voltage VP1; then when performing a programming operation on the flash type FPGA, the positive high voltage HV in the driving-stage conversion module cannot be transmitted to N9 and N10 due to the clamping of the voltage-dividing switching transistors N� and N8, improving the safety voltage tolerance of N7, N8, N9, and N10.

[0017] A further technical solution thereof is that, in any working cycle, the duration of the maintaining stage is greater than the duration of the level conversion stage.

[0018] A further technical solution thereof is that the first signal is a single-ended signal and the second signal is a differential signal. In the first-stage conversion module, the sources of the PMOS transistors P1 and P2 are connected together and connected to the intermediate voltage VP1, the drain of P1 is connected to the gate of P2 and the drain of the NMOS transistor N1, the drain of P2 is connected to the gate of P1 and the drain of the NMOS transistor N2, and the sources of N1 and N2 are connected together and connected to GND;

[0019] The source of the PMOS transistor P0 is connected to the core low voltage VDD, the drain of P0 is connected to the drain of the NMOS transistor N0, the source of N0 is connected to GND, the gates of P0 and N0 are connected together and obtain the first signal, the drain of P0 outputs the inverted signal of the first signal and is connected to the gate of N1, and the gate of N2 obtains the first signal; the drains of P1 and P2 output the second signal as a pair of differential pairs.

[0020] The beneficial technical effects of the present invention are:

[0021] The present application discloses a level conversion circuit based on a logic process for a flash type FPGA. The level conversion circuit performs three-level voltage conversion through three conversion modules, first converting to an intermediate voltage and then to the highest voltage, reducing the pressure of each-level conversion, ensuring the ability to drive the next level, improving the conversion speed, and providing a large driving ability for the last level.

[0022] In addition, considering that the level conversion circuit is designed based on the breakdown voltage of the device, and the device cannot operate at the breakdown voltage for a long time, a voltage-dividing switching transistor is connected in series in the level conversion circuit for voltage division. At the same time, by combining the timing control of the gate voltage control signal, the working time of the device at the breakdown voltage is reduced, thereby improving the reliability of the device. Brief Description of the Drawings

[0023] Figure 1 is the circuit diagram of the level conversion circuit in an embodiment.

[0024] Figure 2 is the schematic diagram of the voltage domain conversion of the signals in the level conversion circuit of the present application when performing a programming operation on a flash type FPGA.

[0025] Figure 3 is the schematic diagram of the voltage domain conversion of the signals in the level conversion circuit of the present application when performing an erasing operation on a flash type FPGA.

[0026] Figure 4 is the waveform schematic diagram of the first signal, the second signal, the third signal, the fourth signal and the gate voltage control signal in the level conversion circuit of the present application. Detailed Embodiment

[0027] The following further describes the detailed embodiments of the present invention with reference to the accompanying drawings.

[0028] The present application discloses a level conversion circuit based on a logic process for a flash type FPGA. Please refer to Figure 1 , the level conversion circuit includes a first-stage conversion module, an intermediate-stage conversion module and a driving-stage conversion module cascaded in sequence. The first-stage conversion module is used to convert the input first signal Sig1 in the VDD-GND voltage domain into a second signal Sig2 in the VP1-GND voltage domain and output it to the intermediate-stage conversion module. The intermediate-stage conversion module is used to convert the input second signal Sig2 in the VP1-GND voltage domain into a third signal Sig3 in the VP1-VN voltage domain and output it to the driving-stage conversion module. The driving-stage conversion module is used to convert the input third signal Sig3 in the VP1-VN voltage domain into a driving signal Sig4 in the VP2-VN voltage domain and output it to drive the word line of the flash type FPGA. The sizes of the devices in the driving-stage conversion module are all relatively large to ensure the driving ability.

[0029] During the working process, the control logic process outputs the corresponding voltage combination to complete the erasure operation or programming operation of the flash FPGA. The voltage combination includes the core low voltage VDD provided by the logic process, the intermediate voltage VP1 provided by the logic process, the driving stage voltage VP2 provided by the logic process, and the negative voltage VN. VP2≥VP1≥VDD. Among them, GND is the ground voltage at zero level, and VN<0.

[0030] When performing a programming operation on the flash FPGA, the voltage values of the core low voltage VDD, the intermediate voltage VP1, and the driving stage voltage VP2 provided by the control logic process increase in sequence, VDD<VP1<VP2. And the voltage value of the driving stage voltage VP2 is the positive high voltage HV required for programming the flash memory cell, VP2 = HV. Then the voltage domain relationship of each signal is as Figure 2 shown. In this state, the driving stage conversion module outputs a driving signal Sig4 in the VP2-VN voltage domain to control the word line to apply the positive high voltage HV to the gate terminal of the flash memory cell to complete the programming operation. For example, typically, the positive high voltage HV required for programming the flash memory cell is 8.8V, then VDD = 1.5V, VP1 = 3.6V, VP2 = 8.8V, VN = -2.5V can be controlled. At this time, the driving stage conversion module outputs the driving signal Sig4 to control the word line to apply 8.8V to the gate terminal of the flash memory cell.

[0031] When performing an erasure operation on the flash FPGA, the voltage values of the intermediate voltage VP1 and the driving stage voltage VP2 provided by the control logic process are equal to the voltage value of the core low voltage VDD, VDD = VP1 = VP2. The negative voltage VN provided by the control logic process is the negative high voltage LV required for erasing the flash memory cell, VN = LV. Then the voltage domain relationship of each signal is as Figure 3 shown. In this state, the driving stage conversion module outputs a driving signal Sig4 in the VP2-VN voltage domain to control the word line to apply the negative high voltage LV to the gate terminal of the flash memory cell to complete the erasure operation. For example, typically, the negative high voltage LV required for programming the flash memory cell is -9.5V, then VDD = VP1 = VP2 = 1.5V, VN = -9.5V can be controlled. At this time, the driving stage conversion module outputs the driving signal Sig4 to control the word line to apply -9.5V to the gate terminal of the flash memory cell.

[0032] Thus, through three conversion modules for three-level voltage conversion, first converting to the intermediate voltage and then to the highest voltage, the pressure of each level of conversion is reduced, the ability to drive the next level is ensured, the conversion speed is increased, and a larger driving ability is provided at the last level.

[0033] In one embodiment, the input first signal Sig1 is a single-ended signal, and the second signal Sig2, the third signal Sig3, and the drive signal Sig4 are all differential signals. Then, as Figure 1 shown, in the first-stage conversion module, the sources of PMOS transistors P1 and P2 are connected together and connected to the intermediate voltage VP1. The drain of P1 is connected to the gate of P2 and the drain of NMOS transistor N1. The drain of P2 is connected to the gate of P1 and the drain of NMOS transistor N2. The sources of N1 and N2 are connected together and connected to GND. P1, P2, N1, and N2 form a positive feedback structure for differential input. The source of PMOS transistor P0 is connected to the core low voltage VDD. The drain of P0 is connected to the drain of NMOS transistor N0. The source of N0 is connected to GND. The gates of P0 and N0 are connected together and receive the first signal Sig1. P0 and N0 form an inverter. The drain of P0 outputs the inverted signal Sig1_N of the first signal Sig1 and is connected to the gate of N1. The gate of N2 receives the first signal Sig1. The drains of P1 and P2 are used as a pair of differential outputs to output the second signal Sig2, including Sig2_P and Sig2_N. The drain of P1 outputs Sig2_P in phase with the first signal Sig1, and the drain of P2 outputs Sig2_N.

[0034] The intermediate-stage conversion module and the drive-stage conversion module mainly include a positive feedback structure for differential input. The positive feedback structures for differential input in the intermediate-stage conversion module are respectively connected to the intermediate voltage VP1 and the negative voltage VN. The positive feedback structures for differential input in the drive-stage conversion module are respectively connected to the drive-stage voltage VP2 and the negative voltage VN. In one embodiment, voltage-dividing switching transistors for voltage division are respectively provided in the intermediate-stage conversion module and the drive-stage conversion module, and the voltage-dividing switching transistors in the two conversion modules are both controlled by the gate voltage control signal V_CHG. The gate voltage control signal V_CHG is at different voltage values at different time periods in a working cycle of the level conversion circuit to adjust the states of the voltage-dividing switching transistors, reduce the working time of the devices in the level conversion circuit under the breakdown voltage, and thus improve the reliability of the devices in the level conversion circuit.

[0035] As Figure 1As shown, in the intermediate stage conversion module, the sources of PMOS transistors P3, P4, P5, and P6 are connected together and connected to the intermediate voltage VP1. The drain of P4 is connected to the drain of NMOS transistor N3, and the source of N3 is connected to the drain of NMOS transistor N5. The drain of P5 is connected to the drain of NMOS transistor N4, and the source of N4 is connected to the drain of NMOS transistor N6. The sources of N5 and N6 are connected together and connected to the negative voltage VN. The drains of P3, the gates of P4, the drains of P5, and the gates of N5 are all connected together. The drains of P6, the gates of P5, the drains of P4, and the gates of N6 are all connected together. The gates of P3 and P6 are used as a differential pair to obtain the second signal Sig2. The gate of P3 is connected to the drain of P1 to obtain Sig2_P, and the gate of P6 is connected to the drain of P2 to obtain Sig2_N. The gates of N5 and N6 are used as a differential pair to output the third signal Sig3 including Sig3_P and Sig3_N. The gate of N6 outputs Sig3_P in phase with the first signal Sig1, and the gate of N5 outputs the other path Sig3_N. N3 and N4 are used as voltage dividing switch transistors in the intermediate stage conversion module. The gates of N3 and N4 are connected together and controlled by the gate voltage control signal V_CHG.

[0036] In the driving stage conversion module, the sources of PMOS transistors P7 and P8 are connected together and connected to the driving stage voltage VP2. The drain of P7 is connected to the gate of P8 and the drain of NMOS transistor N7. The drain of P8 is connected to the gate of P7 and the drain of NMOS transistor N8. The source of N7 is connected to the drain of NMOS transistor N9. The source of N8 is connected to the drain of NMOS transistor N10. The sources of N9 and N10 are connected together and connected to the negative voltage VN. The gates of N9 and N10 are used as a differential pair to obtain the third signal Sig3. The gate of N9 is connected to the gate of N6 to obtain Sig3_P, and the gate of N10 is connected to the gate of N5 to obtain Sig3_N. The drains of N7 and N8 are used as a differential pair to output the driving signal Sig4 including Sig4_P and Sig4_N. The drain of N8 outputs Sig4_P in phase with the first signal Sig1, and the drain of N7 outputs the other path Sig4_N. N7 and N8 are used as voltage dividing switch transistors in the driving stage conversion module. The gates of N7 and N8 are connected together and controlled by the gate voltage control signal V_CHG.

[0037] During a working cycle of performing a programming operation on a flash - type FPGA, the working cycle sequentially includes a level - conversion stage and a holding stage. The level - conversion stage is used to complete the conversion of signals in different voltage domains, and the holding stage is used to maintain the state of the signals. (1) During the level - conversion stage in the time period from T0 to T1 at the start of the working cycle, the voltage value of the gate - voltage control signal V_CHG is equal to the intermediate voltage VP1, and when performing the programming operation, VDD < VP1 < VP2. The positive high - voltage HV in the driving - stage conversion module cannot be transmitted to N9 and N10 due to the clamping of the voltage - dividing switching transistors N7 and N8. At this time, the voltage differences between the gates, sources, and drains of N7, N8, N9, and N10 are all small, improving the safety voltage tolerance of N7, N8, N9, and N10. (2) During the holding stage in the time period from T1 to T2 of the working cycle, the voltage value of the gate - voltage control signal V_CHG is the negative voltage VN, the voltage - dividing switching transistors N3 and N4 in the intermediate - stage conversion module are turned off, and the voltage - dividing switching transistors N7 and N8 in the driving - stage conversion module are turned off. The state of the level - conversion circuit is maintained by the voltages of the parasitic capacitors C0, C1, C2, and C3 of the circuit without a pull - down drive. The charges existing on the parasitic capacitors C0, C1, C2, and C3 hold data but are less than the breakdown voltage of the device to protect P3, P4, P5, and P6 in the intermediate - stage conversion module and P7 and P8 in the driving - stage conversion module.

[0038] Among them, the parasitic capacitors in the intermediate - stage conversion module include the parasitic capacitor C0 between P4 and N3 in the intermediate - stage conversion module and the parasitic capacitor C1 between P5 and N4. The parasitic capacitor C2 in the driving - stage conversion module includes the parasitic capacitor between P7 and N7 and the parasitic capacitor C3 between P8 and N8.

[0039] During a working cycle of performing an erasing operation on a flash - type FPGA, the working cycle sequentially includes a level - conversion stage and a holding stage. The level - conversion stage is used to complete the conversion of signals in different voltage domains, and the holding stage is used to maintain the state of the signals. (1) During the level - conversion stage in the time period from T0 to T1 at the beginning of the working cycle, the voltage value of the gate - voltage control signal V_CHG is equal to the intermediate voltage VP1, and when performing the erasing operation, VDD = VP1 = VP2. (2) During the holding stage in the time period from T1 to T2 of the working cycle, the voltage value of the gate - voltage control signal V_CHG is the negative voltage VN, and when performing the erasing operation, VN = negative high voltage LV. Similar to performing a programming operation, the voltage - dividing switch transistors N3 and N4 in the intermediate - stage conversion module are turned off, and the voltage - dividing switch transistors N7 and N8 in the driving - stage conversion module are turned off. The state of the level - conversion circuit is maintained by the voltages of the parasitic capacitors C0, C1, C2, and C3 of the circuit without a pull - down drive. The charges existing on the parasitic capacitors C0, C1, C2, and C3 hold data but are less than the breakdown voltage of the device to protect P3, P4, P5, and P6 in the intermediate - stage conversion module and P7 and P8 in the driving - stage conversion module.

[0040] The durations of the level - conversion stage and the holding stage are set according to the actual situation. Generally, the duration of the level - conversion stage is set to be the duration of completing the conversion of the voltage domain of the signal and driving the word - line circuit, plus a certain design margin. After determining the duration of the level - conversion stage, the remaining duration of a working cycle is the holding stage. According to the actual simulation results, the longest duration of completing the conversion of the voltage domain of the signal is about 1.5 us. So, the level - conversion stage can be set to 2 us. If a working cycle is 10 us in total, then the duration of the holding stage is 8 us. In this example, the level - conversion stage can also be set to 3 us and the duration of the holding stage to 7 us. Generally, however, within any working cycle, the duration of the holding stage is greater than the duration of the level - conversion stage. Please refer to Figure 4 the waveform comparison schematic diagram shown.

[0041] In one example, during a programming cycle of a flash FPGA, VDD = 1.5V, VP1 = 3.6V, VP2 = 8.8V, and VN = -2.5V. The voltage difference between VP2 and VN is 11.3V, which is 0.7V below the 12V breakdown voltage of a 5V device. The gate voltages of N3, N4, N7, and N8 are controlled by a gate voltage control signal V_CHG. During the level shift phase T0-T1 at the beginning of each operating cycle, V_CHG = VP1 = 3.6V. The 8.8V voltage of VP2 cannot be transmitted to N9 and N10 due to the clamping of N7 and N8 in series. At this time, the voltage differences between the gate, source, and drain of N7, N8, N9, and N10 are relatively small, providing a large safety voltage margin. During the maintenance phase T1 to T2 of the remaining half of each working cycle, V_CHG = VN = -2.5V, and N3, N4, N7, and N8 are in the off state, thereby protecting P3, P4, P5, P6, P7, and P8.

[0042] During an erase cycle of a flash FPGA, VDD = VP1 = VP2 = 1.5V, and VN = -9.5V. The voltage difference between VP2 and VN is 11V, which is 1V below the 12V breakdown voltage of a 5V device. The gate voltages of N3, N4, N7, and N8 are controlled by the gate voltage control signal V_CHG. During the level shift phase (T0-T1) at the beginning of each operating cycle, V_CHG = VP1 = 1.5V. During the hold phase (T1-T2) of the remaining half of each operating cycle, V_CHG = VN = -9.5V, turning off N3, N4, N7, and N8, thereby protecting P3, P4, P5, P6, P7, and P8.

[0043] The above description is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is understood that other improvements and variations directly derived or imagined by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included in the scope of protection of the present invention.

Claims

1. A level conversion circuit based on a logic process for a flash-type FPGA, characterized in that The level conversion circuit includes a first-stage conversion module, an intermediate-stage conversion module, and a driving-stage conversion module connected in cascade in sequence; The first-stage conversion module is configured to convert a first signal in the VDD-GND voltage domain input thereto into a second signal in the VP1-GND voltage domain and output the second signal to the intermediate-stage conversion module; the intermediate-stage conversion module is configured to convert the second signal in the VP1-GND voltage domain input thereto into a third signal in the VP1-VN voltage domain and output the third signal to the driving-stage conversion module; the driving-stage conversion module is configured to convert the third signal in the VP1-VN voltage domain input thereto into a driving signal in the VP2-VN voltage domain and output the driving signal to control the word line of the flash-type FPGA; The control logic process outputs a corresponding voltage combination to complete the erasing operation or programming operation of the flash-type FPGA. The voltage combination includes the core low voltage VDD provided by the logic process, the intermediate voltage VP1 provided by the logic process, the driving-stage voltage VP2 provided by the logic process, and the negative voltage VN. Wherein, GND is the ground voltage, and VP2≥VP1≥VDD; When performing the erasing operation on the flash-type FPGA, the voltage values of the intermediate voltage VP1 and the driving-stage voltage VP2 provided by the control logic process are equal to the voltage value of the core low voltage VDD, and the negative voltage VN provided by the control logic process is the negative high voltage LV required for erasing the flash memory cell. The driving-stage conversion module outputs a driving signal in the VP2-VN voltage domain to control the word line to apply the negative high voltage LV to the gate terminal of the flash memory cell to complete the erasing operation.

2. The level conversion circuit according to claim 1, wherein When performing the programming operation on the flash-type FPGA, the voltage values of the core low voltage VDD, the intermediate voltage VP1, and the driving-stage voltage VP2 provided by the control logic process increase in sequence, and the voltage value of the driving-stage voltage VP2 is the positive high voltage HV required for programming the flash memory cell. The driving-stage conversion module outputs a driving signal in the VP2-VN voltage domain to control the word line to apply the positive high voltage HV to the gate terminal of the flash memory cell to complete the programming operation.

3. The level conversion circuit according to claim 1, wherein Voltage-dividing switching tubes for voltage division are respectively arranged in the intermediate-stage conversion module and the driving-stage conversion module, and the voltage-dividing switching tubes in the two conversion modules are both controlled by a gate voltage control signal. The gate voltage control signal is different voltage values at different time periods of a working cycle of the level conversion circuit to adjust the states of the voltage-dividing switching tubes and reduce the working duration of the devices in the level conversion circuit under the breakdown voltage.

4. The level conversion circuit according to claim 3, characterized in that Both the second signal and the third signal are differential signals. In the intermediate-stage conversion module, the sources of PMOS transistors P3, P4, P5, and P6 are connected together and connected to the intermediate voltage VP1. The drain of P4 is connected to the drain of NMOS transistor N3, and the source of N3 is connected to the drain of NMOS transistor N5. The drain of P5 is connected to the drain of NMOS transistor N4, and the source of N4 is connected to the drain of NMOS transistor N6. The sources of N5 and N6 are connected together and connected to the negative voltage VN. The drains of P3, the gate of P4, the drain of P5, and the gate of N5 are all connected together. The drains of P6, the gate of P5, the drain of P4, and the gate of N6 are all connected together. The gates of P3 and P6 serve as a differential pair for obtaining the second signal, and the gates of N5 and N6 serve as a differential pair for outputting the third signal. N3 and N4 serve as voltage-dividing switch transistors in the intermediate-stage conversion module, and the gates of N3 and N4 are connected together and controlled by the gate voltage control signal.

5. The level conversion circuit according to claim 3, wherein Both the third signal and the drive signal are differential signals. In the drive-stage conversion module, the sources of PMOS transistors P7 and P8 are connected together and connected to the drive-stage voltage VP2. The drain of P7 is connected to the gate of P8 and the drain of NMOS transistor N7. The drain of P8 is connected to the gate of P7 and the drain of NMOS transistor N8. The source of N7 is connected to the drain of NMOS transistor N9. The source of N8 is connected to the drain of NMOS transistor N10. The sources of N9 and N10 are connected together and connected to the negative voltage VN. The gates of N9 and N10 serve as a differential pair for obtaining the third signal, and the drains of N7 and N8 serve as a differential pair for outputting the drive signal. N7 and N8 serve as voltage-dividing switch transistors in the drive-stage conversion module, and the gates of N7 and N8 are connected together and controlled by the gate voltage control signal.

6. The level conversion circuit according to claim 4 or 5, characterized in that, During any one working cycle of performing a programming operation or an erasing operation on the flash-type FPGA, the working cycle sequentially includes a level conversion stage and a holding stage. The level conversion stage is used to complete the conversion of signals in different voltage domains, and the holding stage is used to maintain the state of the signals. During the holding stage of the working cycle, the voltage value of the gate voltage control signal is the negative voltage VN. The voltage-dividing switch transistors N3 and N4 in the intermediate-stage conversion module are turned off, and the voltage-dividing switch transistors N7 and N8 in the drive-stage conversion module are turned off. The state of the level conversion circuit is maintained by the voltage of the parasitic capacitance of the circuit without a pull-down drive. The charge existing on the parasitic capacitance holds data but is less than the breakdown voltage of the device to protect P3, P4, P5, and P6 in the intermediate-stage conversion module, and to protect P7 and P8 in the drive-stage conversion module. Among them, the parasitic capacitance in the intermediate-stage conversion module includes the parasitic capacitance between P4 and N3 and the parasitic capacitance between P5 and N4 in the intermediate-stage conversion module. The parasitic capacitance in the drive-stage conversion module includes the parasitic capacitance between P7 and N7 and the parasitic capacitance between P8 and N8.

7. The level conversion circuit according to claim 6, wherein During any working cycle of performing a programming operation or an erasing operation on the flash type FPGA, within the level conversion stage of the working cycle, the voltage value of the gate voltage control signal is equal to the intermediate voltage VP1; then when performing a programming operation on the flash type FPGA, the positive high voltage HV in the driving stage conversion module cannot be transmitted to N9 and N10 due to the clamping of the voltage dividing switching transistors N7 and N8, improving the safety voltage tolerance of N7, N8, N9, and N10.

8. The level conversion circuit according to claim 7, wherein During any working cycle, the duration of the holding stage is greater than the duration of the level conversion stage.

9. The level conversion circuit according to claim 1, wherein The first signal is a single-ended signal, and the second signal is a differential signal. In the first-stage conversion module, the sources of the PMOS transistors P1 and P2 are connected together and connected to the intermediate voltage VP1. The drain of P1 is connected to the gate of P2 and the drain of the NMOS transistor N1. The drain of P2 is connected to the gate of P1 and the drain of the NMOS transistor N2. The sources of N1 and N2 are connected together and connected to GND; The source of the PMOS transistor P0 is connected to the core low voltage VDD. The drain of P0 is connected to the drain of the NMOS transistor N0. The source of N0 is connected to GND. The gates of P0 and N0 are connected together and receive the first signal. The drain of P0 outputs the inverted signal of the first signal and is connected to the gate of N1. The gate of N2 receives the first signal. The drains of P1 and P2 output the second signal as a pair of differential pairs.

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