Pixel structure and method for manufacturing a pixel structure

Abstract

A pixel structure (2003) and a manufacturing method of the pixel structure (2003), the pixel structure (2003) comprising: a modulation gate group, the modulation gate group comprising: at least one first modulation gate (PGA) and at least one second modulation gate (PGB) arranged on a first surface (2011) of a substrate (201), the second modulation gate (PGB) and the first modulation gate (PGA) are respectively complementary modulation; and the substrate (201) comprising: two carrier storage regions, respectively located on two sides of the substrate (201) in a first direction, the first direction being a direction parallel to the first surface (2011); and a carrier collection region (202) located between the two carrier storage regions in the first direction and in contact with the modulation gate group on the first surface (2011), wherein the carrier collection region (202) and the two carrier storage regions have the same doping type, the carrier collection region (202) and the substrate (201) have opposite doping types, and the doping concentration of the carrier collection region (202) is greater than the doping concentration of the substrate (201).

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a pixel structure and a method for manufacturing the pixel structure. Background Technology

[0002] 3D imaging based on Time of Flight (TOF) is a technology that measures the time of flight of light waves to generate depth information. Modulated light waves generated by a laser are reflected after encountering an object and received by a sensor. The 3D information of the object is calculated by determining the time difference between the emission and reflection of the light.

[0003] like Figure 1 As shown, Indirect Time of Flight (i-TOF) technology calculates the time of flight by comparing the phase difference between the received reflected light and the emitted light, thereby obtaining the depth information of the measured object. Specifically, it uses control signals of different phases to modulate and collect photogenerated carriers, integrating them over different time periods to ultimately calculate the phase difference between the reflected and emitted signals.

[0004] As mentioned above, the pixel design for i-TOF aims to achieve modulation within the pixel structure: collecting and reading photogenerated carriers generated by the device at different time intervals. The specific design is as follows... Figure 2 As shown, there are usually two complementary TAPs: TAPA and TAPB. Ideally, the photogenerated carriers generated in time period A are Sa, and all Sa are collected by TAPA. The photogenerated carriers generated in other time periods (time period B) are Sb, and all Sb are collected by TAPB. Typically, the switching frequency of TAPA and TAPB matches the modulation frequency of the infrared light emitted by the laser. A performance metric for evaluating pixel design quality is modulation contrast (MC), also known as modulation and demodulation efficiency, where MC satisfies the following formula:

[0005] MC=(Sa-Sb) / (Sa+Sb)(Equation 1).

[0006] Based on the above, if the light is only emitted during time period A, TAPA will collect all the photogenerated carriers Sa, and TAPB will collect carriers Sb = 0. Substituting Sb = 0 into Equation 1, we get MC = 100%. However, due to non-ideal factors in the device design, a portion of the photogenerated carriers generated during time period A will be collected by TAPB, and the actual MC will be lower than 100%.

[0007] In 3D imaging, due to factors such as noise and modulation frequency limitations, the distance to an object measured by an i-TOF camera is not 100% accurate. The basic idea for improving ranging accuracy is to allow pixels to absorb as much effective modulated light as possible and to more precisely distribute the generated charge carriers to different gates. Furthermore, the higher the frequency of this modulation process, the higher the accuracy.

[0008] Currently, to improve the spatial resolution of i-TOF cameras, TOF pixel structures are evolving towards smaller pixel structures. Smaller pixel structures lead to reduced light intake, thus decreasing the ranging accuracy of i-TOF. To compensate for this loss of light intake, i-TOF pixels need to achieve high modulation contrast at high modulation frequencies.

[0009] A major factor affecting the MC at high frequencies (>100MHz) is the carrier collection rate. For example... Figure 3 As shown, due to the low absorption coefficient of silicon devices for near-infrared light, TOF devices require a relatively thick silicon layer (>4µm) to absorb sufficient infrared light. Furthermore, the potential change at the bottom of the device is very small, resulting in low carrier velocity and a longer time required to reach the collection point at the top.

[0010] If these charge carriers generated at the bottom are not effectively collected at the designated collection point within a sufficiently short time, they will be collected by other collection points in subsequent time periods, leading to a decrease in MC and affecting ranging accuracy. Moreover, this problem of MC decrease due to excessively long charge carrier collection time is more severe at high frequencies. Summary of the Invention

[0011] This application provides a pixel structure and a method for manufacturing the pixel structure, which solves the problem of low modulation and demodulation efficiency of small pixel structures.

[0012] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0013] A first aspect of this application provides a pixel structure, comprising: a modulation gate group, the modulation gate group comprising: at least one first modulation gate, respectively disposed sequentially on a first surface of a substrate; at least one second modulation gate, respectively disposed sequentially on the first surface, the at least one second modulation gate and the at least one first modulation gate being complementaryly modulated; and the substrate comprising: at least two carrier storage regions, the at least two carrier storage regions comprising: a first carrier storage region and a second carrier storage region located on opposite sides of the substrate in a first direction, the first direction being a direction parallel to the first surface; and a carrier collection region located between the at least two carrier storage regions in the first direction and in contact with the at least one first modulation gate and the at least one second modulation gate on the first surface, wherein the carrier collection region has the same doping type as the at least two carrier storage regions and the carrier collection region has the opposite doping type to the substrate. Thus, a PN junction depletion region is formed at the location adjacent to the substrate in the carrier collection region. The substrate ions on both sides of the PN junction depletion region have opposite electrical charges, creating an electric field. When the electric field is sufficient to prevent further transfer of holes and electrons, the PN junction depletion region reaches its equilibrium size.

[0014] Furthermore, the doping concentration of the carrier collection region is greater than that of the substrate. Therefore, during the formation of the aforementioned PN junction depletion region, the formed PN junction depletion region is more biased towards the substrate. When the substrate is irradiated, carriers are generated inside the substrate. Because the PN junction depletion region is more biased towards the substrate, the carriers within the substrate enter the carrier collection region under the influence of the electric field of the PN junction depletion region. In the prior art, the carrier concentration at the bottom of the substrate is low, and the potential change is limited to a very shallow region from one surface inwards. This results in low carrier velocity at the bottom of the substrate, requiring a longer time to reach the carrier collection point on the first surface, affecting the modulation and demodulation efficiency of the pixel structure. In this application, the substrate potential changes more uniformly from the first surface to the bottom of the substrate, increasing the carrier velocity at the bottom of the substrate, allowing carriers to be collected quickly, improving the modulation and demodulation efficiency of the pixel structure, and thus improving ranging accuracy.

[0015] In one optional implementation, the carrier collection region includes: a first doped region and a second doped region, located on either side of the carrier collection region in the first direction; and a third doped region, located between the first doped region and the second doped region, wherein the doping concentration of the first doped region and the second doped region is greater than the doping concentration of the third doped region. Therefore, when the pixel structure is reset, the carriers in the substrate are concentrated on the first surface of the substrate. If the carrier collection region uses a single doping concentration, a local potential well is formed in the middle of the substrate surface, preventing the carriers from being removed during the reset process. If the carrier collection region uses a doping method where the first and second doped regions on either side of the carrier collection region have high doping concentrations, while the third doped region in the middle of the carrier collection region has a low doping concentration, the formation of a local potential well in the middle is avoided. This facilitates the smooth removal of carriers in the middle of the first surface of the substrate during the reset process, making the pixel structure easier to reset.

[0016] In one optional implementation, the at least two carrier storage regions include a first carrier storage region and a second carrier storage region. The first carrier storage region is close to the first modulation gate and far from the second modulation gate, and the second carrier storage region is close to the second modulation gate and far from the first modulation gate. The at least one first modulation gate and the at least one second modulation gate are disposed on the first surface along the first direction. The at least one first modulation gate includes a first end closest to the first carrier storage region and a second end far from the first carrier storage region. The at least one second modulation gate also includes a first end closest to the second carrier storage region and a second end far from the second carrier storage region. The first doped region is located between the first and second ends of the at least one first modulation gate in the first direction, and the second doped region is located between the first and second ends of the at least one second modulation gate in the first direction. Thus, a distance is provided between the first carrier storage region and the first doped region for modulation by the first modulation gate, and a distance is provided between the second carrier storage region and the second doped region for modulation by the second modulation gate.

[0017] In one optional implementation, the doping concentration of the first doped region is 10-100 times that of the third doped region, and the doping concentration of the second doped region is 10-100 times that of the third doped region. This increases the concentration difference between the first and third doped regions, as well as between the second and third doped regions, which is beneficial for pixel structure repositioning.

[0018] In one optional implementation, the first doped region and the second doped region are symmetrically arranged with respect to a first axis, and the third doped region is also symmetrical with respect to the first axis, wherein the first axis is perpendicular to the first surface. Thus, when at least one first modulation gate and at least one second modulation gate are complementaryly modulated, the ability of charge carriers in the substrate to enter the first charge carrier storage region and the second charge carrier storage region is the same.

[0019] In one optional implementation, the at least one first modulation gate and the at least one second modulation gate are disposed on the first surface along the first direction. The at least two carrier storage regions include a first carrier storage region and a second carrier storage region. The first carrier storage region is close to the first modulation gate and far from the second modulation gate, and the second carrier storage region is close to the second modulation gate and far from the first modulation gate. The at least one first modulation gate includes a first end closest to the first carrier storage region and a second end far from the first carrier storage region. The at least one second modulation gate includes a first end closest to the second carrier storage region and a second end far from the second carrier storage region. The carrier collection region is located between the first ends of the at least one first modulation gate and the first ends of the at least one second modulation gate in the first direction. Thus, a distance is provided between the first carrier storage region and the carrier collection region for the first modulation gate to regulate, and a distance is provided between the second carrier storage region and the carrier collection region for the second modulation gate to regulate.

[0020] In one optional implementation, the length of the carrier collection region is equal to the length of the substrate in a direction perpendicular to the first surface. This allows PN junction depletion regions to be formed on the substrate on both sides of the carrier collection region, enabling carriers in the substrate on both sides of the carrier collection region to flow into the carrier collection region under the influence of the electric field of the PN junction depletion region, thereby improving the modulation and demodulation efficiency of the pixel structure.

[0021] In one alternative implementation, the length of the carrier collection region is less than the length of the substrate in a direction perpendicular to the first surface. This allows a PN junction depletion region to be formed at the bottom of the substrate, enabling carriers at the bottom of the substrate to flow into the carrier collection region under the influence of the electric field in the PN junction depletion region, thereby improving the modulation and demodulation efficiency of the pixel structure.

[0022] In one optional implementation, the carrier storage region includes: a first carrier storage region adjacent to the at least one first modulation gate, and a second carrier storage region adjacent to the at least one second modulation gate; wherein a first gate is disposed between the at least one first modulation gate and the first carrier storage region, and a second gate is disposed between the at least one second modulation gate and the second carrier storage region; wherein the at least one first modulation gate and the at least one second modulation gate are used to receive AC modulation signals, and the first gate and the second gate are used to receive DC modulation signals. Thus, the DC signal received by the first gate can shield the influence of the AC signal received by the at least one first modulation gate on the first carrier storage region. Similarly, the DC signal received by the second gate can shield the influence of the AC signal received by the at least one second modulation gate on the second carrier storage region.

[0023] In one optional implementation, the doping concentration of the carrier collection region is 1000-10000 times that of the substrate. This increases the concentration difference between the carrier collection region and the substrate, which is beneficial for the depletion region of the PN junction to be biased towards the substrate. This makes it easier for carriers in the substrate to enter the carrier collection region under the influence of an electric field, thereby improving the modulation and demodulation efficiency of the pixel structure.

[0024] In one alternative implementation, the carrier collection region is P-type doped and the substrate is N-type doped; or, the carrier collection region is N-type doped and the substrate is P-type doped. This facilitates the formation of a PN junction depletion region between the substrate and the carrier collection region, improving the modulation and demodulation efficiency of the pixel structure.

[0025] In one optional implementation, the modulation gate group further includes: at least one third modulation gate, each sequentially disposed on a first surface of the substrate; and at least one fourth modulation gate, each sequentially disposed on the first surface. The at least one first modulation gate, the at least one second modulation gate, the at least one third modulation gate, and the at least one fourth modulation gate are complementaryly modulated. The first modulation gate and the second modulation gate are centrally symmetrical about the first surface, and the third modulation gate and the fourth modulation gate are also centrally symmetrical about the first surface. The at least two carrier storage regions further include: a third carrier storage region and a fourth carrier storage region located on opposite sides of the substrate in a second direction, the second direction being parallel to the first surface and perpendicular to the first direction. The carrier collection region is located between the third carrier storage region and the fourth carrier storage region in the second direction. This allows for more flexible modulation of the modulation gates.

[0026] A second aspect of this application provides a method for manufacturing a pixel structure. The method includes: forming at least two carrier storage regions on a substrate by ion implantation, wherein the at least two carrier storage regions include a first carrier storage region and a second carrier storage region located on opposite sides of the substrate in a first direction, the first direction being parallel to a first surface; forming a carrier collection region on the substrate by ion implantation; wherein the carrier collection region is located between the first carrier storage region and the second carrier storage region in the first direction, the doping concentration of the carrier collection region is greater than the doping concentration of the substrate, the doping type of the carrier collection region is the same as that of the at least two carrier storage regions, and the doping type of the carrier collection region is opposite to that of the substrate; and disposing at least one first modulation gate and at least one second modulation gate on a first surface of the substrate; wherein the at least one second modulation gate and the at least one first modulation gate are complementaryly modulated, and the carrier collection region is in contact with the at least one first modulation gate and the at least one second modulation gate on the first surface.

[0027] In one optional implementation, the at least two carrier storage regions include a first carrier storage region and a second carrier storage region. The first carrier storage region is close to the first modulation gate and far from the second modulation gate, and the second carrier storage region is close to the second modulation gate and far from the first modulation gate. The at least one first modulation gate includes a first end closest to the first carrier storage region and a second end furthest from the first carrier storage region. The at least one second modulation gate includes a first end closest to the second carrier storage region and a second end furthest from the second carrier storage region. The provisioning of at least one first modulation gate and at least one second modulation gate on the first surface of the substrate includes: disposing the at least one first modulation gate and the at least one second modulation gate along the first direction on the first surface, such that the carrier collection region is located between the first end of the at least one first modulation gate and the first end of the at least one second modulation gate in the first direction.

[0028] In one optional implementation, forming a carrier collection region on a substrate by ion implantation includes: forming a first doped region and a second doped region on the substrate by ion implantation; wherein the first doped region and the second doped region are located on opposite sides of the carrier collection region in a first direction; and forming a third doped region on the substrate by ion implantation, wherein the doping concentrations of the first doped region and the second doped region are both greater than the doping concentration of the third doped region, and the third doped region is located between the first doped region and the second doped region.

[0029] In one optional implementation, forming a carrier collection region on a substrate by ion implantation includes: forming a first doped region and a second doped region on the substrate by ion implantation; wherein the first doped region and the second doped region are located on opposite sides of the carrier collection region in a first direction; ions from the first doped region and the second doped region diffuse to a third region to form a third doped region, wherein the doping concentration of the first doped region and the second doped region is greater than the doping concentration of the third doped region, and the third doped region is located between the first doped region and the second doped region.

[0030] In one optional implementation, the at least two carrier storage regions include a first carrier storage region and a second carrier storage region. The first carrier storage region is close to the first modulation gate and far from the second modulation gate, and the second carrier storage region is close to the second modulation gate and far from the first modulation gate. The at least one first modulation gate includes a first end closest to the first carrier storage region and a second end furthest from the first carrier storage region. The at least one second modulation gate includes a first end closest to the second carrier storage region and a second end furthest from the second carrier storage region. The provisioning of at least one first modulation gate and at least one second modulation gate on the first surface of the substrate includes: disposing the at least one first modulation gate and the at least one second modulation gate along the first direction on the first surface, such that the first doped region is located between the first end and the second end of the at least one first modulation gate in the first direction, and such that the second doped region is located between the first end and the second end of the at least one second modulation gate in the first direction.

[0031] In one optional implementation, the doping concentration of the first doped region is 10-100 times that of the third doped region, and the doping concentration of the second doped region is 10-100 times that of the third doped region.

[0032] In one optional implementation, the first doped region and the second doped region are symmetrically arranged with respect to the first axis, and the third doped region is symmetrical with respect to the first axis, wherein the first axis is perpendicular to the first surface.

[0033] In one alternative implementation, the length of the carrier collection region in a direction perpendicular to the first surface is less than or equal to the length of the substrate.

[0034] In one optional implementation, the at least two carrier storage regions include: a first carrier storage region adjacent to the at least one first modulation gate, and a second carrier storage region adjacent to the at least one second modulation gate. The method further includes: disposing a first gate between the at least one first modulation gate and the first carrier storage region; and disposing a second gate between the at least one second modulation gate and the second carrier storage region; wherein the first modulation gate and the second modulation gate are used to receive AC modulation signals, and the first gate and the second gate are used to receive DC modulation signals.

[0035] In one alternative implementation, the doping concentration of the carrier collection region is 1,000 to 10,000 times that of the substrate.

[0036] In one alternative implementation, the carrier collection region is p-type doped and the substrate is n-type doped; or, the carrier collection region is n-type doped and the substrate is p-type doped.

[0037] In one optional implementation, the modulation gate group further includes: at least one third modulation gate, which is sequentially disposed on a first surface of the substrate; at least one fourth modulation gate, which is sequentially disposed on the first surface, wherein the at least one first modulation gate, the at least one second modulation gate, the at least one third modulation gate, and the at least one fourth modulation gate are complementaryly modulated; the first modulation gate and the second modulation gate are centrally symmetrical about the first surface, and the third modulation gate and the fourth modulation gate are centrally symmetrical about the first surface; the at least two carrier storage regions further include: a third carrier storage region and a fourth carrier storage region located on opposite sides of the substrate in a second direction, wherein the second direction is parallel to the first surface and perpendicular to the first direction; the carrier collection region is located between the third carrier storage region and the fourth carrier storage region in the second direction. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of an i-TOF image acquisition method in the prior art;

[0039] Figure 2 This is a schematic diagram of carrier transmission in a pixel structure in the prior art;

[0040] Figure 3 This is a schematic diagram illustrating another method of carrier transport in a pixel structure in the prior art.

[0041] Figure 4 This is a schematic diagram of the structure of a terminal device provided in an embodiment of this application;

[0042] Figure 5 for Figure 4 A schematic diagram of the structure of the display module;

[0043] Figure 6a This is a schematic diagram of the structure of another terminal device provided in an embodiment of this application;

[0044] Figure 6b This is a schematic diagram of depth image acquisition provided in an embodiment of this application;

[0045] Figure 7 for Figure 6b A schematic diagram of the structure of a central camera;

[0046] Figure 7a A top view of the pixel structure provided in the embodiments of this application;

[0047] Figure 7b for Figure 7a AA section view in the middle;

[0048] Figure 7c for Figure 7b A schematic diagram of carrier transport within a pixel structure;

[0049] Figure 7d A top view of another pixel structure provided in an embodiment of this application;

[0050] Figure 8 A graph showing the internal potential change of a pixel structure provided in an embodiment of this application;

[0051] Figure 9 A schematic diagram of another pixel structure provided in an embodiment of this application;

[0052] Figure 10 A potential change curve of the first surface of the pixel structure provided in the embodiments of this application;

[0053] Figure 11 This is a schematic diagram of another pixel structure provided in an embodiment of this application;

[0054] Figure 12a This is a schematic diagram of another pixel structure provided in an embodiment of this application;

[0055] Figure 12b This is a schematic diagram of another pixel structure provided in an embodiment of this application;

[0056] Figure 13a This is a schematic diagram of another pixel structure provided in an embodiment of this application;

[0057] Figure 13b This is a schematic diagram of another pixel structure provided in an embodiment of this application;

[0058] Figure 14 This is a schematic diagram of another pixel structure provided in an embodiment of this application;

[0059] Figure 15 A flowchart illustrating a method for manufacturing a pixel structure according to an embodiment of this application;

[0060] Figure 15a , Figure 15b , Figure 15c To execute Figure 15 A schematic diagram of the product structure obtained after each step;

[0061] Figure 16 A flowchart illustrating another method for manufacturing a pixel structure provided in this application embodiment;

[0062] Figure 16a , Figure 16b To execute Figure 16 A schematic diagram of the product structure obtained after each step;

[0063] Figure 17 A flowchart illustrating another method for manufacturing a pixel structure provided in this application embodiment;

[0064] Figure 18 A flowchart illustrating another method for manufacturing a pixel structure provided in this application embodiment;

[0065] Figure 18a To execute Figure 18 A schematic diagram of the product structure obtained after each step. Detailed Implementation

[0066] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0067] In the following description, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0068] Furthermore, in this application, directional terms such as "upper" and "lower" are defined relative to the orientation of the components shown in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and can change accordingly depending on the orientation of the components in the accompanying drawings.

[0069] The following explains the terminology that may appear in the embodiments of this application.

[0070] N-type doping (N stands for Negative, named for the negative charge of electrons): In silicon (or germanium) crystals doped with a small amount of phosphorus (or antimony) impurities, because the semiconductor atoms (such as silicon atoms) are replaced by impurity atoms, four of the five outer electrons of the phosphorus atom form covalent bonds with the surrounding semiconductor atoms, leaving the extra electron almost unbound and relatively easy to become a free electron. Thus, N-type semiconductors become semiconductors with a high electron concentration, and their conductivity is mainly due to the conductivity of free electrons.

[0071] P-type doping (P stands for Positive, named for the positive charge of holes): In silicon (or germanium) crystals doped with a small amount of impurity boron (or indium), when the semiconductor atoms (such as silicon atoms) are replaced by impurity atoms, a "hole" is created when the three outer electrons of the boron atom form covalent bonds with the surrounding semiconductor atoms. This hole may attract bound electrons to "fill" it, making the boron atom a negatively charged ion. Thus, this type of semiconductor, containing a high concentration of "holes" ("equivalent" to positive charge), becomes a conductive material.

[0072] PN junction depletion layer: Compared to the P-type region, the N-type semiconductor has an excess of free electrons, and compared to the P-type region, the P-type has an excess of holes. Therefore, when N-doped and P-doped semiconductor wafers are placed together to form a junction, electrons migrate to the P-side and holes migrate to the N-side. The departure of electrons from the N-side to the P-side leaves positive donor ions behind the N-side, and similarly leaves negative acceptor ions on the P-side.

[0073] After the transfer, the diffused electrons come into contact with holes on the P-side and are eliminated through recombination. The same applies to the diffusion holes on the N-side. The end result is that the diffused electrons and holes disappear, leaving behind charged ions adjacent to the interface in a region without moving carriers (this is why it's called the depletion region, where carriers are depleted). Uncompensated ions are positive on the N-side and negative on the P-side. This creates an electric field that provides a force against the continued exchange of charge carriers. When the electric field is strong enough to prevent further transfer of holes and electrons, the depletion region reaches its equilibrium size.

[0074] Charge carriers: There are two types of charge carriers in semiconductors: electrons and holes. They are charged particles that can move in a directed manner under the influence of an electric field.

[0075] Ion implantation: When an ion beam is directed at a solid material in a vacuum, it is resisted by the solid material and its speed gradually decreases until it eventually remains in the solid material. This phenomenon is called ion implantation.

[0076] This application provides a terminal device. The terminal device includes, for example, a mobile phone, tablet computer, personal digital assistant (PDA), in-vehicle computer, etc. This application does not impose any special limitations on the specific form of the aforementioned terminal device. For ease of explanation, the following description uses a terminal device as an example. Figure 4 The explanation is based on the mobile phone shown.

[0077] The aforementioned terminal device 01, such as Figure 4 As shown, the main components include, but are not limited to, the display module 10. This includes the display module 10, the mid-frame 11, and the back cover 12. The side of the mid-frame 11 facing the display module 10 supports the display module 10, while the side facing the back cover 12 houses internal components such as a battery, printed circuit board (PCB), camera, and antenna. The back cover 12 is fastened to the mid-frame 11 to protect these internal components.

[0078] In some embodiments of this application, such as Figure 5 As shown, the display module 10 includes a display panel (DP) 101. The display panel 101 can be a liquid crystal display (LCD). In this case, the display module 10 also includes a back light unit (BLU) 102 for providing a light source to the LCD.

[0079] Alternatively, in some other embodiments of this application, the above-mentioned display screen 101 can be an organic light emitting diode (OLED) display screen, which is capable of self-illumination, so the above-mentioned BLU 102 does not need to be provided in the display module 10.

[0080] Furthermore, the above description is based on the example of a terminal device 01 including one display module 10. In some embodiments, the terminal device 01 may include one or at least two display modules 10.

[0081] Furthermore, as the integration level of terminal device 01 increases, terminal device 01 may also include, for example... Figure 6a The camera 100 shown is a depth camera, capable of acquiring depth information of the object being photographed, in order to achieve gesture recognition or facial recognition, etc.

[0082] The aforementioned camera 100 can be based on TOF 3D imaging technology, such as... Figure 6bAs shown, the camera 100 sends a modulated emitted light signal S1 to the object being photographed, such as a face. After the light signal S1 is reflected by the face, the resulting reflected light signal S2 is received by the camera 100. This allows the camera 100 to obtain the depth information (i.e., distance information) of the object being measured by calculating the time difference between the emitted light signal S1 and the reflected light signal S2, thereby achieving face recognition. In some embodiments, the terminal device 01 may include at least one camera 100.

[0083] In some embodiments of this application, the camera 100 includes a lens and, as in... Figure 7 The image sensor 200 shown includes a plurality of pixel units 2001 and a substrate 2002. Each pixel unit 2001 and the substrate disposed below the pixel unit 2001 form a pixel structure 2003.

[0084] The aforementioned camera 100 also includes a readout circuit 210, a control circuit 211, and an image processing circuit 212 coupled to the pixel circuit of the pixel unit 2001. The control circuit 211 performs photoelectric conversion on the pixel unit 2001 and transmits the converted electrical signal to the readout circuit 210 during the readout time of the pixel circuit. The readout circuit 210 can perform analog-to-digital conversion and signal amplification on the input signal.

[0085] Next, the readout circuit 210 transmits the processed electrical signal to the image processing circuit 212. The image processing circuit 212 can use image signal processing (ISP) technology to generate a digital image signal based on the received electrical signal, and then use digital signal processing (DSP) to convert the digital image signal into depth information.

[0086] Figure 7a This is a top view of the pixel structure provided in the embodiments of this application. Figure 7b for Figure 7a AA section view in the image. Figure 7a , Figure 7b As shown, the pixel structure 2003 includes a substrate 201. This application embodiment does not limit the material of the substrate; for example, the substrate material can be silicon.

[0087] A modulation gate group is provided on the substrate, the modulation gate group including at least one first modulation gate and at least one second modulation gate. The at least one first modulation gate is sequentially disposed on the first surface 2011 of the substrate 201, and the at least one second modulation gate is sequentially disposed on the first surface 2011. The at least one second modulation gate and the at least one first modulation gate are respectively complementaryly modulated.

[0088] The first modulation gate and the second modulation gate can be one or more, but Figure 7b Let's take one example to illustrate.

[0089] like Figure 7b As shown, the first modulation gate includes: a first left modulation gate PGA.

[0090] The second modulation gate includes: a first right modulation gate PGB.

[0091] It should be noted that "PG" is the abbreviation for photo gate (grating diode).

[0092] Wherein, the at least one first modulation gate and the at least one second modulation gate are complementaryly modulated, which can be: during time period A, the first left modulation gate PGA is turned on and the first right modulation gate PGB is turned off.

[0093] During time periods other than time period A, such as time period B, the first right modulation gate PGB is turned on, and the first left modulation gate PGA is turned off. Based on the above, it can be considered that the first left modulation gate PGA and the first right modulation gate PGB are complementaryly modulated.

[0094] The first surface 2011 can be any surface of the substrate 201. In this embodiment, the first surface 2011 is the surface of the substrate used to collect charge carriers, and the at least one first modulation gate and the at least one second modulation gate are both disposed on the first surface 2011, and the charge carrier collection region 202 is in contact with the at least one first modulation gate and the at least one second modulation gate.

[0095] In some embodiments of this application, when the transistor is an N-type transistor, the material constituting the semiconductor substrate 201 can be a P-type semiconductor material. Furthermore, the gate of each transistor may include a gate oxide layer (GOL) near the semiconductor substrate 201, and a polysilicon layer (PL) located on the surface of the gate oxide layer away from the semiconductor substrate 201.

[0096] The substrate 201 may include at least two carrier storage regions and a carrier collection region 202.

[0097] The at least two carrier storage regions are located on opposite sides of the substrate 201 in a first direction, which is parallel to the first surface 2011. The carrier collection region 202 is located between the two carrier storage regions in this first direction. The first direction can be... Figure 7a The direction of the X-axis in the diagram.

[0098] The carrier storage region can be two or more.

[0099] like Figure 7d As shown, in one implementation of this application, there are four carrier storage regions: a first carrier storage region FDA1, a second carrier storage region FDA2, a third carrier storage region FDB1, and a fourth carrier storage region FDB2. The first carrier storage region FDA1, the second carrier storage region FDA2, the third carrier storage region FDB1, and the fourth carrier storage region FDB2 are located at the four corners of the first surface, respectively.

[0100] The modulation gate group includes: a first modulation gate PGA1, a second modulation gate PGA2, a third modulation gate PGB1, and a fourth modulation gate PGB2. The first modulation gate PGA1 and the second modulation gate PGA2 are centrally symmetrical about a first surface, and the third modulation gate PGB1 and the fourth modulation gate PGB2 are also centrally symmetrical about the first surface. The first modulation gate PGA1, the second modulation gate PGA2, the third modulation gate PGB1, and the fourth modulation gate PGB2 can be complementaryly modulated.

[0101] During time period A, the first modulation gate PGA1 is turned on, and the second modulation gate PGA2, the third modulation gate PGB1 and the fourth modulation gate PGB2 are turned off. The first carrier collection region FDA1 is used to collect carriers from the first modulation gate PGA1.

[0102] During time period B, the second modulation gate PGA2 is turned on, and the first modulation gate PGA1, the third modulation gate PGB1 and the fourth modulation gate PGB2 are turned off. The second carrier storage region FDA2 is used to collect carriers from the second modulation gate PGA2.

[0103] During time period C, the third modulation gate PGB1 is turned on, the first modulation gate PGA1, the second modulation gate PGA2 and the fourth modulation gate PGB2 are turned off, and the third carrier collection region FDB1 is used to collect carriers from the third modulation gate PGB1.

[0104] During time period D, the fourth modulation gate PGB2 is turned on, the first modulation gate PGA1, the second modulation gate PGA2 and the third modulation gate PGB1 are turned off, and the fourth carrier storage region FDB2 is used to collect carriers from the fourth carrier collection region PGB2.

[0105] The first carrier storage region FDA1 and the second carrier storage region FDA2 are located on opposite sides of the substrate in a first direction. The first direction is, for example, and Figure 7d The diagonal line 'a' extends in the same direction.

[0106] The carrier collection region is located in this first direction between the first carrier storage region FDA1 and the second carrier storage region FDA2.

[0107] The third carrier storage region FDB1 and the fourth carrier storage region FDB2 are located on opposite sides of the substrate in the second direction.

[0108] The carrier collection region is located in this second direction between the third carrier storage region FDB1 and the fourth carrier storage region FDB2. The second direction is, for example, and Figure 7d The diagonal line b in the diagram extends in the same direction.

[0109] in, Figure 7d The sectional views of both diagonal a and diagonal b can be referenced. Figure 7b The description will not be repeated here.

[0110] In another implementation of this application, such as Figure 7a As shown, there are two carrier storage regions. These carrier storage regions may include: a first carrier storage region FDA located on the left side of substrate 201, and a second carrier storage region FDB located on the right side of substrate 201.

[0111] The first carrier storage area FDA is used to collect carriers in the PGA, and the second carrier storage area FDB is used to collect carriers in the PGB.

[0112] It should be noted that "FD" is the abbreviation for floating diffusion.

[0113] The following explanation will take the case where there are two carrier storage regions as an example.

[0114] When the substrate is irradiated with infrared light, charge carriers are generated inside it. The charge carrier collection region 202 collects the charge carriers in the substrate 201. Under the modulation of the first left modulation gate PGA or the first right modulation gate PGB, the charge carriers in the substrate 201 are stored in the first charge carrier storage region FDA through the first left modulation gate PGA or in the second charge carrier storage region FDB through the first right modulation gate PGB.

[0115] Next, refer to Figure 7a The carrier collection region 202 has the same doping type as the first carrier storage region FDA and the second carrier storage region FDB, while the doping type of the carrier collection region 202 is opposite to that of the substrate 201.

[0116] This application does not limit the specific doping type of the carrier collection region 202 and the substrate 201 in the embodiments. For example, in one implementation of this application, the carrier collection region 202 and the first carrier storage region FDA and the second carrier storage region FDB can be p-type doped, and the substrate 201 can be n-type doped.

[0117] Free electrons in carrier collection region 202 diffuse into substrate 201, while holes in substrate 201 diffuse into carrier collection region 202. The diffused electrons and holes contact and recombine, forming a PN junction depletion region 203 adjacent to the carrier collection region 202 and substrate 201. Charged ions adjacent to the interface remain in the region without moving carriers. Uncompensated ions are positive on the substrate 201 side and negative on the carrier collection region 202 side, creating an electric field that provides a force against the continuous exchange of charge carriers. When the electric field is sufficient to prevent further transfer of holes and electrons, the PN junction depletion region 203 reaches its equilibrium size.

[0118] In another implementation of this application, the carrier collection region 202, the first carrier storage region FDA, and the second carrier storage region FDB are N-type doped, and the substrate 201 is P-type doped. Holes in the carrier collection region 202 diffuse into the substrate 201, while free electrons in the substrate 201 diffuse into the carrier collection region 202. The diffused electrons and holes come into contact and are eliminated through recombination. Similarly, a PN junction depletion region 203 is formed at the adjacent position of the carrier collection region 202 and the substrate 201.

[0119] The doping concentration of the carrier collection region 202 can be greater than that of the substrate 201. For example, the doping concentration of the carrier collection region 202 is 1000-10000 times that of the substrate 201. Electrons or holes readily transfer from high-concentration regions to low-concentration regions until they are uniformly distributed. Therefore, during the formation of the PN junction depletion region, electrons or holes in the carrier collection region 202 are more likely to transfer to the substrate 201, and the formed PN junction depletion region 203 is more biased towards the substrate 201.

[0120] like Figure 7b As shown, the PN junction depletion region 203 includes a first PN junction depletion region 2031 located in the substrate 201 and a second PN junction depletion region 2032 located in the carrier collection region 202, wherein the range of the first PN junction depletion region 2031 is larger than the range of the first PN junction depletion region 2032.

[0121] like Figure 7c As shown, when the substrate 201 is irradiated by light, charge carriers are generated inside the substrate 201. The ions on both sides of the PN junction depletion region 203 have opposite charges, which will generate a transverse electric field. Since the PN junction depletion region 203 is located more in the substrate 201, the electric field has a greater effect on the charge carriers in the substrate 201, causing the charge carriers in the substrate 201 to enter the charge carrier collection region 202.

[0122] Next, refer to Figure 7c The carrier collection region 202 can contact the first left modulation gate PGA and the first right modulation gate PGB on the first surface 2011. Carriers in the substrate 201 can flow to the first surface 2011 under the modulation of the first left modulation gate PGA and the first right modulation gate PGB, and then flow to the first carrier storage region FDA through the first left modulation gate PGA, or flow to the second carrier storage region FDB through the first right modulation gate PGB.

[0123] For example, during time period A, the first left modulation gate PGA is turned on and the first right modulation gate PGB is turned off. Charge carriers in the substrate flow to the first surface of the substrate under the modulation of the first left modulation gate PGA and are then stored in the FDA.

[0124] During time period B, the first right modulation gate PGB is turned on and the first left modulation gate PGA is turned off. The charge carriers in the substrate flow to the first surface of the substrate under the modulation of the first right modulation gate PGB and are then stored in the FDB.

[0125] Assuming the number of carriers in the first carrier storage region FDA is Sa and the number of carriers in the second carrier storage region FDB is Sb, substituting Sa and Sb into Equation 1 yields the modulation and demodulation efficiency of the pixel structure.

[0126] Figure 8 A graph showing the change in potential inside the substrate as a function of substrate depth, provided for an embodiment of this application. Figure 8 As shown, the vertical axis represents electric potential, and the horizontal axis represents substrate depth, where the substrate depth is the vertical distance between each point in the substrate and the first surface 2011 of the substrate.

[0127] Line 01 is a curve showing the change of the internal potential of the substrate with the substrate depth in the prior art, and line 02 is a curve showing the change of the internal potential of the substrate with the substrate depth in the embodiment of this application.

[0128] In the prior art, the carrier concentration at the bottom of the substrate is low and the potential is flat, so the potential change in the substrate is limited to a very shallow area. Compared with the prior art, the embodiments of this application improve the carrier concentration at the bottom of the substrate by setting a carrier collection area, so that the potential inside the substrate changes uniformly and the potential steepness inside the substrate is improved, which is beneficial to improve the velocity of carriers at the bottom of the pixel structure.

[0129] The pixel structure provided in this application embodiment forms a PN junction depletion region adjacent to the substrate. The doping concentration of the carrier collection region is greater than that of the substrate, making it easier for electrons or holes in the carrier collection region to diffuse into the substrate during the formation of the PN junction depletion region. This results in the PN junction depletion region being more biased towards the substrate. The substrate ions on both sides of the PN junction depletion region have opposite electrical charges, creating an electric field. When the substrate is irradiated, carriers are generated inside the substrate. Because the PN junction depletion region is more biased towards the substrate, the electric field on both sides of the PN junction depletion region has a greater effect on the carriers within the substrate. Under the influence of the electric field of the PN junction depletion region, the carriers within the substrate enter the carrier collection region. In the prior art, the carrier concentration at the bottom of the substrate is low, and the potential change is limited to a very shallow region from one surface inwards. This results in low carrier velocity at the bottom of the substrate, requiring a longer time to reach the carrier collection point on the first surface, thus affecting the modulation and demodulation efficiency of the pixel structure. The substrate potential of this application changes more uniformly from the first surface to the bottom of the substrate, which increases the carrier velocity at the bottom of the substrate, enabling carriers to be collected quickly, improving the modulation and demodulation efficiency of the pixel structure, and thus improving the ranging accuracy.

[0130] In some possible embodiments, such as Figure 7b As shown, the pixel structure 2003 is a symmetrical structure about the center line OO. The first left modulation gate PGA and the first right modulation gate PGB, as well as FDA and FDB, are all symmetrical about the center line OO of the pixel structure 2003. In this way, FDA and FDB can have the same ability to absorb charge carriers in the substrate 201.

[0131] The embodiments of this application do not limit the structure of the carrier collection region 202. In one implementation of this application, such as Figure 7b As shown, the carrier collection region 202 has a uniform doping concentration, and the doping concentration does not change in the first direction.

[0132] In another implementation of this application, the doping concentration of the carrier collection region 202 exhibits a "dense-light-dense" doping distribution in the first direction, such as... Figure 9 As shown, the carrier collection region 202 may include a first doped region 2021, a second doped region 2022 and a third doped region 2023. The first doped region 2021 and the second doped region 2022 are located on both sides of the carrier collection region 202 in the first direction, and the third doped region 2023 is located between the first doped region 2021 and the second doped region 2022.

[0133] The doping concentrations of the first doping region 2021 and the second doping region 2022 are both greater than the doping concentration of the third doping region 2023.

[0134] For example, the doping concentration of the first doped region 2021 is 10-100 times that of the third doped region 2023, and the doping concentration of the second doped region 2022 is 10-100 times that of the third doped region 2023.

[0135] When the carrier collection region is doped with a single concentration, a local potential well is formed at the center of the carrier collection region on the substrate surface when the pixel structure is reset. This makes it difficult for carriers at the center of the first surface to enter the carrier collection region, which is not conducive to the reset of the pixel structure.

[0136] If the carrier collection region adopts a "dense-light-dense" doping method, a local potential well will not be formed in the center of the carrier collection region on the substrate surface when the pixel structure is reset. This is beneficial for the carriers on the first surface of the substrate to be successfully removed during the reset process, making the pixel structure easier to reset.

[0137] A third doped region 2023 with the same doping type and lower doping concentration is set in the carrier collection region 202, which makes the pixel structure easier to reset.

[0138] A third doped region 2023 with the same doping type and lower doping concentration is set in the carrier collection region 202, which makes the pixel structure easier to reset.

[0139] The following is combined with Figure 10 The following is a specific example of how substrate 201 is p-type doped and carrier collection region 202 is n-type doped.

[0140] Figure 10 This is a potential distribution curve of the first surface of the substrate during pixel structure reset, as provided in an embodiment of this application. Figure 10 As shown, the vertical axis represents the electric potential, and the horizontal axis represents the substrate width. The substrate width can be the vertical distance from any point on the first surface of the substrate to the first carrier storage region.

[0141] When the substrate 201 is p-type doped and the carrier collection region 202 is n-type doped, the carriers reaching the first surface are electrons.

[0142] Line 04 shows the potential distribution curve on the first surface 1011 of the substrate when the pixel structure is reset, using a single concentration of doping in the carrier collection region. As shown in line 04, when the carrier collection region uses a single concentration of doping, the potential at the middle position of the first surface shows a local "concave" area in the opposite direction. The carriers at the middle position cannot flow to both sides under the action of the applied electric field, resulting in the electrons at the middle position not being successfully extracted during the reset process.

[0143] Line 03 shows the potential distribution curve on the first surface 1011 of the substrate when the pixel structure is reset, using a "dense-light-dense" doping method in the carrier collection region. As shown in line 03, when the carrier collection region uses a "dense-light-dense" doping method, the potential at the middle position of the first surface shows a local "convex" region in the opposite direction. The carriers at the middle position can flow to both sides under the action of the applied electric field, which is conducive to the smooth removal of electrons from the first surface of the substrate during the reset process, making the pixel structure easier to reset.

[0144] In some possible embodiments, such as Figure 9 As shown, the first doped region 2021 and the second doped region 2022 are symmetrical about the center line OO of the pixel structure 2003, and the third doped region 2023 is symmetrical about the center line OO of the pixel structure 2003. Therefore, when the first left modulation gate PGA and the first right modulation gate PGB are complementaryly modulated, the carriers in the substrate have the same ability to enter the first carrier storage region FDA and the second carrier storage region FDB.

[0145] The embodiment of this application does not limit the length of the carrier collection region 202.

[0146] In one implementation of this application, such as Figure 7b As shown, in a direction perpendicular to the first surface 2011, the length of the carrier collection region 202 is equal to the length of the substrate 201. The length of the carrier collection region 202 can be the distance that the carrier collection region 202 extends from the first surface into the substrate along the Y-axis.

[0147] Next, refer to Figure 7bThe carrier collection region 202 extends longitudinally through the substrate 201, and the PN junction depletion region 203 is located on the substrate on both sides of the carrier collection region 202.

[0148] Therefore, a PN junction depletion region can be formed on the substrate on both sides of the carrier collection region, allowing carriers in the substrate on both sides of the carrier collection region to flow into the carrier collection region under the action of the electric field of the PN junction depletion region, thereby improving the modulation and demodulation efficiency of the pixel structure.

[0149] In another implementation of this application, the length of the carrier collection region 202 is less than the length of the substrate 201 in the direction perpendicular to the first surface 2011.

[0150] like Figure 11 As shown, a U-shaped doped region is formed in the substrate 201, and a carrier collection region 202 is located within the U-shaped doped region 203, wherein the opening of the U-shaped doped region faces the first surface 2011 of the doped structure.

[0151] The carrier collection region 202 and the U-shaped doped region are adjacent to form a U-shaped PN junction depletion region 203. Under the action of the U-shaped PN junction depletion region 203, the carriers in the U-shaped doped region flow from the U-shaped doped region to the carrier collection region.

[0152] Those skilled in the art can select an appropriate length for the carrier collection region 202 as needed, and these are all within the scope of protection of this application.

[0153] The embodiments of this application do not limit the number of the first modulation gate and the second modulation gate, nor the positional relationship between the carrier collection region 202 and the modulation gate.

[0154] The first carrier storage region FDA can be close to the at least one first modulation gate and far away from the at least one second modulation gate, and the second carrier storage region FDB can be close to the at least one second modulation gate and far away from the at least one first modulation gate.

[0155] The at least one first modulation gate and the at least one second modulation gate are disposed on the first surface along the first direction, and the at least one first modulation gate includes a first end closest to the first carrier storage region FDA and a second end furthest from the first carrier storage region FDB.

[0156] Similarly, the at least one second modulation gate includes a first end closest to the second carrier storage region FDB and a second end furthest from the second carrier storage region FDB.

[0157] The first doped region is located between the first end and the second end of the at least one first modulation gate in the first direction, and the second doped region is located between the first end and the second end of the at least one second modulation gate in the first direction.

[0158] In one implementation of this application, there is one first modulation gate and one second modulation gate, and the first modulation gate and the second modulation gate are complementaryly modulated.

[0159] like Figure 7a As shown, the first modulation gate includes a first left modulation gate PGA, and the second modulation gate includes a first right modulation gate PGB. The first left modulation gate PGA and the first right modulation gate PGB are sequentially disposed on the first surface 2011 along the first direction. The carrier collection region is located below the first left modulation gate PGA and the first right modulation gate PGB, so that the carriers in the carrier collection region can enter the first left modulation gate PGA or the first right modulation gate PGB through the first surface of the substrate.

[0160] In some possible embodiments, the carrier collection region 202 employs a single doping concentration.

[0161] The first left modulation gate PGA and the first right modulation gate PGB each have a first end and a second end opposite to each other. The first end of the first left modulation gate PGA is close to the first carrier storage region FDA, and the second end of the first left modulation gate PGA is far from the first carrier storage region FDA. The first end of the first right modulation gate PGB is close to the second carrier storage region FDB, and the second end of the first right modulation gate PGB is far from the second carrier storage region FDB. The second end of the first left modulation gate PGA is opposite to the second end of the first right modulation gate PGB.

[0162] The first end of the at least one first modulation gate is the first end of the first left modulation gate PGA, and the second end of the at least one first modulation gate is the second end of the first left modulation gate PGA.

[0163] The first end of the at least one second modulation gate is the first end of the first right modulation gate PGB, and the second end of the at least one second modulation gate is the second end of the first right modulation gate PGB.

[0164] The aforementioned carrier collection region 202 is in contact with the at least one first modulation gate and the at least one second modulation gate on the first surface 2011. For example, the carrier collection region 202 is in contact with each first modulation gate and each second modulation gate on the first surface.

[0165] The first interface of the carrier collection region 202 may be located between the first and second ends of the first left modulation gate PGA. The first interface of the carrier collection region 202 is adjacent to the first carrier storage region FDA.

[0166] This allows the carrier collection region 202 and the first left modulation gate PGA to contact the first surface 2011, and allows a distance to be left between the first carrier storage region FDA and the first interface of the carrier collection region to regulate the carriers entering the first left modulation gate PGA, so that the carriers entering the first left modulation gate PGA flow to the first carrier storage region FDA under the modulation of the first left modulation gate PGA.

[0167] The second interface of the carrier collection region 202 can be located between the first and second ends of the first right modulation gate PGB. Specifically, the second interface of the carrier collection region 202 is close to the second carrier storage region FDB.

[0168] This allows the carrier collection region 202 and the first right modulation gate PGB to contact the first surface 2011, and allows a distance to be left between the second carrier storage region FDB and the second interface of the carrier collection region for regulating the carriers entering the first right modulation gate PGB, so that the carriers entering the first right modulation gate PGB flow to the second carrier storage region FDB under the modulation of the first right modulation gate PGB.

[0169] In other possible embodiments of this application, the carrier collection region 202 exhibits a "dense-light-dense" doping distribution in the first direction. For example... Figure 9 As shown, the carrier collection region 202 includes: a first doped region 2021, a second doped region 2022 and a third doped region 2023.

[0170] The first interface of the first doped region 2021 may not exceed the first end of the first left modulation gate PGA, and the first interface of the first doped region 2021 is close to the first carrier storage region FDA.

[0171] This allows the first doped region 2021 to contact the first left modulation gate PGA on the first surface 2011, and provides a distance between the first carrier storage region FDA and the first interface of the first doped region 2021 for regulating the carriers entering the first left modulation gate PGA, so that the carriers entering the first left modulation gate PGA flow to the first carrier storage region FDA under the modulation of the first left modulation gate PGA.

[0172] The first interface of the second doped region 2022 may not exceed the first end of the first right modulation gate PGB, and the first interface of the second doped region 2022 is close to the second carrier storage region FDB.

[0173] This allows the second doped region 2022 to contact the first right modulation gate PGB on the first surface, and provides a distance between the second carrier storage region FDB and the first interface of the second doped region 2022 for regulating the carriers entering the first right modulation gate PGB, so that the carriers entering the first right modulation gate PGB flow to the second carrier storage region FDB under the modulation of the first right modulation gate PGB.

[0174] The second interface of the first doped region 2021 may not exceed the second end of the first left modulation gate PGA, wherein the second interface of the first doped region 2021 is the interface between the second doped region 2022 and the third doped region 2023.

[0175] This allows the third doped region 2023, located between the first doped region 2021 and the second doped region 2022, to contact the first left modulation gate PGA on the first surface. This allows the carriers in the third doped region 2023 to enter the first left modulation gate PGA through the first surface, while leaving a distance to regulate the carriers entering the first left modulation gate PGA. This allows the carriers entering the first left modulation gate PGA to flow to the first carrier storage region FDA under the modulation of the first left modulation gate PGA.

[0176] The second interface of the second doped region 2022 may not exceed the second end of the first right modulation gate PGB, wherein the second interface of the second doped region 2022 is the interface between the second doped region 2022 and the third doped region 2023.

[0177] This allows the third doped region 2023, located between the first doped region 2021 and the second doped region 2022, to contact the first right modulation gate PGB on the first surface. This allows the carriers in the third doped region 2023 to enter the first right modulation gate PGB through the first surface, while leaving a distance for regulating the carriers entering the first right modulation gate PGB. This allows the carriers entering the first right modulation gate PGB to flow to the second carrier storage region FDB under the modulation of the first right modulation gate PGB.

[0178] In another implementation of this application, there are multiple first and second modulation gates. For example, as shown in the figure, the first modulation gate includes a first left modulation gate TGA and a second left modulation gate PGA connected in series. The second modulation gate includes a first right modulation gate TGB and a second right modulation gate PGB connected in series. The first left modulation gate TGA and the first right modulation gate TGB are complementaryly modulated, and the second left modulation gate PGA and the second right modulation gate PGB are also complementaryly modulated. That is, when the first left modulation gate PGA is on, the first right modulation gate PGB is off, and when the first right modulation gate PGB is on, the first left modulation gate PGA is off. Simultaneously, when the first right modulation gate PGA is on, the second right modulation gate PGB is off, and when the second right modulation gate PGB is on, the first right modulation gate PGA is off.

[0179] For example, during time period A, the first left modulation gate TGA and the second left modulation gate PGA are turned on, while the first right modulation gate TGB and the second right modulation gate PGB are turned off.

[0180] During other time periods outside of time period A, such as time period B, the first right modulation gate TGB and the second right modulation gate PGB are turned on, while the first left modulation gate TGA and the second left modulation gate PGA are turned off.

[0181] It should be noted that "TG" is the abbreviation for turbo gate (acceleration modulation diode).

[0182] The first left modulation gate TGA, the second left modulation gate PGA, the second right modulation gate PGB, and the first right modulation gate TGB are sequentially disposed on the first surface 2011 of the substrate 201 along the first direction. The first left modulation gate TGA, the second left modulation gate PGA, the first right modulation gate TGB, and the second right modulation gate PGB are all in contact with the carrier collection region 202 on the first surface 2011, so that the carriers in the carrier collection region can enter the first left modulation gate TGA, the second left modulation gate PGA, the first right modulation gate TGB, and the second right modulation gate PGB through the first surface.

[0183] In some possible embodiments, such as Figure 12a As shown, the carrier collection region 202 uses a single doping concentration.

[0184] in, Figure 12aThe first left modulation gate TGA, second left modulation gate PGA, first right modulation gate TGB, and second right modulation gate PGB each include a first end and a second end opposite to each other. The first end of the first left modulation gate TGA is close to the first carrier storage region FDA, and the second end of the first left modulation gate TGA is far from the first carrier storage region FDA, and the second end of the first left modulation gate TGA is opposite to the first end of the second left modulation gate PGA. The first end of the first right modulation gate TGB is close to the second carrier storage region FDB, and the second end of the first right modulation gate TGB is far from the second carrier storage region FDB, and the second end of the first right modulation gate TGB is opposite to the first end of the second right modulation gate PGB. The second end of the second left modulation gate PGA is close to the second end of the second right modulation gate PGB.

[0185] The first end of the at least one first modulation gate is the first end of the first left modulation gate TGA, and the second end of the at least one first modulation gate is the second end of the second left modulation gate PGA.

[0186] The first end of the at least one second modulation gate is the first end of the first right modulation gate TGB, and the second end of the at least one second modulation gate is the second end of the second right modulation gate PGB.

[0187] The first interface of the carrier collection region 202 may be located between the first and second ends of the first left modulation gate TGA.

[0188] This allows the carrier collection region 202 and the first left modulation gate TGA to contact the first surface 2011, and allows a distance to be left between the first carrier storage region FDA and the first interface of the carrier collection region to regulate the carriers entering the first left modulation gate TGA, so that the carriers entering the first left modulation gate TGA flow to the first carrier storage region FDA.

[0189] The second interface of the carrier collection region 202 can be located between the first and second ends of the first right modulation gate TGB.

[0190] This allows the carrier collection region 202 and the first right modulation gate TGB to contact the first surface 2011, and allows a distance to be left between the second carrier storage region FDB and the second interface of the carrier collection region to regulate the carriers entering the first right modulation gate TGB, so that the carriers entering the first right modulation gate TGB flow to the second carrier storage region FDB.

[0191] In some other possible embodiments of this application, the carrier collection region 202 exhibits a "dense-light-dense" doping distribution in the first direction. For example... Figure 12bAs shown, the carrier collection region 202 includes a first doped region 2021, a second doped region 2022 and a third doped region 2023 arranged sequentially along a first direction.

[0192] The first interface of the first doped region 2021 may not exceed the first end of the first left modulation gate TGA.

[0193] This allows the first doped region 2021 to contact the first left modulation gate TGA on the first surface, and provides a distance between the first carrier storage region FDA and the first interface of the first doped region 2021 for regulating the carriers entering the first left modulation gate TGA, so that the carriers entering the first left modulation gate TGA flow to the first carrier storage region FDA under the modulation of the first left modulation gate TGA.

[0194] The first interface of the second doped region 2022 may not exceed the first end of the first right modulation gate TGB.

[0195] This allows the second doped region 2022 to contact the first right modulation gate TGB on the first surface, and provides a distance between the second carrier storage region FDB and the first interface of the second doped region 2022 for regulating the carriers entering the first right modulation gate TGB, so that the carriers entering the first right modulation gate TGB flow to the second carrier storage region FDB under the modulation of the first right modulation gate TGB.

[0196] The second interface of the first doped region 2021 may not exceed the second end of the second left modulation gate PGA.

[0197] This allows the third doped region 2023, located between the first doped region 2021 and the second doped region 2022, to contact the second left modulation gate PGA on the first surface. This allows the carriers in the third doped region 2023 to enter the second left modulation gate PGA through the first surface, while leaving a distance to regulate the carriers entering the second right modulation gate PGB, so that the carriers entering the second right modulation gate PGB flow to the first carrier storage region FDA.

[0198] The second interface of the second doped region 2022 may not exceed the second end of the second right modulation gate PGB.

[0199] This allows the third doped region 2023, located between the first doped region 2021 and the second doped region 2022, to contact the second right modulation gate PGB on the first surface. This allows the carriers in the third doped region 2023 to enter the second right modulation gate PGB through the first surface, while leaving a distance to regulate the carriers entering the second right modulation gate PGB, so that the carriers entering the second right modulation gate PGB flow to the second carrier storage region FDB.

[0200] For example, such as Figure 13a As shown, there are three first modulation gates: the first left modulation gate TGA1, the second left modulation gate TGA2, and the third left modulation gate PGA. There are also three second modulation gates: the first right modulation gate TGB1, the second right modulation gate TGB2, and the third right modulation gate PGB.

[0201] The first left modulation gate TGA1 and the first right modulation gate TGB1 are complementaryly modulated; the second left modulation gate TGA2 and the second right modulation gate TGB2 are complementaryly modulated; and the third left modulation gate PGA and the third right modulation gate PGB are complementaryly modulated. That is, when the first left modulation gate TGA1 is on, the first right modulation gate TGB1 is off; and when the first right modulation gate TGB1 is on, the first left modulation gate TGA1 is off. When the second left modulation gate TGA2 is on, the second right modulation gate TGB2 is off; and when the second right modulation gate TGB2 is on, the second left modulation gate TGA2 is off. Simultaneously, when the third left modulation gate PGA is on, the third right modulation gate PGB is off; and when the third right modulation gate PGB is on, the third left modulation gate PGA is off.

[0202] For example, during time period A, the first left modulation gate TGA1, the second left modulation gate TGA2, and the third left modulation gate PGA are turned on, while the first right modulation gate TGB1, the second right modulation gate TGB2, and the third right modulation gate PGB are turned off.

[0203] During other time periods outside of time period A, such as time period B, the first right modulation gate TGB1, the second right modulation gate TGB2, and the third right modulation gate PGB are turned on, while the first left modulation gate TGA1, the second left modulation gate TGA2, and the third left modulation gate PGA are turned off.

[0204] The first left modulation gate TGA1, the second left modulation gate TGA2, the third left modulation gate PGA, the third right modulation gate PGB, the second right modulation gate TGB2, and the first right modulation gate TGB1 can be sequentially disposed on the first surface 2011 of the substrate 201 along the first direction. The first left modulation gate TGA1, the second left modulation gate TGA2, the third left modulation gate PGA, the third right modulation gate PGB, the second right modulation gate TGB2, and the first right modulation gate TGB1 are all in contact with the carrier collection region 202 on the first surface 2011.

[0205] like Figure 13a As shown, the first left modulation gate TGA1, the second left modulation gate TGA2, the third left modulation gate PGA, the third right modulation gate PGB, the second right modulation gate TGB2, and the first right modulation gate TGB1 each have opposing first and second ends. The first end of the first left modulation gate TGA1 is close to the first carrier storage region FDA. The second end of the first left modulation gate TGA1 is opposite to the first end of the second left modulation gate TGA2, and the second end of the second left modulation gate TGA2 is opposite to the first end of the third left modulation gate PGA. The second end of the third left modulation gate PGA is opposite to the second end of the third right modulation gate PGB. The first end of the first right modulation gate TGB1 is close to the second carrier storage region FDB. The second end of the first right modulation gate TGB1 is opposite to the first end of the second right modulation gate TGB2, and the second end of the second right modulation gate TGB2 is opposite to the first end of the third right modulation gate PGB.

[0206] The first end of the at least one first modulation gate is the first end of the first left modulation gate TGA1, and the second end of the at least one first modulation gate is the second end of the third left modulation gate PGA.

[0207] The first end of the at least one second modulation gate is the first end of the first right modulation gate TGB1, and the second end of the at least one second modulation gate is the second end of the third right modulation gate PGB.

[0208] Figure 13a The carrier collection region 202 in the middle can use a single doping concentration.

[0209] The first interface of the carrier collection region 202 can be located between the first end and the second end of the first left modulation gate TGA1.

[0210] This allows the carrier collection region 202 and the first left modulation gate TGA1 to contact the first surface 2011, and allows a distance to be left between the first carrier storage region FDA and the first interface of the carrier collection region to regulate the carriers entering the first left modulation gate TGA1, so that the carriers entering the first left modulation gate TGA1 flow to the first carrier storage region FDA.

[0211] The second interface of the carrier collection region 202 can be located between the first and second ends of the first right modulation gate TGB1.

[0212] This allows the carrier collection region 202 and the first right modulation gate TGB1 to contact the first surface 2011, and allows a distance to be left between the second interface of the second carrier storage region FDB and the carrier collection region to regulate the carriers entering the first right modulation gate TGB1, so that the carriers entering the first right modulation gate TGB1 flow to the second carrier storage region FDB.

[0213] In some other possible embodiments of this application, the carrier collection region 202 exhibits a "dense-light-dense" doping distribution in the first direction. For example... Figure 13b As shown, the carrier collection region 202 includes a first doped region 2021, a second doped region 2022 and a third doped region 2023 arranged sequentially along a first direction.

[0214] The first interface of the first doped region 2021 may not exceed the first end of the first left modulation gate TGA1.

[0215] This allows the first doped region 2021 to contact the first left modulation gate TGA1 on the first surface, and provides a distance between the first carrier storage region FDA and the first interface of the first doped region 2021 for regulating the carriers entering the first left modulation gate TGA1, so that the carriers entering the first left modulation gate TGA1 flow to the first carrier storage region FDA under the modulation of the first left modulation gate TGA1.

[0216] The first interface of the second doped region 2022 may not exceed the first end of the first right modulation gate TGB1.

[0217] This allows the second doped region 2022 to contact the first right modulation gate TGB1 on the first surface, and provides a distance between the second carrier storage region FDB and the first interface of the second doped region 2022 for regulating the carriers entering the first right modulation gate TGB1, so that the carriers entering the first right modulation gate TGB1 flow to the second carrier storage region FDB under the modulation of the first right modulation gate TGB1.

[0218] The second interface of the first doped region 2021 may not exceed the second end of the third left modulation gate PGA.

[0219] This allows the third doped region 2023, located between the first doped region 2021 and the second doped region 2022, to contact the third left modulation gate PGA on the first surface. This allows the carriers in the third doped region 2023 to enter the third left modulation gate PGA through the first surface, while leaving a distance to regulate the carriers entering the third left modulation gate PGA, so that the carriers entering the third left modulation gate PGA flow to the first carrier storage region FDA.

[0220] The second interface of the second doped region 2022 may not exceed the second end of the third right modulation gate PGB.

[0221] Thus, the third doped region 2023 located between the first doped region 2021 and the second doped region 2022 can contact the third right modulation gate PGB on the first surface, allowing the carriers in the third doped region 2023 to enter the third right modulation gate PGB through the first surface, while leaving a distance to regulate the carriers entering the third right modulation gate PGB, so that the carriers entering the third right modulation gate PGB flow to the second carrier storage region FDB.

[0222] Furthermore, a first gate is provided between the at least one first modulation gate and the first carrier storage region FDA, and a second gate is provided between the at least one second modulation gate and the second carrier storage region FDB.

[0223] like Figure 14 As shown, there are two first modulation gates: a first left modulation gate (TGA) and a second left modulation gate (PGA) connected in series. There are also two second modulation gates: a first right modulation gate (TGB) and a second right modulation gate (PGB) connected in series. The first gate is TXA, and the second gate is TXB.

[0224] The first gate TXA and the second gate TXB can be symmetrical about the center line OO of the pixel structure 2003.

[0225] This makes it possible for charge carriers in the substrate to have the same ability to enter the first charge carrier storage region FDA and the second charge carrier storage region FDB.

[0226] One end of the at least one first modulation gate is coupled to the carrier collection region 202, and the other end is connected to the first carrier storage region FDA through the first gate TXA. Carriers in the carrier collection region 202 can reach the FDA in sequence through the first modulation gate and the first gate TXA.

[0227] One end of the at least one second modulation gate is coupled to the carrier collection region 202, and the other end is coupled to the second carrier storage region FDB through the second gate TXB. Carriers in the carrier collection region 202 can reach the FDB in sequence through the second modulation gate and the second gate TXB.

[0228] TXA and TXB are used to receive DC modulation signals. In this case, during time periods A and B, the first gate TXA and the second gate TXB can remain in a conducting state.

[0229] Therefore, the DC signal received by the first gate TXA can shield the effect of the AC signal received by the at least one first modulation gate on the first carrier storage region FDA.

[0230] Similarly, the DC signal received by the second gate TXB can shield the influence of the AC signal received by the at least one second modulation gate on the second carrier storage region FDB.

[0231] Furthermore, by adjusting the voltage value of the first gate, the steepness of the potential distribution between the first carrier storage region FDA and the first modulation gate can be increased, which is beneficial for carriers in the substrate to flow into the first carrier storage region FDA. By adjusting the voltage value of the second gate, the steepness of the potential distribution between the second carrier storage region FDB and the second modulation gate can be increased, which is beneficial for carriers in the substrate to flow into the second carrier storage region FDB.

[0232] This application provides a method for manufacturing a pixel structure. Figure 15 This is a flowchart illustrating a method for manufacturing a pixel structure according to an embodiment of this application. Figure 15 As shown, the method includes the following steps:

[0233] S101, such as Figure 15a As shown, two carrier storage regions are formed on substrate 201 by ion implantation.

[0234] The first surface can be any surface of the substrate 201. The two carrier storage regions are located on opposite sides of the substrate 201 in a first direction, which is parallel to the first surface 2011.

[0235] Before ion implantation, a mask can be placed on the first surface 1011 of the substrate. The mask can be placed in the middle of the first surface 1011, leaving areas on both sides of the first surface 1011 for ion implantation. Ion implantation can be performed in these areas to change the doping type of the area and obtain the carrier storage region.

[0236] The mask can be removed after ion implantation is complete.

[0237] The doping type of the two carrier storage regions is opposite to that of the substrate 201.

[0238] For example, the two carrier storage regions are N-type doped and the substrate is P-type doped, or the two carrier storage regions are P-type doped and the substrate is N-type doped.

[0239] S102, such as Figure 15b As shown, a carrier collection region 202 is formed on the substrate 201 by ion implantation.

[0240] The carrier collection region 202 is located between the two carrier storage regions in the first direction. The doping concentration of the carrier collection region 202 is greater than that of the substrate 201. The carrier collection region 202 has the same doping type as the two carrier storage regions, and the doping type of the carrier collection region 202 is opposite to that of the substrate 201.

[0241] Before ion implantation, a mask can be set on both sides of the first surface 1011 of the substrate to leave an area for ion implantation in the middle of the first surface 1011. Ion implantation can be performed in this area to change the doping type of the area and obtain the carrier collection region 202.

[0242] The mask can be removed after ion implantation is complete.

[0243] The length of the carrier collection region can be adjusted by controlling the ion energy to regulate the ion implantation depth. In one implementation of this application, the length of the carrier collection region is less than the length of the substrate in the direction perpendicular to the first surface. In another implementation of this application, the length of the carrier collection region is equal to the length of the substrate.

[0244] This allows for the formation of a carrier collection region 202 with a single concentration.

[0245] like Figure 16As shown, in one implementation of this application, step S102, which involves forming a carrier collection region 202 on the substrate 201 via ion implantation, may include the following steps:

[0246] S1021, such as Figure 16a As shown, a first doped region 2021 and a second doped region 2022 are formed on a substrate 201 by ion implantation.

[0247] The first doped region 2021 and the second doped region 2022 are located on both sides of the carrier collection region 202 in the first direction.

[0248] Before ion implantation, three photomasks can be set on the first surface 1011 of the substrate to leave an area for ion implantation on the first surface 1011. Ion implantation can be performed in this area to change the doping type of the area, resulting in the first doped region 2021 and the second doped region 2022.

[0249] The mask can be removed after ion implantation is complete.

[0250] S1022, such as Figure 16b As shown, a third doped region 2023 is formed on the substrate 201 by ion implantation.

[0251] The doping concentrations of the first doped region 2021 and the second doped region 2022 are both greater than the doping concentration of the third doped region 2023, and the third doped region 2023 is located between the first doped region 2021 and the second doped region 2022.

[0252] Before ion implantation, two photomasks can be set on the first surface 1011 of the substrate, and an area for ion implantation can be left on the first surface 1011. Ion implantation can be performed in this area to change the doping type of the area and obtain the third doped region 2023.

[0253] The mask can be removed after ion implantation is complete.

[0254] Thus, a carrier collection region with a doping concentration distribution of "dense-light-dense" in the first direction can be obtained.

[0255] like Figure 17 As shown, in another implementation of this application, step S102, which involves forming a carrier collection region 202 on the substrate 201 via ion implantation, may include the following steps:

[0256] S1023, such as Figure 16aAs shown, a first doped region 2021 and a second doped region 2022 are formed on a substrate 201 by ion implantation.

[0257] The first doped region 2021 and the second doped region 2022 are located on both sides of the carrier collection region 202 in the first direction.

[0258] The doping methods for the first and second doped regions can be referred to in S1021 above, and will not be repeated here.

[0259] S1024, Next, as Figure 16b As shown, ions from the first doped region 2021 and the second doped region 2022 diffuse into the third region to form the third doped region 2023.

[0260] Wherein, the doping concentration of the first doped region 2021 and the second doped region 2022 is greater than the doping concentration of the third doped region 2023, and the third doped region 2023 is located between the first doped region 2021 and the second doped region 2022.

[0261] Therefore, compared with step S1022, there is no need for a mask or ion implantation, which simplifies the manufacturing process.

[0262] S103, such as Figure 15c As shown, at least one first modulation gate and at least one second modulation gate are disposed on the first surface 2011 of the substrate 201.

[0263] Among them, such as Figure 15 As shown, the first modulation gate includes a first left modulation gate PGA, and the second modulation gate includes a first right modulation gate PGB.

[0264] The first left modulation gate PGA and the first right modulation gate PGB are complementaryly modulated, and the carrier collection region 202 is in contact with the first left modulation gate PGA and the first right modulation gate PGB on the first surface 2011.

[0265] In one implementation of this application, the carrier collection region 202 adopts a single doping concentration.

[0266] The provision of at least one first modulation gate and at least one second modulation gate on the first surface 2011 of the substrate 201 includes:

[0267] The at least one first modulation gate and the at least one second modulation gate are disposed on the first surface 2011 along the first direction, such that the carrier collection region 202 is located between the first end of the at least one first modulation gate and the first end of the at least one second modulation gate in the first direction.

[0268] In another implementation of this application, the carrier collection region 202 includes: a first doped region 2021, a second doped region 2022, and a third doped region 2023.

[0269] The provision of at least one first modulation gate and at least one second modulation gate on the first surface 2011 of the substrate 201 includes:

[0270] The at least one first modulation gate and the at least one second modulation gate are disposed on the first surface 2011 along the first direction, such that the first doped region 2021 is located between the first end and the second end of the at least one first modulation gate in the first direction, and the second doped region 2022 is located between the first end and the second end of the at least one second modulation gate in the first direction.

[0271] like Figure 18 As shown, in another implementation of this application, the method further includes:

[0272] S104, such as Figure 18a As shown, a first gate is disposed between the at least one first modulation gate and the first carrier storage region FDA, and a second gate is disposed between the at least one second modulation gate and the second carrier storage region FDB.

[0273] Wherein, the first modulation gate and the second modulation gate are used to receive AC modulation signals, and the first gate and the second gate are used to receive DC modulation signals.

[0274] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A pixel structure, characterized in that, The pixel structure includes: Modulation gate group, the modulation gate group comprising: At least one first modulation gate is sequentially disposed on the first surface of the substrate; At least one second modulation gate is sequentially disposed on the first surface, and the at least one second modulation gate and the at least one first modulation gate are respectively complementaryly modulated; as well as The substrate includes: At least two carrier storage regions, the at least two carrier storage regions comprising: a first carrier storage region and a second carrier storage region respectively located on opposite sides of the substrate in a first direction, wherein the first direction is parallel to the first surface; and A carrier collection region is located between the first carrier storage region and the second carrier storage region in the first direction and is in contact with the modulation gate group on the first surface, wherein the doping concentration of the carrier collection region is greater than the doping concentration of the substrate, the carrier collection region has the same doping type as the at least two carrier storage regions, and the carrier collection region has the opposite doping type to the substrate; The carrier collection region includes: The first doped region and the second doped region are respectively located on both sides of the carrier collection region in the first direction; and The third doping region is located between the first doping region and the second doping region, wherein the doping concentration of the first doping region and the second doping region is greater than the doping concentration of the third doping region.

2. The pixel structure as described in claim 1, characterized in that, The first carrier storage region is adjacent to the at least one first modulation gate and distant from the at least one second modulation gate, and the second carrier storage region is adjacent to the at least one second modulation gate and distant from the at least one first modulation gate, wherein: The at least one first modulation gate and the at least one second modulation gate are disposed on the first surface along the first direction, and the at least one first modulation gate includes a first end closest to the first carrier storage region and a second end furthest from the first carrier storage region, and the at least one second modulation gate includes a first end closest to the second carrier storage region and a second end furthest from the second carrier storage region. Wherein, the first doped region is located between the first end and the second end of the at least one first modulation gate in the first direction, and the second doped region is located between the first end and the second end of the at least one second modulation gate in the first direction.

3. The pixel structure as described in claim 1, characterized in that, The doping concentration of the first doped region is 10-100 times that of the third doped region, and the doping concentration of the second doped region is 10-100 times that of the third doped region.

4. The pixel structure as described in claim 1, characterized in that, The first doped region and the second doped region are symmetrically arranged with respect to the first axis, and the third doped region is symmetrical with respect to the first axis, wherein the first axis is perpendicular to the first surface.

5. The pixel structure as described in claim 1, characterized in that, The at least one first modulation gate and the at least one second modulation gate are disposed on the first surface along the first direction, the first carrier storage region is close to the at least one first modulation gate and far away from the at least one second modulation gate, and the second carrier storage region is close to the at least one second modulation gate and far away from the at least one first modulation gate, wherein: The at least one first modulation gate includes a first end closest to the first carrier storage region and a second end furthest from the first carrier storage region; the at least one second modulation gate includes a first end closest to the second carrier storage region and a second end furthest from the second carrier storage region. The carrier collection region is located in the first direction between the first end of the at least one first modulation gate and the first end of the at least one second modulation gate.

6. The pixel structure as described in any one of claims 1 to 5, characterized in that, In a direction perpendicular to the first surface, the length of the carrier collection region is equal to the length of the substrate.

7. The pixel structure as described in any one of claims 1 to 5, characterized in that, In a direction perpendicular to the first surface, the length of the carrier collection region is less than the length of the substrate.

8. The pixel structure as described in any one of claims 1 to 5, characterized in that, The carrier storage region includes: a first carrier storage region adjacent to the at least one first modulation gate, and a second carrier storage region adjacent to the at least one second modulation gate; Wherein, a first gate is provided between the at least one first modulation gate and the first carrier storage region, and a second gate is provided between the at least one second modulation gate and the second carrier storage region; Wherein, the at least one first modulation gate and the at least one second modulation gate are used to receive AC modulation signals, and the first gate and the second gate are used to receive DC modulation signals.

9. The pixel structure as described in any one of claims 1 to 5, characterized in that, The doping concentration of the carrier collection region is 1,000 to 10,000 times that of the substrate.

10. The pixel structure according to any one of claims 1 to 5, characterized in that, The carrier collection region is p-type doped, and the substrate is n-type doped. Alternatively, the carrier collection region may be N-type doped and the substrate may be P-type doped.

11. The pixel structure as described in any one of claims 1 to 5, characterized in that, The modulation gate group further includes: At least one third modulation gate is sequentially disposed on the first surface of the substrate; At least one fourth modulation gate is sequentially disposed on the first surface, and the at least one first modulation gate, the at least one second modulation gate, the at least one third modulation gate and the at least one fourth modulation gate are respectively complementaryly modulated; The first modulation gate and the second modulation gate are symmetrical about the center of the first surface, and the third modulation gate and the fourth modulation gate are symmetrical about the center of the first surface; The at least two carrier storage regions further include: a third carrier storage region and a fourth carrier storage region located on both sides of the substrate in a second direction, respectively, wherein the second direction is parallel to the first surface and perpendicular to the first direction; The carrier collection region is located between the third carrier storage region and the fourth carrier storage region in the second direction.

12. A method for manufacturing a pixel structure, characterized in that, The method includes: At least two carrier storage regions are formed on a substrate by ion implantation, wherein the at least two carrier storage regions include: a first carrier storage region and a second carrier storage region located on both sides of the substrate in a first direction, wherein the first direction is a direction parallel to the first surface of the substrate; A carrier collection region is formed on the substrate by ion implantation; wherein the carrier collection region is located between the first carrier storage region and the second carrier storage region in the first direction, the doping concentration of the carrier collection region is greater than the doping concentration of the substrate, the doping type of the carrier collection region is the same as that of the at least two carrier storage regions, and the doping type of the carrier collection region is opposite to that of the substrate; A modulation gate group is disposed on a first surface of the substrate, wherein the modulation gate group includes at least one first modulation gate and at least one second modulation gate; the at least one second modulation gate and the at least one first modulation gate are respectively complementaryly modulated, and the carrier collection region is in contact with the modulation gate group on the first surface; The process of forming a carrier collection region on the substrate via ion implantation includes: A first doped region and a second doped region are formed on a substrate by ion implantation; wherein the first doped region and the second doped region are located on both sides of the carrier collection region in the first direction; A third doped region is formed on the substrate by ion implantation, wherein the doping concentrations of the first doped region and the second doped region are both greater than the doping concentration of the third doped region, and the third doped region is located between the first doped region and the second doped region.

13. The method for manufacturing a pixel structure as described in claim 12, characterized in that, The first carrier storage region is adjacent to the at least one first modulation gate and distant from the at least one second modulation gate, and the second carrier storage region is adjacent to the at least one second modulation gate and distant from the at least one first modulation gate, wherein: The at least one first modulation gate includes a first end closest to the first carrier storage region and a second end furthest from the first carrier storage region; the at least one second modulation gate includes a first end closest to the second carrier storage region and a second end furthest from the second carrier storage region. The provision of at least one first modulation gate and at least one second modulation gate on the first surface of the substrate includes: The at least one first modulation gate and the at least one second modulation gate are disposed on the first surface along the first direction, such that the carrier collection region is located between the first end of the at least one first modulation gate and the first end of the at least one second modulation gate in the first direction.

14. The method for manufacturing a pixel structure as described in claim 12, characterized in that, The process of forming a carrier collection region on the substrate via ion implantation includes: A first doped region and a second doped region are formed on a substrate by ion implantation; wherein the first doped region and the second doped region are located on both sides of the carrier collection region in the first direction; Ions from the first doped region and the second doped region diffuse into the third region to form a third doped region, wherein the doping concentration of the first doped region and the second doped region is greater than the doping concentration of the third doped region, and the third doped region is located between the first doped region and the second doped region.

15. The method for manufacturing a pixel structure as described in claim 13, characterized in that, The first carrier storage region is adjacent to the at least one first modulation gate and distant from the at least one second modulation gate, and the second carrier storage region is adjacent to the at least one second modulation gate and distant from the at least one first modulation gate, wherein: The at least one first modulation gate includes a first end closest to the first carrier storage region and a second end furthest from the first carrier storage region; the at least one second modulation gate includes a first end closest to the second carrier storage region and a second end furthest from the second carrier storage region. The provision of at least one first modulation gate and at least one second modulation gate on the first surface of the substrate includes: The at least one first modulation gate and the at least one second modulation gate are disposed on the first surface along the first direction, such that the first doped region is located between the first end and the second end of the at least one first modulation gate in the first direction, and the second doped region is located between the first end and the second end of the at least one second modulation gate in the first direction.

16. The method for manufacturing a pixel structure as described in any one of claims 13-15, characterized in that, The doping concentration of the first doped region is 10-100 times that of the third doped region, and the doping concentration of the second doped region is 10-100 times that of the third doped region.

17. The method for manufacturing a pixel structure as described in any one of claims 13-15, characterized in that, The first doped region and the second doped region are symmetrically arranged with respect to the first axis, and the third doped region is symmetrical with respect to the first axis, wherein the first axis is perpendicular to the first surface.

18. The method for manufacturing a pixel structure as described in any one of claims 12-15, characterized in that, In a direction perpendicular to the first surface, the length of the carrier collection region is less than or equal to the length of the substrate.

19. The method for manufacturing a pixel structure as described in any one of claims 13-15, characterized in that, The at least two carrier storage regions include: a first carrier storage region adjacent to the at least one first modulation gate, and a second carrier storage region adjacent to the at least one second modulation gate; the method further includes: A first gate is disposed between the at least one first modulation gate and the first carrier storage region; A second gate is disposed between the at least one second modulation gate and the second carrier storage region; wherein the first modulation gate and the second modulation gate are used to receive AC modulation signals, and the first gate and the second gate are used to receive DC modulation signals.

20. The method for manufacturing a pixel structure as described in any one of claims 12-15, characterized in that, The doping concentration of the carrier collection region is 1,000 to 10,000 times that of the substrate.

21. The method for manufacturing a pixel structure according to any one of claims 12-15, characterized in that, The carrier collection region is p-type doped, and the substrate is n-type doped. Alternatively, the carrier collection region may be N-type doped and the substrate may be P-type doped.

22. The method for manufacturing a pixel structure as described in any one of claims 12-15, characterized in that, The modulation gate group further includes: At least one third modulation gate is sequentially disposed on the first surface of the substrate; At least one fourth modulation gate is sequentially disposed on the first surface, and the at least one first modulation gate, the at least one second modulation gate, the at least one third modulation gate and the at least one fourth modulation gate are respectively complementaryly modulated; The first modulation gate and the second modulation gate are symmetrical about the center of the first surface, and the third modulation gate and the fourth modulation gate are symmetrical about the center of the first surface; The at least two carrier storage regions further include: a third carrier storage region and a fourth carrier storage region located on both sides of the substrate in a second direction, respectively, wherein the second direction is parallel to the first surface and perpendicular to the first direction; The carrier collection region is located between the third carrier storage region and the fourth carrier storage region in the second direction.

Images