A chip architecture and a signal integrity testing method

Abstract

The present application discloses a chip architecture and a signal integrity test method. The chip architecture includes a plurality of modules to be tested and a test module. The test module includes a function register, a data register, and a status register. When the test module receives a test instruction for the communication link of any one of the modules to be tested, the function register and the data register corresponding to the test instruction are configured according to the test instruction, so that the status register and / or the pins of the module to be tested output test results. The present application does not require the chip to be installed on the main board. Directly based on the test module inside the chip architecture, the signal test results of the communication links of each module to be tested can be obtained. The process is simple and fast, the test cost is low, the test scope is clear, the test effects of different modules to be tested can be determined accurately and quickly, and the signal integrity of the chip is ensured.

Description

Technical Field

[0001] The present invention relates to the field of chip testing, and particularly to a chip architecture and a signal integrity testing method. Background Art

[0002] Currently, the testing of chips usually includes wafer testing and FT (Final Test) after chip packaging, including current testing, voltage testing, function testing, timing testing, etc. Signal integrity testing is different from wafer testing and FT testing. Generally, it is to test the entire link during the operation of the chip after the chip is installed on the motherboard. This testing method depends on the mutual support of the motherboard and the chip. However, since the range of the communication link is significantly extended beyond the original chip range, even if there is a problem with the communication link, it is impossible to determine whether the problem of the link is caused by the signal integrity of the chip, nor can it be checked whether there is a problem inside the chip, and it is impossible to adjust the link on the external motherboard according to the situation of the chip.

[0003] Therefore, how to provide a solution to the above technical problems is an issue that those skilled in the art need to solve currently. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a chip architecture and a signal integrity testing method that can be independent of the motherboard dependence and perform signal integrity testing separately. The specific solutions are as follows:

[0005] A chip architecture includes a plurality of modules to be tested and a test module. Each of the modules to be tested is respectively connected to a system bus or a peripheral bus. The test module is connected to both the system bus and the peripheral bus. The test module includes:

[0006] A function register for controlling the conduction or closing of the communication link of any one of the modules to be tested;

[0007] A data register corresponding to each of the modules to be tested for temporarily storing data on the communication link of the module to be tested;

[0008] A status register for verifying whether the data in the data register corresponding to any one of the modules to be tested is correct;

[0009] When the test module receives a test instruction for the communication link of any one of the modules to be tested, it configures the function register and the data register corresponding to the test instruction to enable the status register and / or the pins of the module to be tested to output test results.

[0010] Preferably, the plurality of modules to be tested include:

[0011] One or more of ARM, DDR, PCIe, USB, UART, GPIO, WDT, I2C, and SPI;

[0012] Wherein the ARM, the DDR, the PCIe, and the USB are all connected to the system bus, and the UART, the GPIO, the WDT, the I2C, and the SPI are all connected to the peripheral bus.

[0013] Preferably, the chip architecture further includes:

[0014] A bus conversion protocol bridge connecting the system bus and the peripheral bus.

[0015] Preferably, the function register includes a transmit link enable register and a receive link enable register;

[0016] The data register includes a transmit data register and a receive data register;

[0017] The status register is specifically used to verify whether the data in the receive data register is correct.

[0018] Preferably, the receive data register and the status register are both read-only registers, and the function register and the transmit data register are both read-write registers.

[0019] Correspondingly, the present application also discloses a signal integrity test method, which is applied to the chip architecture described in any one of the above, and includes:

[0020] Configure all modules to be tested to enable all the modules to be tested to work properly;

[0021] Send a test instruction for the communication link of any one of the modules to be tested to the test module to configure the function register and the data register corresponding to the test instruction, so that the status register and / or the pins of the module to be tested output test results;

[0022] Read the test result in the status register or the test result obtained by the signal detection device connected to the pins, and judge whether the signal integrity of the communication link meets the requirements according to the test result.

[0023] Preferably, the test instruction includes a transmit link test instruction, and / or a receive link test instruction, and / or a loopback link test instruction.

[0024] Preferably, when the test instruction is the transmission link test instruction, the process of sending a test instruction for the communication link of any of the modules under test to the test module, configuring the function register with the test instruction and the data register corresponding to the test instruction, so that the status register and / or the pins of the module under test output the test result includes:

[0025] Send the transmission link test instruction to the test module, and write the test data corresponding to the transmission link test instruction into the transmission data register;

[0026] Set the position corresponding to the transmission link test instruction on the transmission link enable register to the enable bit, so that the pins of the module under test output the test result corresponding to the test data;

[0027] Correspondingly, the process of reading the test result in the status register or the test result obtained by the signal detection device connected to the pin, and judging whether the signal integrity of the communication link meets the requirements according to the test result includes:

[0028] Read the test result obtained by the signal detection device connected to the pin. If the test result is consistent with the test data, it is determined that the signal integrity of the transmission link meets the requirements.

[0029] Preferably, when the test instruction is the reception link test instruction, the process of sending a test instruction for the communication link of any of the modules under test to the test module, configuring the function register with the test instruction and the data register corresponding to the test instruction, so that the status register and / or the pins of the module under test output the test result includes:

[0030] Send the reception link test instruction to the test module, and set the position corresponding to the reception link test instruction on the reception link enable register to the enable bit;

[0031] Send test data to the module under test through the pins of the module under test, so that the corresponding reception data register records the reception data corresponding to the test data, and the status register verifies whether the reception data is consistent with the test data and records the test result;

[0032] Correspondingly, the process of reading the test result in the status register or the test result obtained by the signal detection device connected to the pin, and judging whether the signal integrity of the communication link meets the requirements according to the test result includes:

[0033] Read the test result in the status register. If the test result indicates that the received data is consistent with the test data, it is determined that the signal integrity of the receiving link meets the requirements.

[0034] Preferably, when the test instruction is the loopback link test instruction, the process of sending a test instruction for the communication link of any one of the modules under test to the test module, configuring the function register and the data register corresponding to the test instruction with the test instruction, so that the status register and / or the pins of the module under test output the test result includes:

[0035] Send the loopback link test instruction to the test module and write the test data corresponding to the loopback link test instruction into the transmit data register;

[0036] Externally connect the transmit pin and the receive pin of the module under test;

[0037] Set the positions corresponding to the loopback link test instruction in both the transmit link enable register and the receive link enable register to the enable bit;

[0038] Correspondingly, the process of reading the test result in the status register or the test result obtained by the signal detection device connected to the pin, and determining whether the signal integrity of the communication link meets the requirements according to the test result includes:

[0039] Read the test result in the status register. If the test result indicates that the received data is consistent with the test data, it is determined that the signal integrity of the communication link meets the requirements.

[0040] This application discloses a chip architecture, including multiple modules under test and a test module. The test module includes a function register, a data register, and a status register. When the test module receives a test instruction for the communication link of any one of the modules under test, it configures the function register and the data register corresponding to the test instruction according to the test instruction, so that the status register and / or the pins of the module under test output the test result. This application does not require the chip to be installed on the motherboard. Directly based on the test module inside the chip architecture, the signal test results of the communication links of each module under test can be obtained. The process is simple and fast, the test cost is low, the test scope is clear, and the test effects of different modules under test can be determined accurately and quickly, ensuring the signal integrity of the chip. Description of the Drawings

[0041] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained according to the provided drawings.

[0042] Figure 1 It is the structural distribution diagram of a chip architecture in an embodiment of the present invention;

[0043] Figure 2 It is the test schematic diagram of a chip architecture in an embodiment of the present invention;

[0044] Figure 3 It is the step flowchart of a signal integrity test method in an embodiment of the present invention. Detailed implementation manners

[0045] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0046] Signal integrity testing is different from wafer testing and FT testing. Generally, it is to test the entire link during the operation of the chip after the chip is installed on the main board. This testing method depends on the mutual support of the main board and the chip. However, since the range of the communication link is significantly extended beyond the original chip range, even if there is a problem with the communication link, it is impossible to determine whether the problem of the link is caused by the signal integrity of the chip, nor can it be checked whether there is a problem inside the chip, and it is impossible to adjust the link on the external main board according to the situation of the chip.

[0047] This application does not require the chip to be installed on the main board. Directly based on the test module inside the chip architecture, the signal test results of the communication link of each module to be tested can be obtained. The process is simple and fast, the test cost is low, the test range is clear, and it can accurately and quickly determine the test effects of different modules to be tested, ensuring the signal integrity of the chip.

[0048] An embodiment of the present invention discloses a chip architecture, including a plurality of modules to be tested and a test module. Each module to be tested is respectively connected to the system bus or the peripheral bus. The test module is connected to both the system bus and the peripheral bus. The test module includes:

[0049] A function register for controlling the conduction or closing of the communication link of any module to be tested;

[0050] Data registers corresponding to each module under test, used to temporarily store data on the communication link of the module under test;

[0051] Status register, used to verify whether the data in the data register corresponding to any module under test is correct;

[0052] When the test module receives a test instruction for the communication link of any module under test, it configures the function register and the data register corresponding to the test instruction to enable the status register and / or the pins of the module under test to output test results.

[0053] See Figure 1 As shown, the modules under test in the chip architecture are preset functional modules, including one or more of ARM (Advanced RISC Machines), DDR (Double Data Rate, double data rate synchronous dynamic random access memory), PCIe (Peripheral Component Interconnect Express, the latest bus and interface standard), USB (Universal Serial BUS, universal serial bus), UART (Universal Asynchronous Receiver / Transmitter, universal asynchronous receiver / transmitter), GPIO (General Purpose Input Output, general purpose input / output), WDT (Watchdog Timer, watchdog timer circuit), I2C (Inter-Integrated Circuit, two-wire serial bus), and SPI (Serial Peripheral Interface, serial peripheral interface);

[0054] Among them, ARM, DDR, PCIe, and USB are high-speed modules, all connected to the system bus AHB, and UART, GPIO, WDT, I2C, and SPI are low-speed modules, all connected to the peripheral bus APB.

[0055] At this time, the test module SI-TM (Signal Integrity test module) is connected to both the system bus AHB and the peripheral bus APB.

[0056] In addition, the chip architecture also includes: an AHB to APB Bridge that connects the system bus AHB (Advanced High-performance Bus) and the peripheral bus APB (Advanced Peripheral Bus) to perform bus protocol conversion.

[0057] It can be understood that in this embodiment, the signal integrity test of each module to be tested in the chip architecture is implemented by means of a test module. In the test module, corresponding function registers, data registers, and status registers are provided for each module to be tested. Specifically, the function registers include a transmit link enable register and a receive link enable register; the data registers include a transmit data register and a receive data register; the status register is specifically used to verify whether the data in the receive data register is correct. Further, both the receive data register and the status register are read-only registers, and the function registers and the transmit data register are both read-write registers.

[0058] As shown in Tables 1 - 3 below, in the transmit link enable register, receive link enable register, and status register, there are status bit values corresponding to each module to be tested, which are specifically set according to the actual situation. Tables 1 - 3 are an example. Among them, when starting to transmit and starting to receive, the enable bit is set. The so-called no problem in the status register means that the verification result is correct or consistent.

[0059] Table 1 Internal Settings of Transmit Link Enable Register

[0060]

[0061] Table 2 Internal Settings of Receive Link Enable Register

[0062]

[0063] Table 3 Internal Settings of Status Register

[0064]

[0065] Further, each module to be tested corresponds to two data registers: a transmit data register and a receive data register. Taking the DDR module to be tested as an example, the internal settings of the data register are shown in Table 4 below. The register descriptions of other modules to be tested are similar.

[0066] Table 4 Internal Settings of Data Register

[0067]

[0068] Specifically, still taking any module to be tested as an example, its specific signal integrity test can be as Figure 2 shown, where the signal integrity test includes a transmit link test, a receive link test, and a loopback link test.

[0069] When an external device performs a transmit link test on this chip architecture, the following steps will be executed to make the chip architecture respond internally:

[0070] Send a transmission link test instruction to the test module and write the test data corresponding to the transmission link test instruction into the transmission data register;

[0071] Set the position corresponding to the transmission link test instruction on the transmission link enable register to the enable bit, so that the pins of the module under test output the test results corresponding to the test data;

[0072] Read the test results obtained by the signal detection device connected to the pins. If the test results are consistent with the test data, it is determined that the signal integrity of the transmission link meets the requirements.

[0073] It can be understood that the pins of the module under test that output the test results here are the output pins of the module under test. Generally, an oscilloscope can be selected as the signal detection device. Compare the test results displayed by the oscilloscope with the test data in the original transmission link test instruction. If they are consistent, the signal integrity of the transmission link meets the requirements.

[0074] Similarly, when an external device performs a receive link test on this chip architecture, the following steps will be executed to make the chip architecture respond internally:

[0075] Send a receive link test instruction to the test module and set the position corresponding to the receive link test instruction on the receive link enable register to the enable bit;

[0076] Send test data to the module under test through the pins of the module under test, so that the corresponding receive data register records the receive data corresponding to the test data, and the status register verifies whether the receive data is consistent with the test data and records the test results;

[0077] Read the test results in the status register. If the test results show that the receive data is consistent with the test data, it is determined that the signal integrity of the receive link meets the requirements.

[0078] It can be understood that the pins of the module under test through which the test data is sent here are the receive pins. The status register compares the receive data in the receive data register with the test data in the receive link test instruction. If they are consistent, it can be determined that the signal integrity of the receive link of the current module under test meets the requirements.

[0079] Furthermore, when performing a loopback test on the chip architecture, it is actually to loop connect the transmission link and the receive link, that is, externally connect the transmission pin and the receive pin of the module under test, so that the test results output through the transmission pin of the module under test return to the receive data register again as the test data received by the receive pin. Specifically, when an external device performs a loopback test on this chip architecture, the following steps will be executed to make the chip architecture respond internally:

[0080] Send a loopback link test instruction to the test module and write the test data corresponding to the loopback link test instruction into the transmit data register;

[0081] Externally connect the transmit pin and receive pin of the module under test;

[0082] Set the positions corresponding to the loopback link test instruction on both the transmit link enable register and the receive link enable register to the enable bit;

[0083] Read the test result in the status register. If the test result indicates that the received data is consistent with the test data, it is determined that the signal integrity of the communication link meets the requirements.

[0084] It can be seen that this application does not require installing the chip on the motherboard and does not require special equipment. It can directly obtain the signal test results of the communication links of each module under test based on the test module inside the chip architecture. The process is simple and fast, with low test costs, a clear test scope, and can accurately and quickly determine the test effects of different modules under test, ensuring the signal integrity of the chip.

[0085] Correspondingly, the embodiment of this application also discloses a signal integrity test method, which is applied to any one of the above chip architectures. See Figure 3 as shown, including:

[0086] S1: Configure all modules under test to enable all modules under test to work properly;

[0087] S2: Send a test instruction for the communication link of any module under test to the test module to configure the function register and data register corresponding to the test instruction, so that the status register and / or the pins of the module under test output the test result;

[0088] S3: Read the test result in the status register or the test result obtained through the signal detection device connected to the pins, and determine whether the signal integrity of the communication link meets the requirements according to the test result.

[0089] Specifically, the test instruction includes a transmit link test instruction, and / or a receive link test instruction, and / or a loopback link test instruction.

[0090] Specifically, when the test instruction is a transmit link test instruction, step S2 includes:

[0091] Send a transmit link test instruction to the test module and write the test data corresponding to the transmit link test instruction into the transmit data register;

[0092] Set the position corresponding to the transmit link test instruction on the transmit link enable register to the enable bit, so that the pins of the module under test output the test result corresponding to the test data;

[0093] Correspondingly, step S3 includes:

[0094] Read the test result obtained by the signal detection device connected to the pin. If the test result is consistent with the test data, it is determined that the signal integrity of the transmission link meets the requirements.

[0095] Specifically, when the test instruction is a receive link test instruction, step S2 includes:

[0096] Send a receive link test instruction to the test module, and set the position corresponding to the receive link test instruction in the receive link enable register to the enable bit;

[0097] Send test data to the module under test through the pins of the module under test, so that the corresponding receive data register records the receive data corresponding to the test data, and the status register verifies whether the receive data is consistent with the test data and records the test result;

[0098] Correspondingly, step S3 includes:

[0099] Read the test result in the status register. If the test result is that the receive data is consistent with the test data, it is determined that the signal integrity of the receive link meets the requirements.

[0100] Specifically, when the test instruction is a loopback link test instruction, step S2 includes:

[0101] Send a loopback link test instruction to the test module, and write the test data corresponding to the loopback link test instruction into the transmit data register;

[0102] Connect the transmit pin and receive pin of the module under test externally;

[0103] Set the positions corresponding to the loopback link test instruction in both the transmit link enable register and the receive link enable register to the enable bit;

[0104] Correspondingly, step S3 includes:

[0105] Read the test result in the status register. If the test result is that the receive data is consistent with the test data, it is determined that the signal integrity of the communication link meets the requirements.

[0106] This application does not require the chip to be installed on the main board. Directly based on the test module inside the chip architecture, the signal test results of the communication links of each module under test can be obtained. The process is simple and fast, the test cost is low, the test range is clear, and the test effects of different modules under test can be determined accurately and quickly, ensuring the signal integrity of the chip.

[0107] Finally, it should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the existence of additional identical elements in the process, method, article or device comprising said element.

[0108] The above has introduced in detail a chip architecture and a signal integrity test method provided by the present invention. Specific examples are used in this text to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A chip architecture, characterized in that, it includes a plurality of modules to be tested and a test module. Each of the modules to be tested is respectively connected to a system bus or a peripheral bus, and the test module is connected to both the system bus and the peripheral bus. The test module includes: Function registers, used to control the conduction or disconnection of the communication link of any one of the modules to be tested; Data registers corresponding to each of the modules to be tested, used to temporarily store the data on the communication link of the module to be tested; Status registers, used to verify whether the data in the data register corresponding to any one of the modules to be tested is correct; When the test module receives a test instruction for the communication link of any one of the modules to be tested, configure the function register and the data register corresponding to the test instruction according to the test instruction, so that the status register and / or the pins of the module to be tested output test results.

2. The chip architecture according to claim 1, characterized in that, The plurality of modules to be tested include: One or several of ARM, DDR, PCIe, USB, UART, GPIO, WDT, I2C and SPI; Among them, the ARM, the DDR, the PCIe, and the USB are all connected to the system bus, and the UART, the GPIO, the WDT, the I2C, and the SPI are all connected to the peripheral bus.

3. The chip architecture according to claim 2, characterized in that, It further includes: A bus conversion protocol bridge connecting the system bus and the peripheral bus.

4. The chip architecture according to any one of claims 1 to 3, characterized in that, The function register includes a transmit link enable register and a receive link enable register; The data register includes a transmit data register and a receive data register; The status register is specifically used to verify whether the data in the receive data register is correct.

5. The chip architecture according to claim 4, characterized in that, Both the receive data register and the status register are read-only registers, and both the function register and the transmit data register are read-write registers.

6. A signal integrity test method, characterized in that, Applied to the chip architecture according to any one of claims 1 to 5, it includes: Configure all the modules to be tested so that all the modules to be tested work properly; Send a test instruction for the communication link of any one of the modules to be tested to the test module, and configure the function register and the data register corresponding to the test instruction according to the test instruction, so that the status register and / or the pins of the module to be tested output test results; Read the test results in the status register or the test results obtained by a signal detection device connected to the pins, and judge whether the signal integrity of the communication link meets the requirements according to the test results.

7. The signal integrity test method according to claim 6, characterized in that, The test instruction includes a transmit link test instruction, and / or a receive link test instruction, and / or a loopback link test instruction.

8. The signal integrity test method according to claim 7, characterized in that, When the test instruction is the transmission link test instruction, the process of sending a test instruction for the communication link of any of the modules under test to the test module, configuring the function register and the data register corresponding to the test instruction with the test instruction, so that the status register and / or the pins of the module under test output the test result includes: Sending the transmission link test instruction to the test module, and writing the test data corresponding to the transmission link test instruction into the transmit data register; Setting the position corresponding to the transmission link test instruction on the transmission link enable register to the enable bit, so that the pins of the module under test output the test result corresponding to the test data; Correspondingly, the process of reading the test result in the status register or the test result obtained by the signal detection device connected to the pin, and judging whether the signal integrity of the communication link meets the requirements according to the test result includes: Reading the test result obtained by the signal detection device connected to the pin. If the test result is consistent with the test data, it is determined that the signal integrity of the transmission link meets the requirements.

9. According to the signal integrity test method described in claim 7, wherein, When the test instruction is the reception link test instruction, the process of sending a test instruction for the communication link of any of the modules under test to the test module, configuring the function register and the data register corresponding to the test instruction with the test instruction, so that the status register and / or the pins of the module under test output the test result includes: Sending the reception link test instruction to the test module, and setting the position corresponding to the reception link test instruction on the reception link enable register to the enable bit; Sending test data to the module under test through the pins of the module under test, so that the corresponding receive data register records the receive data corresponding to the test data, and the status register verifies whether the receive data is consistent with the test data and records the test result; Correspondingly, the process of reading the test result in the status register or the test result obtained by the signal detection device connected to the pin, and judging whether the signal integrity of the communication link meets the requirements according to the test result includes: Reading the test result in the status register. If the test result is that the receive data is consistent with the test data, it is determined that the signal integrity of the reception link meets the requirements.

10. According to the signal integrity test method described in claim 9, wherein, When the test instruction is the loopback link test instruction, the process of sending a test instruction for the communication link of any of the modules under test to the test module, configuring the function register and the data register corresponding to the test instruction with the test instruction, so that the status register and / or the pins of the module under test output the test result includes: Sending the loopback link test instruction to the test module, and writing the test data corresponding to the loopback link test instruction into the transmit data register; Externally connecting the transmit pin and the receive pin of the module under test; Set the positions corresponding to the loopback link test instruction in both the transmit link enable register and the receive link enable register to the enable bit; Correspondingly, the process of reading the test result in the status register or the test result obtained by a signal detection device connected to the pin, and determining whether the signal integrity of the communication link meets the requirements according to the test result includes: Read the test result in the status register. If the test result indicates that the received data is the same as the test data, it is determined that the signal integrity of the communication link meets the requirements.

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