Reset circuit verification method and device, electronic equipment and medium

Abstract

The present disclosure provides a reset circuit verification method and device, electronic equipment and medium, relates to the technical field of computers, and particularly to the field of chips. The implementation scheme is: a reset circuit is used to execute a verification use case to obtain a first reset count value of each reset source in a plurality of reset sources and a second reset count value of each functional module in a plurality of functional modules, wherein the first reset count value of each reset source is the number of reset instructions detected by the reset source in the process of executing the verification use case, and the second reset count value of each functional module is the number of reset instructions detected by the functional module in the process of executing the verification use case; and for each functional module in the plurality of functional modules, at least based on the second reset count value of the functional module and the first reset count value of each reset source in at least one reset source corresponding to the functional module, a verification result of the reset circuit is determined.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of computer, in particular, to the field of chip, and more particularly, to a reset circuit verification method and device, electronic equipment, computer readable storage medium and computer program product. BACKGROUND

[0002] The reset function of a circuit is the basis for its normal operation. Once a problem occurs, it may cause functional disorder or even scrap. Therefore, it is of great significance to specially verify the reset circuit to ensure its correctness.

[0003] The methods described in this section can not necessarily be the methods previously conceived or used. Unless otherwise indicated, nothing in this section should be assumed to be prior art merely because it is included in this section. Similarly, nothing in this section should be assumed to be known or to be in the prior art merely because it is included in this section. SUMMARY

[0004] The present disclosure provides a reset circuit verification method and device, electronic equipment, computer readable storage medium and computer program product.

[0005] According to an aspect of the present disclosure, a reset circuit verification method is provided, wherein the reset circuit includes a plurality of reset sources and a plurality of functional modules, each of the plurality of functional modules is capable of obtaining a reset instruction from at least one of the plurality of reset sources, the method comprising: executing a verification use case by using the reset circuit to obtain a first reset count value of each of the plurality of reset sources and a second reset count value of each of the plurality of functional modules, wherein the first reset count value of each of the plurality of reset sources is the number of reset instructions detected by the reset source in the process of executing the verification use case, and the second reset count value of each of the plurality of functional modules is the number of reset instructions detected by the functional module in the process of executing the verification use case; and for each of the plurality of functional modules, determining a verification result of the reset circuit based at least on the second reset count value of the functional module and the first reset count value of each of the at least one reset source corresponding to the functional module.

[0006] According to another aspect of this disclosure, a reset circuit verification apparatus is provided, wherein the reset circuit includes a plurality of reset sources and a plurality of functional modules, each of the plurality of functional modules being capable of acquiring a reset command from at least one of the plurality of reset sources. The apparatus includes: an acquisition unit configured to execute verification test cases using the reset circuit to obtain a first reset count value for each of the plurality of reset sources and a second reset count value for each of the plurality of functional modules, wherein the first reset count value for each reset source is the number of reset commands detected at that reset source during the execution of the verification test cases, and the second reset count value for each functional module is the number of reset commands detected at that functional module during the execution of the verification test cases; and a first determination unit configured to determine, for each of the plurality of functional modules, a verification result for the reset circuit based at least on the second reset count value of that functional module and the first reset count value of each of the at least one reset source corresponding to that functional module.

[0007] According to another aspect of this disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the methods described above.

[0008] According to another aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions, wherein the computer instructions are used to cause a computer to perform the methods described above.

[0009] According to another aspect of this disclosure, a computer program product is provided, including a computer program, wherein the computer program implements the above-described method when executed by a processor.

[0010] According to one or more embodiments of this disclosure, it is possible to conveniently and effectively verify the connectivity between the reset source and the functional module in the reset circuit.

[0011] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0012] The accompanying drawings exemplify embodiments and form part of the specification, serving together with the textual description to explain exemplary implementations of the embodiments. The illustrated embodiments are for illustrative purposes only and do not limit the scope of the claims. Throughout the drawings, the same reference numerals refer to similar but not necessarily identical elements.

[0013] Figure 1 A schematic diagram of an exemplary system in which the various methods described herein may be implemented according to embodiments of the present disclosure is shown;

[0014] Figure 2 A flowchart illustrating a verification method for a reset circuit according to an embodiment of the present disclosure is shown;

[0015] Figure 3 A schematic diagram showing the correspondence between multiple reset sources and multiple functional modules according to embodiments of the present disclosure is illustrated.

[0016] Figure 4 A schematic diagram illustrating the acquisition of reset source-side and functional module-side count values ​​according to an embodiment of the present disclosure is shown;

[0017] Figure 5 A schematic diagram of a reset circuit verification method according to an embodiment of the present disclosure is shown;

[0018] Figure 6 A structural block diagram of a reset circuit verification device according to an embodiment of the present disclosure is shown; and

[0019] Figure 7 Structural block diagram of an exemplary electronic device that can be used to implement embodiments of the present disclosure. Detailed Implementation

[0020] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0021] In this disclosure, unless otherwise stated, the use of terms such as "first," "second," etc., to describe various elements is not intended to limit the positional, temporal, or importance relationships of these elements; such terms are merely used to distinguish one element from another. In some examples, the first element and the second element may refer to the same instance of that element, while in other cases, based on the context, they may refer to different instances.

[0022] The terminology used in the description of the various examples in this disclosure is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context explicitly indicates otherwise, an element may be one or more unless the number of elements is specifically limited. Furthermore, the term "and / or" as used in this disclosure covers any one of the listed items and all possible combinations thereof.

[0023] A reset circuit includes a reset source, functional modules, and a reset network for instruction transmission between the reset source and functional modules. In related technologies, RDC tools are commonly used to verify reset circuits. RDC verification can perform code inspection from a design perspective to ensure the correctness of clock and reset logic in the code, and is generally used for verifying the internal logic of functional modules. However, RDC tools cannot verify the reset network within the reset circuit; in other words, it is difficult to verify the connectivity between the reset source and functional modules in the reset circuit using RDC tools.

[0024] Based on this, this disclosure proposes a reset circuit verification method. The method utilizes a reset circuit to execute verification test cases, obtaining a first reset count value for each of a plurality of reset sources and a second reset count value for each of a plurality of functional modules. Based on this, for each of the multiple functional modules, the verification result of the reset circuit is determined at least based on the second reset count value of that functional module and the first reset count value of at least one of the at least one reset source corresponding to that functional module. Therefore, based on the correspondence between reset sources and functional modules in the reset circuit, the connectivity between reset sources and functional modules can be verified conveniently and effectively through the count values ​​on the reset source side and the count values ​​on the functional module side. This helps developers to promptly identify problems in the reset network of the reset circuit and accelerates the development process.

[0025] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0026] Figure 1 A schematic diagram of an exemplary system 100 in which the various methods and apparatus described herein can be implemented according to embodiments of this disclosure is shown. Reference Figure 1 The system 100 includes one or more client devices 101, 102, 103, 104, 105 and 106, a server 120, and one or more communication networks 110 coupling the one or more client devices to the server 120. The client devices 101, 102, 103, 104, 105 and 106 can be configured to execute one or more applications.

[0027] In embodiments of this disclosure, server 120 may run one or more services or software applications that enable the execution of a reset circuit verification method.

[0028] In some embodiments, server 120 may also provide other services or software applications that may include non-virtual and virtual environments. In some embodiments, these services may be provided as web-based services or cloud services, such as to users of client devices 101, 102, 103, 104, 105 and / or 106 under a Software as a Service (SaaS) model.

[0029] exist Figure 1 In the configuration shown, server 120 may include one or more components that implement the functions performed by server 120. These components may include software components, hardware components, or combinations thereof that can be executed by one or more processors. Users operating client devices 101, 102, 103, 104, 105, and / or 106 can sequentially interact with server 120 using one or more client applications to utilize the services provided by these components. It should be understood that various different system configurations are possible and may differ from system 100. Therefore, Figure 1 This is an example of a system used to implement the various methods described herein, and is not intended to be limiting.

[0030] Users can use client devices 101, 102, 103, 104, 105, and / or 106 to obtain count values ​​on the reset source side and the functional module side. The client devices can provide an interface that allows users to interact with the client devices. The client devices can also output information to the user via this interface. Although... Figure 1 Only six client devices are described, but those skilled in the art will understand that this disclosure can support any number of client devices.

[0031] Client devices 101, 102, 103, 104, 105, and / or 106 may include various types of computer devices, such as portable handheld devices, general-purpose computers (such as personal computers and laptops), workstation computers, wearable devices, smart screen devices, self-service terminal devices, service robots, gaming systems, thin clients, various messaging devices, sensors, or other sensing devices. These computer devices can run various types and versions of software applications and operating systems, such as Microsoft Windows, Apple iOS, UNIX-like operating systems, Linux or Linux-like operating systems (such as Google Chrome OS); or include various mobile operating systems, such as Microsoft Windows Mobile OS, iOS, Windows Phone, and Android. Portable handheld devices may include cellular phones, smartphones, tablets, personal digital assistants (PDAs), etc. Wearable devices may include head-mounted displays (such as smart glasses) and other devices. Gaming systems may include various handheld gaming devices, internet-enabled gaming devices, etc. Client devices are capable of executing various applications, such as various internet-related applications, communication applications (such as email applications), short message service (SMS) applications, and can use various communication protocols.

[0032] Network 110 can be any type of network well known to those skilled in the art, and can support data communication using any of a variety of available protocols (including but not limited to TCP / IP, SNA, IPX, etc.). By way of example only, one or more networks 110 can be a local area network (LAN), an Ethernet-based network, a token ring network, a wide area network (WAN), the Internet, a virtual network, a virtual private network (VPN), an intranet, an extranet, a public switched telephone network (PSTN), an infrared network, a wireless network (e.g., Bluetooth, WIFI), and / or any combination of these and / or other networks.

[0033] Server 120 may include one or more general-purpose computers, special-purpose server computers (e.g., PC (personal computer) servers, UNIX servers, mid-range servers), blade servers, mainframe computers, server clusters, or any other suitable arrangement and / or combination. Server 120 may include one or more virtual machines running a virtual operating system, or other computing architectures involving virtualization (e.g., one or more flexible pools of logical storage devices that can be virtualized to maintain virtual storage devices for servers). In various embodiments, server 120 may run one or more services or software applications that provide the functionality described below.

[0034] The computing unit in server 120 can run one or more operating systems, including any of the aforementioned operating systems and any commercially available server operating system. Server 120 can also run any of a variety of additional server applications and / or middleware applications, including HTTP servers, FTP servers, CGI servers, JAVA servers, database servers, etc.

[0035] In some implementations, server 120 may include one or more applications to analyze and merge data feeds and / or event updates received from users of client devices 101, 102, 103, 104, 105 and / or 106. Server 120 may also include one or more applications to display data feeds and / or real-time events via one or more display devices of client devices 101, 102, 103, 104, 105 and / or 106.

[0036] In some implementations, server 120 can be a server for a distributed system or a server integrated with blockchain. Server 120 can also be a cloud server, or an intelligent cloud computing server or intelligent cloud host with artificial intelligence technology. A cloud server is a host product in the cloud computing service system, designed to address the shortcomings of traditional physical hosts and Virtual Private Server (VPS) services, such as high management difficulty and weak business scalability.

[0037] System 100 may also include one or more databases 130. In some embodiments, these databases may be used to store data and other information. For example, one or more of the databases 130 may be used to store information such as audio files and video files. Databases 130 may reside in various locations. For example, a database used by server 120 may be local to server 120, or it may be located away from server 120 and may communicate with server 120 via a network-based or dedicated connection. Databases 130 may be of different types. In some embodiments, the database used by server 120 may be, for example, a relational database. One or more of these databases may store, update, and retrieve data from and from the databases in response to commands.

[0038] In some embodiments, one or more of the databases 130 may also be used by an application to store application data. The databases used by the application may be of different types, such as key-value stores, object stores, or regular stores supported by a file system.

[0039] Figure 1 The system 100 can be configured and operated in various ways to enable the application of the various methods and apparatus described in this disclosure.

[0040] The technical solutions disclosed herein involve the collection, storage, use, processing, transmission, provision, and disclosure of users' personal information.

[0041] Figure 2 The flowchart illustrates a reset circuit verification method according to an exemplary embodiment of the present disclosure, wherein the reset circuit includes a plurality of reset sources and a plurality of functional modules, each of the plurality of functional modules being capable of obtaining a reset command from at least one of the plurality of reset sources, such as... Figure 2 As shown, the method includes: step S201, executing a verification test case using a reset circuit to obtain a first reset count value for each of the multiple reset sources and a second reset count value for each of the multiple functional modules, wherein the first reset count value for each reset source is the number of reset commands detected at that reset source during the execution of the verification test case, and the second reset count value for each functional module is the number of reset commands detected at that functional module during the execution of the verification test case; and step S202, for each of the multiple functional modules, determining the verification result of the reset circuit based at least on the second reset count value of the functional module and the first reset count value of each of the at least one reset source corresponding to the functional module.

[0042] Therefore, based on the correspondence between the reset source and the functional module in the reset circuit, the connectivity between the reset source and the functional module can be verified conveniently and effectively by using the count values ​​on the reset source side and the count values ​​on the functional module side. This can help developers discover problems in the reset network in the reset circuit in a timely manner and accelerate the development process.

[0043] The reset circuit can be in hardware form or in code form; no limitation is made here.

[0044] Figure 3 A schematic diagram illustrating the correspondence between multiple reset sources and multiple functional modules in an exemplary reset circuit is shown. Figure 3 As shown, the reset circuit includes 5 reset sources and 8 functional modules. The 5 reset sources are global reset, user reset, MCU reset, mode 0 reset, and mode 1 reset. The 8 functional modules are IP0, IP1, IP2, IP3, IP4, IP5, IP6, and P7. Between the 5 reset sources and 8 functional modules is a tree-structured reset network with multiple nodes. This network transmits signals from the reset sources to different reset ports on the functional modules to complete the corresponding reset functions.

[0045] Will Figure 3The correspondence between the 5 reset sources and 8 functional modules is represented in a table, as shown in Table 1 below.

[0046] Table 1

[0047]

[0048] It is understood that the number of reset sources and functional modules described above is merely an example, and this disclosure does not limit the number of reset sources and functional modules in the reset circuit.

[0049] At the same time, a layered structure can also be allowed in the reset circuit, for example, in Figure 3 The right side of the functional module IP0 can be further connected to IP0.0 and IP0.1. The reset instructions for IP0.0 and IP0.1 originate from IP0, and the reset instructions for IP0 originate from global reset and mode 0 reset. Therefore, the correspondence between IP0.0 and IP0.1 and the reset source can be deduced; that is, the reset sources corresponding to IP0.0 and IP0.1 are also global reset and mode 0 reset. Thus, for the layer where IP0.0 and IP0.1 reside, a correspondence between the reset source side and the functional module side, as shown in Table 1, can be established. By analogy, this disclosure can establish a correspondence between the reset source side and the functional module side for each layer in a multi-layer structure, and then perform subsequent steps S201 and S202 for each functional module of each layer.

[0050] According to some embodiments, the functional module may be an intellectual property module (IP module).

[0051] According to some embodiments, the reset command may include at least one of cold reset, warm reset, hard reset, soft reset, system reset, and functional reset. The verification method disclosed herein does not limit the type of reset command, thus enabling it to adapt to verification in various scenarios and with strong generalization.

[0052] According to some embodiments, the reset circuit can be located in the chip.

[0053] For step S201, a verification test case is executed using a reset circuit to obtain a first reset count value for each of the multiple reset sources and a second reset count value for each of the multiple functional modules.

[0054] According to some embodiments, by creating a counter and attaching the created counter to the reset source side and the functional module side respectively, a first reset count value for each of the multiple reset sources and a second reset count value for each of the multiple functional modules can be obtained.

[0055] In one implementation, the creation and mounting of the counter can be achieved via a script.

[0056] Figure 4 A schematic diagram illustrating an embodiment of the present disclosure for obtaining count values ​​on the reset source side and the functional module side is shown, as follows: Figure 4 As shown, a corresponding counter is attached to each of the five reset sources in the reset circuit to obtain the first reset count value detected by each reset source during the execution of the verification test case; a corresponding counter is attached to each of the eight functional modules in the reset circuit to obtain the second reset count value detected by each functional module during the execution of the verification test case.

[0057] According to some embodiments, a reset path table is obtained before attaching the counter to each reset source and each functional module; and the location where the counter corresponding to each reset source is attached and the location where the counter corresponding to each functional module is attached are determined based on the reset path table.

[0058] In one implementation, a counter corresponding to each reset source is attached to the output port of the reset source, and a counter corresponding to each functional module is attached to the input port of the functional module.

[0059] For step S202, for each of the multiple functional modules, the verification result of the reset circuit can be determined based at least on the consistency between the second reset count value of the functional module and the first reset count value of each of the at least one reset source corresponding to the functional module.

[0060] According to some embodiments, multiple functional modules can be divided into one or more reset types, and at least one reset source corresponding to each functional module is the same as at least one reset source corresponding to the reset type to which the functional module belongs. Determining the verification result of the reset circuit based at least on the second reset count value of the functional module and the first reset count value of each of the at least one reset source corresponding to the functional module may include: for each of the one or more reset types, determining the type count value of the reset type based on the first count value of each of the at least one reset source corresponding to the reset type; and determining the verification result of the reset circuit based on the second reset count value of the functional module and the type count value of the reset type to which the functional module belongs.

[0061] Since there are a large number of functional modules in the reset circuit that correspond to the same reset source, multiple functional modules can be divided into one or more reset types based on the consistency of the reset source corresponding to each functional module. The count value on the reset source side can be determined based on each reset type, which can effectively reduce the amount of data processing and improve the verification efficiency.

[0062] As mentioned above Figure 3 Taking the exemplary reset circuit shown as an example, the correspondence between multiple reset sources and multiple functional modules can be seen from Table 1. It can be observed that among the eight functional modules, there are functional modules with the same corresponding reset source. Grouping these functional modules with the same reset source into one reset type yields the correspondence shown in Table 2 below.

[0063] Table 2

[0064]

[0065] Type 1 includes IP0 and IP4, Type 2 includes IP1 and IP7, Type 3 includes IP2 and IP6, and Type 4 includes IP3 and IP5.

[0066] Therefore, only the type count value corresponding to each reset type needs to be calculated for types 1-4. After the type count values ​​corresponding to types 1-4 are determined, for each functional module, it is only necessary to determine the type count value of the reset type to which the functional module belongs and the second reset count value of the functional module to perform verification.

[0067] According to some embodiments, determining the type count value of the reset type based on the first count value of each of the at least one reset source corresponding to the reset type may include: determining the type count value of the reset type based on the sum of the first count values ​​of each of the at least one reset source corresponding to the reset type.

[0068] When the connection between the reset source side and the functional module side of the reset circuit is good, for each functional module, the sum of the second reset count value of the functional module and the first count value of each of the at least one reset source corresponding to the functional module should be consistent. Therefore, by determining the type count value of the reset type as the sum of the first count values ​​of each of the at least one reset source corresponding to the reset type, the sum of the first count values ​​can be applied to the count value comparison for each functional module in the reset type.

[0069] According to some embodiments, before determining the verification result of the reset circuit, for each of the plurality of reset sources, the timestamp of each reset instruction among the first reset count value and reset instructions of that reset source is determined, and for each of the plurality of functional modules, the timestamp of each reset instruction among the second reset count value and reset instructions of that functional module is determined; wherein, determining the verification result of the reset circuit based at least on the second reset count value of the functional module and the first reset count value of each of the at least one reset source corresponding to the functional module may include: determining the verification result of the reset circuit based on the timestamp of each reset instruction among the second reset count value and reset instructions of the functional module and the timestamp of each reset instruction among the first reset count value and reset instructions of each of the at least one reset source corresponding to the functional module, and the second reset count value of the functional module and the first reset count value of each of the at least one reset source corresponding to the functional module.

[0070] Therefore, it is possible to track the reset instructions transmitted between the reset source side and the functional module side based on the timestamp of each reset instruction in the second reset count reset instructions of the functional module and the timestamp of each reset instruction in the first reset count reset instructions of each reset source corresponding to the functional module.

[0071] According to some embodiments, the verification result of the reset circuit is determined as follows: for any one of the reset instructions in the second reset count value of the functional module, if the time difference between the timestamp of the reset instruction and the timestamp of any one of the reset instructions of each of the at least one reset source corresponding to the functional module is not within the preset time range, the verification result of the reset circuit is determined to be unsuccessful.

[0072] Since the length of the transmission path between any reset source and any functional module in the reset network is fixed and constant, the time difference between the timestamp corresponding to the triggering of the count at the reset source and the timestamp corresponding to the triggering of the count at the functional module for the transmission of a reset command from the reset source to the functional module should be within a preset time range.

[0073] Therefore, for any reset instruction among the second reset count value and reset instructions of the functional module, if the time difference between the timestamp of the reset instruction and the timestamp of any reset instruction from any of the at least one reset source corresponding to the functional module is not within the preset duration, it indicates that the reset instruction received by the functional module was not issued from any of the at least one reset source corresponding to it. This confirms an abnormality in the reset instruction transmission from the reset source side to the functional module side. Regardless of whether the second reset count value of the functional module is consistent with the first reset count value of each of the at least one reset source corresponding to the functional module, the verification result of the reset circuit can be determined as failing.

[0074] According to some embodiments, a queue can be used to store the timestamps of multiple reset sources in the reset circuit. Specifically, on the reset source side, when any reset source detects a reset command and counts once, the timestamp corresponding to that count is stored in the queue. For any reset command among the second reset count value and reset commands of the functional module, if the time difference between the timestamp of the reset command and any timestamp in the queue is not within a preset duration, it can be determined that the verification result of the reset circuit is failed.

[0075] According to some embodiments, the reset instruction includes a reset enable instruction and a reset release instruction, the first reset count value includes a first enable count value and a first release count value, the second reset count value includes a second enable count value and a second release count value, and wherein determining the verification result of the reset circuit includes at least one of the following methods: determining the verification result of the reset circuit based on the second enable count value of the functional module and the first enable count value of each of the at least one reset source corresponding to the functional module; and determining the verification result of the reset circuit based on the second release count value of the functional module and the first release count value of each of the at least one reset source corresponding to the functional module. Therefore, by refining the reset instruction into a reset enable instruction and a reset release instruction, verification can be performed on the reset enable instruction and the reset release instruction respectively, thereby further improving the accuracy of the verification.

[0076] According to some embodiments, determining the verification result of the reset circuit based at least on the second reset count value of the functional module and the first reset count value of each of the at least one reset source corresponding to the functional module further includes at least one of the following: for each of the plurality of reset sources, determining the verification result of the reset circuit based on the first enable count value and the first release count value of the reset source; and for each of the plurality of functional modules, determining the verification result of the reset circuit based on the second enable count value and the second release count value of the functional module.

[0077] Since the number of reset enable instructions and reset release instructions is always equal during the execution of the reset function, whether on the reset source side or the functional module side, the accuracy of the verification can be further improved by verifying the consistency of the count of reset enable instructions and the count of reset release instructions on both the reset source side and the functional module side.

[0078] Figure 5 A schematic diagram of an exemplary reset circuit verification method is shown. (As follows) Figure 5 As shown, the reset circuit verification method can be implemented using 501~506 as follows.

[0079] 501. Establish a reset relationship table based on the design information of the reset circuit;

[0080] 502. Summarize the reset type table based on the reset relationship table;

[0081] 503. Create counters for all reset sources and functional modules;

[0082] 504. Based on the reset path information table, the created counters are attached to the ports of each reset source and functional module to collect the first reset count value and timestamp information of each reset source, as well as the second reset count value and timestamp information of each functional module during the verification process.

[0083] 505. The reset network is verified by analyzing the first reset count value and timestamp information of each reset source and the second reset count value and timestamp information of each functional module.

[0084] 506. An analysis report is obtained based on the verification results.

[0085] Among them, 502~505 can be implemented by script. When the design code of the reset circuit changes, it is generally only necessary to update the reset relationship table and the reset path information table and re-execute the script.

[0086] Figure 6A structural block diagram of a reset circuit verification apparatus according to an exemplary embodiment of the present disclosure is shown. The reset circuit includes a plurality of reset sources and a plurality of functional modules. Each functional module is capable of acquiring a reset command from at least one of the reset sources. The apparatus 600 includes: an acquisition unit 601 configured to execute verification test cases using the reset circuit to obtain a first reset count value for each of the reset sources and a second reset count value for each of the functional modules, wherein the first reset count value for each reset source is the number of reset commands detected at that reset source during the execution of the verification test cases, and the second reset count value for each functional module is the number of reset commands detected at that functional module during the execution of the verification test cases; and a first determination unit 602 configured to determine, for each of the functional modules, a verification result for the reset circuit based at least on the second reset count value of that functional module and the first reset count value of each of the at least one reset source corresponding to that functional module.

[0087] According to some embodiments, multiple functional modules can be divided into one or more reset types, and at least one reset source corresponding to each functional module is the same as at least one reset source corresponding to the reset type to which the functional module belongs. The determining unit includes: a first determining subunit configured to determine a type count value for each of the one or more reset types based on a first count value of each of the at least one reset source corresponding to that reset type; and a second determining subunit configured to determine a verification result for the reset circuit based on a second reset count value of the functional module and the type count value of the reset type to which the functional module belongs.

[0088] According to some embodiments, the first determining subunit includes: a subunit for determining a type count value of the reset type based on the sum of first count values ​​of each of at least one reset source corresponding to the reset type.

[0089] According to some embodiments, the apparatus further includes: a second determining unit configured to, before determining the verification result of the reset circuit, determine, for each of a plurality of reset sources, a timestamp of each of a first reset count value and a reset instruction of the reset source, and for each of a plurality of functional modules, determine a timestamp of each of a second reset count value and a reset instruction of the functional module; wherein the first determining unit includes: a subunit configured to determine the verification result of the reset circuit based on the timestamp of each of the second reset count value and a reset instruction of the functional module and the timestamp of each of the first reset count value and a reset instruction of the at least one reset source corresponding to the functional module, and the second reset count value of the functional module and the first reset count value of the at least one reset source corresponding to the functional module.

[0090] According to some embodiments, the first determining unit further includes: a subunit for determining that the verification result of the reset circuit is unsuccessful in response to any one of the second reset count reset instructions of the functional module, in response to the time difference between the timestamp of the reset instruction and the timestamp of any one of the reset instructions of at least one reset source corresponding to the functional module being outside the preset time range.

[0091] According to some embodiments, the reset instruction includes a reset enable instruction and a reset release instruction, the first reset count value includes a first enable count value and a first release count value, the second reset count value includes a second enable count value and a second release count value, and wherein the first determining unit includes at least one of the following sub-units: a sub-unit for determining the verification result of the reset circuit based on the second enable count value of the functional module and the first enable count value of each of the at least one reset source corresponding to the functional module; and a sub-unit for determining the verification result of the reset circuit based on the second release count value of the functional module and the first release count value of each of the at least one reset source corresponding to the functional module.

[0092] According to some embodiments, the first determining unit further includes at least one of the following subunits: a subunit for determining the verification result of the reset circuit based on a first enable count value and a first release count value of the reset source for each of the plurality of reset sources; and a subunit for determining the verification result of the reset circuit based on a second enable count value and a second release count value of the functional module for each of the plurality of functional modules.

[0093] According to some embodiments, the reset command includes at least one of cold reset, warm reset, hard reset, soft reset, system reset, and functional reset.

[0094] According to some embodiments, the reset circuit is located in the chip.

[0095] According to embodiments of this disclosure, an electronic device is also provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform any of the methods described above.

[0096] According to embodiments of this disclosure, a non-transitory computer-readable storage medium storing computer instructions is also provided, wherein the computer instructions are used to cause a computer to perform any of the methods described above.

[0097] According to embodiments of this disclosure, a computer program product is also provided, including a computer program, wherein the computer program implements any of the methods described above when executed by a processor.

[0098] refer to Figure 7 The present invention describes a structural block diagram of an electronic device 700 that can serve as a server or client of the present disclosure, which is an example of a hardware device that can be applied to various aspects of the present disclosure. The electronic device is intended to represent various forms of digital electronic computer devices, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0099] like Figure 7 As shown, the electronic device 700 includes a computing unit 701, which can execute various appropriate instructions and processes based on a computer program stored in a read-only memory (ROM) 702 or a computer program loaded into a random access memory (RAM) 703 from a storage unit 708. The RAM 703 may also store various programs and data required for the operation of the electronic device 700. The computing unit 701, ROM 702, and RAM 703 are interconnected via a bus 704. An input / output (I / O) interface 705 is also connected to the bus 704.

[0100] Multiple components in electronic device 700 are connected to I / O interface 705, including: input unit 706, output unit 707, storage unit 708, and communication unit 709. Input unit 706 can be any type of device capable of inputting information to electronic device 700. Input unit 706 can receive input digital or character information and generate key signal inputs related to user settings and / or function control of electronic device, and may include, but is not limited to, a mouse, keyboard, touchscreen, trackpad, trackball, joystick, microphone, and / or remote control. Output unit 707 can be any type of device capable of presenting information, and may include, but is not limited to, a monitor, speaker, video / audio output terminal, vibrator, and / or printer. Storage unit 708 may include, but is not limited to, hard disk and optical disk. Communication unit 709 allows electronic device 700 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks, and may include, but is not limited to, modems, network cards, infrared communication devices, wireless communication transceivers, and / or chipsets, such as Bluetooth™ devices, 802.11 devices, WiFi devices, WiMax devices, cellular communication devices, and / or the like.

[0101] The computing unit 701 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 701 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 701 performs the various methods and processes described above, such as the reset circuit verification method. For example, in some embodiments, the reset circuit verification method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 708. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 700 via ROM 702 and / or communication unit 709. When the computer program is loaded into RAM 703 and executed by the computing unit 701, one or more steps of the reset circuit verification method described above may be performed. Alternatively, in other embodiments, the computing unit 701 may be configured to perform the reset circuit verification method by any other suitable means (e.g., by means of firmware).

[0102] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0103] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0104] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0105] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0106] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0107] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0108] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0109] While embodiments or examples of this disclosure have been described with reference to the accompanying drawings, it should be understood that the methods, systems, and devices described above are merely exemplary embodiments or examples, and the scope of the invention is not limited by these embodiments or examples, but only by the granted claims and their equivalents. Various elements in the embodiments or examples may be omitted or replaced by their equivalents. Furthermore, the steps may be performed in a different order than that described in this disclosure. Further, various elements in the embodiments or examples may be combined in various ways. Importantly, as the technology evolves, many elements described herein can be replaced by equivalents that appear after this disclosure.

Claims

1. A method for verifying a reset circuit, wherein, The reset circuit includes multiple reset sources and multiple functional modules. Each of the multiple functional modules is capable of obtaining a reset command from at least one of the multiple reset sources. The method includes: The verification test case is executed using the reset circuit to obtain a first reset count value for each of the plurality of reset sources and a second reset count value for each of the plurality of functional modules, wherein the first reset count value for each reset source is the number of reset commands detected at that reset source during the execution of the verification test case, and the second reset count value for each functional module is the number of reset commands detected at that functional module during the execution of the verification test case. For each of the plurality of reset sources, determine the timestamp of each reset instruction among the first reset count value reset instructions for that reset source; and for each of the plurality of functional modules, determine the timestamp of each reset instruction among the second reset count value reset instructions for that functional module; and For each of the plurality of functional modules, the verification result of the reset circuit is determined based at least on the second reset count value of that functional module and the first reset count value of each of the at least one reset source corresponding to that functional module, including: Based on the timestamp of each reset instruction in the second reset count value of the functional module and the timestamp of each reset instruction in the first reset count value of each reset source corresponding to the functional module, as well as the second reset count value of the functional module and the first reset count value of each reset source corresponding to the functional module, the verification result of the reset circuit is determined; and For any one of the reset instructions in the second reset count value of the functional module, if the time difference between the timestamp of the reset instruction and the timestamp of any one of the reset instructions of each of the at least one reset source corresponding to the functional module is not within the preset time range, the verification result of the reset circuit is determined to be unsuccessful.

2. The method according to claim 1, wherein, The multiple functional modules can be divided into one or more reset types, and at least one reset source corresponding to each functional module is the same as at least one reset source corresponding to the reset type to which the functional module belongs. Furthermore, determining the verification result of the reset circuit based at least on the second reset count value of the functional module and the first reset count value of each of the at least one reset source corresponding to the functional module includes: For each of the one or more reset types, a type count value for that reset type is determined based on a first count value of each of the at least one reset source corresponding to that reset type; and Based on the second reset count value of the functional module and the type count value of the reset type to which the functional module belongs, the verification result of the reset circuit is determined.

3. The method according to claim 2, wherein, The determination of the type count value of the reset type based on the first count value of each of the at least one reset source corresponding to the reset type includes: The type count value of the reset type is determined based on the sum of the first count values ​​of each of the at least one reset source corresponding to the reset type.

4. The method according to any one of claims 1 to 3, wherein, The reset instruction includes a reset enable instruction and a reset release instruction; the first reset count value includes a first enable count value and a first release count value; and the second reset count value includes a second enable count value and a second release count value. Furthermore, determining the verification result of the reset circuit includes at least one of the following methods: Based on the second enable count value of the functional module and the first enable count value of each of the at least one reset source corresponding to the functional module, the verification result of the reset circuit is determined; and Based on the second release count value of the functional module and the first release count value of each of the at least one reset source corresponding to the functional module, the verification result of the reset circuit is determined.

5. The method according to claim 4, wherein, The determination of the verification result of the reset circuit based at least on the second reset count value of the functional module and the first reset count value of each of the at least one reset source corresponding to the functional module further includes at least one of the following: For each of the plurality of reset sources, the verification result of the reset circuit is determined based on the first enable count value and the first release count value of the reset source. and For each of the plurality of functional modules, the verification result of the reset circuit is determined based on the second enable count value and the second release count value of that functional module.

6. The method according to any one of claims 1 to 3, wherein, The reset command includes at least one of cold reset, warm reset, hard reset, soft reset, system reset, and function reset.

7. The method according to any one of claims 1 to 3, wherein, The reset circuit is located within the chip.

8. A reset circuit verification device, wherein, The reset circuit includes multiple reset sources and multiple functional modules. Each of the multiple functional modules is capable of obtaining a reset command from at least one of the multiple reset sources. The device includes: The acquisition unit is configured to execute a verification test case using the reset circuit to obtain a first reset count value for each of the plurality of reset sources and a second reset count value for each of the plurality of functional modules, wherein the first reset count value for each reset source is the number of reset commands detected at that reset source during the execution of the verification test case, and the second reset count value for each functional module is the number of reset commands detected at that functional module during the execution of the verification test case. The second determining unit is configured to, before determining the verification result of the reset circuit, determine, for each of the plurality of reset sources, a timestamp of each reset instruction among a first reset count value of the reset source, and for each of the plurality of functional modules, a timestamp of each reset instruction among a second reset count value of the functional module; and The first determining unit is configured to, for each of the plurality of functional modules, determine the verification result of the reset circuit based at least on the second reset count value of the functional module and the first reset count value of each of the at least one reset source corresponding to the functional module, including: A subunit for determining the verification result of the reset circuit based on the timestamp of each reset instruction in the second reset count of the functional module and the timestamp of each reset instruction in the first reset count of each reset source corresponding to the functional module, as well as the second reset count of the functional module and the first reset count of each reset source corresponding to the functional module; and For any one of the reset instructions for the second reset count value of the functional module, if the time difference between the timestamp of the reset instruction and the timestamp of any one of the reset instructions of each of the at least one reset source corresponding to the functional module is not within the preset time range, the sub-unit whose verification result for the reset circuit is determined to be unsuccessful.

9. The apparatus according to claim 8, wherein, The multiple functional modules can be divided into one or more reset types, and at least one reset source corresponding to each functional module is the same as at least one reset source corresponding to the reset type to which the functional module belongs. And wherein the first determining unit includes: A first determining subunit is configured to, for each of the one or more reset types, determine a type count value for the reset type based on a first count value of each of at least one reset source corresponding to that reset type; and The second determining subunit is configured to determine the verification result of the reset circuit based on the second reset count value of the functional module and the type count value of the reset type to which the functional module belongs.

10. The apparatus according to claim 9, wherein, The first determining subunit includes: A subunit for determining the type count value of a reset type based on the sum of the first count values ​​of each of at least one reset source corresponding to the reset type.

11. The apparatus according to any one of claims 8 to 10, wherein, The reset instruction includes a reset enable instruction and a reset release instruction; the first reset count value includes a first enable count value and a first release count value; and the second reset count value includes a second enable count value and a second release count value. Furthermore, the first determining unit includes at least one of the following sub-units: A sub-unit for determining the verification result of the reset circuit based on the second enable count value of the functional module and the first enable count value of each of the at least one reset source corresponding to the functional module; and A sub-unit for determining the verification result of the reset circuit based on the second release count value of the functional module and the first release count value of each of the at least one reset source corresponding to the functional module.

12. The apparatus according to claim 11, wherein, The first determining unit further includes at least one of the following sub-units: A sub-unit for determining the verification result of the reset circuit based on a first enable count value and a first release count value of the reset source for each of the plurality of reset sources; and A sub-unit for determining the verification result of the reset circuit based on the second enable count value and the second release count value of the functional module for each of the plurality of functional modules.

13. The apparatus according to any one of claims 8 to 10, wherein, The reset command includes at least one of cold reset, warm reset, hard reset, soft reset, system reset, and function reset.

14. The apparatus according to any one of claims 8 to 10, wherein, The reset circuit is located within the chip.

15. An electronic device comprising: At least one processor; as well as A memory that is communicatively connected to the at least one processor; in The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-7.

16. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-7.

17. A computer program product comprising a computer program, wherein, The computer program, when executed by a processor, implements the method of any one of claims 1-7.

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