A face recognition method and motherboard supporting edge computing

Abstract

The present invention discloses a face recognition method and mainboard supporting edge computing, which overcomes the problems of high power consumption, high heat dissipation and high difficulty in production, processing and assembly of prior art equipment. The method includes an AI processor unit, a power supply unit, a DDR unit, an EMMC unit and an interface unit. The method determines whether the current junction temperature of the AI ​​processor is higher than the junction temperature threshold of the AI ​​processor. If so, cloud computing power is selected for comparison, otherwise local computing power is used. If the local face feature library contains the face information, the comparison result is output, otherwise cloud comparison is performed. After the cloud comparison is successful, the current face comparison frequency is judged. If it is greater than the average frequency, the face feature is updated to the local feature library. The present invention combines local computing power with cloud computing power to reduce local computing power requirements. It adopts a fanless design with a compact structure and reduces power consumption. High-frequency faces are updated to the local feature library to further improve the local comparison success rate.

Description

Technical Field

[0001] The present invention relates to the field of face recognition, and in particular to a face recognition method and a mainboard supporting edge computing. Background Art

[0002] Facial recognition is a biometric technology that identifies people based on their facial features. Facial recognition devices use monocular or binocular cameras to capture images or video streams containing faces, detect and track faces in the images, and then perform a series of related application operations on the detected facial images; including image acquisition, feature positioning, identity confirmation and search, etc. The facial recognition motherboard is the key to supporting the core operation of the entire system.

[0003] For example, a "face recognition motherboard structure" disclosed in a Chinese patent document, with the announcement number CN211454631U, includes a motherboard body, shock-absorbing sleeves are sleeved on the four corners of the motherboard body, a heat sink is provided in parallel on the surface of the motherboard body, and a number of mounting brackets are fixedly connected to the four sides of the heat sink. One side of the bottom of the mounting bracket is fixedly connected to the bottom plate, a fixed sleeve is provided on the top of the bottom plate, and slide grooves are provided on both sides of the fixed sleeve. A shock-absorbing plate is provided in parallel on the top of the bottom plate, a shock-absorbing rod is provided at the bottom of the shock-absorbing plate, and the bottom end of the shock-absorbing rod is connected to the support plate. The two ends of the support plate are rotatably connected to the pulley through a connecting piece, and the pulley is slidably connected to the slide groove, and the bottom of the support plate is fixedly connected to the spring; through the structure of the shock-absorbing rod, shock-absorbing plate, spring, etc. The setting can buffer the vibration when the fan is running, so that the mainboard has a good shock-resistant effect; the four corners of the mainboard are equipped with shock-absorbing sleeves, so that the mainboard has a certain anti-collision effect, avoiding damage to the mainboard; the above technical solution collects facial information for facial recognition equipment, and uses local algorithms for local comparison, and the facial information does not need to be transmitted to the background cloud; in order to improve the efficiency of facial recognition, high local computing power is required, so there are generally problems of high power consumption and high heat dissipation of equipment, which require harsh heat dissipation treatment; in order to reduce fan vibration, complex structures such as shock-absorbing rods, shock-absorbing plates, and springs are also required, which will make production, processing and assembly difficult and inconvenient for mass production. Summary of the Invention

[0004] The purpose of the present invention is to overcome the problems of high power consumption, high heat dissipation and great difficulty in production, processing and assembly of existing equipment, and provide a face recognition method and motherboard that supports edge computing. It adopts a combination of local computing power and cloud computing power to reduce local computing power requirements, thereby reducing power consumption, so that a fanless design can be adopted with a compact structure, while improving face recognition efficiency.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: a face recognition method supporting edge computing, comprising the following steps:

[0006] S1: Determine whether the current junction temperature of the AI ​​processor is higher than the AI ​​processor junction temperature threshold. If so, proceed to step S2; otherwise, proceed to step S3.

[0007] S2: Use cloud computing power to pre-process the facial image, perform cloud-based comparison on the facial data, and then proceed to step S4 while outputting the comparison results;

[0008] S3: Use local computing power to perform a comparison and search the local facial feature database for facial data. If the local facial feature database contains the facial information, the search is successful and the comparison result is output. Otherwise, proceed to step S2.

[0009] S4: After the cloud comparison is successful, the current face comparison frequency is determined. If it is greater than the average face comparison frequency, the process proceeds to step S5.

[0010] S5: Update the facial features to the local feature library and output the comparison results.

[0011] The present invention is aimed at face recognition and proposes a face recognition method that supports edge computing. It adopts a combination of local computing power and cloud computing power to reduce local computing power requirements, and adopts a strategy for selecting local and cloud computing power resources based on the junction temperature of the AI ​​processor to judge whether the current junction temperature of the AI ​​processor is higher than the junction temperature threshold of the AI ​​processor. If so, the cloud computing power is given priority for comparison, otherwise the local computing power is used; in this way, the current junction temperature of the AI ​​processor is effectively controlled, thereby preventing the temperature of the face recognition mainboard from being too high; if the current junction temperature of the AI ​​processor is lower than the junction temperature threshold of the AI ​​processor, the local computing power is given priority for comparison, and if the local face feature library contains the face information, the comparison result is output, otherwise the cloud comparison is performed; after the cloud comparison is successful, the current face comparison frequency is judged, and if it is greater than the average face comparison frequency, that is, the face usage frequency is high, the face feature is updated to the local feature library, thereby further improving the local comparison success rate.

[0012] Preferably, the face image preprocessing in step S2 is to segment the face image into multiple small blocks, and then calculate the similarity of each small block. The similarity calculation formula is as follows: Where S i Indicates similarity, They represent the LBP histogram features of each small block, and D represents the dimension of multi-scale LBP.

[0013] A face recognition motherboard supporting edge computing adopts a face recognition method supporting edge computing, including an AI processor unit, a power supply unit, a DDR unit, an EMMC unit, and an interface unit; the AI ​​processor unit includes an AI processor supporting local computing power, a BOOT startup circuit, and an encryption circuit; the BOOT startup circuit provides configuration of the AI ​​processor startup mode; and the encryption circuit is connected to the AI ​​processor using an I2C method.

[0014] The AI ​​processor unit is connected to the power supply unit, DDR unit, EMMC unit and interface unit respectively, and the power supply unit is also connected to the DDR unit, EMMC unit and interface unit respectively.

[0015] Preferably, the power supply unit includes an overvoltage and overcurrent protection circuit, a voltage conversion circuit and a power-on timing control circuit, and the power supply unit outputs 5V, 3.3V, 1.8V and 0.8V voltage power supplies.

[0016] Preferably, the interface unit is an interface provided by the face recognition mainboard to the outside, including a camera interface, a network interface, a wireless interface, a power interface, an LCD screen interface, a touch screen interface, an RS232 serial port, a relay interface, a Wiegand interface, a fill light interface, an RFID interface, a GPIO interface, a USB interface and an audio interface.

[0017] Preferably, the camera interface adopts a dual MIPI interface that supports dual-channel cameras for capturing facial video images, and the dual-channel cameras adopt RGB+IR lenses.

[0018] Preferably, the EMMC unit stores embedded system firmware boot, system, algorithm firmware, app and userdata.

[0019] Preferably, the DDR chip types in the DDR unit are LPDDR4 and LPDDR4x.

[0020] Preferably, the overvoltage and overcurrent protection circuit includes a resistor R103, a resistor R104, a resistor R105, a resistor R106, a resistor R107, a diode D101, a diode D102, a diode D103, a transistor Q100, a transistor Q101, a MOS transistor Q102, a capacitor C105 and a chip U102; one end of the resistor R104 is connected to the DC power supply DCIN1, the E pole of the transistor Q100, the A pole of the diode D103, one end of the resistor R103, the E pole of the transistor Q101, the K pole of the diode D101 and the S pole of the MOS transistor Q102, the other end of the resistor R104 is connected to the K pole of the diode D102 and one end of the resistor R105, the A pole of the diode D102 The first terminal of the transistor Q100 is connected to the ground, the other end of the resistor R105 is connected to the B terminal of the transistor Q100, the C terminal of the transistor Q100 is connected to the C terminal of the transistor Q101, the A terminal of the diode D101, one end of the resistor R106 and the G terminal of the MOS transistor Q102, the K terminal of the diode D103 and one end of the capacitor C105 are connected to the 2 pin of the chip U102, the 3 pin of the chip U102 is grounded, the other end of the resistor R103 is connected to one end of the resistor R107 and the B terminal of the transistor Q101, the other end of the resistor R107 is connected to the 1 pin of the chip U102, the other end of the resistor R106 is grounded, and the D terminal of the MOS transistor Q102 is connected to the DC power supply 12V; the model of the chip U102 is HT7082A-2.

[0021] Preferably, the power-on timing control circuit includes capacitor C210, capacitor C211, capacitor C230, capacitor C216, capacitor C217, capacitor C218, capacitor C231, capacitor C438, chip U202, resistor R205, resistor R208, resistor R211, resistor R209, resistor R210, resistor R214, MOS tube Q200, MOS tube Q201, inductor L203 and inductor B200; one end of capacitor C210 is connected to power supply VDD5V, one end of capacitor C211 is connected to chip U202, and the other end of capacitor C211 is connected to chip U202. Pin 2 of chip U202 is connected to the ground, the other end of capacitor C210 is grounded, the other end of capacitor C211 is grounded, pin 4 of chip U202 is grounded, pin 6 of chip U202 is connected to one end of resistor R205 and one end of capacitor C230, the other end of resistor R205 is connected to power supply VDD5V, the other end of capacitor C230 is grounded, pin 5 of chip U202 is connected to one end of inductor L203, the other end of inductor L203 is connected to one end of resistor R208, one end of capacitor C216, one end of capacitor C217, and one end of inductor L208. One end of capacitor C218, one end of capacitor C231, one end of resistor R209 are connected to the S pole of MOS tube Q200, the other end of resistor R208 is connected to pin 8 of chip U202 and one end of resistor R211, the other end of resistor R211 is grounded, the other end of capacitor C216 is grounded, the other end of capacitor C217 is grounded, the other end of capacitor C218 is grounded, the other end of capacitor C231 is connected to the other end of resistor R209, one end of resistor R210 and the G pole of MOS tube Q200, the other end of resistor R210 is connected One end is connected to the D electrode of the MOS tube Q201, the G electrode of the MOS tube Q201 is connected to one end of the resistor R214, one end of the capacitor C438, and one end of the resistor R219, the other end of the resistor R214 is connected to the S electrode of the MOS tube Q201 and grounded, the other end of the capacitor C438 is grounded, the other end of the resistor R219 is connected to the CORE interface, the D electrode of the MOS tube Q200 is connected to one end of the inductor B200, and the other end of the inductor B200 is connected to the USB interface; the model of the chip U202 is SY8029.

[0022] Therefore, the present invention has the following beneficial effects:

[0023] 1. Combining local computing power with cloud computing power to reduce local computing power requirements;

[0024] 2. Fanless design, compact structure and reduced power consumption;

[0025] 3. Update high-frequency faces to the local feature library to further improve the local comparison success rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a flow chart of the face recognition method;

[0027] Figure 2 This is the face recognition motherboard structure diagram;

[0028] Figure 3 This is a diagram of the AI ​​processor unit structure;

[0029] Figure 4 It is the structural diagram of the interface unit;

[0030] Figure 5 This is the overvoltage and overcurrent protection circuit diagram;

[0031] Figure 6 This is the power-on timing control circuit diagram;

[0032] Figure 7 This is the circuit diagram of the DDR unit;

[0033] Figure 8 This is the EMMC unit circuit diagram;

[0034] Figure 9 This is the circuit diagram of the interface unit.

[0035] In the figure: 1, AI processor unit 2, power supply unit 3, DDR unit 4, EMMC unit 5, interface unit 11, AI processor 12, BOOT startup circuit 13, encryption circuit 501, camera interface 502, network interface wireless interface 504, power interface 505, LCD screen interface 506, touch screen interface 507, RS232 serial port relay interface 509, Wiegand interface 510, fill light interface 511, RFID interface 512, GPIO interface 513, USB interface 514, audio interface DETAILED DESCRIPTION

[0036] The present embodiment will be further described below with reference to the accompanying drawings and specific implementation plans.

[0037] This embodiment provides a face recognition method that supports edge computing. Figure 1 The face recognition method flow chart includes the following steps:

[0038] S1: Determine whether the current junction temperature of the AI ​​processor is higher than the AI ​​processor junction temperature threshold. If so, proceed to step S2; otherwise, proceed to step S3.

[0039] S2: Use cloud computing power to pre-process the facial image, perform cloud-based comparison on the facial data, and then proceed to step S4 while outputting the comparison results;

[0040] S3: Use local computing power to perform a comparison and search the local facial feature database for facial data. If the local facial feature database contains the facial information, the search is successful and the comparison result is output. Otherwise, proceed to step S2.

[0041] S4: After the cloud comparison is successful, the current face comparison frequency is determined. If it is greater than the average face comparison frequency, the process proceeds to step S5.

[0042] S5: Update the facial features to the local feature library and output the comparison results.

[0043] The face image preprocessing in step S2 is to segment the face image into multiple small blocks and then calculate the similarity of each small block. The similarity calculation formula is as follows:

[0044] Where S i Indicates similarity, Denote the LBP histogram features of each small block, D denotes the dimension of multi-scale LBP. According to the biological structure of the face, the face is divided into a pair of eyes, a nose, a mouth, a pair of eyebrows and a contour. The similarities of all the calculated components are added together to obtain the final matching value.

[0045] When performing facial feature comparison based on the local computing power of AI processor 11 of AI processor unit 1, according to actual testing at room temperature of 25°C, the internal junction temperature of a certain AI processor will increase by 12.8 degrees Celsius, or 20.6%, when using internal computing power compared to when not using internal computing power. Therefore, by reducing the usage frequency of the local computing power of the local AI processor, the power consumption of the motherboard can be effectively controlled, heat dissipation can be reduced, and the difficulty of heat dissipation processing can be reduced. The specific process of reducing the usage frequency of the local computing power of the local AI processor is as follows:

[0046] Assume: the threshold for using local computing power is: Th_comp; the AI ​​processor junction temperature threshold is: Th_temp; the current junction temperature of the AI ​​processor is: AI_temp; the current face comparison frequency is: Com_fre; the average face comparison frequency is: Ave_fre; the strategy for selecting local and cloud computing power resources based on the AI ​​processor junction temperature is to determine whether the current junction temperature of the AI ​​processor is higher than the AI ​​processor junction temperature threshold. If so, cloud computing power is prioritized for comparison; otherwise, local computing power is used. This effectively controls the current junction temperature of the AI ​​processor, thereby preventing the temperature of the face recognition motherboard from being too high. If the current junction temperature of the AI ​​processor is lower than the AI ​​processor junction temperature threshold, local computing power is prioritized for comparison. If the local facial feature library contains the facial information, the comparison result is output; otherwise, cloud comparison is performed. After the cloud comparison is successful, the current face comparison frequency is determined. If it is higher than the average face comparison frequency, that is, the face is used frequently, the facial feature is updated to the local feature library, thereby further improving the local comparison success rate.

[0047] This embodiment also provides a face recognition motherboard supporting edge computing, using a face recognition method supporting edge computing. Figure 2 This is a structural diagram of the face recognition motherboard, including: AI processor unit 1, power supply unit 2, DDR unit 3, EMMC unit 4, and interface unit 5; the AI ​​processor unit is connected to the power supply unit, DDR unit, EMMC unit, and interface unit respectively, and the power supply unit is also connected to the DDR unit, EMMC unit, and interface unit respectively.

[0048] Figure 3 This is the AI ​​processor unit structure diagram. AI processor unit 1 includes an AI processor 11 that supports local computing power, a boot circuit 12, and an encryption circuit 13. AI processor 11 provides local computing power, temperature detection, interfaces, codec capabilities, and ISP effect support. The boot circuit configures the AI ​​processor's startup mode. The encryption circuit encrypts and decrypts device data and algorithms. The encryption circuit connects to the AI ​​processor via I2C.

[0049] The power supply unit 2 includes an overvoltage and overcurrent protection circuit, a voltage conversion circuit, and a power-on timing control circuit, and outputs 5V, 3.3V, 1.8V, and 0.8V voltage power supplies for use by other units.

[0050] The DDR unit 3 is used to execute the operation of the face recognition embedded operating system.

[0051] The EMMC unit 4 is used to store the embedded system firmware boot, system, algorithm firmware, app and userdata; using EMMCs of different capacities or allocating userdata spaces of different capacities can meet the storage requirements of facial feature libraries of different capacities.

[0052] Figure 4 This is a structural diagram of the interface unit, including: a camera interface 501, a network interface 502 or a wireless interface 503, and a power interface 504. In order to enable the face recognition motherboard to meet the actual application requirements of different usage scenarios, it also includes an LCD screen interface 505, a touch screen interface 506, an RS232 serial port 507, a relay interface 508, a Wiegand interface 509, a fill light interface 510, an RFID interface 511, a GPIO interface 512, a USB interface 513, an audio interface 514, etc.

[0053] The camera interface 501 adopts dual MIPI interfaces, which can simultaneously support dual cameras to capture facial video images; the dual cameras can use RGB+IR lenses to meet the needs of face recognition in application scenarios such as different ambient light and liveness detection.

[0054] The network interface provides 100M / 1000M network bandwidth as a channel for information interaction between the face recognition mainboard and the cloud background; the wireless interface, as a wireless alternative to the network interface, can be a WIFI / Bluetooth module or a 4G module, a 5G module, or other wireless communication modules that meet the bandwidth requirements, as well as MINI-PCIE, M.2 and other interface forms that support these modules.

[0055] Figure 5This is an overvoltage and overcurrent protection circuit diagram, including resistor R103, resistor R104, resistor R105, resistor R106, resistor R107, diode D101, diode D102, diode D103, transistor Q100, transistor Q101, MOS transistor Q102, capacitor C105 and chip U102; one end of resistor R104 is connected to DC power supply DCIN1, the E pole of transistor Q100, the A pole of diode D103, one end of resistor R103, the E pole of transistor Q101, the K pole of diode D101 and the S pole of MOS transistor Q102, the other end of resistor R104 is connected to the K pole of diode D102 and one end of resistor R105, and the A pole of diode D102 is connected to Ground, the other end of resistor R105 is connected to the B pole of transistor Q100, the C pole of transistor Q100 is connected to the C pole of transistor Q101, the A pole of diode D101, one end of resistor R106 and the G pole of MOS transistor Q102, the K pole of diode D103 and one end of capacitor C105 are connected to pin 2 of chip U102, pin 3 of chip U102 is grounded, the other end of resistor R103 is connected to one end of resistor R107 and the B pole of transistor Q101, the other end of resistor R107 is connected to pin 1 of chip U102, the other end of resistor R106 is grounded, and the D pole of MOS transistor Q102 is connected to DC 12V; the model of chip U102 is HT7082A-2.

[0056] Figure 6This is a power-on timing control circuit diagram; including capacitor C210, capacitor C211, capacitor C230, capacitor C216, capacitor C217, capacitor C218, capacitor C231, capacitor C438, chip U202, resistor R205, resistor R208, resistor R211, resistor R209, resistor R210, resistor R214, MOS tube Q200, MOS tube Q201, inductor L203 and inductor B200; one end of capacitor C210 is connected to power supply VDD5V, one end of capacitor C211 is connected to chip U2 Pin 2 of chip U202 is connected to the other end of capacitor C210 and ground, the other end of capacitor C211 is grounded, pin 4 of chip U202 is grounded, pin 6 of chip U202 is connected to one end of resistor R205 and one end of capacitor C230, the other end of resistor R205 is connected to power supply VDD5V, the other end of capacitor C230 is grounded, pin 5 of chip U202 is connected to one end of inductor L203, the other end of inductor L203 is connected to one end of resistor R208, one end of capacitor C216, one end of capacitor C217, and capacitor C One end of capacitor C218, one end of capacitor C231, one end of resistor R209 are connected to the S pole of MOS tube Q200, the other end of resistor R208 is connected to pin 8 of chip U202 and one end of resistor R211, the other end of resistor R211 is grounded, the other end of capacitor C216 is grounded, the other end of capacitor C217 is grounded, the other end of capacitor C218 is grounded, the other end of capacitor C231 is connected to the other end of resistor R209, one end of resistor R210 and the G pole of MOS tube Q200, and the other end of resistor R210 is connected to the The end is connected to the D pole of the MOS tube Q201, the G pole of the MOS tube Q201 is connected to one end of the resistor R214, one end of the capacitor C438 and one end of the resistor R219, the other end of the resistor R214 is connected to the S pole of the MOS tube Q201 and grounded, the other end of the capacitor C438 is grounded, the other end of the resistor R219 is connected to the CORE interface, the D pole of the MOS tube Q200 is connected to one end of the inductor B200, and the other end of the inductor B200 is connected to the USB interface; the model of the chip U202 is SY8029.

[0057] Figure 7 This is a circuit diagram of a DDR unit, including chip U2, resistor R243, resistor R244, resistor R245 and resistor R248; the G2 pin of chip U2 is connected to one end of resistor R243, the other end of resistor R243 is connected to the power supply voltage and one end of resistor R244, the other end of resistor R244 is connected to the T2 pin of chip U2, the J8 pin of chip U2 is connected to one end of resistor R245, the other end of resistor R245 is connected to the J9 pin of chip U2, the P8 pin of chip U2 is connected to one end of resistor R248, and the other end of resistor R248 is connected to the P9 pin of chip U2.

[0058] Figure 8 This is the EMMC unit circuit diagram, including chip U3A, chip U402, resistors R408-R416, resistor R406, resistors R427-R429 and capacitors C428-C435; one end of the resistors R408-R416 is connected to the 1.8V power supply voltage, the other end of the resistor R408 is connected to the B6 pin of the chip U3A, the other end of the resistor R409 is connected to the B5 pin of the chip U3A, the other end of the resistor R410 is connected to the B4 pin of the chip U3A, the other end of the resistor R411 is connected to the B3 pin of the chip U3A, the other end of the resistor R412 is connected to the B2 pin of the chip U3A, and the resistor R413 is connected to the B4 pin of the chip U3A. The other end of resistor R414 is connected to the A4 pin of chip U3A, the other end of resistor R415 is connected to the A3 pin of chip U3A, the other end of resistor R416 is connected to the M5 pin of chip U3A, one end of resistor R406 is connected to one end of resistor R429 and the H5 pin of chip U3A, the other end of resistor R429 is grounded, one end of resistor R428 is connected to the 1.8V power supply voltage, the other end of resistor R428 is connected to the 1 pin of chip U402, the 3 pin of chip U402 is grounded, the 5 pin of chip U402 is connected to one end of resistor R427, and the resistor R The other end of 427 is connected to the 4 pin of chip U402 and the K5 pin of chip U3A. The power supply voltage 3.3V is connected to one end of capacitors C428-C430, the E6 pin of chip U3A, the F5 pin of chip U3A, the J10 pin of chip U3A and the K9 pin of chip U3A. The other end of capacitors C428-C430 is grounded. The power supply voltage 1.8V is connected to one end of capacitors C431-C433, the C6 pin of chip U3A, the M4 pin of chip U3A, the N4 pin of chip U3A, the P3 pin of chip U3A and the P5 pin of chip U3A. The other end of capacitors C431-C433 is grounded. One end of capacitor C434-C435 is connected to the C2 pin of chip U3A, and the other end of capacitor C434-C435 is grounded. The A6 pin of chip U3A, the E7 pin of chip U3A, the G5 pin of chip U3A, the H10 pin of chip U3A, the J5 pin of chip U3A, the K8 pin of chip U3A, the C4 pin of chip U3A, the N2 pin of chip U3A, the N5 pin of chip U3A, the P4 pin of chip U3A and the P6 pin of chip U3A are grounded; the model of chip U3A is KLM8G1GETF-B041, and the model of chip U402 is SN74LVC1G08DCKR.

[0059] Figure 9The circuit diagram of the interface unit includes chip U602, resistors R600-R604, resistors R606-R608, resistors R610-R614, resistor R616, resistors R620-R624, and capacitor C600; one end of resistor R624 is connected to pin 39 of chip U602, the other end of resistor R624 is grounded, one end of resistor R623 is connected to pin 34 of chip U602, one end of resistor R622 is connected to pin 33 of chip U602, and the other end of resistor R622 is grounded. One end is grounded, one end of the resistor R621 is connected to the 32nd pin of the chip U602, one end of the resistor R620 is connected to the 31st pin of the chip U602, one end of the resistor R616 is connected to the 22nd pin of the chip U602, one end of the resistor R614 is connected to the 23rd pin of the chip U602, one end of the resistor R613 is connected to the 24th pin of the chip U602, one end of the resistor R612 is connected to the 25th pin of the chip U602, one end of the resistor R611 is connected to the 26th pin of the chip U602, and the resistors R614 and R613 are connected to the 24th pin of the chip U602. One end of resistor R610 is connected to pin 27 of chip U602, one end of resistor R608 is connected to pin 15 of chip U602, one end of resistor R607 is connected to pin 16 of chip U602, one end of resistor R604 is connected to pin 17 of chip U602, one end of resistor R603 is connected to pin 18 of chip U602, one end of resistor R602 is connected to pin 19 of chip U602, one end of resistor R601 is connected to pin 20 of chip U602, and one end of resistor R601 is connected to pin 1 The other end is connected to one end of capacitor C600, the other end of capacitor C600 is grounded, one end of resistor R600 is connected to pin 14 of chip U602, one end of resistor R606 is connected to pin 13 of chip U602, pin 11 of chip U602 is connected to pin 40 of chip U602, pin 3 of chip U602 and pin 8 of chip U602 are connected to pin 38 of chip U602, and pin 0 of chip U602 is grounded; the model of chip U602 is RTL8211F-CG.

[0060] The working process of the present invention is as follows: determine whether the current junction temperature of the AI ​​processor is higher than the AI ​​processor junction temperature threshold. If so, cloud computing power is given priority for comparison, otherwise local computing power is used; thereby effectively controlling the current junction temperature of the AI ​​processor, thereby preventing the temperature of the face recognition motherboard from being too high; if the current junction temperature of the AI ​​processor is lower than the AI ​​processor junction temperature threshold, local computing power is given priority for comparison. If the local face feature library contains the face information, the comparison result is output, otherwise cloud comparison is performed; after the cloud comparison is successful, the current face comparison frequency is judged. If it is greater than the average face comparison frequency, that is, the face usage frequency is high, the face feature is updated to the local feature library, thereby further improving the local comparison success rate.

[0061] The present invention is not limited to the embodiments described above. The above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent transformations, improvements, etc. made based on the technical essence of the present invention shall fall within the scope of protection claimed by the present invention.

Claims

1. A face recognition method supporting edge computing, characterized in that: The following steps are involved: S1: Determine whether the current junction temperature of the AI ​​processor is higher than the AI ​​processor junction temperature threshold. If so, proceed to step S2; otherwise, proceed to step S3. S2: Use cloud computing power to pre-process the facial image, perform cloud-based comparison on the facial data, and then proceed to step S4 while outputting the comparison results; S3: Use local computing power to perform a comparison and search the local facial feature database for facial data. If the local facial feature database contains the facial information, the search is successful and the comparison result is output. Otherwise, proceed to step S2. S4: After the cloud comparison is successful, the current face comparison frequency is determined. If it is greater than the average face comparison frequency, the process proceeds to step S5. S5: Update the facial features to the local feature library and output the comparison results.

2. A face recognition method supporting edge computing according to claim 1, characterized in that: The face image preprocessing in step S2 is to segment the face image into multiple small blocks, each of which includes a pair of eyes, a nose, a mouth, a pair of eyebrows, and a contour. The similarity of each small block is then calculated, and the similarities of all the calculated components are added together to obtain the final matching value. The similarity calculation formula is as follows: Where, Indicates similarity, 、 Represents the LBP histogram features of each small block, Represents the dimension of multi-scale LBP.

3. A face recognition motherboard supporting edge computing, characterized in that: A face recognition method supporting edge computing according to claim 1 is adopted, comprising an AI processor unit (1), a power supply unit (2), a DDR unit (3), an EMMC unit (4), and an interface unit (5); the AI ​​processor unit (1) comprises an AI processor (11) supporting local computing power, a BOOT startup circuit (12), and an encryption circuit (13); the BOOT startup circuit (12) provides the configuration of the startup mode of the AI ​​processor (11); the encryption circuit (13) is connected to the AI ​​processor (11) in an I2C manner, and the DDR unit executes the operation of the face recognition embedded operating system.

4. A face recognition motherboard supporting edge computing according to claim 3, characterized in that: The power supply unit (2) comprises an overvoltage and overcurrent protection circuit, a voltage conversion circuit and a power-on timing control circuit, and the power supply unit (2) outputs 5V, 3.3V, 1.8V and 0.8V voltage power supplies.

5. The face recognition motherboard supporting edge computing according to claim 3, characterized in that: The interface unit (5) is an interface provided by the face recognition mainboard to the outside, including a camera interface (501), a network interface (502), a wireless interface (503), a power interface (504), an LCD interface (505), a touch screen interface (506), an RS232 serial port (507), a relay interface (508), a Wiegand interface (509), a fill light interface (510), an RFID interface (511), a GPIO interface (512), a USB interface (513) and an audio interface (514). The network interface provides a 100M / 1000M network bandwidth as a channel for information interaction between the face recognition mainboard and the cloud backend.

6. A face recognition motherboard supporting edge computing according to claim 5, wherein the camera interface (501) adopts a dual MIPI interface that supports dual-channel cameras for capturing facial video images, and the dual-channel cameras adopt RGB+IR lenses.

7. The face recognition motherboard supporting edge computing according to claim 3, characterized in that: The EMMC unit (4) internally stores embedded system firmware boot, system, algorithm firmware, app and userdata.

8. The face recognition motherboard supporting edge computing according to claim 3, characterized in that: The DDR chip types in the DDR unit (3) are LPDDR4 and LPDDR4x.

9. The face recognition motherboard supporting edge computing according to claim 4, characterized in that: The overvoltage and overcurrent protection circuit includes a resistor R103, a resistor R104, a resistor R105, a resistor R106, a resistor R107, a diode D101, a diode D102, a diode D103, a transistor Q100, a transistor Q101, a MOS transistor Q102, a capacitor C105 and a chip U102; one end of the resistor R104 is connected to the DC power supply DCIN1, the E pole of the transistor Q100, the A pole of the diode D103, one end of the resistor R103, the E pole of the transistor Q101, the K pole of the diode D101 and the S pole of the MOS transistor Q102, the other end of the resistor R104 is connected to the K pole of the diode D102 and one end of the resistor R105, and the A pole of the diode D102 is connected to the Ground, the other end of resistor R105 is connected to the B pole of transistor Q100, the C pole of transistor Q100 is connected to the C pole of transistor Q101, the A pole of diode D101, one end of resistor R106 and the G pole of MOS transistor Q102, the K pole of diode D103 and one end of capacitor C105 are connected to pin 2 of chip U102, pin 3 of chip U102 is grounded, the other end of resistor R103 is connected to one end of resistor R107 and the B pole of transistor Q101, the other end of resistor R107 is connected to pin 1 of chip U102, the other end of resistor R106 is grounded, and the D pole of MOS transistor Q102 is connected to DC 12V; the model of chip U102 is HT7082A-2.

10. The face recognition motherboard supporting edge computing according to claim 4, characterized in that: The power-on timing control circuit includes capacitor C210, capacitor C211, capacitor C230, capacitor C216, capacitor C217, capacitor C218, capacitor C231, capacitor C438, chip U202, resistor R205, resistor R208, resistor R211, resistor R209, resistor R210, resistor R214, MOS transistor Q200, MOS transistor Q201, inductor L203 and inductor B200; one end of capacitor C210 is connected to power supply VDD5V, one end of capacitor C211 is connected to chip U20 2, the other end of capacitor C210 is grounded, the other end of capacitor C211 is grounded, pin 4 of chip U202 is grounded, pin 6 of chip U202 is connected to one end of resistor R205 and one end of capacitor C230, the other end of resistor R205 is connected to power supply VDD5V, the other end of capacitor C230 is grounded, pin 5 of chip U202 is connected to one end of inductor L203, the other end of inductor L203 is connected to one end of resistor R208, one end of capacitor C216, one end of capacitor C217, and capacitor C2 One end of 18, one end of capacitor C231, one end of resistor R209 and the S pole of MOS tube Q200 are connected, the other end of resistor R208 is connected to pin 8 of chip U202 and one end of resistor R211, the other end of resistor R211 is grounded, the other end of capacitor C216 is grounded, the other end of capacitor C217 is grounded, the other end of capacitor C218 is grounded, the other end of capacitor C231 is connected to the other end of resistor R209, one end of resistor R210 and the G pole of MOS tube Q200, and the other end of resistor R210 is connected The chip U202 is connected to the D-pole of the MOS transistor Q201, the G-pole of the MOS transistor Q201 is connected to one end of the resistor R214, one end of the capacitor C438, and one end of the resistor R219. The other end of the resistor R214 is connected to the S-pole of the MOS transistor Q201 and grounded. The other end of the capacitor C438 is grounded. The other end of the resistor R219 is connected to the CORE interface. The D-pole of the MOS transistor Q200 is connected to one end of the inductor B200, and the other end of the inductor B200 is connected to the USB interface. The model of the chip U202 is SY8029.

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