A test structure, a manufacturing method thereof, and a monitoring method using the test structure

Abstract

The embodiment of the present invention discloses a test structure, a manufacturing method thereof and a monitoring method using the test structure. The test structure is used to monitor process anomalies of forming a device structure in a die area of ​​a wafer, and includes: a shallow trench isolation region extending along a first direction and at least two active regions isolated by the shallow trench isolation region; at least two gate structures extending along a second direction formed on the shallow trench isolation region and the active region, wherein the gate structure overlaps at least two active regions, and the line width of the gate structure is consistent with the line width of the gate structure with the minimum line width formed in the device structure; an interlayer dielectric layer covering the gate structure, the active region and the shallow trench isolation region, wherein contact holes are formed in the interlayer dielectric layer covering the active regions on both sides of the gate structure of the test structure; at least two metal traces extending along the first direction formed on the interlayer dielectric layer, the metal traces corresponding to the at least two active regions one by one, and electrically contacting the corresponding active regions through the contact holes.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a test structure, a manufacturing method thereof, and a monitoring method using the test structure. Background Art

[0002] With the rapid development of semiconductor technology, more and more devices are integrated in integrated circuits. In particular, as the critical dimension (CD) of devices becomes smaller and smaller, the size of devices and the distance between devices also become smaller and smaller. Interference between devices is inevitable, which in turn affects the reliability of integrated circuits. In particular, some key processes in the integrated circuit manufacturing process, such as active area formation process, gate structure (such as Poly gate) formation process, sidewall (Spacer) formation process, interlayer dielectric layer (ILD) formation process, contact hole (Contact) formation process, metal wiring formation process, etc., their process stability will not only affect the performance of the device itself, but also cause interference between devices. Therefore, it is necessary to monitor the stability of the above key processes.

[0003] Mature large-scale production lines have special monitoring methods for the above core processes, such as the critical dimensions of the lines and the film thickness. At the same time, there is a defect inspection after the process. Although these monitoring methods for process stability are timely, they often have "blind spots" for some problems. For example, the hole defects buried deep in the interlayer dielectric layer are difficult to detect by existing means due to their concealment. In the prior art, for example, for a method of monitoring holes appearing in the interlayer dielectric layer, U.S. Patent US6774989B1 provides an optical method, but this method requires special optical instruments on the one hand, which is relatively expensive; on the other hand, since the appearance of holes in the interlayer dielectric layer is random on the wafer, the monitoring efficiency of this method is relatively low. Therefore, it is necessary to find other more practical and effective methods, including monitoring holes appearing in the interlayer dielectric layer.

[0004] In addition, as the density of integrated circuit devices increases, the mutual interference effect between devices due to leakage is becoming more and more serious. The drift of core process dimensions is an important reason for interference between devices and reduced reliability of integrated circuits. However, this reliability problem cannot be revealed by the above-mentioned online graphic monitoring method. So far, there is no simple and direct monitoring method for the impact of abnormal process deviation on the deterioration of reliability between devices in integrated circuits. Therefore, in actual semiconductor manufacturing practice, there is an urgent need for a monitoring method that can reflect both process deviations and the reliability impact caused by deviations. Summary of the invention

[0005] The object of the present invention is to provide a test structure, a manufacturing method thereof and a monitoring method using the test structure to solve the above problems existing in the prior art.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] One aspect of the present invention provides a test structure formed in a test area of ​​a wafer for monitoring process abnormalities of forming a device structure in a die area of ​​the wafer.

[0008] The test structure includes:

[0009] A shallow trench isolation region extending along a first direction and at least two active regions isolated by the shallow trench isolation region;

[0010] At least two gate structures extending along the second direction are formed on the shallow trench isolation region and the active region, wherein the gate structure overlaps at least two active regions, and the line width of the gate structure is consistent with the line width of the gate structure with the smallest line width formed in the device structure;

[0011] an interlayer dielectric layer covering the gate structure, the active area and the shallow trench isolation area, wherein contact holes are formed in the interlayer dielectric layer on the active areas on both sides of the gate structure covering the test structure;

[0012] At least two metal traces extending along the first direction are formed on the interlayer dielectric layer, wherein the metal traces correspond to the at least two active regions one by one and are electrically contacted with the corresponding active regions through the contact holes.

[0013] In an optional embodiment, the test area is located in a scribe line of the wafer, and the length of the gate structure in the second direction is greater than 1 / 2 of the width of the scribe line.

[0014] In an optional embodiment, the test structure further includes:

[0015] A first pad and a second pad are respectively connected to any two adjacent metal traces of the at least two metal traces;

[0016] The length of the plurality of active regions in the first direction is greater than 4 / 5 of the distance between the first pad and the second pad.

[0017] In an optional embodiment, the test structure further includes:

[0018] Sidewall spacers are formed on both sides of the gate structure along the second direction.

[0019] In an alternative embodiment,

[0020] The line width of the active region is consistent with the line width of the active region with the smallest line width formed in the device structure; and / or

[0021] The size of the contact hole is consistent with the size of the contact hole formed in the device structure; and / or

[0022] The line width of the metal routing line is consistent with the line width of the metal routing line with the smallest line width formed in the device structure.

[0023] In an optional embodiment, a source region and a drain region are further formed in the active region, and are respectively located on two sides of the gate structure.

[0024] Another aspect of the present invention provides a method for manufacturing a test structure, the test structure being used to monitor process anomalies of a device structure formed in a die region of a wafer, the method comprising:

[0025] Forming a shallow trench isolation region extending along a first direction and at least two active regions isolated by the shallow trench isolation region in a test region of the wafer, wherein the shallow trench isolation region and the active region are formed synchronously with the shallow trench isolation region and the active region in the device structure;

[0026] At least two gate structures extending along the second direction are formed on the shallow trench isolation region and the active region, wherein the gate structure overlaps at least two active regions, and the gate structure is formed synchronously with the gate structure in the device structure, and the line width is consistent with the line width of the gate structure with the smallest line width formed in the device structure;

[0027] Forming an interlayer dielectric layer covering the gate structure, the active area and the shallow trench isolation area, wherein contact holes are formed in the interlayer dielectric layer covering the active areas on both sides of the gate structure of the test structure, and wherein the contact holes are formed synchronously with the contact holes formed in the device structure;

[0028] At least two metal traces extending along a first direction are formed on the interlayer dielectric layer, wherein the metal traces are formed synchronously with the metal traces in the device structure, and the metal traces in the test structure correspond one-to-one to the at least two active areas and are electrically contacted with the corresponding active areas through contact holes in the test structure.

[0029] In an optional embodiment, the test area is located in a scribe line of the wafer, and a length of the gate structure in the test structure in the second direction is greater than 1 / 2 of a width of the scribe line.

[0030] In an optional embodiment, the method further comprises:

[0031] forming a first pad and a second pad, respectively connecting any two adjacent metal traces of the at least two metal traces;

[0032] The length of the plurality of active regions in the first direction is greater than 4 / 5 of the distance between the first pad and the second pad.

[0033] In an optional embodiment, the method further comprises:

[0034] A source region and a drain region are formed in the active region of the test structure, respectively located on both sides of the gate structure in the test structure, and the source region and the drain region are formed synchronously with the source region and the drain region in the device structure.

[0035] Another aspect of the present invention provides a method for monitoring process abnormalities of a device structure formed in a die region on a wafer using the test structure described in the first aspect.

[0036] The method comprises:

[0037] Connecting any two adjacent metal traces of the at least two metal traces to the first pad and the second pad respectively;

[0038] Applying a voltage difference between the first pad and the second pad to obtain a leakage current;

[0039] Based on the magnitude of the leakage current, the process abnormality of the device structure and its future reliability as a product can be determined.

[0040] The beneficial effects of the present invention are as follows:

[0041] Through the test structure of the present invention, the stability of multiple core processes can be monitored, such as the formation processes of active areas, gate structures, side walls, interlayer dielectric layers, contact holes, metal routing, etc. Once the leakage current is found to increase, it means that one or more of the above core processes may be abnormal. It can be further combined with other test parameters to screen out which process has an abnormality, quickly identify the root cause of the problem and take timely measures to reduce the cost of trial and error and reduce losses. On the other hand, through the leakage size of the test structure, we can intuitively obtain the degree of interference between the devices in the tube core area due to leakage between each other. This test is simple and convenient, and does not require the wafer to be destroyed, so it is a simple and efficient testing method. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The specific implementation modes of the present invention are further described in detail below in conjunction with the accompanying drawings.

[0043] Figure 1 FIG. 4 is a schematic diagram of a wafer including a die area and a test area according to an embodiment of the present invention.

[0044] Figure 2 FIG. 1 is a schematic diagram of an active region and a shallow trench isolation region in a die region according to an embodiment of the present invention.

[0045] Figure 3 FIG. 1 is a schematic diagram of abnormal dimensions of an active area and a shallow trench isolation area in a die region according to an embodiment of the present invention.

[0046] Figure 4 FIG. 4 is a schematic diagram of the structure of a MOS device formed in a die region according to an embodiment of the present invention.

[0047] Figure 5 The figure is a flow chart of a method for manufacturing a test structure according to an embodiment of the present invention.

[0048] Figure 6 FIG. 4 is a schematic diagram of a test structure according to an embodiment of the present invention.

[0049] Figure 7 FIG. 1 is a partially enlarged stereoscopic view of a test structure according to an embodiment of the present invention.

[0050] Figure 8 FIG. 4 is a schematic diagram of a test structure connected with a pad according to an embodiment of the present invention.

[0051] Figure 9-10 FIG. 1 is a schematic diagram of an abnormality in an active region forming process according to an embodiment of the present invention.

[0052] Figure 11-Figure 12 FIG. 1 is a schematic diagram of an abnormality in a contact hole forming process according to an embodiment of the present invention.

[0053] Figure 13-Figure 14 A schematic diagram of an abnormal metal routing process according to an embodiment of the present invention. DETAILED DESCRIPTION

[0054] In order to explain the present invention more clearly, the present invention is further described below in conjunction with embodiments and drawings. Similar components in the drawings are represented by the same reference numerals. It should be understood by those skilled in the art that the content specifically described below is illustrative rather than restrictive, and the protection scope of the present invention should not be limited thereto.

[0055] The terms “on”, “formed on” and “disposed on” in the present disclosure may mean that one layer is directly formed or disposed on another layer, or may mean that one layer is indirectly formed or disposed on another layer, i.e., there are other layers between the two layers.

[0056] It should be noted that, although the terms "first", "second", etc. may be used herein to describe various parts, components, elements, regions, layers and / or parts, these parts, components, elements, regions, layers and / or parts should not be limited by these terms. Instead, these terms are used to distinguish one part, component, element, region, layer and / or part from another.

[0057] In the present invention, unless otherwise specified, the expression "patterning process" generally includes the steps of photoresist coating, exposure, development, etching, photoresist stripping, etc. The expression "one-time patterning process" means a process of forming a patterned layer, component, member, etc. using one mask.

[0058] like Figure 1 As shown, semiconductor integrated circuits are realized by transferring circuits to wafers through various manufacturing processes such as patterning processes. During wafer processing, due to the size limitation of the exposure field of the photolithography machine, the wafer can be divided into multiple repeated exposure areas (shots) 10. The size of the exposure area is determined based on the capability of the photolithography machine and the effective utilization rate of the wafer. The size of the chip is often smaller than this area, so an exposure area can include multiple repeatedly arranged die areas 100, and adjacent die areas 100 are isolated by dicing lanes 105, and finally multiple dies are obtained by cutting the dicing lanes 105. Subsequently, the single die is packaged to obtain the final chip.

[0059] In the die area, active devices such as power devices, logic devices, etc. are manufactured according to the needs of the integrated circuit to be manufactured. In the manufacturing process, some key processes are often involved, including active area formation process, gate (such as polysilicon gate) formation process, sidewall formation process, interlayer dielectric layer formation process, contact hole formation process, and metal wiring formation process.

[0060] For example, taking the formation of a MOS transistor in the die region as an example, the typical steps of forming a MOS transistor include:

[0061] S10, forming a plurality of trenches on the wafer by a patterning process, and filling the trenches with an insulating medium such as SiO2 to form shallow trench isolation regions 20, and the wafer between the shallow trench isolation regions 20 constitutes an active region 22 for forming active devices, such as Figure 2 shown.

[0062] The isolation effect of the shallow trench isolation region 20 may be reduced due to the formation of voids when the trench is filled with an insulating dielectric, especially when the aspect ratio of the trench is larger.

[0063] In addition, the line width W1 (lateral width parallel to the wafer surface and perpendicular to the extension direction) of the active region 22 may increase due to fluctuations in the photolithography or etching process, while the pitch P1 of the active region is constant (e.g. Figure 3 and Figure 2 The pitch P1 of the active region 22 is the same, but Figure 3The line width of the active region 22 is relatively large), which results in the shallow trench isolation region 20 being narrowed, which also affects the isolation effect of the shallow trench isolation region 20. Therefore, the stability of the active region formation process needs to be monitored.

[0064] It should be noted that the pitch of the device structure referred to in the present invention refers to the sum of the line width of the device structure itself and the spacing between adjacent device structures.

[0065] S11, forming a well region 23 in the active region 22 by ion implantation, such as Figure 4 shown.

[0066] S12, forming a gate insulating layer 24 to cover the wafer.

[0067] S13 , forming a gate structure 25 , such as a polysilicon gate, on the gate insulating layer 24 .

[0068] In the actual process, the line width (lateral width perpendicular to the extension direction) W2 of the gate structure is a key process parameter that needs to be monitored. The line width of the gate structure may become larger due to fluctuations in the photolithography or etching process. Therefore, it is necessary to monitor the stability of the gate structure formation process.

[0069] S14 , forming LDD (Lightly Doped Drain) regions 26 in the well regions 23 on both sides of the gate structure 25 .

[0070] S15. In order to prevent short channel and hot carrier effects caused by lateral diffusion of source and drain ion implantation, sidewall spacers 27 are usually formed on both sides of the gate structure 25, for example, by a self-alignment process.

[0071] In the actual process, the line width (lateral width) W3 of the sidewall is also a key process parameter that needs to be monitored. The line width of the sidewall may increase due to fluctuations in the furnace tube film formation or etching process. Therefore, it is necessary to monitor the stability of the sidewall formation process.

[0072] S16 , using the polycrystalline gate and the sidewall spacer as masks, for example, forming a source region S and a drain region D in the well region 23 through an ion implantation process.

[0073] S17 , forming an interlayer dielectric layer 28 covering the gate structure 25 and the spacer 27 .

[0074] The interlayer dielectric layer 28 covers the gate structure 25 and the sidewalls 27, and covers the wafer surface between adjacent sidewalls 27, that is, the gaps between adjacent sidewalls 27 are also filled by the interlayer dielectric layer 28. In the actual process, when filling the gaps between the sidewalls, hole defects may be formed in the interlayer dielectric layer 28, that is, the adjacent interlayer dielectric layers are not isolated by an interlayer dielectric layer such as silicon dioxide, but by air plus silicon dioxide, which is bound to affect the isolation effect of the interlayer dielectric layer, and even cause interference (disturbance) between adjacent devices due to leakage, so the process stability of the interlayer dielectric layer also needs to be monitored.

[0075] S18 . Form a contact hole 29 in the interlayer dielectric layer 28 .

[0076] In the actual process, fluctuations in the photolithography or etching process may cause the size W4 of the contact hole to become larger and the formation position to shift, so the stability of the contact hole formation process also needs to be monitored.

[0077] S19 , forming a metal wiring 30 on the interlayer dielectric layer, and electrically connecting the metal wiring 30 to the source and drain through the contact hole 29 .

[0078] In the actual process, fluctuations in the photolithography or etching process may cause the line width W5 of the metal trace to increase and the formed position to shift, so the stability of the metal trace formation process also needs to be monitored.

[0079] It should be noted that the design of integrated circuits must closely match their manufacturing processes. For a specific process platform, the device size must follow the design rules given by the process platform during design. These rules often define the minimum size that can be achieved by the process. For example, for a 90-nanometer process platform, the polysilicon gate feature size (minimum line width) of the device structure manufactured on this platform cannot be less than 90 nanometers.

[0080] In fact, in addition to the core devices of the smallest size, a process platform often provides other auxiliary devices of larger size. Therefore, the line width and active area pitch of each active area 22 formed in the tube core area may not be consistent. In general, the smaller the device size, the smaller its pitch will be. Taking a typical 90-nanometer process platform as an example, it is required that when designing a series of active area line width and active area pitch parameters, the minimum line width (characteristic size) and minimum pitch of the active area cannot be less than 0.1 nanometers and 0.25 microns respectively. The smallest size device is often the most core device of the process platform and the device with the greatest process difficulty. Therefore, during wafer processing, it is often the key monitoring object.

[0081] Similarly, when designing and manufacturing gate structures, contact holes and metal routing, the above process limitations also need to be followed.

[0082] In order to monitor the stability of the above key processes, the present invention provides a test structure, which is fabricated in an area outside the die area of ​​the wafer, referred to herein as a test area. Preferably, the test area is formed in Figure 1 The test structure is arranged in the dicing lane 105. No additional wafer space is occupied, thereby improving the utilization rate of the wafer.

[0083] Figure 5 A method for manufacturing the test structure of the present invention is shown, comprising:

[0084] S50, forming a shallow trench isolation region extending along a first direction and at least two active regions isolated by the shallow trench isolation region in the test region, wherein the active region and the shallow trench isolation region in the test region are formed synchronously with the active region and the shallow trench isolation region in the die region.

[0085] In a specific example, if Figure 4 and Figure 6 As shown, a plurality of shallow trench isolation regions 61 extending along the x direction and a plurality of active regions 60 isolated by the shallow trench isolation regions 61 are formed in the test region, wherein the shallow trench isolation regions 61 and Figure 2 The shallow trench isolation region 20 in the middle core region is formed simultaneously, and the active region 60 and Figure 2 The active area 22 in the middle die area is formed simultaneously.

[0086] Specifically, it includes forming a trench on the wafer using photolithography and etching processes, and filling the trench with an insulating medium, thereby forming a shallow trench isolation region 20 and an active region 22 in the die region, and forming a shallow trench isolation region 61 and an active region 60 in the test region. The above-mentioned "synchronous formation" means that the steps of photolithography, etching, filling, etc. are synchronized in the die region and the test region.

[0087] The device structure that needs to be monitored in the die area is formed synchronously with the test structure in the test area to ensure that any process changes in the die area will be "copied" to the test area, which is the basis for monitoring.

[0088] As mentioned above, in actual processes, the line width W1 and active area pitch P1 of the multiple active areas 22 formed in the tube core area may be different. The process drift obviously has the greatest impact on the active area with a narrow line width. For example, if the line width increases by 0.1 micron, for the active area with a line width of 1 micron and the active area with a line width of 10 microns, the latter obviously has a smaller line width change rate and is less affected.

[0089] Therefore, for monitoring the line width of the active area, it is more necessary to monitor the process stability of the active area with the smallest line width (correspondingly, the smallest pitch). Therefore, during the manufacturing process, when the mask is used for the composition process, the line width of the active area 60 in the test area is formed to be consistent with the line width of the active area with the smallest line width (characteristic size) in the die area.

[0090] Taking a 60-micron-wide scribe line as an example, if the minimum line width of the active area of ​​the 90-nanometer process platform is placed, more than 200 lines can be placed. In order to avoid the loading effect, the light transmittance of the active area 60 of the test structure needs to be as consistent as possible with the pattern of the tube core area during design. Avoid the loading effect causing the active area 60 of the test structure to have a large difference in morphology with the active area 22 in the tube core area, thereby causing monitoring distortion.

[0091] S52, forming at least two gate structures extending along the second direction on the active area and the shallow trench isolation area, overlapping with at least two active areas, wherein the gate structure in the test area is formed synchronously with the gate structure in the die.

[0092] In the test structure of the present invention, there are at least two active regions 60 extending in the x-direction, and at least two gate structures 62 extending in the y-direction. The extent to which the active region 60 extends in the x-direction at least overlaps with the two gate structures 62 (the term "overlap" described herein does not mean that the overlapping components are in contact with each other, for example, the active region 60 and the gate structure 62 are in contact, and there may be other components between the two according to actual needs, so the term "overlap" refers to the overlap of the projections of the two on the wafer). Similarly, in the y-direction, the extent to which each gate structure 62 extends at least overlaps with two active regions.

[0093] In a specific example, if Figure 4 and Figure 6 As shown, a gate material layer is deposited on the gate insulating layer, and a gate structure 25 is formed in the die region and a gate structure 62 is formed in the test region through a patterning process.

[0094] As mentioned above, in the actual process, the line widths W2 of the multiple gate structures 25 formed in the tube core area can be different. Generally, the narrow line process is the most difficult and most likely to drift. On the other hand, process drift has a greater impact on narrow line devices. Therefore, for the monitoring of the line width of the gate structure, it is more necessary to monitor the process stability of the gate structure with the smallest line width.

[0095] Therefore, when manufacturing the gate structure, when using the mask for patterning, the line width of the gate structure in the test area is made consistent with the line width of the gate structure with the minimum line width (characteristic size) in the die area.

[0096] Figure 7 Show Figure 6 A three-dimensional schematic diagram of the area shown in the dotted box.

[0097] S54, forming an interlayer dielectric layer covering the gate structure, the active area and the shallow trench isolation area, wherein contact holes are formed in the interlayer dielectric layer in the active area on both sides of the gate structure, wherein the contact holes in the test area are formed synchronously with the contact holes in the tube core area.

[0098] In a specific example, if Figure 4 and Figure 6 , 7 As shown, an interlayer dielectric layer 28 (e.g., SiO2) is covered on the tube core area and the test area, and then a contact hole 29 is formed in the tube core area through a composition process and a contact hole 63 is simultaneously formed in the test area, respectively exposing the source and drain regions on both sides of the gate structure 25 and the active area 60 on both sides of the gate structure 62.

[0099] In order to more clearly show the contact hole 63, the interlayer dielectric layer is Figure 7 It should be noted that the production of the contact hole actually includes the steps of forming a through hole in the interlayer dielectric layer and filling the through hole with a metal such as tungsten to form a metal plug. Therefore, in the figure, the contact hole 63 can actually represent a metal plug, that is, the metal trace 64 is electrically connected to the active area through the metal plug.

[0100] Since the gate structure 62 serves as a mask, contact holes are formed on each active region 60 overlapping therewith, and are distributed on both sides of the gate structure 62 .

[0101] Figure 7 As shown in FIG. 1 , two gate structures 62 are provided, so three contact holes are formed for each active region overlapping with the gate structures 62. However, the present invention is not limited thereto. Figure 6 In the example shown, there are more gate structures 62 and more contact holes 63 are formed on each active region 60 .

[0102] S56. Form at least two metal traces on the interlayer dielectric layer, wherein the metal traces extend along a first direction, correspond to the active areas one by one, and are electrically contacted with the corresponding active areas through contact holes, wherein the metal traces in the test area are formed synchronously with the metal traces in the core area.

[0103] In a specific example, if Figure 4 and Figure 6 , 7 As shown, a metal layer is covered in the die area and the test area, and a metal trace 30 and a metal trace 64 are simultaneously formed in the die area and the test area through a patterning process.

[0104] Similar to the gate structure, in the actual process, the line width W5 of the metal trace 30 formed in the tube core area can be different. Generally speaking, the narrow line process is the most difficult and most likely to drift. On the other hand, process drift has a greater impact on narrow line devices. Therefore, for metal trace line width monitoring, what needs to be monitored more is the process stability of the metal trace with the smallest line width.

[0105] In addition, when the sidewall spacer 27 is manufactured in the die area, if the stability of the sidewall spacer process needs to be monitored, the method of the present invention further includes after step S53 and before step S54:

[0106] Sidewall spacers are formed on both sides of the gate structure in the test area along the second direction, and the sidewall spacers in the test area are formed synchronously with the sidewall spacers in the core area.

[0107] In a specific example, if Figure 4 and Figure 7 As shown, the spacers 27 and 65 are formed simultaneously in the die area and the test area by patterning process. The line width of the spacers 65 in the test area is consistent with the line width of the spacers 27 in the die area.

[0108] Optionally, in the test area, a source and a drain are formed synchronously with the source and the drain in the die area, and are respectively located on both sides of the gate structure 62 (or the sidewall 65 if there is one).

[0109] The source and drain regions are also formed in the test region, which is more conducive to reducing the contact resistance between the active region and the contact hole in the test region, thereby achieving the effect of reducing the parasitic resistance.

[0110] Through the above steps, a Figure 6 and 7 However, it should be noted that the test structure does not necessarily need to be manufactured according to the above method, and under the guidance of the present invention, those skilled in the art can also implement it through other methods and / or steps.

[0111] Next, it will be introduced how to realize the monitoring of key process parameters of the die area through the above structure.

[0112] Monitoring of gate structure / sidewall / interlayer dielectric layer formation process

[0113] The inventors analyzed the gate structures and sidewalls with abnormal (increased) line widths in the finished devices and found that such structures are often accompanied by holes in the interlayer dielectric layer. The reason is that the gate structure and / or sidewalls become larger, and the gap between adjacent gate structures / sidewalls becomes smaller when the pitch remains unchanged. As a result, when the interlayer dielectric layer is deposited, the ability to fill the interlayer dielectric layer in the gap is weakened, and the probability of hole generation increases. In addition, the narrower the gap, the greater the probability of holes, and the greater the possibility of leakage current caused by interference between devices.

[0114] Therefore, the abnormality of the gate structure and / or the sidewall line width in the core area may be characterized by whether there are holes in the interlayer dielectric layer of the test structure. That is, if there are holes in the interlayer dielectric layer of the test structure, then the gate structure and / or the sidewall line width in the core area may be abnormal.

[0115] Furthermore, it is necessary to find a method for monitoring the holes appearing in the interlayer dielectric layer.

[0116] US Patent No. 6774989B1 provides an optical method, but this method requires specialized optical instruments and is relatively costly. On the other hand, since the appearance of holes in the interlayer dielectric layer on the wafer is random, the monitoring efficiency of this method is relatively low.

[0117] The inventors found that when holes appear in the interlayer dielectric layer of the test structure, Figure 7 When two metal traces 64 are subjected to a high voltage difference, the leakage current between the contact holes 63 on two adjacent active regions 60 will increase dramatically because the holes cause the insulation of the interlayer dielectric layer to deteriorate.

[0118] Therefore, the present invention can further convert hole monitoring into electrical performance (leakage current) detection, which is the theoretical basis for the test structure of the present invention to have the ability to monitor related processes.

[0119] like Figure 8 As shown, by electrically connecting two adjacent metal traces to pads 66 and 67, respectively, applying a voltage difference to pads 66 and 67, and measuring the leakage current, it is possible to monitor whether the leakage current is abnormal. For example, if it exceeds a predetermined threshold, the leakage current is determined to be abnormal, thereby generating an alarm.

[0120] The filling capacity of the interlayer dielectric layer is directly related to the aspect ratio of the pattern on the wafer before filling. According to experience, holes are easily generated when the aspect ratio is greater than 4. Taking a 90-nanometer platform as an example, assuming that the thickness of the gate structure 62 is 1500 angstroms, the process may produce a pattern with an aspect ratio of more than 4.

[0121] To this end, in order to enhance the sensitivity of the test structure of the present invention to voids, for the gate structure 62 in the test structure, preferably, its line width is consistent with the line width of the gate structure with the smallest line width in the tube core area (when the pitch is constant, it means that the spacing between adjacent gate structures is also the smallest), so that the place with the largest aspect ratio appears between adjacent gate structures, that is, the place where voids in the interlayer dielectric layer are most likely to occur.

[0122] Once the leakage current is detected to exceed the preset threshold, it means that the characteristic size (minimum line width) of the gate structure in the core region may be abnormally enlarged. As mentioned above, monitoring the characteristic size abnormality of the gate structure in the core region is the most necessary monitoring in the gate structure formation process.

[0123] As mentioned above, the test structure has at least two active regions 60 . If there are only two active regions, the metal traces 64 corresponding to the two active regions are connected to the pads 66 and 67 , respectively.

[0124] Alternatively, the number of active areas can be greater, but when measuring, only two adjacent ones need to be selected to connect pad 66 and pad 67 to complete the measurement, such as Figure 6 Two metal traces 64 are shown in FIG.

[0125] As mentioned above, in theory, the active area 60 and gate structure 62 of the test structure only need two each to overlap, thereby forming a contact hole 63 and two corresponding metal traces 64, so as to achieve the above-mentioned capture of the hole. However, the appearance of all holes has time and space uncertainty. Such a structure makes it probabilistic whether there is a void defect between two metal traces 64. When the hole happens to fall between the two metal traces 64, the insulation effect of the interlayer dielectric layer between them will be degraded under high voltage, resulting in large leakage, and then it can be judged that the gate structure and / or the sidewall feature size of the tube core area may be abnormal.

[0126] However, in a preferred example, within the scope permitted by the design and manufacturing rules, the gate structure 62 (or side wall) is extended as far as possible in the y direction to overlap with as many active areas 60 as possible. Preferably, the length of the gate structure in the y direction is more than 1 / 2 of the width of the scribe line, that is, it overlaps with the active area 60 involved in 1 / 2 of the width of the scribe line as much as possible.

[0127] In the present invention, the term “above” includes the number itself, for example, “above 1 / 2” means including 1 / 2, such as 1 / 2, 2 / 3, 3 / 4, 3 / 5, 4 / 5, 1.

[0128] In this way, long thin gaps are formed between adjacent gate structures (or sidewalls), further weakening the filling capacity of the interlayer dielectric layer (in other words, the longer the gate structure / sidewall, the greater the probability of voids). If a void is generated, it is easy to form a void belt along the y direction. The void belt increases the probability of void defects falling on the Figure 7 When the hole happens to fall between two metal traces 64, the insulation effect of the interlayer dielectric layer between them will be degraded under high voltage, and large leakage will occur between the contact holes on the adjacent active areas.

[0129] In another preferred example, within the scope allowed by the design and manufacturing rules, the active region 60 is extended as much as possible in the x direction and overlaps as many gate structures 62 as possible. Preferably, the length of the active region 60 in the x direction is more than 4 / 5 of the spacing between the pads 66 and 67, so that more hole defect "catchers" will appear in the x direction.

[0130] like Figure 7 As shown in the figure, the active area overlaps with the two gate structures, and three hole defect "catchers" appear in the I / II / III regions. Since the contact holes corresponding to the same active area are connected by the same metal trace, any "catcher" that catches a hole defect will cause a sudden increase in the total leakage current, which in turn reflects the abnormality of the online process and the reliability of the integrated circuit.

[0131] In addition to the gate structure and / or the sidewall process, changes in the filling capacity of the interlayer dielectric layer itself will undoubtedly also produce holes. Therefore, in addition to being able to monitor the stability of the gate structure and / or the sidewall process in the tube core area, the above-mentioned test structure can also monitor the stability of the interlayer dielectric layer filling process. In other words, if holes are detected in the interlayer dielectric layer of the above-mentioned test structure, it is judged that the characteristic dimensions of the gate structure and / or the sidewall in the tube core area may be abnormal or the interlayer dielectric layer filling process may be abnormal. Combined with conventional online testing methods, the specific key process where the abnormality occurs can be accurately determined.

[0132] Because the design rules of the test structure are exactly the same as those of the die area, if holes appear in the test area in theory, there is a high probability that holes will also appear in some places in the die area, causing chip performance to deteriorate.

[0133] Compared with US6774989B1, since the principle of the present invention is simple, the efficiency is high, and there is no additional process and equipment added, the test structure can be used as an effective means to monitor the above three processes whether in the mass production stage or the new product development stage, and therefore has important production practice significance.

[0134] Monitoring of the active area formation process

[0135] like Fig. 9 In the case of abnormal line width of the active area in the die area, when the active area lithography or etching process fluctuates, the width of the active area 60 increases, and since the pitch is unchanged, the effective isolation thickness of the shallow trench isolation area 61 decreases. The reduction in the thickness of the isolation layer will inevitably lead to an increase in leakage between adjacent active areas.

[0136] In addition, when the shallow trench isolation region 61 is filled with dielectric, the process conditions are abnormal, resulting in the appearance of the dielectric in the shallow trench isolation region. Fig.10 When the hole shown is Fig.10As shown in the figure, as the equivalent thickness of the isolation layer decreases, the leakage between the active areas will also increase significantly.

[0137] Therefore, monitoring the active area formation process in the die region involves monitoring the abnormality of the active area line width and monitoring the stability of the filling process of the insulating medium (forming the shallow trench isolation region) in the trench.

[0138] Regardless of which of the above anomalies, the test structure of the present invention can be implemented. Figure 8 In the structure shown, different voltages are applied to two adjacent metal traces to test the leakage current. Generally speaking, the leakage current increases exponentially as the distance between the two traces decreases.

[0139] As described above, for monitoring the abnormality of the line width of the active area in the tube core area, the abnormality of the line width (characteristic size) of the active area with the smallest line width is most needed to be monitored. For this reason, preferably, the line width of the active area 60 of the test structure is consistent with the line width of the active area with the smallest line width in the tube core area, that is, during the formation process, the same mask as the mask used to form the active area with the smallest line width in the tube core area is used to synchronously form the line width of the active area of ​​the test area.

[0140] It has been verified in practice that the above test structure is suitable for processes below 90 nanometers, especially processes below 65 nanometers, because when the active area pitch is reduced to below 0.2 microns, the leakage current and the active area size change enter the sensitive area, and a change of only a few nanometers in the active area line width can cause the leakage current to change by an order of magnitude.

[0141] Monitoring of contact hole formation process

[0142] like Fig.11 As shown, when the alignment between the contact hole 63 and the active area 60 drifts along the y direction (ie, overlay deviation occurs), especially when the contact hole is partially located above the shallow trench isolation area 61, it is equivalent to reducing the width between the contact hole 63 and the shallow trench isolation area.

[0143] like Fig.12 As shown, if the characteristic size of the contact hole 63 increases by an amount a (changed from a solid line to a dotted line in the figure), the distance between the contact holes on the adjacent active regions will be reduced by 2a.

[0144] Both of the above situations will cause an increase in leakage current, especially the abnormality of the characteristic size will directly lead to a sharp increase in leakage current. The test structure of the present invention can achieve monitoring. Figure 8 In the structure shown, different voltages are applied to two adjacent metal traces to test the leakage current. Both of the above situations will cause an increase in leakage current, especially the abnormality of feature size will directly lead to a sharp increase in leakage current.

[0145] Therefore, in order to monitor the abnormality of the contact hole in the die area, the size of the contact hole of the test structure is consistent with the size of the contact hole in the die area.

[0146] Monitoring of metal trace formation process

[0147] The impact of the metal routing process on the electrical properties of this structure is similar to that of the contact hole.

[0148] like Fig.13 As shown, the metal trace 64 has drifted along the y direction (i.e., overlay deviation occurs) which will affect the Figure 8 The leakage between the metal wiring and the contact hole and between the metal wiring in the structure shown further affects the overall current of the test structure of the present invention.

[0149] like Fig.14 As shown, the increase in the line width of the metal trace 64 (from a solid line to a dotted line) will also affect the Figure 8 The leakage between the metal wiring and the contact hole and between the metal wiring in the structure shown further affects the overall current of the test structure of the present invention.

[0150] Therefore, in order to monitor the abnormality of the metal routing process in the die area, the line width of the metal routing of the test structure is consistent with the line width of the metal routing with the smallest line width in the die area.

[0151] It can be seen that the test structure of the present invention can monitor the stability of multiple core processes. Once the leakage current increases, it means that one or more of the above core processes may be abnormal. The structure is sensitive and efficient in reflecting process abnormalities. It can further combine other test parameters to screen out which process has abnormalities, quickly identify the root cause of the problem and take timely measures to reduce trial and error costs and losses.

[0152] On the other hand, the leakage of the test structure can be used to intuitively determine the degree of interference between devices in the die area due to leakage between them. The test method is simple and convenient, and does not require the wafer to be damaged. Therefore, the test method is simple, efficient, and easy to apply in practice.

[0153] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not limitations on the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is impossible to list all the embodiments here. All obvious changes or modifications derived from the technical solution of the present invention are still within the protection scope of the present invention.

Claims

1. A test structure formed in a test area of ​​a wafer for monitoring process anomalies in forming a device structure in a die area of ​​the wafer, It is characterized in that The test structure includes: A shallow trench isolation region extending along a first direction and at least two active regions isolated by the shallow trench isolation region; At least two gate structures extending along the second direction are formed on the shallow trench isolation region and the active region, wherein the gate structure overlaps at least two active regions, and the line width of the gate structure is consistent with the line width of the gate structure with the smallest line width formed in the device structure; An interlayer dielectric layer covering the gate structure, the active area and the shallow trench isolation area in the test structure, wherein contact holes are formed in the interlayer dielectric layer covering the active areas on both sides of the gate structure in the test structure; At least two metal traces extending along a first direction are formed on the interlayer dielectric layer, wherein the metal traces correspond to the at least two active regions one by one and are electrically contacted with the corresponding active regions through the contact holes.

2. The test structure according to claim 1, characterized in that: The test area is located in a scribe line of the wafer, and a length of a gate structure in the test structure in the second direction is greater than 1 / 2 of a width of the scribe line.

3. The test structure according to claim 2, characterized in that: Also includes: A first pad and a second pad are respectively connected to any two adjacent metal traces of the at least two metal traces; The length of the plurality of active regions in the first direction is greater than 4 / 5 of the distance between the first pad and the second pad.

4. The test structure according to claim 1, characterized in that: Also includes: Sidewall spacers are formed on both sides of the gate structure along the second direction.

5. The test structure according to any one of claims 1 to 4, characterized in that: The line width of the active region is consistent with the line width of the active region with the smallest line width formed in the device structure; and / or The size of the contact hole is consistent with the size of the contact hole formed in the device structure; and / or The line width of the metal routing line is consistent with the line width of the metal routing line with the smallest line width formed in the device structure.

6. The test structure according to any one of claims 1 to 4, characterized in that: A source region and a drain region are also formed in the active region and are respectively located on two sides of the gate structure.

7. A method for manufacturing a test structure for monitoring process anomalies in forming a device structure in a die region of a wafer, characterized in that: The method comprises: Forming a shallow trench isolation region extending along a first direction and at least two active regions isolated by the shallow trench isolation region in a test region of a wafer, wherein the shallow trench isolation region and the active region are formed synchronously with the shallow trench isolation region and the active region in the device structure; At least two gate structures extending along the second direction are formed on the shallow trench isolation region and the active region in the test region, wherein the gate structure overlaps at least two active regions, and the gate structure is formed synchronously with the gate structure in the device structure, and the line width is consistent with the line width of the gate structure with the smallest line width formed in the device structure; forming an interlayer dielectric layer covering the gate structure, the active area and the shallow trench isolation area in the test area, wherein contact holes are formed in the interlayer dielectric layer covering the active areas on both sides of the gate structure of the test structure, and wherein the contact holes are formed synchronously with the contact holes formed in the device structure; At least two metal traces extending along a first direction are formed on the interlayer dielectric layer, wherein the metal traces are formed synchronously with the metal traces in the device structure, and the metal traces in the test structure correspond one-to-one to the at least two active areas and are electrically contacted with the corresponding active areas through contact holes in the test structure.

8. The method according to claim 7, characterized in that The test area is located in a scribe line of the wafer, and a length of a gate structure in the test structure in the second direction is greater than 1 / 2 of a width of the scribe line.

9. The method according to claim 8, characterized in that Also includes: forming a first pad and a second pad, respectively connecting any two adjacent metal traces of the at least two metal traces; The length of the plurality of active regions in the first direction is greater than 4 / 5 of the distance between the first pad and the second pad.

10. The method according to any one of claims 7 to 9, characterized in that: Also includes: A source region and a drain region are formed in the active region of the test structure, respectively located on both sides of the gate structure in the test structure, and the source region and the drain region are formed synchronously with the source region and the drain region in the device structure.

11. A method for monitoring process anomalies of a device structure formed in a die region on a wafer, characterized in that: Using the test structure according to any one of claims 1 to 6, The method comprises: Connecting any two adjacent metal traces of the at least two metal traces to the first pad and the second pad respectively; Applying a voltage difference to the first pad and the second pad to obtain a leakage current; The magnitude of the leakage current reflects abnormality in the process of forming the device structure.

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