Latch Circuit

Abstract

The present invention relates to a latch circuit, comprising: a transmission module, comprising a first output terminal and a second output terminal, wherein the first output terminal is used to output a first signal of a first level state according to an input signal, and the second output terminal is used to output a second signal of a second level state according to the input signal, wherein the first level state and the second level state are different; an output module, connected to the first output terminal and the second output terminal respectively, and used to generate an output signal according to the first signal and the second signal; and a feedback control module, connected to the output terminal of the output module, the first output terminal, and the second output terminal respectively, and used to control the level state of the first output terminal to be the first level state, and control the level state of the second output terminal to be the second level state according to the output signal, the first signal, and the second signal.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to a latch circuit. Background Art

[0002] As the feature size of integrated circuits continues to decrease, the power supply voltage and logic gate node capacitance continue to decrease, making circuits more sensitive to radiation. The reduction in power supply voltage and node capacitance results in a decrease in the amount of charge stored on the node, making the circuit susceptible to radiation-induced soft errors. When a high-energy particle, such as an alpha or neutron, hits an off-state transistor in a sequential circuit, it disturbs the logic value stored at the node to its complementary value. This phenomenon, which occurs in sequential logic circuits, is called a single event upset (SEU).

[0003] The intermediate nodes and output nodes of traditional CMOS latch circuits are very sensitive to radiation effects. When high-energy particles hit any of the above sensitive nodes, the logic value of the impacted node may change to its complement. Due to the circuit structure of the latch, the logic level change of any sensitive node will be transferred to another node through the feedback path between the two inverters, resulting in the transmission of erroneous logic and ultimately affecting the output logic value of the latch.

[0004] The amount of charge that a high-energy particle deposits in a sensitive node and causes a single-particle upset is called the critical charge. The critical charge depends on the capacitance of the node and the supply voltage of the circuit. These two parameters decrease as the scale of integrated circuit technology expands, so the critical charge of the sensitive node also gradually decreases. Therefore, a particle with lower energy hitting a sensitive node may cause a single-particle upset. The typical technology for SEU reinforcement of latches is triple-modular redundant latches (TMR), in which three parallel latches and a voter circuit are used to eliminate the problem of single-particle upsets. However, although TMR can completely prevent the occurrence of single-particle upset events, this technology will generate higher power consumption, larger area overhead, and higher latency. In addition, only the nodes inside the three latches of the triple-modular redundant latch are completely immune to SEU. When high-energy particles bombard the voter circuit, single-particle upsets may still occur. Therefore, how to minimize power consumption, delay, and area overhead while maintaining SEU immunity has become an urgent problem to be solved. Summary of the invention

[0005] Based on this, it is necessary to provide a latch circuit that can eliminate single-particle upsets at each node in the latch circuit and reduce the power consumption of the latch circuit.

[0006] The present application provides a latch circuit, comprising:

[0007] A transmission module, comprising a first output end and a second output end, wherein the first output end is used to output a first signal in a first level state according to an input signal, and the second output end is used to output a second signal in a second level state according to the input signal, wherein the first level state and the second level state are different;

[0008] an output module, connected to the first output terminal and the second output terminal respectively, and configured to generate an output signal according to the first signal and the second signal;

[0009] A feedback control module is connected to the output end of the output module, the first output end, and the second output end, respectively, and is used to control the level state of the first output end to be the first level state, and control the level state of the second output end to be the second level state according to the output signal, the first signal, and the second signal.

[0010] In one embodiment, the transmission module includes:

[0011] a first transmission circuit, wherein an input end of the first transmission circuit is used to receive the input signal, and an output end of the first transmission circuit is the first output end, which is used to output a first signal in a first level state according to the input signal under the control of a control signal;

[0012] A second transmission circuit, wherein the input end of the second transmission circuit is used to receive the input signal, and the output end of the second transmission circuit is the second output end, which is used to output a second signal in a second level state according to the input signal under the control of a control signal.

[0013] In one embodiment, the first transmission circuit includes:

[0014] A first transmission gate, wherein an input end of the first transmission gate is used to receive the input signal, a controlled end of the first transmission gate is used to receive the control signal, and an output end of the first transmission gate is the first output end.

[0015] In one embodiment, the second transmission circuit includes:

[0016] a second transmission gate, wherein an input end of the second transmission gate is used to receive the input signal, and a controlled end of the second transmission gate is used to receive the control signal;

[0017] An inverter, wherein an input end of the inverter is connected to an output end of the second transmission gate, and an output end of the inverter is the second output end.

[0018] In one embodiment, the output module includes:

[0019] a first pull-up circuit, wherein a first end of the first pull-up circuit is connected to the first output end, and a second end of the first pull-up circuit is connected to the second output end;

[0020] A first pull-down circuit, wherein a first end of the first pull-down circuit is connected to the first output end, a second end of the first pull-down circuit is connected to the second output end, and a third end of the first pull-down circuit is connected to a third end of the first pull-up circuit to jointly output the output signal.

[0021] In one embodiment, the first pull-up circuit comprises:

[0022] a first transistor, wherein a first terminal of the first transistor is connected to a power supply voltage, and a control terminal of the first transistor is connected to the second output terminal;

[0023] A second transistor, wherein a first end of the second transistor is connected to a second end of the first transistor, a control end of the second transistor is connected to the first output end, and a second end of the second transistor is a third end of the first pull-up circuit.

[0024] In one embodiment, the first pull-down circuit comprises:

[0025] a third transistor, wherein a first end of the third transistor is a third end of the first pull-down circuit, and a control end of the third transistor is connected to the first output end;

[0026] a fourth transistor, wherein a first terminal of the fourth transistor is connected to the second terminal of the third transistor, a control terminal of the fourth transistor is connected to the second output terminal, and a second terminal of the fourth transistor is grounded.

[0027] In one embodiment, the feedback control module includes:

[0028] A first feedback circuit is connected to the output end of the output module, the second output end and the first output end respectively, and is used to control the level state of the first output end to be the first level state according to the output signal and the second signal;

[0029] The second feedback circuit is connected to the output end of the output module, the first output end and the second output end respectively, and is used to control the level state of the second output end to be the second level state according to the output signal and the first signal.

[0030] In one embodiment, the first feedback circuit includes:

[0031] a second pull-up circuit, wherein a first end of the second pull-up circuit is connected to the second output end, a second end of the second pull-up circuit is connected to the output end of the output module, and a third end of the second pull-up circuit is connected to the first output end;

[0032] A second pull-down circuit, wherein a first end of the second pull-down circuit is connected to the second output end, a second end of the second pull-down circuit is connected to the output end of the output module, and a third end of the second pull-down circuit is connected to the first output end.

[0033] In one embodiment, the second feedback circuit includes:

[0034] a third pull-up circuit, wherein a first end of the third pull-up circuit is connected to the first output end, a second end of the third pull-up circuit is connected to the output end of the output module, and a third end of the third pull-up circuit is connected to the second output end;

[0035] A third pull-down circuit, wherein a first end of the third pull-down circuit is connected to the first output end, a second end of the third pull-down circuit is connected to the output end of the output module, and a third end of the third pull-down circuit is connected to the second output end.

[0036] In the above latch circuit, the first output end of the transmission module outputs a first signal in a first level state according to the input signal, the second output end outputs a second signal in a second level state according to the input signal, the output module generates an output signal according to the first signal and the second signal, and the feedback control module controls the level state of the first output end to be the first level state and controls the level state of the second output end to be the second level state according to the output signal, the first signal and the second signal, thereby eliminating the influence of a single-particle flip on the first output end, the second output end and the output end of the output module, realizing the function of resisting single-particle flip of the internal node of the latch circuit, and the circuit structure is simple and the circuit power consumption is low. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 is a schematic block diagram of a latch circuit in the first embodiment;

[0039] Figure 2 is a block diagram of a latch circuit in the second embodiment;

[0040] Figure 3 is a schematic diagram of a latch circuit in the first embodiment;

[0041] Figure 4 is a schematic diagram of a latch circuit in a second embodiment;

[0042] Figure 5 is a schematic diagram of a latch circuit in a third embodiment;

[0043] Figure 6 is a schematic diagram of a latch circuit in a fourth embodiment;

[0044] Figure 7 is a schematic diagram of a latch circuit in a fifth embodiment;

[0045] Figure 8 Schematic diagram of the latch circuit in the sixth embodiment. DETAILED DESCRIPTION

[0046] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0048] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first output terminal may be referred to as a second output terminal, and similarly, a second output terminal may be referred to as a first output terminal. Both the first output terminal and the second output terminal are output terminals of a transmission module, but they are not the same output terminal.

[0049] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0050] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0051] Figure 1 FIG. 1 is a block diagram of a latch circuit in the first embodiment. Figure 1 As shown, in this embodiment, a latch circuit is provided, including: a transmission module 102 , an output module 104 and a feedback control module 106 .

[0052] The transmission module 102 includes a first output terminal 1 and a second output terminal 2, wherein the first output terminal 1 is used to output a first signal in a first level state according to an input signal D, and the second output terminal 2 is used to output a second signal in a second level state according to the input signal D, wherein the first level state and the second level state are different; the level state is divided into a high level state and a low level state, wherein the first level state and the second level state are different means that when the first level state is a high level state, the second level state is a low level state, and when the first level state is a low level state, the second level state is a high level state.

[0053] The output module 104 is connected to the first output terminal 1 and the second output terminal 2 respectively, and is used to generate an output signal Q according to the first signal and the second signal.

[0054] The feedback control module 106 is connected to the output terminal 3, the first output terminal 1, and the second output terminal 2 of the output module 104, respectively, and is used to control the level state of the first output terminal 1 to be the first level state, and control the level state of the second output terminal 2 to be the second level state according to the output signal Q, the first signal, and the second signal.

[0055] In the above latch circuit, the first output end of the transmission module outputs a first signal in a first level state according to the input signal, the second output end outputs a second signal in a second level state according to the input signal, the output module generates an output signal according to the first signal and the second signal, and the feedback control module controls the level state of the first output end to be the first level state and controls the level state of the second output end to be the second level state according to the output signal, the first signal and the second signal, thereby eliminating the influence of a single-particle flip on the first output end, the second output end and the output end of the output module, realizing the function of resisting single-particle flip of the internal node of the latch circuit, and the circuit structure is simple and the circuit power consumption is low.

[0056] Figure 2 FIG. 1 is a block diagram of a latch circuit in the second embodiment. Figure 2 As shown, in one embodiment, the transmission module 102 includes: a first transmission circuit 202 and a second transmission circuit 204; the input end of the first transmission circuit 202 is used to receive the input signal D, the output end of the first transmission circuit 202 is the first output end 1, and the first transmission circuit 202 is used to output a first signal of a first level state according to the input signal D under the control of a control signal; the input end of the second transmission circuit 204 is used to receive the input signal D, the output end of the second transmission circuit 204 is the second output end 2, and the second transmission circuit 204 is used to output a second signal of a second level state according to the input signal D under the control of a control signal.

[0057] Figure 3 FIG. 1 is a schematic diagram of a latch circuit in the first embodiment. Figure 3 As shown, in one embodiment, the first transmission circuit 202 includes: a first transmission gate, the input end of the first transmission gate is used to receive the input signal D, the controlled ends CLKB and CLK of the first transmission gate are used to receive the control signal, and the output end of the first transmission gate is the first output end 1. When the controlled end CLKB receives the control signal "1" and the controlled end CLK receives the control signal "0", the first transmission gate is turned on and outputs a first signal of a first level state according to the input signal D, and when the controlled end CLKB receives the control signal "0" and the controlled end CLK receives the control signal "1", the first transmission gate is turned off.

[0058] like Figure 3As shown, in one embodiment, the second transmission circuit 204 includes: a second transmission gate 302 and an inverter 304, the input end of the second transmission gate 302 is used to receive the input signal D, and the controlled end of the second transmission gate 302 is used to receive the control signal; the input end of the inverter 304 is connected to the output end of the second transmission gate 302, and the output end of the inverter 304 is the second output end 2. The controlled terminals CLKB and CLK of the second transmission gate 302 are used to receive the control signal. When the controlled terminal CLKB receives the control signal "1" and the controlled terminal CLK receives the control signal "0", the second transmission gate 302 is turned on and outputs a signal of a first level state to the inverter 304 according to the input signal D. The inverter 304 outputs a second signal of a second level state according to the received signal of the first level state. When the controlled terminal CLKB receives the control signal "0" and the controlled terminal CLK receives the control signal "1", the second transmission gate 302 is turned off, wherein the first transmission gate and the second transmission gate receive the same control signal at the same time, that is, the first transmission gate and the second transmission gate are turned on and off at the same time.

[0059] Figure 4 FIG. 1 is a schematic diagram of a latch circuit in the second embodiment. Figure 4 As shown, in one embodiment, the output module 104 includes: a first pull-up circuit 206 and a first pull-down circuit 208; the first end of the first pull-up circuit 206 is connected to the first output end 1, and the second end of the first pull-up circuit 206 is connected to the second output end 2; the first end of the first pull-down circuit 208 is connected to the first output end 1, the second end of the first pull-down circuit 208 is connected to the second output end 2, and the third end of the first pull-down circuit 208 is connected to the third end of the first pull-up circuit 206, so as to jointly output the output signal Q.

[0060] Figure 5 FIG. 4 is a schematic diagram of a latch circuit in the third embodiment. Figure 5 As shown, in one embodiment, the first pull-up circuit 206 includes: a first transistor 306 and a second transistor 308, wherein the first end of the first transistor 206 is connected to the power supply voltage V1, wherein the power supply voltage V1 satisfies that when the first transistor 306 and the second transistor 308 are both turned on, the output terminal Q is at a high level, and when the first transistor 306 and the second transistor 308 are turned off, the output terminal Q is at a low level. The control end of the first transistor 306 is connected to the second output terminal 2; the first end of the second transistor 308 is connected to the second end of the first transistor 306, the control end of the second transistor 308 is connected to the first output terminal 1, and the second end of the second transistor 308 is the third end of the first pull-up circuit 206.

[0061] In one embodiment, the first transistor 306 is a first PMOS transistor, and the second transistor 308 is a first NMOS transistor. In this case, the source of the first PMOS transistor is the first end of the first transistor 306, the gate of the first PMOS transistor is the control end of the first transistor 306, and the drain of the first PMOS transistor is the second end of the first transistor 306; the drain of the first NMOS transistor is the first end of the second transistor 308, the gate of the first NMOS transistor is the control end of the second transistor 308, and the source of the first NMOS transistor is the second end of the second transistor 308.

[0062] like Figure 5 As shown, in one embodiment, the first pull-down circuit 208 includes: a third transistor 310 and a fourth transistor 312, the first end of the third transistor 310 is the third end of the first pull-down circuit 208, and the control end of the third transistor 310 is connected to the first output end 1; the first end of the fourth transistor 312 is connected to the second end of the third transistor 310, the control end of the fourth transistor 312 is connected to the second output end 2, and the second end of the fourth transistor 312 is grounded.

[0063] In one embodiment, the third transistor 310 is a second PMOS transistor, and the fourth transistor 312 is a second NMOS transistor. In this case, the source of the second PMOS transistor is the first end of the third transistor 310, the gate of the second PMOS transistor is the control end of the third transistor 310, and the drain of the second PMOS transistor is the second end of the third transistor 310; the drain of the second NMOS transistor is the first end of the fourth transistor 312, the gate of the second NMOS transistor is the control end of the fourth transistor 312, and the source of the second NMOS transistor is the second end of the fourth transistor 312.

[0064] Figure 6 FIG. 4 is a schematic diagram of a latch circuit in the fourth embodiment. Figure 6As shown, in one embodiment, the feedback control module 106 includes: a first feedback circuit 210 and a second feedback circuit 212, the first feedback circuit 210 is respectively connected to the output terminal 3, the second output terminal 2 and the first output terminal 1 of the output module 104, and is used to control the level state of the first output terminal 1 to the first level state according to the output signal Q and the second signal; the second feedback circuit 212 is respectively connected to the output terminal 3, the first output terminal 1 and the second output terminal 2 of the output module 104, and is used to control the level state of the second output terminal 2 to the second level state according to the output signal Q and the first signal. That is, the first feedback circuit 210 locks the level state of the first output terminal 1 to the first level state according to the output signal Q and the second signal, and the second feedback circuit 212 locks the level state of the second output terminal 2 to the second level state according to the output signal Q and the second signal, thereby achieving the purpose of resisting single-particle upset.

[0065] Figure 7 FIG. 5 is a schematic diagram of a latch circuit in the fifth embodiment. Figure 7 As shown, in one embodiment, the first feedback circuit 210 includes: a second pull-up circuit 314 and a second pull-down circuit 316, wherein the first end of the second pull-up circuit 314 is connected to the second output end 2, the second end of the second pull-up circuit 314 is connected to the output end 3 of the output module 104, and the third end of the second pull-up circuit 314 is connected to the first output end 1; the first end of the second pull-down circuit 316 is connected to the second output end 2, the second end of the second pull-down circuit 316 is connected to the output end 3 of the output module 104, and the third end of the second pull-down circuit 316 is connected to the first output end 1.

[0066] like Figure 7 As shown, in one embodiment, the second feedback circuit 212 includes: a third pull-up circuit 318 and a third pull-down circuit 320, wherein a first end of the third pull-up circuit 318 is connected to the first output end 1, a second end of the third pull-up circuit 318 is connected to the output end 3 of the output module 104, and a third end of the third pull-up circuit 318 is connected to the second output end 2; a first end of the third pull-down circuit 320 is connected to the first output end 1, a second end of the third pull-down circuit 320 is connected to the output end 3 of the output module 104, and a third end of the third pull-down circuit 320 is connected to the second output end 2.

[0067] Figure 8 FIG. 4 is a schematic diagram of a latch circuit in the sixth embodiment. Figure 8As shown, in one embodiment, the second pull-up circuit 314 includes: a fifth transistor 402 and a sixth transistor 404, wherein the first end of the fifth transistor 402 is connected to the power supply voltage V2, wherein the power supply voltage V2 satisfies that when the fifth transistor 402 and the sixth transistor 404 are both turned on, the first output terminal 1 is locked to a high level state, and when the fifth transistor 402 and the sixth transistor 404 are turned off, the first output terminal 1 is locked to a low level state. The control end of the fifth transistor 402 is connected to the second output terminal 2; the first end of the sixth transistor 404 is connected to the second end of the fifth transistor 402, the control end of the sixth transistor 404 is connected to the output terminal 3 of the output module 104, and the second end of the sixth transistor 404 is connected to the first output terminal 1.

[0068] In one embodiment, the fifth transistor 402 is a third PMOS tube, and the sixth transistor 404 is a third NMOS tube. In this case, the source of the third PMOS tube is the first end of the fifth transistor 402, the gate of the third PMOS tube is the control end of the fifth transistor 402, and the drain of the third PMOS tube is the second end of the fifth transistor 402; the drain of the third NMOS tube is the first end of the sixth transistor 404, the gate of the third NMOS tube is the control end of the sixth transistor 404, and the source of the third NMOS tube is the second end of the sixth transistor 404.

[0069] like Figure 8 As shown, in one embodiment, the second pull-down circuit 316 includes: a seventh transistor 406 and an eighth transistor 408, wherein the first end of the seventh transistor 406 is connected to the first output end 1, and the control end of the seventh transistor 406 is connected to the output end 3 of the output module 104; the first end of the eighth transistor 408 is connected to the second end of the seventh transistor 406, the control end of the eighth transistor 408 is connected to the second output end 2, and the second end of the eighth transistor 408 is grounded.

[0070] In one embodiment, the seventh transistor 406 is a fourth PMOS tube, and the eighth transistor 408 is a fourth NMOS tube. In this case, the source of the fourth PMOS tube is the first end of the seventh transistor 406, the gate of the fourth PMOS tube is the control end of the seventh transistor 406, and the drain of the fourth PMOS tube is the second end of the seventh transistor 406; the drain of the fourth NMOS tube is the first end of the eighth transistor 408, the gate of the fourth NMOS tube is the control end of the eighth transistor 408, and the source of the fourth NMOS tube is the second end of the eighth transistor 408.

[0071] like Figure 8As shown, in one embodiment, the third pull-up circuit 318 includes: a ninth transistor 410 and a tenth transistor 412, wherein the first end of the ninth transistor 410 is connected to the power supply voltage V3, wherein the power supply voltage V3 satisfies that when the ninth transistor 410 and the tenth transistor 412 are both turned on, the second output terminal 2 is locked to a high level state, and when the ninth transistor 410 and the tenth transistor 412 are turned off, the second output terminal 2 is locked to a low level state. The control end of the ninth transistor 410 is connected to the output terminal 3 of the output module 104; the first end of the tenth transistor 412 is connected to the second end of the ninth transistor 410, the control end of the tenth transistor 412 is connected to the first output terminal 1, and the second end of the tenth transistor 412 is connected to the second output terminal 2.

[0072] In one embodiment, the ninth transistor 410 is a fourth PMOS tube, and the ninth transistor 410 is a fifth PMOS tube. At this time, the source of the fourth PMOS tube is the first end of the ninth transistor 410, the gate of the fourth PMOS tube is the control end of the ninth transistor 410, and the drain of the fourth PMOS tube is the second end of the ninth transistor 410; the source of the fifth PMOS tube is the first end of the tenth transistor 412, the gate of the fifth PMOS tube is the control end of the tenth transistor 412, and the drain of the fifth PMOS tube is the second end of the tenth transistor 412.

[0073] like Figure 8 As shown, in one embodiment, the third pull-down circuit 320 includes: an eleventh transistor 414 and a twelfth transistor 416, the first end of the eleventh transistor 414 is connected to the second output end 2, and the control end of the eleventh transistor 414 is connected to the first output end 1; the first end of the twelfth transistor 416 is connected to the second end of the eleventh transistor 414, the control end of the twelfth transistor 416 is connected to the output end 3 of the output module 104, and the second end of the twelfth transistor 416 is grounded.

[0074] In one embodiment, the eleventh transistor 414 is a fifth NMOS tube, and the twelfth transistor 416 is a sixth NMOS tube. In this case, the drain of the fifth NMOS tube is the first end of the eleventh transistor 414, the gate of the fifth NMOS tube is the control end of the eleventh transistor 414, and the source of the fifth NMOS tube is the second end of the eleventh transistor 414; the drain of the sixth NMOS tube is the first end of the twelfth transistor 416, the gate of the sixth NMOS tube is the control end of the twelfth transistor 416, and the source of the sixth NMOS tube is the second end of the twelfth transistor 416.

[0075] The following Figure 8Take as an example to illustrate the working process of the latch circuit. When CLK=“1” and CLKB=“0”, the latch circuit of the present invention is in a transparent state, the first transmission gate and the second transmission gate 302 are in a conducting state, the logic values ​​(level states) of the first signal at the first output terminal 1 and the second signal at the second output terminal 2 are a set of complementary signals (high level state and low level state, respectively), the first signal and the second signal directly act on the output module 104, and transmit the input signal D to the output terminal 3 of the output module 104, so as to obtain the output signal Q. At this time, only the pull-up circuit or the pull-down circuit is turned on in the first feedback circuit 210 and the second feedback circuit 212, that is, one of the first feedback circuit 210 and the second feedback circuit 212 is a pull-up circuit turned on, and the other is a pull-down circuit turned on. In order to prevent the influence of the outside world on the first output terminal 1 and the second output terminal 2, there is no path directly from the power supply (V2, V3) to the ground, and at the same time, the purpose of reducing the overall power consumption of the latch circuit can be achieved. When CLK=“0” and CLKB=“1”, the latch circuit of the present invention is in a latched state, the first transmission gate and the second transmission gate 302 are turned off, the first output terminal 1 and the second output terminal 2 are disconnected from the input signal D, and since a cross feedback loop is formed between the output terminal 3 of the output module 104 and the first output terminal 1 and the second output terminal 2 through the first feedback circuit 210 and the second feedback circuit 212, the first output terminal 1 and the second output terminal 2 continue to maintain the previous level state, and the output signal Q of the output terminal 3 of the output module 104 is determined by the output module 104. The principle of the latch circuit of the present invention to resist single particle upset is as follows:

[0076] When the logic value latched by the latch circuit is "1" (the input signal D is at a high level), that is, the logic value of the first output terminal 1 is "1" (the level state of the first output terminal 1 is at a high level) and the logic value of the second output terminal 2 is "0" (the level state of the second output terminal 2 is at a low level), the logic value of the output terminal 3 of the output module 104 is "1". If a single-particle flip occurs at the first output terminal 1, that is, the logic state of the first output terminal 1 changes from "1" to "0", due to the time delay of the logic state, the change in the logic state of the first output terminal 1 does not affect the logic state of the output terminal 3, the fifth transistor 402 and the sixth transistor 404 are turned on, and the connection point between the first feedback circuit 210 and the first output terminal 1 is pulled up to the logic value "1". Therefore, the logic state of the first output terminal 1 is also restored to "1", eliminating the influence of the single-particle flip at the first output terminal 1.

[0077] Similarly, when the logic value latched by the latch circuit is "1", that is, the logic value of the first output terminal 1 is "1" and the logic value of the second output terminal 2 is "0", the logic value of the output terminal 3 of the output module 104 is "1". If a single-particle flip occurs at the second output terminal 2, that is, the logic state of the second output terminal 2 changes from "0" to "1", the logic value of the output terminal 3 is "1", the eleventh transistor 414 and the twelfth transistor 416 are turned on, and the connection point between the second feedback circuit 212 and the second output terminal 2 is pulled down to the logic value "0". Therefore, the logic state of the second output terminal 2 is also restored to "0", eliminating the influence of the single-particle flip at the second output terminal 2.

[0078] When the logic value latched by the latch circuit is "0", that is, the logic value of the first output terminal 1 is "0" and the logic value of the second output terminal 2 is "1", the logic value of the output terminal 3 of the output module 104 is "0". If a single-particle flip occurs at the first output terminal 1, that is, the logic state of the first output terminal 1 changes from "0" to "1", at this time, the logic value of the output terminal 3 of the output module 104 is "0", the seventh transistor 406 and the eighth transistor 408 are turned on, and the connection point between the first feedback circuit 210 and the first output terminal 1 is pulled down to the logic value "0". Therefore, the logic state of the first output terminal 1 is also restored to "0".

[0079] When the logic value latched by the latch circuit is "0", that is, the logic value of the first output terminal 1 is "0" and the logic value of the second output terminal 2 is "1", the logic value of the output terminal 3 of the output module 104 is "0". If a single-particle flip occurs at the second output terminal 2, that is, the logic state of the second output terminal 2 changes from "1" to "0", the logic value of the output terminal 3 of the output module 104 is "0", the ninth transistor 410 and the tenth transistor 412 are turned on, and the connection point between the second feedback circuit 212 and the second output terminal 2 is pulled up to the logic value "1". Therefore, the logic state of the second output terminal 2 is also restored to "1".

[0080] When a single-particle upset occurs at the output terminal 3 of the output module 104, since the logic states of the first output terminal 1 and the second output terminal 2 are determined, the logic value of the output terminal 3 will also remain in the correct state through the output module 104. The function of resisting single-particle upsets at each node inside the latch circuit can be fully realized, and the circuit structure is simple, which can effectively reduce power consumption, delay and area overhead.

[0081] The present application also provides an electronic device, comprising any latch circuit described above.

[0082] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0083] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0084] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A latch circuit, characterized in that: include: A transmission module, comprising a first output end and a second output end, wherein the first output end is used to output a first signal in a first level state according to an input signal, and the second output end is used to output a second signal in a second level state according to the input signal, wherein the first level state and the second level state are different; an output module, connected to the first output terminal and the second output terminal respectively, and configured to generate an output signal according to the first signal and the second signal; a feedback control module, connected to the output end of the output module, the first output end, and the second output end, respectively, and configured to control the level state of the first output end to be the first level state, and control the level state of the second output end to be the second level state according to the output signal, the first signal, and the second signal; The feedback control module comprises: A first feedback circuit is connected to the output end of the output module, the second output end and the first output end respectively, and is used to control the level state of the first output end to be the first level state according to the output signal and the second signal; The second feedback circuit is connected to the output end of the output module, the first output end and the second output end respectively, and is used to control the level state of the second output end to be the second level state according to the output signal and the first signal.

2. The latch circuit according to claim 1, characterized in that: The transmission module comprises: a first transmission circuit, wherein an input end of the first transmission circuit is used to receive the input signal, and an output end of the first transmission circuit is the first output end, which is used to output a first signal in a first level state according to the input signal under the control of a control signal; A second transmission circuit, wherein the input end of the second transmission circuit is used to receive the input signal, and the output end of the second transmission circuit is the second output end, which is used to output a second signal in a second level state according to the input signal under the control of a control signal.

3. The latch circuit according to claim 2, characterized in that: The first transmission circuit comprises: A first transmission gate, wherein an input end of the first transmission gate is used to receive the input signal, a controlled end of the first transmission gate is used to receive the control signal, and an output end of the first transmission gate is the first output end.

4. The latch circuit according to claim 2, characterized in that: The second transmission circuit comprises: a second transmission gate, wherein an input end of the second transmission gate is used to receive the input signal, and a controlled end of the second transmission gate is used to receive the control signal; An inverter, wherein an input end of the inverter is connected to an output end of the second transmission gate, and an output end of the inverter is the second output end.

5. The latch circuit according to claim 1, wherein: The output module comprises: a first pull-up circuit, wherein a first end of the first pull-up circuit is connected to the first output end, and a second end of the first pull-up circuit is connected to the second output end; A first pull-down circuit, wherein a first end of the first pull-down circuit is connected to the first output end, a second end of the first pull-down circuit is connected to the second output end, and a third end of the first pull-down circuit is connected to a third end of the first pull-up circuit to jointly output the output signal.

6. The latch circuit according to claim 5, characterized in that: The first pull-up circuit comprises: a first transistor, wherein a first terminal of the first transistor is connected to a power supply voltage, and a control terminal of the first transistor is connected to the second output terminal; A second transistor, wherein a first end of the second transistor is connected to a second end of the first transistor, a control end of the second transistor is connected to the first output end, and a second end of the second transistor is a third end of the first pull-up circuit.

7. The latch circuit according to claim 5, characterized in that: The first pull-down circuit comprises: a third transistor, wherein a first end of the third transistor is a third end of the first pull-down circuit, and a control end of the third transistor is connected to the first output end; a fourth transistor, wherein a first terminal of the fourth transistor is connected to the second terminal of the third transistor, a control terminal of the fourth transistor is connected to the second output terminal, and a second terminal of the fourth transistor is grounded.

8. The latch circuit according to claim 1, wherein: The first feedback circuit comprises: a second pull-up circuit, wherein a first end of the second pull-up circuit is connected to the second output end, a second end of the second pull-up circuit is connected to the output end of the output module, and a third end of the second pull-up circuit is connected to the first output end; A second pull-down circuit, wherein a first end of the second pull-down circuit is connected to the second output end, a second end of the second pull-down circuit is connected to the output end of the output module, and a third end of the second pull-down circuit is connected to the first output end.

9. The latch circuit according to claim 1, wherein: The second feedback circuit comprises: a third pull-up circuit, wherein a first end of the third pull-up circuit is connected to the first output end, a second end of the third pull-up circuit is connected to the output end of the output module, and a third end of the third pull-up circuit is connected to the second output end; A third pull-down circuit, wherein a first end of the third pull-down circuit is connected to the first output end, a second end of the third pull-down circuit is connected to the output end of the output module, and a third end of the third pull-down circuit is connected to the second output end.

10. The latch circuit according to claim 8, characterized in that: The second pull-up circuit comprises: a fifth transistor, wherein a first terminal of the fifth transistor is connected to a power supply voltage, and a control terminal of the fifth transistor is connected to the second output terminal; A sixth transistor, wherein a first end of the sixth transistor is connected to the second end of the fifth transistor, a control end of the sixth transistor is connected to the output end of the output module, and a second end of the sixth transistor is connected to the first output end.

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