Configurable gated cell, configurable track-and-hold circuit, and phase interpolating frequency divider

Abstract

The present application relates to the technical field of control circuit, and an embodiment thereof provides a configurable gating unit, a configurable track-and-hold circuit and a phase interpolation frequency divider, wherein the configurable gating unit comprises N D flip-flops, an adder, a comparator and a phase detector; the N D flip-flops are used for outputting triggered states respectively in response to N phase-different reference clocks; the adder is used for counting the number of D flip-flops in the N D flip-flops that meet preset states, wherein the preset states include high-level states or low-level states; the comparator is used for outputting corresponding level signals according to the size relationship between the number counted by the adder and a preset value; and the phase detector is used for outputting corresponding level signals according to the phase relationship between the output level signals of the comparator and feedback signals. The embodiment provided by the present application can suppress the generation of glitches in the output signals according to the dynamically selected delay time.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of control circuit, in particular to a configurable gating unit, a configurable track-and-hold circuit and a phase interpolation frequency divider. BACKGROUND

[0002] The phase interpolation frequency divider based on phase switching technology can effectively suppress the quantization noise of the PLL by reducing the frequency division step. However, due to the PVT (Process Voltage Temperature) fluctuation, the existing phase interpolation frequency divider has two problems: 1) the output clock phase is prone to drift. The traditional PI frequency divider is easily affected by the nonlinear factors in the circuit, which causes the output clock phase to deviate, resulting in weakening of the quantization noise suppression effect; 2) the phase switching timing is difficult to control. In the phase switching process of the traditional PI frequency divider, glitches are easily generated. The fixed delay generated by the track-and-hold circuit can eliminate the glitches, but it is easily affected by the PVT fluctuation, resulting in that the glitches cannot be completely eliminated, and the subsequent frequency divider has functional errors.

[0003] The existing technical problems include: (1) the output clock phase is prone to drift in the prior art. The traditional PI frequency divider is easily affected by the nonlinear factors in the circuit, which causes the output clock phase to deviate, resulting in weakening of the quantization noise suppression effect; (2) the phase switching timing is difficult to control in the prior art. In the phase switching process of the traditional PI frequency divider, glitches are easily generated. The fixed delay generated by the track-and-hold circuit can eliminate the glitches, but it is easily affected by the PVT fluctuation, resulting in that the glitches cannot be completely eliminated, and the subsequent frequency divider has functional errors. SUMMARY

[0004] The purpose of the embodiments of the present application is to provide a configurable gating unit, a configurable track-and-hold circuit and a phase interpolation frequency divider, which can realize different delays according to the requirements, eliminate switching glitches, and ensure that the clock phase output by the phase interpolation frequency divider can be normally switched under different PVT conditions.

[0005] In order to achieve the above-mentioned purpose, the first aspect of the present application provides a configurable gating unit, comprising: an adder, a comparator, a phase detector and N D flip-flops;

[0006] The D flip-flop is used to output the triggered state in response to the input reference clock; the adder is used to count the number of D flip-flops in the N D flip-flops that meet the preset state, and the preset state includes the high level state or the low level state; the comparator is used to output the corresponding level signal according to the size relationship between the number counted by the adder and the preset value; and the phase detector is used to output the corresponding level signal according to the phase relationship between the output level signal of the comparator and the feedback signal.

[0007] Preferably, the configurable gating unit further comprises a mapping unit; the mapping unit is used to map the input phase information into corresponding level value as the preset value input into the comparator.

[0008] Preferably, the input phase information is related to the input signal of the feedback end of the configurable gating unit.

[0009] Preferably, the Q ends of the N D flip-flops are connected with the input end of the adder; the output end of the adder is connected with the first input end of the comparator; the output end of the comparator is connected with the first input end of the phase detector; the second input end of the phase detector is connected with the feedback end of the configurable gating unit; the output end of the phase detector is used as the output end of the configurable gating unit; the clock ends of the N D flip-flops are used to input N phase different reference clocks; the reset ends of the N D flip-flops are connected with the feedback end of the configurable gating unit; the enable ends of the adder and the N D flip-flops are connected with the output end of the configurable gating unit through inverters

[0010] Preferably, the output end of the adder is connected with the first input end of the comparator through a truncator; the truncator is used to cut a preset number of bits from the highest bit of the output signal of the adder and input into the first input end of the comparator.

[0011] Preferably, the number of bits of the phase information when adopting binary representation is the same as the preset number of bits.

[0012] Preferably, the phases of the N phase different reference clocks are equally spaced by 360° / N.

[0013] In the second aspect of the present application, a configurable track and hold circuit is further provided, comprising: the foregoing configurable gating unit, a controlled switch and a holding capacitor; the output end of the configurable gating unit is connected with the control end of the controlled switch, and the feedback end of the configurable gating unit is connected with the first control end of the controlled switch; one end of the holding capacitor is connected with the first control end of the controlled switch, and the other end is grounded.

[0014] In a third aspect of the invention, a phase interpolation frequency divider is also provided, comprising: the aforementioned configurable track-and-hold circuit, a phase interpolator, and a phase switching controller; the phase switching controller generates phase information to control the phase interpolator to generate an output signal corresponding to the phase information; the phase information is also used as input to a mapping unit in the configurable gating unit; the configurable gating unit and the input of the phase interpolator share N reference clocks with different phases; the output terminal of the configurable gating unit is connected to the control terminal of the controlled switch, and the feedback terminal of the configurable gating unit is connected to the first controlled terminal of the controlled switch; the second controlled terminal of the controlled switch is connected to the output terminal of the phase interpolator, and one end of the holding capacitor is connected to the first controlled terminal of the controlled switch, and the other end is grounded.

[0015] Preferably, the phase interpolation frequency divider is applied in a phase-locked loop circuit.

[0016] The above technical solution has the following beneficial effects:

[0017] (1) The configurable gating unit can generate corresponding control signals according to the required switching phase distance and provide them to the controlled switch, thereby completing the seamless phase switching at a long distance, avoiding switching glitches, and speeding up the phase switching time.

[0018] (2) A phase switching controller with configurable gated units is adopted to achieve a wider delay range. The delay time is dynamically selected according to the circuit state to suppress the generation of glitches during phase switching. A phase interpolation divider with configurable gated units is adopted to enhance the PVT robustness of the phase interpolation divider.

[0019] Other features and advantages of the embodiments of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0020] The accompanying drawings are provided to further illustrate embodiments of the present invention and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings:

[0021] Figure 1 A schematic diagram of the structure of a configurable gating unit according to an embodiment of the present invention is shown.

[0022] Figure 2 The schematic diagram illustrates the circuit connection of a configurable gating unit according to an embodiment of the present invention;

[0023] Figure 3 A timing diagram of a configurable gating unit according to an embodiment of the present invention is shown schematically;

[0024] Figure 4 The diagram illustrates the relationship between the duration of the hold signal and the control signal SW in a tracking and holding circuit according to an embodiment of the present invention.

[0025] Figure 5 This schematic diagram illustrates an application of a track-and-hold circuit in the prior art.

[0026] Figure 6 A schematic diagram of the phase interpolation frequency divider according to an embodiment of the present invention is shown.

[0027] Figure 7 The diagram shows three types of glitch waveforms during the phase switching process from state 1 to state 2.

[0028] Figure 8 The diagram schematically illustrates the simulation results of the phase interpolation frequency divider according to an embodiment of the present invention during the phase switching process;

[0029] Figure 9 The schematic diagram illustrates a phase interpolation frequency divider according to an embodiment of the present invention applied to a Ring-VCO-based phase-locked loop.

[0030] Figure 10 The schematic illustration shows the output spectrum simulation results of the phase interpolation divider according to an embodiment of the present invention applied to a Ring-VCO-based phase-locked loop. Detailed Implementation

[0031] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the scope of the present invention.

[0032] Figure 1 A schematic diagram illustrating the structure of a configurable gating unit according to an embodiment of the present invention is shown. Figure 1 As shown, this embodiment provides a configurable gating unit, including: an adder, a comparator, a phase detector, and N D flip-flops; the D flip-flops are used to respond to an input reference clock and output a triggered state; the adder is used to count the number of D flip-flops among the N D flip-flops that meet a preset state, the preset state including a high-level state or a low-level state; the comparator is used to output a corresponding level signal according to the relationship between the number counted by the adder and a preset value; the phase detector is used to output a corresponding level signal according to the phase relationship between the output level signal of the comparator and the feedback signal.

[0033] In the above embodiments, by using the functions of level triggering or edge triggering of the D flip-flop, under the triggering of the reference clock, the D flip-flop is in one of the two stable trigger states "0" and "1", and the trigger state is output through the output pin Q and The adder and the comparator present the corresponding trigger state over time as the reference clock changes. The adder and the comparator can be implemented by using devices with logic operations, such as a single-chip microcomputer, a microprocessor, etc., can be implemented by using two separate logic devices, or can be implemented by using codes corresponding to the functions in the same logic device. The adder and the comparator can also be implemented by using electronic elements or electronic circuits corresponding to the functions.

[0034] Through the above circuit structure, when the phase of the feedback signal is switched, a certain time length of high level or low level can be generated according to the phases of the N-way reference clock, the phase of the feedback signal, and the preset value, so as to suppress the glitches in the feedback signal. The certain time length is related to the preset value, that is, the preset value is used to control the certain time length. The preset value of the comparator is configurable, which includes setting the input level of one of the input pins of the comparator as the reference level, or setting the preset value as the comparison reference in the logic device.

[0035] As shown in FIG. 1, in an embodiment provided by the present application, the configurable gating unit further includes a mapping unit; the mapping unit is used to map the input phase information into a corresponding level value as the preset value input to the comparator. Figure 1 When the signal required as the comparison reference is related parameter information, such as phase information, the different related parameters need to be corresponded to different level values. For example, the common expression form of the phase information is expressed in degrees or several bits, and when the input phase information is one of 16 possible phases, one of the input level values of the comparator after the mapping unit is one of the 16 quantized level values.

[0036] In an embodiment provided by the present application, the input phase information is related to the input signal of the feedback end of the configurable gating unit. The present embodiment provides a negative feedback method applied to the phase adjustment scene. When the phase information of the input signal of the feedback end is used as the preset value of the comparator to participate in the comparison, the level signal output by the comparator and the phase information of the feedback signal can form a certain correlation, which is reflected in the starting time and the duration of the level signal output by the phase detector. Through the above embodiment, by using the output signal as the feedback signal, different time delays can be achieved according to the requirements, the switching glitches of the output signal are eliminated, and the output quality of the output signal is improved.

[0037] Figure 2 The circuit connection diagram of the configurable gating unit according to the embodiment of the present application is shown schematically. As shown in the figure, Figure 2 the connection relationship between the above devices is provided in the embodiment, which is specifically as follows: the Q terminals of the N D flip-flops are connected with the input terminal of the adder; the output terminal of the adder is connected with the first input terminal of the comparator; the output terminal of the comparator is connected with the first input terminal of the phase detector; the second input terminal of the phase detector is connected with the feedback terminal of the configurable gating unit; the output terminal of the phase detector serves as the output terminal of the configurable gating unit; the clock terminals of the N D flip-flops are used for inputting N-phase reference clocks different in phase; the reset terminals of the N D flip-flops are connected with the feedback terminal of the configurable gating unit; the enable terminals of the adder and the N D flip-flops are connected with the output terminal of the configurable gating unit through inverters.

[0038] The working flow of the configurable gating unit circuit provided in the embodiment is as follows: the left N D flip-flops receive N-phase reference clocks, where the number of N is 8, and the reference clocks can be generated by, for example, a phase interpolator (PI). The phase of each phase clock is equally spaced at 360° / 8. When the rising edge of the reset signal rst of the D flip-flop comes, the D flip-flop is reset, the Q terminal outputs “0”, the adder is reset, at this time, it also outputs “0”, and the enable signal en is switched from “0” to “1”. The reset signal rst is from the input of the feedback terminal, which can be, for example, the feedback from the output terminal of a frequency divider, denoted as FOUT. The output signal cnt of the adder is increased by 1 every 1 / 8TDIV. The comparator is used for comparing the output signal cnt of the adder and the output signal cmp of the mapping unit. The relationship between the high two bits acc<4:3> of the adder output and the cmp signal is cmp=2·acc<4:3>. The working logic of the comparator is: if cnt is greater than cmp, the output signal Cout of the adder is switched to logic “1”, and the enable signal en is switched to logic “0”. The phase detector is composed of two D flip-flops and an AND gate. When the rising edge of FOUT comes, the enable signal en signal is set to “1”, and the output signal sw is set to “0” and kept all the time. When the rising edge of the Cout signal comes, the output of the flip-flop connected with Cout is set to “1”, so that the output of the AND gate is “1”, and since the output of the AND gate is connected with the rst reset terminal of the D flip-flop, the en signal is set to “0”, and the corresponding sw signal is set to “1”, thereby the generation of the sw signal is completed. When the next rising edge of FOUT comes, the above working flow and timing sequence are repeated. Figure 3 The timing diagram of the configurable gating unit according to the embodiment of the present application is shown schematically. As shown in the figure, Figure 3As shown, the timing of FOUT, en, cnt and Cout presents the relationship in the figure. By using this configurable track-and-hold method, glitches in various phase switching processes can be eliminated.

[0039] In an embodiment of the present application, the output of the adder is connected to the first input of the comparator through a truncator; the truncator is used to truncate a preset number of bits from the highest bit of the output signal of the adder and input to the first input of the comparator. A programmable gate (PG) unit generates a control signal SW of the gate switch according to the high two bits of the output signal acc<4:0> of the adder. Figure 4 The relationship between the duration of the hold signal and the control signal SW in the track-and-hold circuit according to an embodiment of the present application is schematically shown. As shown, Figure 4 As shown, the low level width of the SW signal generated by the configurable gate unit in the embodiment is determined according to the phase distance to be switched by the circuit. If the two phases before and after the switching are the most different (i.e. the phase distance is the largest), the highest bit of the adder is "11" at this time, and the PG unit generates a low level of 7T / 8 width; on the contrary, the PG unit generates a low level of T / 8 width. Wherein, <4:0> is a representation method of the bus, indicating that acc is composed of 5 bits, which are acc<5> to acc<0> respectively.

[0040] In an embodiment of the present application, the number of bits of the phase information when using binary representation is the same as the preset number of bits. For example, when the D flip-flop is 8, the output state of the adder is 8, and when the preset number of bits is 2 bits, the possible combinations of the high two bits are "11", "10", "01" and "00". At this time, the input phase information is acc<4:3>, which is also a two-bit signal. In another embodiment, when a 16-way clock is used for switching for the reference clock, the bit width of the 2-bit signal of acc<4:3> in the foregoing example needs to be increased to 3 bits, and the corresponding preset number of bits should also be 3 bits.

[0041] Figure 5 The application schematic diagram of the track-and-hold circuit in the prior art is schematically shown, and Figure 6 The structure schematic diagram of the phase interpolation frequency divider according to an embodiment of the present application is schematically shown. By comparing the two diagrams, the improvement of the present application relative to the prior art phase interpolation frequency divider is that a configurable gate unit in Figure 6 is added. As shown, Figure 6As shown, it provides a configurable track and hold (T&H) circuit, comprising: the aforementioned configurable gating unit, a controlled switch and a holding capacitor; the output end of the configurable gating unit is connected to the control end of the controlled switch, and the feedback end of the configurable gating unit is connected to the first controlled end of the controlled switch; one end of the holding capacitor is connected to the first controlled end of the controlled switch, and the other end is grounded. The T&H circuit is used to keep the voltage level of the phase interpolator output constant during phase switching. When the controlled switch is turned on, the output of the phase interpolator is fed to the next stage frequency divider. The configurable T&H circuit provided by the embodiment of the present application can eliminate glitches in specific phase switching conditions without occupying too much area and power consumption. At the same time, the following problems existing in the prior art T&H circuit are overcome: since the pulse width generated by the prior art T&H circuit cannot be adjusted, when PVT (Process, Voltage, Temperature) fluctuates, glitches cannot be effectively eliminated in far phase switching conditions, thereby causing functional errors.

[0042] Figure 7 Three glitch waveform diagrams during phase switching from state 1 to state 2 are shown. As shown in Figure 7 , state 1 is the clock before phase switching, state 2 is the clock after phase switching, "output" in the figure is the actual output clock of the circuit, and "track and hold" is a sampling switch control signal. The low level of "track and hold" indicates that the "output" continuously maintains a high level, and the high level indicates that it is not maintained. Case 1: the holding time holding window just lasts until the rising edge of the clock after switching comes, and no glitch is generated, which is an ideal case; case 2: the holding time holding window lasts for a short time and ends before the rising edge of the clock after switching comes, and a glitch is generated; case 3: the holding time holding window lasts for a long time, and no glitch is generated. Since the actual working environment, different working temperatures and power supply voltage fluctuations will cause jitter to the clock edges of state 1 and 2, the fixed delay structure adopted in the traditional phase interpolation frequency divider can only provide a fixed delay (as shown in Figure 7 , "hold"), and the jump between the above state 1, 2 and 3 is easy to occur, and it is difficult to ensure the robustness of the phase interpolation circuit, and the circuit still faces the risk of glitch (as Figure 7The configurable switch delay circuit provides adjustable delay in a certain range, compensates the clock edge jitter of state 1 and state 2 caused by PVT, enhances the robustness of the phase interpolation frequency divider circuit, and has a certain adjustable delay range, so as to support more bit phase interpolation frequency divider circuit, such as 32-phase clock, 64-phase clock, etc. As the number of clock phases increases, the phase step decreases, so that the effect of suppressing quantization noise can be achieved, thereby improving the phase noise performance of the entire phase-locked loop circuit.

[0043] In an embodiment provided by the application, the phase interpolation frequency divider comprises the configurable track-and-hold circuit, the phase interpolator and the phase switching controller provided in the foregoing embodiment; and the connection mode can refer to Figure 6 The phase switching controller generates phase information for controlling the phase interpolator to generate an output signal corresponding to the phase information; the phase information is also input to the mapping unit in the configurable gate unit; the configurable gate unit shares N-phase different reference clocks with the input of the phase interpolator; the output end of the configurable gate unit is connected to the control end of the controlled switch, and the feedback end of the configurable gate unit is connected to the first control end of the controlled switch; the second control end of the controlled switch is connected to the output end of the phase interpolator, and one end of the hold capacitor is connected to the first control end of the controlled switch, and the other end is connected to the ground.

[0044] Wherein the FIN end is connected to the phase interpolator and the configurable gate unit, the FIN is an input signal, the output end of the phase interpolator is connected to the controlled switch, which is an input signal of the controlled switch, one end of the hold capacitor is connected to the output end of the switch, and the other end is connected to the ground, the FOUT is an output signal, and simultaneously as a feedback input signal input to the configurable gate unit and the phase switching controller, the NPI is connected to the phase switching controller, which is an input signal, the output end of the phase switching controller is connected to the phase interpolator, the output acc<4:3> of the phase switching controller is connected to the configurable gate unit, the output sw of the configurable gate unit is connected to the controlled switch, and is a control signal. The programmable gate (PG) unit generates the control signal SW of the gate switch according to the high two bits of the adder output signal acc<4:0>.

[0045] Figure 8 The signal simulation comparison results of the phase interpolation frequency divider provided by the embodiment of the application in the phase switching process are shown. As Figure 8As shown, when the tracking hold circuit of the prior art is adopted, the phase interpolation divider generates glitches during phase switching; when the configurable tracking hold circuit of the present application is adopted, the phase interpolation divider does not generate glitches during phase switching; when the phase switching distance is changed, the configurable tracking hold circuit of the present application can dynamically adjust the SW pulse width, and always keeps no glitches generated.

[0046] Figure 9 The structure schematic diagram of the phase interpolation divider according to the embodiment of the present application applied to the Ring-VCO-based phase-locked loop is schematically shown. As shown in Figure 9 As shown, in the phase-locked loop circuit provided by the embodiment, in particular, the fractional charge pump type phase-locked loop (PLL) based on Ring-VCO, it comprises a phase frequency detector (PFD), a charge pump (CP), a low pass filter (LPF), a voltage controlled oscillator (VCO), a phase interpolation divider (PIDIV), and a sigma delta modulator (SDM). The phase frequency detector completes the detection of the phase error between the feedback clock and the reference clock, and converts the phase error into a voltage signal with different pulse widths; the charge pump charges or discharges the low pass filter according to the phase detection result output by the phase frequency detector; the low pass filter filters out high-frequency current and converts the current into voltage; the voltage controlled oscillator is controlled by the voltage VC output by the low pass filter, and outputs an oscillation signal with a corresponding frequency; the phase interpolation divider divides the output signal of the voltage controlled oscillator by N.f according to the preset frequency division ratio. After several times of negative feedback, the edges of the feedback clock DIV and the reference clock CLK are aligned, and the phase-locked loop completes locking. The voltage controlled oscillator outputs an oscillation signal with a desired frequency. The sigma delta modulator is used to generate a fractional frequency division ratio according to the input fractional frequency division ratio control word frac. The fractional frequency division ratio frac. and the integer frequency division ratio N are added by an adder to obtain the frequency division ratio control word of the phase interpolation divider.

[0047] Figure 10 The output spectrum simulation result of the phase interpolation divider applied to the Ring-VCO-based phase-locked loop is shown. As shown in Figure 10 As shown, when the output frequency point is 440MHz, the output spectrum purity of the phase-locked loop is good, the frequency division ratio step is reduced from 1 to 1 / 32, and 30dB quantization noise suppression improvement is brought.

[0048] Through the above circuit structure, tracking hold circuit, phase interpolation frequency divider or phase-locked loop circuit in the multiple embodiments based on the same inventive concept, the spurs can be effectively eliminated, and the robustness in phase switching is improved.

[0049] Those skilled in the art will understand that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage, etc.) containing computer-usable program code.

[0050] The present application is described with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, as well as combinations of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing apparatus to produce a machine, so that the instructions, which are executed via the processor of the computer or other programmable data processing apparatus, generate a means for implementing the functions specified in the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus that carries out the functions specified in one or more flows and / or blocks.

[0051] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including instruction apparatus, which implements the functions specified in the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus that carries out the functions specified in one or more flows and / or blocks.

[0052] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus, so that a series of operation steps are performed on the computer or other programmable data processing apparatus to produce a computer-implemented process, so that the instructions executed on the computer or other programmable data processing apparatus provide a process for implementing the functions specified in the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus that carries out the functions specified in one or more flows and / or blocks.

[0053] In a typical configuration, the computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memories.

[0054] Memory can include non-persistent memory, Random Access Memory (RAM), and / or non-volatile memory, such as read only memory (ROM) or flash memory, in a computer readable medium. Memory is an example of computer readable media.

[0055] Computer readable media includes permanent and non-permanent, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read only memory (ROM), electrically erasable programmable read only memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital versatile disc (DVD), or other optical storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information accessible to a computing device. According to the definition herein, computer readable media does not include transitory media, such as modulated data signals and carrier waves.

[0056] It should also be noted that the terms "comprising", "containing", or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or apparatus that comprises a list of elements does not include only those elements in the list, but can also include other elements not expressly listed or inherent to such process, method, article or apparatus. Without further limitation, an element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article or apparatus that includes the element.

[0057] The above merely provides an example of the present application and is not intended to limit the present application. The present application can have various modifications and changes for those skilled in the art. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application shall be included in the scope of claims of the present application.

Claims

1. A configurable gating unit, comprising: The configurable tracking hold circuit comprises: an adder, a comparator, a phase discriminator and N D flip-flops; the D flip-flops are configured to output triggered states in response to an input reference clock; the adder is configured to count the number of D flip-flops in the N D flip-flops that meet a preset state, the preset state comprising a high level state or a low level state; the comparator is configured to output a corresponding level signal according to the size relationship between the number of D flip-flops that meet the preset state counted by the adder and a preset value; the phase discriminator is configured to output a corresponding level signal according to the phase relationship between the level signal output by the comparator and a feedback signal; the Q terminals of the N D flip-flops are connected to the input terminal of the adder; the output terminal of the adder is connected to the first input terminal of the comparator; the output terminal of the comparator is connected to the first input terminal of the phase discriminator; the second input terminal of the phase discriminator is connected to the feedback terminal of the configurable gating unit; the output terminal of the phase discriminator serves as the output terminal of the configurable gating unit; the clock terminals of the N D flip-flops are configured to input N-phase different reference clocks; the reset terminals of the N D flip-flops are connected to the feedback terminal of the configurable gating unit; the enable terminals of the adder and the N D flip-flops are connected to the output terminal of the configurable gating unit through inverters; the output terminal of the adder is connected to the first input terminal of the comparator through a truncator, and the truncator is configured to input a preset number of bits from the highest bit of the output signal of the adder to the first input terminal of the comparator.

2. The configurable gating cell of claim 1, wherein, The configurable gating unit further comprises a mapping unit; the mapping unit is configured to map input phase information into a corresponding level value as the preset value input to the comparator.

3. The configurable gating cell of claim 2, wherein, The input phase information is related to the input signal of the feedback terminal of the configurable gating unit, and the feedback terminal is configured to input the feedback signal.

4. The configurable gating cell of claim 2, wherein, The number of bits of the phase information in binary representation is the same as the preset number of bits.

5. The configurable gating cell of claim 1, wherein, The phases of the N-phase different reference clocks have the same phase interval of 360° / N between adjacent phases.

6. A configurable track-and-hold circuit, characterized by The configurable tracking hold circuit comprises: a controlled switch, a holding capacitor, and the configurable gating unit of any one of claims 3 to 5; the output terminal of the configurable gating unit is connected to the control terminal of the controlled switch, and the feedback terminal of the configurable gating unit is connected to the first control terminal of the controlled switch; one end of the holding capacitor is connected to the first control terminal of the controlled switch, and the other end is grounded.

7. A phase interpolating frequency divider characterized by comprising: The configurable tracking hold circuit comprises: a phase interpolator, a phase switching controller, and the configurable tracking hold circuit of claim 6; the phase switching controller generates phase information to control the phase interpolator to generate an output signal corresponding to the phase information; the phase information is also input to the mapping unit in the configurable gating unit; the configurable gating unit shares the N-phase different reference clocks with the input of the phase interpolator; the output terminal of the configurable gating unit is connected to the control terminal of the controlled switch, and the feedback terminal of the configurable gating unit is connected to the first control terminal of the controlled switch; The second control end of the controlled switch is connected with the output end of the phase interpolator. One end of the holding capacitor is connected with the first control end of the controlled switch, and the other end is grounded.

8. The phase interpolator frequency divider of claim 7, wherein, The phase interpolation frequency divider is applied in a phase-locked loop circuit.

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