Semiconductor memory device

Abstract

A semiconductor storage device of one embodiment includes a first delay circuit that delays a first signal and in which a delay time is variable, a first selection circuit that selects either a second signal or a third signal on the basis of the first signal delayed by the first delay circuit, a first output buffer that outputs a fourth signal on the basis of a signal selected by the first selection circuit, a first output pad that outputs the fourth signal to the outside, and a counter that can count the number of outputs of the fourth signal.

Description

TECHNICAL FIELD

[0001] Embodiments relate to a semiconductor storage device. BACKGROUND

[0002] As a semiconductor storage device, a NAND type flash memory is known.

[0003] [Related Art Document]

[0004] [Patent Document]

[0005] [Patent Document 1] U.S. Patent Application Publication No. 2016 / 0225420 Specification SUMMARY

[0006] [Problem to be Solved by the Invention]

[0007] To provide a semiconductor storage device capable of improving operation reliability.

[0008] [Technical Means for Solving the Problem]

[0009] The semiconductor storage device of the present embodiment includes a first delay circuit that delays a first signal and in which a delay time is variable, a first selection circuit that selects either a second signal or a third signal on the basis of the first signal delayed by the first delay circuit, a first output buffer that outputs a fourth signal on the basis of the signal selected by the first selection circuit, a first output pad that outputs the fourth signal to the outside, and a counter that can count the number of times of output of the fourth signal. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a block diagram of a memory system of the first embodiment.

[0011] Figure 2 is a circuit diagram of a memory cell array included in the semiconductor storage device of the first embodiment.

[0012] Figure 3 is a cross-sectional view of a memory cell array included in the semiconductor storage device of the first embodiment.

[0013] Figure 4A is a circuit diagram showing a part of an input / output circuit included in the semiconductor storage device of the first embodiment.

[0014] Figure 4B is a circuit diagram of an output buffer included in the input / output circuit of Figure 4A

[0015] Figure 5 is a flowchart showing the operation of the input / output circuit in a test operation and a read operation of the semiconductor storage device of the first embodiment. ​

[0016] Figure 6 is a timing chart showing various signals in a test operation of the semiconductor storage device of the first embodiment.

[0017] Figure 7 is a diagram showing a deviation of an output timing of a signal output from an input / output circuit.

[0018] Figure 8 is a circuit diagram showing a first example of a part of an input / output circuit provided in the semiconductor storage device of the second embodiment.

[0019] Figure 9 is a circuit diagram showing a second example of a part of an input / output circuit provided in the semiconductor storage device of the second embodiment.

[0020] Figure 10 is a circuit diagram showing a part of an input / output circuit provided in the semiconductor storage device of the third embodiment.

[0021] Figure 11 is a circuit diagram showing a part of an input / output circuit provided in the semiconductor storage device of the fourth embodiment.

[0022] Figure 12A is a circuit diagram showing a first variation example of a delay circuit in an input / output circuit.

[0023] Figure 12B is a circuit diagram showing a second variation example of a delay circuit in an input / output circuit. DETAILED DESCRIPTION

[0024] Hereinafter, the embodiments will be described with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout all the drawings.

[0025] 1. First Embodiment

[0026] The semiconductor storage device of the first embodiment will be described. Hereinafter, as the semiconductor storage device, a three-dimensionally stacked NAND type flash memory in which memory cell transistors are three-dimensionally stacked on a semiconductor substrate will be described as an example.

[0027] 1.1 Regarding Configuration

[0028] 1.1.1 Regarding Overall Configuration of Memory System

[0029] First, the overall configuration of a memory system including the semiconductor storage device of the present embodiment will be described using Figure 1 Figure 1 is a block diagram of the memory system of the present embodiment.

[0030] ​As shown in the figure, a memory system 1 is provided with a NAND type flash memory 100 and a controller 300. The NAND type flash memory 100 and the controller 300 can constitute a semiconductor memory device by, for example, their combination, as the example, a memory card such as an SD card or an SSD (solid state drive) is cited. TM

[0031] The NAND type flash memory 100 is provided with a plurality of memory cells, and stores data non-volatilely. The controller 300 is connected to the NAND type flash memory 100 through a NAND bus, and is connected to a host machine not shown through a host bus not shown. And, the controller 300 controls the NAND type flash memory 100, and in addition, accesses the NAND type flash memory 100 in response to a command received from the host machine. The host machine is, for example, a digital camera or a personal computer, and the host bus is, for example, a bus corresponding to an SD interface. TM

[0032] The NAND bus performs transmission and reception of signals corresponding to a NAND interface. Specific examples of the signals are a chip enable signal CEn, an instruction latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn and / REn (an inverted signal of the signal REn), a ready / busy signal R / Bn, an input / output signal DQ, and a lock signal DQS and / DQS (an inverted signal of the signal DQS).

[0033] The chip enable signal CEn is a signal for setting the NAND type flash memory 100 to be enabled, and is established at, for example, a Low ("L") level. In addition, "established" means a state in which a signal (or logic) is active (active), and as a term with respect thereto, "negated" means a state in which a signal (or logic) is inactive (inactive). The instruction latch enable signal CLE is a signal indicating that the signal DQ is an instruction, and is established at, for example, a High ("H") level. The address latch enable signal ALE is a signal indicating that the signal DQ is an address, and is established at, for example, an "H" level. The write enable signal WEn is a signal for extracting a received signal into the NAND type flash memory 100, and is established at, for example, an "L" level every time an instruction and an address are received from the controller 300. Therefore, every time the write enable signal WEn is triggered, the signal DQ is extracted into the NAND type flash memory 100. The read enable signal REn is a signal for reading out data from the NAND type flash memory 100 by the controller 300. The read enable signal REn is established at, for example, an "L" level. Therefore, the NAND type flash memory 100 outputs the signal DQ to the controller 300 based on the triggered read enable signal REn.

[0034] ​​The ready / busy signal R / Bn is a signal that indicates whether the NAND flash memory 100 is in a busy state or a ready state (a state in which it can receive instructions from the controller 300 or a state in which it cannot receive instructions). For example, it is set to the "L" level when the NAND flash memory 100 is in a busy state.

[0035] The input / output signal DQ is, for example, an 8-bit signal DQ0 to DQ7 (hereinafter, when distinguishing the 8 signals DQ, they are respectively denoted as DQ[0] to DQ[7], and when not distinguishing, they are simply denoted as signal DQ or signal DQ[7:0]). Furthermore, the input / output signal DQ is the entity of data transmitted and received between the NAND flash memory 100 and the controller 300, namely, instructions, addresses, write data, and read data. Clock signals DQS and / DQS control, for example, the timing of the transmission and reception of signals DQ[7:0]. For example, when writing data, signals DQS and / DQS are sent from the controller 300 to the NAND flash memory 100 along with the write data DQ. Then, trigger signals DQS and / DQS are activated, and the NAND flash memory 100 receives the write data DQ synchronously with signals DQS and / DQS. When reading data, signals DQS and / DQS are sent from the NAND flash memory 100 to the controller 300 along with the read data DQ. Signals DQS and / DQS are generated based on the read drive signal REn. Then, signals DQS and / DQS are triggered, and the controller 300 synchronously receives the read data DQ.

[0036] 1.1.2 Regarding the composition of controller 300

[0037] Next use Figure 1 The details of the controller 300's configuration are explained below. Figure 1 As shown, the controller 300 includes a host interface circuit 310, a processor (CPU (Central Processing Unit)) 320, built-in memory (RAM (Random Access Memory)) 330, a buffer memory 340, an ECC circuit 350, and a NAND interface circuit 360.

[0038] The host interface circuit 310 is connected to a host machine (not shown) via a host bus (not shown), and transmits commands and data received from the host machine to the processor 320 and the buffer memory 340, respectively. Additionally, in response to commands from the processor 320, it transmits data from the buffer memory 340 to the host machine.

[0039] The processor 320 controls the overall operation of the controller 300. For example, when the processor 320 receives a write command from the host machine, it responds by issuing a write command to the NAND interface circuit 360. The same applies to read and erase operations. In addition, the processor 320 performs various processes such as wear leveling to manage the NAND flash memory 100.

[0040] The NAND interface circuit 360 is connected to the NAND flash memory 100 via the NAND bus and is responsible for communication with the NAND flash memory 100. Based on commands received from the processor 320, it outputs signals CEn, CLE, ALE, WEn, REn, DQS, and / DQS to the NAND flash memory 100. During writing, the write command issued by the processor 320 and the write data in the buffer memory 340 are transmitted to the NAND flash memory 100 as the DQ signal. During reading, the read command issued by the processor 320 is transmitted to the NAND flash memory 100 as the DQ signal, and the data read from the NAND flash memory 100 is received as the DQ signal and transmitted to the buffer memory 340.

[0041] The buffer memory 340 temporarily stores data that is written or read.

[0042] The built-in memory 330 is a semiconductor memory such as DRAM (Dynamic Random Access Memory), used as the working area of ​​the processor 320. Furthermore, the built-in memory 330 stores firmware or various management tables used to manage the NAND flash memory 100.

[0043] ECC circuit 350 performs error checking and correcting (ECC) processing on the data. That is, when writing data, ECC circuit 350 generates a parity based on the written data; when reading data, it generates a corrector based on the parity to detect and correct errors. Additionally, processor 320 may also have the functionality of ECC circuit 350.

[0044] 1.1.3 Regarding the composition of NAND flash memory 100

[0045] Next use Figure 1 The details of the NAND flash memory 100 are explained below. Additionally, Figure 1 Arrows are used to indicate a portion of the connection between blocks, but the connection between blocks is not limited to this.

[0046] like Figure 1As shown, the NAND-type flash memory 100 includes an input / output circuit 110, a logic control circuit 120, a status register 130, an address register 140, an instruction register 150, a sequencer 160, a ready / busy circuit 170, a voltage generating circuit 180, a memory cell array 190, a row decoder 200, a sense amplifier 210, a data register 220, and a column decoder 230.

[0047] The input / output circuit 110 controls input and output of the signal DQ and output of the signals DQS and / DQS with the controller 300. More specifically, the input / output circuit 110 has an input circuit and an output circuit, which are not shown. The input circuit sends data DAT (write data WD) received from the controller 300 to the data register 220, and sends an address ADD to the address register 140, and sends an instruction CMD to the instruction register 150. The output circuit sends status information STS received from the status register 130, data DAT (read data RD) received from the data register 220, and the address ADD received from the address register 140 to the controller 300. The input / output circuit 110 also has a counter 111. The counter 111 is used at the time of a test operation of the NAND-type flash memory 100, and counts, for example, the number of outputs of data outputted within a certain period. Details of the operation of the counter 111 will be described later. The input / output circuit 110 and the data register 220 are connected via a data bus.

[0048] The logic control circuit 120 receives, for example, the signals CEn, CLE, ALE, WEn, REn, DQS, and / DQS from the controller 300. And, the logic control circuit 120 controls the input / output circuit 110 and the sequencer 160 in accordance with the received signals.

[0049] The status register 130 temporarily holds status information STS. The status information STS is information indicating whether or not a write operation, a read operation, and an erase operation of data, for example, have been normally completed. The controller 300 can determine whether or not the operations have been normally completed by reading the status information STS.

[0050] The address register 140 temporarily holds an address ADD received from the controller 300 via the input / output circuit 110. And, the address register 140 transmits a row address RA to the row decoder 200, and transmits a column address CA to the column decoder 230.

[0051] The instruction register 150 temporarily holds an instruction CMD received from the controller 300 via the input / output circuit 110, and transmits it to the sequencer 160.

[0052] The sequencer 160 controls the overall operation of the NAND type flash memory 100. More specifically, the sequencer 160 controls, for example, the state register 130, the ready / busy circuit 170, the voltage generating circuit 180, the row decoder 200, the sense amplifier 210, the data register 220, and the column decoder 230, etc., to perform a write operation, a read operation, and an erase operation, etc., in accordance with the command CMD stored in the command register 150. The sequencer 160 has a timing circuit (not shown) built therein. The timing circuit measures time in a test operation described later. Of course, the timing circuit can be provided outside the sequencer 160.

[0053] The ready / busy circuit 170 sends a ready / busy signal R / Bn to the controller 300 in accordance with the operation status of the sequencer 160.

[0054] The voltage generating circuit 180 generates voltages necessary for a write operation, a read operation, and an erase operation, etc., under the control of the sequencer 160, and supplies the generated voltages to, for example, the memory cell array 190, the row decoder 200, and the sense amplifier 210, etc. The row decoder 200 and the sense amplifier 210 apply the voltages supplied from the voltage generating circuit 180 to the memory cell transistors in the memory cell array 190.

[0055] The memory cell array 190 has a plurality of blocks BLK (BLK0, BLK1,..., BLK(L-1), where (L-1) is a natural number of 2 or more) including nonvolatile memory cell transistors (hereinafter also referred to as "memory cells") corresponding to rows and columns. Each block BLK includes a plurality of string units SU (SU0, SU1, SU2, SU3,...). Also, each string unit SU includes a plurality of NAND strings. Note that the number of blocks BLK in the memory cell array 190 and the number of strings SU in the block BLK are arbitrary. Details of the memory cell array 190 are described later.

[0056] The row decoder 200 decodes the row address RA. The row decoder 200 selects any one of the blocks BLK and further selects any one of the strings SU based on the decoding result. Also, the row decoder 200 applies necessary voltages to the block BLK.

[0057] The sense amplifier 210 senses data read from the memory cell array 190 at the time of a read operation. Also, the sense amplifier 210 sends the read data RD to the data register 220. In addition, the sense amplifier 210 sends the write data WD to the memory cell array 190 at the time of a write operation.

[0058] The data register 220 has a plurality of latch circuits. The latch circuits hold the write data WD and the read data RD. For example, in the write operation, the data register 220 temporarily holds the write data WD received from the input / output circuit 110 and sends it to the sense amplifier 210. Also, for example, in the read operation, the data register 220 temporarily holds the read data RD received from the sense amplifier 210 and sends it to the input / output circuit 110.

[0059] The column decoder 230 decodes the column address CA and selects the latch circuit in the data register 220 according to the decoding result, for example, in the write operation, the read operation, and the erase operation.

[0060] 1.1.4 Circuit configuration regarding the memory cell array 190

[0061] Next, the circuit configuration of the memory cell array 190 will be described. As described above, the memory cell array 190 has a plurality of blocks BLK (BLK0, BLK1,... BLK(L-1)). Figure 2 is a circuit diagram of an arbitrary block BLK, and the other blocks BLK have the same configuration.

[0062] As shown in the figure, the block BLK includes, for example, four string units SU (SU0 to SU3). Also, each of the string units SU includes a plurality of NAND strings 10.

[0063] Each of the NAND strings 10 includes, for example, eight memory cell transistors MT (MT0 to MT7) and selection transistors ST1, ST2. The memory cell transistor MT has a control gate and a charge storage layer and nonvolatilely holds data. Also, the memory cell transistor MT is connected in series between the source of the selection transistor ST1 and the drain of the selection transistor ST2.

[0064] The gates of the selection transistors ST1 of the respective string units SU0 to SU3 are connected to selection gate lines SGD0 to SGD3, respectively. In contrast, the gates of the selection transistors ST2 of the respective string units SU0 to SU3 are commonly connected to, for example, a selection gate line SGS. Of course, they can be connected to selection gate lines SGS0 to SGS3 that differ for each string unit. Also, the control gates of the memory cell transistors MT0 to MT7 located in the same block BLK are commonly connected to word lines WL0 to WL7, respectively.

[0065] In addition, the drains of the selection transistors ST1 of the NAND strings 10 in the same column in the memory cell array 190 are commonly connected to the bit lines BL (BL0, BL1,..., BL(L-1), where (L-1) is a natural number of 2 or more). That is, the bit lines BL commonly connect the NAND strings 10 among a plurality of blocks BLK. Further, the sources of a plurality of selection transistors ST2 are commonly connected to the source lines SL.

[0066] That is, the string unit SU includes a plurality of NAND strings 10 connected to different bit lines BL and connected to the same selection gate line SGD. In addition, the block BLK includes a plurality of string units SU in which the word lines WL are common. Further, the memory cell array 190 includes a plurality of blocks BLK in which the bit lines BL are common.

[0067] In this example, one memory cell transistor MT can hold, for example, 3 bits of data. The 3 bits of data are referred to as a lower bit, a middle bit, and an upper bit, respectively, from the lower order. Further, in the same string unit SU, a set of the lower bits held by the memory cells connected to the same word line WL is referred to as a lower page, a set of the middle bits is referred to as a middle page, and a set of the upper bits is referred to as an upper page. That is, 3 pages are allocated to one word line WL. Therefore, a "page" can also be defined as a part of a memory space formed by the memory cells connected to the same word line. Further, the writing and reading of data are performed per page. In this example, since one string unit SU includes 8 word lines, each string unit SU includes (3 x 8) = 24 pages, and one block BLK includes 4 string units SU, so each block includes (24 x 4) = 96 pages.

[0068] Figure 3 is a cross-sectional view of a part of the block BLK. As shown in the drawing, on the p-type well region 20, a plurality of NAND strings 10 are formed. That is, on the well region 20, for example, 4 layers of wiring layers 27 functioning as selection gate lines SGS, 8 layers of wiring layers 23 functioning as word lines WL0 to WL7, and, for example, 4 layers of wiring layers 25 functioning as selection gate lines SGD are sequentially laminated. An insulating film not shown is formed between the laminated wiring layers.

[0069] Further, a columnar conductive body 31 is formed which penetrates through the wiring layers 25, 23, 27 to reach the well region 20. On the side surface of the conductive body 31, a gate insulating film 30, a charge storage layer (insulating film) 29, and a block insulating film 28 are sequentially formed, and a memory cell transistor MT, and selection transistors ST1 and ST2 are formed by these. The conductive body 31 functions as a current path of the NAND string 10, and becomes a region forming a channel of each transistor. Further, the upper end of the conductive body 31 is connected to a metal wiring layer 32 functioning as a bit line BL via a contact plug 39.

[0070] An n+ type impurity diffusion layer 33 is formed in the surface region of the well region 20. A contact plug 35 is formed on the diffusion layer 33, and the contact plug 35 is connected to a metal wiring layer 36 functioning as a source line SL. Further, a p+ type impurity diffusion layer 34 is formed in the surface region of the well region 20. A contact plug 37 is formed on the diffusion layer 34, and the contact plug 37 is connected to a metal wiring layer 38 functioning as a well line CPWELL. The well line CPWELL is a line for applying a potential to the conductor 31 via the well region 20.

[0071] The above configuration is in Figure 3 The paper faces are arranged in the depth direction, and a string unit SU is formed by a collection of a plurality of NAND strings 10 arranged in the depth direction.

[0072] 1.1.5 Configuration of the input / output circuit 110

[0073] Next, the circuit configuration of the input / output circuit 110 will be described using Figure 4A FIG. 6. Figure 4A is a circuit diagram showing a part of the input / output circuit of the present embodiment, and particularly focuses on a circuit block for receiving a read enable signal REn and transceiving a signal DQ.

[0074] As shown in the figure, the input / output circuit 110 includes an input buffer 40, inverters 41 to 51, and input / output blocks 80-0 to 80-9.

[0075] The input buffer 40 receives the signals REn and / REn from the controller 30 and outputs a signal corresponding to the signals. The output signal of the input buffer 40 is transmitted to the input / output blocks 80-0 to 80-9 via the inverters 41 to 51. More specifically, the output signal of the input buffer 40 is inverted in the inverter 41, the output signal of the inverter 41 is inverted with the inverters 42 and 43 respectively, the output signal of the inverter 42 is inverted with the inverters 44 and 45 respectively, and the output signal of the inverter 43 is inverted with the inverter 46. Also, the output signal of the inverter 44 is inverted with the inverters 47 and 48 respectively, the output signal of the inverter 45 is inverted with the inverter 49, and the output signal of the inverter 46 is inverted with the inverters 50 and 51 respectively. The output signal of the inverter 47 is input to each of the input / output blocks 80-0 and 80-1, the output signal of the inverter 48 is input to each of the input / output blocks 80-2 and 80-3, and the output signal of the inverter 49 is input to each of the input / output blocks 80-8 and 80-9. In addition, the output signal of the inverter 50 is input to each of the input / output blocks 80-4 and 80-5, and the output signal of the inverter 51 is input to each of the input / output blocks 80-6 and 80-7.

[0076] The input / output block 80-0 includes NAND gates 60-0 to 60-2, a delay circuit 61, a selection circuit 62, a multiplexer (MUX) 63, pre-drivers 64 and 65, an output buffer 66, an input buffer 67, and a counter 111.

[0077] The NAND gate 60-0 performs a NAND operation of a signal OSC CLK [0] (a signal OSC CLK in the input / output block 80-0) and a signal RING EN. Hereinafter, in the case of distinguishing the eight signals OSC CLK in the input / output blocks 80-0 to 80-7, they are respectively denoted as OSC CLK [0] to OSC CLK [7], and in the case of not distinguishing them, they are simply denoted as the signal OSC CLK. The NAND gate 60-1 performs a NAND operation of a signal RE CLK and a signal / RING EN (an inverted signal of the signal RING EN). The NAND gate 60-2 performs a NAND operation of output signals of the NAND gates 60-0 and 60-1. The signal RING EN is a signal given by, for example, the sequencer 160 and established at a test operation to be described later. The signal RE CLK is an output signal of the inverter 47 to 51. The signal OSC CLK [0] is an output signal of the input buffer 67 in the input / output block 80-0.

[0078] The delay circuit 61 receives, as an input signal, an output signal of the NAND gate 60-2 (hereinafter, referred to as a "signal CNT"), adjusts the speed of the signal, and outputs it. The delay circuit 61 includes, for example, a plurality of inverters connected in series.

[0079] The selection circuit 62 receives a plurality of bits of data Data (for example, eight bits of data read out from the memory cell array 190, or a plurality of bits of data given by a tester or the like), and selects one bit thereof, and outputs the selected data (hereinafter, referred to as a "signal DATA E") and its inverted data (hereinafter, referred to as a "signal DATA O"). The MUX 63 selects either one of the two output signals DATA E, DATA O of the selection circuit 62 in accordance with the output signal of the delay circuit 61. The pre-drivers 64 and 65 each receive the two output signals of the MUX 63, respectively shape the waveforms of the signals, and output them. The output buffer 66 receives the output signals of the pre-drivers 64 and 65, and outputs a signal corresponding to the signals. The output buffer 66 has, for example, the configuration shown in Fig. 6. Figure 4B Figure 4B ​is a circuit diagram of the output buffer 66. As shown, the output buffer 66 includes a p-channel MOS transistor 90 and an n-channel MOS transistor 91. The output of the predriver 64 is connected to the gate of the transistor 90, and the output of the predriver 65 is connected to the gate of the transistor 91. The drain of the transistor 90 is connected to the drain of the transistor 91, the source of the transistor 90 is connected to a power supply voltage, and the source of the transistor 91 is grounded. Further, the output signal of the output buffer 66 is output as the signal DQ[0] to the input / output pad.

[0080] The input buffer 67 receives and temporarily holds the signal DQ[0] input from the outside via the input / output pad, and outputs to the NAND gate 60-0. The input buffer 67 is also connected to the counter 111. The counter 111 counts the number of times of the signal OSC_CLK[0], that is, the signal DQ[0] is triggered. That is, the count is incremented (or decremented) at the timing when the signal OSC_CLK[0] changes from logic "H" to logic "L", and from logic "L" to logic "H". Then, the count value is transferred to the sequencer 160.

[0081] Further, since the input / output blocks 80-1 to 80-7 have the same configuration as the input / output block 80-0, the detailed illustration of Figure 4A is omitted. That is, like the input / output block 80-0, the input / output blocks 80-1 to 80-7 also include the NAND gates 60-0 to 60-2, the delay circuit 61, the selection circuit 62, the MUX 63, the predrivers 64 and 65, the output buffer 66, the input buffer 67, and the counter 111. Further, the signals input or output to the input / output blocks 80-1 to 80-7 are the signals DQ[1], DQ[2],..., DQ[7].

[0082] The input / output block 80-8 omits the detailed illustration of the circuit, but generates the signal DQS based on the read enable signal REn. The signal DQS is a signal synchronized with the signal REn. Then, the signal DQS functions as a block for transmitting the read data, for example, at the time of readout, and the read data DQ[7:0] is transmitted to the controller 300 in synchronization with the signal DQS. Also like the input / output block 80-8, the input / output block 80-9 generates the inverted signal of the signal DQS, that is, the signal / DQS.

[0083] Further, Figure 4A in which the counter 111 is provided inside the input / output circuit 110 is described. However, the counter 111 can also be provided outside the input / output circuit 110. For example, the counter 111 can also be provided inside the sequencer 160, inside the controller 300, or inside a tester used at the time of test operation.

[0084] 1.2 Action of input / output circuit 110

[0085] First, the action of the input / output circuit 110 will be described using Figure 5 the flowchart shown in FIG. 10. Figure 5 is a flowchart showing the action of the input / output circuit 110 in the test action and the readout action. The test action of the present embodiment is to adjust the output timing of the data output from the MUX 63 for each of the input / output blocks 80-0 to 80-7 as shown in FIG. 8. Hereinafter, the action of the input / output block 80-0 in the test action and the readout action will be described. Figure 4A

[0086] As shown in the figure, first, the input / output circuit 110 receives the signals REn and / REn (step S10). Next, the signal RE CLK is generated from the input buffer 40, the inverters 41, 42, 44, and 47 in accordance with the signals REn and / REn.

[0087] Next, the sequencer 160 of the NAND flash memory 100, for example, determines whether the current action is the test action (step Sll). In the case of a non-test action, it can be, for example, a normal data readout action, or a readout action of status information, and the like.

[0088] In the case of the test action (step Sll, Yes), the sequencer 160 sets the signal RING EN to the "H" level, for example (step S12). In addition, the logic level of the output signal OSC CLK [0] of the input buffer 67 becomes the "H" level or the "L" level based on the signal DQ [0].

[0089] Next, the MUX 63 selects the readout data (signal DATA_E) / the inverted data (signal DATA_O) based on the operation result of the signals OSC CLK [0], RING EN, / RING EN, and RE CLK (step S13). Next, the output buffer 66 outputs the data selected in step S13 as the signal DQ [0] to the input / output pad (step S14). Subsequently, the input buffer 67 receives the signal DQ [0] output in step S14 via the input / output pad, and outputs the signal DQ [0] as the signal OSC CLK [0] (step S15), which is input to the NAND gate 60-0 and the counter 111.

[0090] Next, the sequencer 160 of the NAND flash memory 100, for example, determines whether the count value of the counter 111 reaches a predetermined specific value (step S16).

[0091] ​When the count value does not reach the specific value (step S16, No), the counter 111, for example, increments the count value by 1 (step S18). In addition, at the timing when the counter 111 initially increments the count, the timing circuit starts measuring the time. And, steps S13 to S16 are performed again until the count value reaches the specific value. On the other hand, when the count value reaches the specific value (step S16, Yes), the timing circuit ends the measurement of the time, and the sequencer 160 of the NAND flash memory 100, for example, acquires the period At measured by the timing circuit (step S17). More specifically, when the count value becomes 1 in step S18, the timing circuit starts measuring the time, and the sequencer 160 determines that the count value reaches 216 in step S16, the timing circuit ends the measurement of the time, when the specific value is 216, for example.

[0092] Next, the sequencer 160 of the NAND flash memory 100, for example, compares the period At acquired in step S17 with the reference value Tref (step S19). In addition, the reference value Tref is a value preset as the time until the count value reaches the specific value, and is 20 ps x 2 16 = 1.31 μs, for example. However, the value is only an example, and can be another value. The reference value Tref is stored in the ROM fuse within the memory cell array 190, together with the specific value to be counted by the counter 111, for example. And, when the power is supplied to the NAND flash memory 100, the reference value Tref is read out to a register not shown by the sequencer 160 without a command from the controller 300.

[0093] When the result of the comparison is that the period At is equal to the reference value Tref (step S19, Yes), the sequencer 160 of the NAND flash memory 100, for example, determines that there is no need to adjust the input / output block 80-0. On the other hand, when the period At is different from the reference value Tref (step S19, No), the sequencer 160, for example, determines whether the period At acquired in step S17 is longer than the reference value Tref (step S20). Next, the sequencer 160 performs adjustment of the input / output block 80-0 based on the result of the determination in step S20. The adjusted data (such as the delay time, etc.) is written to the ROM fuse within the memory cell array 190, for example.

[0094] More specifically, when the period At is longer than the reference value Tref (step S20, Yes), the sequencer 160, for example, increases the driving force of the inverter of the delay circuit 61 (step S21). By this, the output timing of the data output from the MUX 63 is advanced.

[0095] On the other hand, in the case where the period Δt is shorter than the reference value Tref (step S20, No), the sequencer 160, for example, reduces the driving force of the inverter of the delay circuit 61 (step S22). By this, the output timing of the data output from the MUX 63 is delayed.

[0096] Next, the sequencer 160 of the NAND-type flash memory 100, for example, resets the counter 111 (step S23). And, the steps S12-S23 are performed again until the adjustment of the input / output block 80-0 is not necessary, that is, until the period Δt is equal to the reference value Tref or the deviation from the reference value Tref falls within a certain allowable range.

[0097] Next, the sequencer 160 of the NAND-type flash memory 100 performs the steps S12-S23 also on the input / output blocks 80-1-80-7. Next, after the adjustment of all the input / output blocks 80-0-80-7 is completed, the sequencer 160 ends the test operation.

[0098] In the case of a non-test operation (step Sll, No), for example, in the case of a normal data read operation, the sequencer 160 of the NAND-type flash memory 100, for example, sets the signal RING_EN to the "L" level (step S24). At this time, the OSC CLK[0] is ignored. Next, the output buffer 66 outputs the read data (signal DATA_E) as the signal DQ[0] (step S25). More specifically, the signal DQ[0] is triggered and output in synchronization with the trigger of the signal REn.

[0099] In addition, the input / output blocks 80-1-80-7 also perform the test operation and the read operation in the same manner as described above.

[0100] Figure 5 In the case where the steps S12-S22 are performed again after the counter 111 is reset at step S23 in the test operation, for example, is described. However, in the test operation, after the counter 111 is reset at step S23, the step S12 can not be performed and the steps S13-S22 can be performed again.

[0101] In addition, Figure 5 In the case where the data read from the memory cell array 190 is given to the selection circuit 62 in the test operation, for example, is described, but the data can be given to the selection circuit 62 from a tester, for example. In the case, as the signal DQ, a pattern data such as "0" and "1" repeated can be given.

[0102] Next, a specific example of the test operation is described using Figure 6 is described. Figure 6is a timing chart showing various signals in a test operation, and particularly shows signals related to signal DQ[0].

[0103] At time tl, based on signals REn and / REn, signal RE CLK becomes "L" level. As a result, the output of NAND gate 60-1 becomes "H" level regardless of signal RING EN, and as a result, the output of NAND gate 60-2 depends on the output signal of NAND gate 60-0. Also, at time tl, since signal RING EN is "L" level and signal OSC CLK[0] is "H" level, the output signal CNT of NAND gate 60-2 is "L" level.

[0104] Based on the "L" level signal CNT from NAND gate 60-2, MUX 63 selects either of signals DATA E and DATA O. As a result, assume that at time t2, signal DQ[0] shifts from "H" level to "L" level.

[0105] Next, at time t3, a test operation command is received, and sequencer 160 sets signal RING EN to "H" level. As a result, the output signal of NAND gate 60-0 depends on signal OSC CLK[0], that is, the output signal CNT of NAND gate 60-2 is determined by signal OSC CLK[0].

[0106] At subsequent time t4, NAND type flash memory 100 is in a busy state, and the ready / busy signal is "L" level. Also, by shifting signal RING EN from "L" level to "H" level, the output signal CNT of NAND gate 60-2 becomes "H" level.

[0107] Based on the "H" level signal CNT from NAND gate 60-2, MUX 63 selects either of signals DATA E and DATA O. As a result, at time t5, signal DQ[0] shifts from "L" level to "H" level. Next, at time t6, signal OSC CLK[0] shifts from "H" level to "L" level via input buffer 67. In this way, counter 111 detects the shift of signal OSC CLK[0] and starts counting. Also, counter 111 starts counting up, and the timing circuit starts time measurement.

[0108] By shifting signal OSC CLK[0] from "H" level to "L" level, the output signal CNT of NAND gate 60-2 becomes "L" level.

[0109] Based on the "L" level signal CNT from the NAND gate 60-2, the MUX 63 selects either the DATA_E or DATA_O signal. As a result, at time t7, the signal DQ[0] transitions from the "H" level to the "L" level. Additionally, at time t8, via the input buffer 67, the signal OSC_CLK[0] transitions from the "L" level to the "H" level. Next, the counter 111 detects the transition of the signal OSC_CLK[0] and increments the count.

[0110] As shown above, signal DQ[0] is input to MUX63 via input / output pads, input buffer 67, NAND gates 60-0 and 60-2, and delay circuit 61. As a result, Figure 6 As shown, signals DQ[0] and OSC_CLK[0] trigger actions. Then, based on the trigger actions, counter 111 increments. Counter 111 increments until a preset count value is reached ( Figure 6 In the example, it is 2 16 (Of course, it can also be a decrementing count.) Then, the count reaches 2. 16 Then, the timing circuit ends the measurement. Next, the sequencer 160 compares the measured period Δt with the reference value Tref. If the measured period Δt is different from the reference value Tref, the delay time of the delay circuit 61 is adjusted, and the same action is repeated.

[0111] 1.3 Effects of this implementation method

[0112] The configuration of this embodiment improves the operational reliability of the semiconductor memory device. This effect will be explained below. Figure 7 It is a waveform diagram representing the signals DQ[0] to DQ[7], and a waveform diagram representing the effective margin of the entire signal DQ[7:0] obtained as a result.

[0113] The output timing of signal DQ[7:0] may vary due to the uneven characteristics of components in each input / output block 80-0 to 80-7. Figure 7 The above figure illustrates the situation described. As shown, for example, signal DQ[7] performs signal transitions within the permissible timing range, while the transition time of signal DQ[6] is significantly delayed, and conversely, the transition time of signal DQ[2] is too fast. As a result, the effective margin of signal DQ[7:0] as a whole may become extremely narrow.

[0114] Therefore, in the present embodiment, at the time of the test operation, the delay time of the delay circuit 61 is adjusted by feeding back the signal DQ output from the MUX 63 to the delay circuit 61 in each input / output block of the input / output circuit 110. More specifically, the number of times of output of the signal DQ is counted, and the period Δt during which the counted number reaches a certain number, that is, the count value of the counter 111 reaches a certain value, is compared with the reference value Tref. Then, the delay time of the delay circuit 61 is adjusted until the period Δt is equal to the reference value Tref or falls within a certain allowable range from any one of the reference values Tref. As a result, the characteristic unevenness among the plurality of input / output blocks can be corrected. Thus, as shown in the lower drawing of FIG. 10, the transfer timing of the signals DQ[0] to DQ[7] can be made substantially simultaneous, and the effective margin as the positive body of the signal DQ[7:0] can be increased. Figure 7

[0115] In addition, the present embodiment includes the counter 111. Thus, the tester only needs to measure the length of the period Δt until the count value of the counter 111 reaches a certain value. Therefore, the tester does not need to be high-resolution, and even a tester with low resolution can adjust the delay time of the delay circuit 61 with good accuracy.

[0116] 2. Second Embodiment

[0117] Next, the semiconductor storage device of the second embodiment will be described. In the first embodiment, the case where the signal DQ is fed back to the NAND gate 60-0 via the input buffer 67 at the time of the test operation has been described. In contrast to this, the present embodiment is a case where a backup circuit of the pre-driver 65 or the output buffer 66 is provided, and the signal is fed back via either of the backup circuits. Hereinafter, only the points different from the first embodiment will be described.

[0118] 2.1 First Example of Input / Output Circuit 110

[0119] The first example of the input / output circuit 110 of the present embodiment is an example in which the pre-driver backup 68 connected to the pre-driver 65 is provided in each of the input / output blocks 80-0 to 80-7 described in the first embodiment.

[0120] The pre-driver backup 68 has the same circuit configuration as the pre-driver 65, and also has the same circuit characteristics. Then, the pre-driver backup 68 receives the signal selected by the MUX 63, performs waveform shaping in the same manner as the pre-driver 65, and outputs the result as the signal OSC CLK to the NAND gate 60-0 and the counter 111. In each of the input / output blocks 80-0 to 80-7, the feedback path from the input buffer 67 to the counter 111 and the NAND gate 60-0 is abandoned.

[0121] ​In the test operation, the pre-driver backup 68 outputs the signal selected by the MUX 63 as the signal OSC CLK, which is input to the NAND gate 60-0 and the counter 111.

[0122] The operation in the test operation is the same as that explained in the first embodiment Figure 5 and Figure 6 The difference from the first embodiment is that the signal OSC CLK is generated by the pre-driver backup 68 instead of the input buffer 67.

[0123] 2.2 Second example of the input / output circuit 110

[0124] The second example of the input / output circuit 110 of the present embodiment is that the output buffer backup 69 connected to the pre-drivers 64 and 65 is provided in each of the input / output blocks 80-0 to 80-7 explained in the first embodiment.

[0125] The output buffer backup 69 has the same circuit configuration as the output buffer 66 and has the same circuit characteristics. Further, the output buffer backup 69 receives the signal selected by the MUX 63 and temporarily stores the received signal as in the output buffer 66, and outputs the signal as the signal OSC CLK to the NAND gate 60-0 and the counter 111. In each of the input / output blocks 80-0 to 80-7, the feedback path from the input buffer 67 to the counter 111 and the NAND gate 60-0 is abandoned.

[0126] In the test operation, the output buffer backup 69 outputs the signal selected by the MUX 63 as the signal OSC CLK, which is input to the NAND gate 60-0 and the counter 111.

[0127] The operation in the test operation is the same as that explained in the first embodiment Figure 5 and Figure 6 The difference from the first embodiment is that the signal OSC CLK is generated by the output buffer backup 69 instead of the input buffer 67.

[0128] 2.3 Effects of the present embodiment

[0129] According to the configuration of the present embodiment, the data signal (the output signal of the MUX 63) can be fed back without passing through the input / output pad by the backup circuit of the pre-driver or the output buffer. As a result, for example, the influence of the load such as a mounting substrate or a probe card can be avoided.

[0130] 3. Third embodiment

[0131] Next, the semiconductor storage device of the third embodiment will be described. The present embodiment combines the first example of the first embodiment and the second embodiment. Hereinafter, only the points different from the first embodiment will be described.

[0132] 3.1 Configuration of input / output circuit 110

[0133] The input / output circuit 110 of the present embodiment is provided with the pre-driver backup 68 and the selection circuit 70 described in the second embodiment in each of the input / output blocks 80-0 to 80-7 described in the first embodiment.

[0134] The selection circuit 70 receives a signal OSC CLK (hereinafter referred to as a signal "OSC CLK A") fed back from the input buffer 67, and a signal OSC CLK (hereinafter referred to as a signal "OSC CLK B") fed back from the pre-driver backup 68. Next, based on the signal OSC MODE SEL, either one of the signals OSC CLK A and OSC CLK B is selected, and the selected signal is output to the NAND gate 60-0 and the counter 111.

[0135] In the test operation, the selection circuit 70 selects either one of the signal OSC CLK A and the signal OSC CLK B based on the signal OSC MODE SEL from the sequencer 160 of the NAND type flash memory 100, and inputs the selected signal to the NAND gate 60-0 and the counter 111.

[0136] The operation at the time of the test operation is the same as that described in the first embodiment Figure 5 and Figure 6 The only point different from the first and second embodiments is that either the signal OSC CLK A fed back from the input buffer 67 or the signal OSC CLK B fed back from the pre-driver backup 68 is selected based on the signal OSC MODE SEL.

[0137] 3.2 Effects of the present embodiment

[0138] The first example of the first embodiment and the second embodiment can be combined as shown in the present embodiment. Of course, the second example of the first embodiment and the second embodiment can be combined. Thus, since the feedback path can be selected according to the situation, appropriate timing control can be performed.

[0139] 4. Fourth embodiment

[0140] Next, the semiconductor storage device of the fourth embodiment will be described. The present embodiment provides the NAND gates 60-0 to 60-2 between the input buffer 40 and the inverter 41. Hereinafter, only the points different from the first embodiment will be described.

[0141] 4.1 Configuration of the input / output circuit 110

[0142] The input / output circuit 110 of the present embodiment is provided with the selection circuit 71 connected to the input buffer 67, and the NAND gates 60-0 to 60-2 of the input / output block 80-0 explained in the first embodiment are provided between the input buffer 40 and the inverter 41, and the counter 111 is connected to the selection circuit 71.

[0143] The selection circuit 71 receives the signals OSC CLK[0] to OSC CLK[7] fed back from the input buffers 67 of the input / output blocks 80-0 to 80-7. Next, any one of the signals OSC CLK[0] to OSC CLK[7] is selected, and the selected signal is output to the NAND gates 60-0 and the counter 111. The signal DQS and the signal / DQS can also be input to the selection circuit 71. In the input / output blocks 80-0 to 80-7, the NAND gates 60-0 to 60-2 and the counter 111 are omitted.

[0144] In the test operation, the selection circuit 71 selects any one of the signals OSC CLK[0] to OSC CLK[7] based on a signal from the sequencer 160 of the NAND-type flash memory 100, for example, and inputs the selected signal to the NAND gates 60-0 and the counter 111. Next, adjustment related to the input / output block corresponding to the selected signal is performed.

[0145] The operation at the time of the test operation is the same as explained in the first embodiment. Figure 5 and Figure 6 The point of difference from the first embodiment is that the logical operation of the NAND gates 60-0 to 60-2 is performed after the input buffer 40 and before the inverter 41.

[0146] 4.2 Effects of the present embodiment

[0147] According to the configuration of the present embodiment, the signal DQ can be fed back after the input buffer 40 and before the inverter 41. As a result, for example, signal delay occurring in a wider range than the input / output block can be corrected, and the timing control of the signal DQ can be performed with higher precision.

[0148] 5. Variations and the like

[0149] As described above, the semiconductor memory device of the embodiment includes: a first delay circuit (61) that delays a first signal (CNT) for a variable delay time; a first selection circuit (MUX63) that selects either a second signal (DATA_E) or a third signal (DATA_O) based on the first signal (CNT) delayed by the first delay circuit (61); a first output buffer (66) that outputs a fourth signal (DQ) based on the signal selected by the first selection circuit (MUX63); a first output pad that outputs the fourth signal (DQ) to the outside; and a counter (111) that can count the number of times the fourth signal (DQ) is output.

[0150] According to the above configuration, since the output timing of the control signal DQ for each input / output block can be determined, the operational reliability of the semiconductor memory device can be improved. Furthermore, the implementation is not limited to the description above, and various variations are possible.

[0151] In the aforementioned implementation method, Figure 5 Step S19 will be explained using the case where the period Δt measured by the timing circuit is equal to the reference value Tref as an example. However, even if the period Δt differs from the reference value Tref in step S19, it is acceptable as long as the difference is within a certain permissible range.

[0152] In addition, the embodiment described above is illustrated by taking the case where the output of one inverter (e.g., inverter 47) is input to one input / output block (e.g., input / output block 80-0) as an example. Alternatively, the output of one inverter (e.g., inverter 47) can be input to two input / output blocks (e.g., input / output blocks 80-0 and 80-1).

[0153] In addition to the wafer testing steps, the testing operations described in this embodiment can also be performed after shipment. The possibility of timing deviations due to the degradation of various components is also considered. In this case, the same operations as in the previous embodiment can be performed to adjust the delay time of the delay circuit 61. Furthermore, the data in the ROM fuse can be rewritten.

[0154] The delay circuit 61 in the input / output circuit 110 can be, for example... Figure 12A and Figure 12B The circuit shown. The following is a description of... Figure 12A The circuit shown in Figure 12 will be explained.

[0155] Figure 12A This is the first variation of the delay circuit 61. Figure 12AThe delay circuit 61 includes multiple p-channel MOS transistors and n-channel MOS transistors, and adjusts the driving force according to whether some of the transistors are turned on (ON), thereby adjusting the delay. As shown in the figure, the delay circuit 61 includes p-channel MOS transistors 92-0 to 92-4, 94-0 to 94-4, and n-channel MOS transistors 93-0 to 93-4, 95-0 to 95-4. The output of the NAND gate 60-2 is connected to the gates of transistors 92-0 and 93-0. The source of transistor 92-0 is connected in parallel to the drains of transistors 92-1 to 92-4, and the sources of transistors 92-1 to 92-4 are respectively connected to the power supply voltage. The source of transistor 93-0 is connected in parallel to the drains of transistors 93-1 to 93-4, and the sources of transistors 93-1 to 93-4 are respectively grounded. The drain of transistor 92-0 is connected to the drain of transistor 93-0 and the gates of transistors 94-0 and 95-0. The source of transistor 94-0 is connected in parallel to the drains of transistors 94-1 to 94-4, and the sources of transistors 94-1 to 94-4 are connected to the power supply voltage. The source of transistor 95-0 is connected in parallel to the drains of transistors 95-1 to 95-4, and the sources of transistors 95-1 to 95-4 are grounded. The drain of transistor 94-0 is connected to the drain of transistor 95-0 and MUX63.

[0156] Figure 12B This is the second variation of delay circuit 61. Figure 12B The delay circuit 61 connects transistors as capacitors to the output node. Adjusting the source and drain voltages makes the capacitance value variable, thereby adjusting the delay. As shown in the figure, the delay circuit 61 includes p-channel MOS transistors 96-0 to 96-3, 98-0 to 98-3, and n-channel MOS transistors 97-0 to 97-3, 99-0 to 99-3. The output of the NAND gate 60-2 is connected to the gates of transistors 96-0 and 97-0. The source of transistor 96-0 is connected to the power supply voltage, and the source of transistor 97-0 is grounded. The drain of transistor 96-0 is connected to the drain of transistor 97-0, and the gates of transistors 96-1 to 96-3, 97-1 to 97-3, 98-0, and 99-0, respectively. The source of transistor 98-0 is connected to the power supply voltage, and the source of transistor 99-0 is grounded. The drain of transistor 98-0 is connected to the drain of transistor 99-0, transistors 98-1 to 98-3, transistors 99-1 to 99-3 and MUX63, respectively.

[0157] Furthermore, the aforementioned embodiments can be implemented independently without relying on other embodiments. Alternatively, the embodiments can be combined.

[0158] Furthermore, in the embodiment, the semiconductor storage device is described taking a NAND type flash memory as an example, but is not limited to the NAND type flash memory, and can be applied to all other semiconductor memories, and further can be applied to various storage devices other than the semiconductor memories. In addition, the flowcharts described in the embodiment can replace the processing order as much as possible.

[0159] While several embodiments of the present application have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the application. The various embodiments can be implemented in numerous ways, and are not limited to the embodiments described herein. The various embodiments can be implemented in a variety of ways, and various omissions, substitutions, and changes can be made without departing from the scope and spirit of the application. The embodiments or variations thereof and the equivalents thereof included in the scope or spirit of the application are included in the scope of the application recited in the claims and the equivalents thereof.

Claims

1. A semiconductor memory device comprising: The first delay circuit delays the first signal, and the delay time is variable; The first selection circuit selects either the second signal or the third signal based on the first signal delayed by the first delay circuit. The first output buffer outputs the fourth signal based on the signal selected by the first selection circuit; The first output pad outputs the fourth signal to the outside; and The counter can count the number of times the fourth signal is output.

2. The semiconductor memory device of claim 1, wherein the delay time is controlled based on the count value of the counter.

3. The semiconductor memory device according to claim 2, wherein... The semiconductor memory device includes a first operation and a second operation; and The delay time in the first action is controlled.

4. The semiconductor memory device according to claim 3, wherein the semiconductor memory device further comprises: a first wiring capable of feeding back a fifth signal based on the fourth signal as the first signal to the first delay circuit; and The counter counts the number of times the fourth signal is output a certain number of times; The delay time is determined based on the period required to count the specified number of times.

5. The semiconductor memory device according to any one of claims 1 to 3, wherein the semiconductor memory device further comprises: a first wiring capable of feeding back a fifth signal based on the fourth signal as the first signal to the first delay circuit; and The first input buffer is configured in the first wiring and outputs the fifth signal; and The first input buffer can receive written data from the outside.

6. The semiconductor memory device according to claim 4, wherein the semiconductor memory device further comprises a first input buffer disposed on the first wiring and outputting the fifth signal; The first output buffer can receive written data from the outside.

7. The semiconductor memory device according to claim 1, wherein the semiconductor memory device further comprises: First input / output block; Second input / output block; and The third selection circuit can select either the first or the second input / output block; and The first input / output block has the following features: The first delay circuit; The first selection circuit; The first output buffer; The first output pad; The first wiring can feed back the fifth signal, based on the fourth signal, as the first signal to the first delay circuit; and The first input buffer is configured in the first wiring and outputs the fifth signal; The second input / output block has the following features: The second delay circuit delays the sixth signal, and the delay time is variable; The second selection circuit selects either the seventh signal or the eighth signal based on the sixth signal delayed by the second delay circuit. The second output buffer outputs the ninth signal based on the signal selected by the second selection circuit. The second output pad outputs the ninth signal to the outside. The second wiring can use the 10th signal based on the 9th signal as the 6th signal and feed it back to the second delay circuit; and The second input buffer is configured in the second wiring and outputs the 10th signal; and The first and second input buffers can receive written data from the outside; The counter can count the number of times the fourth signal is output when the third selection circuit selects the first wiring, and can count the number of times the ninth signal is output when the third selection circuit selects the second wiring.

8. The semiconductor memory device of claim 1, wherein the semiconductor memory device further comprises a plurality of input / output blocks, each of the plurality of input / output blocks including the first delay circuit, the first selection circuit, the first output buffer, the first output pad, and the counter; and The delay time can be controlled according to each of the input / output blocks.

9. A semiconductor memory device comprising: The first delay circuit delays the first signal, and the delay time is variable; The first selection circuit selects either the second signal or the third signal based on the first signal delayed by the first delay circuit. The first circuit outputs the fourth signal based on the signal selected by the first selection circuit; The first output buffer outputs the fifth signal based on the signal selected by the first selection circuit; The first output pad outputs the fifth signal to the outside; and The counter can count the number of times the fourth signal is output.

10. The semiconductor memory device of claim 9, wherein the semiconductor memory device further comprises: a first driving circuit for shaping the waveform of a signal selected by the first selection circuit; the first circuit comprising: a second driving circuit for shaping the waveform of the signal selected by the first selection circuit.

11. The semiconductor memory device of claim 9, wherein the first circuitry comprises: a second output buffer for outputting the fourth signal based on a signal selected by the first selection circuitry.

12. The semiconductor memory device according to claim 9, wherein the semiconductor memory device further comprises: a first wiring capable of feeding back a sixth signal based on the fourth signal as the first signal to the first delay circuit; The second wiring can use the seventh signal based on the fifth signal as the first signal and feed it back to the first delay circuit; and The second selection circuit can select either the first wiring or the second wiring; and The counter can count the number of times the fourth signal is output when the second selection circuit selects the first wiring, and can count the number of times the fifth signal is output when the second selection circuit selects the second wiring.

13. The semiconductor memory device according to claim 9, wherein the semiconductor memory device further comprises: First input / output block; Second input / output block; and The third selection circuit can select either the first or the second input / output block; and The first input / output block includes: the first delay circuit; The first selection circuit; The first circuit; The first output buffer; The first output pad; and The first wiring can use the sixth signal, based on the fourth signal, as the first signal and feed it back to the first delay circuit; and The second input / output block includes: a second delay circuit that delays the seventh signal, and the delay time is variable; The second selection circuit selects either the eighth or the ninth signal based on the seventh signal delayed by the second delay circuit. The second circuit outputs the 10th signal based on the signal selected by the second selection circuit; The second output buffer outputs the 11th signal based on the signal selected by the second selection circuit. The second output pad outputs the 11th signal to the outside; and The second wiring can use the 12th signal based on the 10th signal as the 7th signal and feed it back to the second delay circuit; and The counter can count the number of times the fourth signal is output when the third selection circuit selects the first wiring, and can count the number of times the tenth signal is output when the third selection circuit selects the second wiring.

14. The semiconductor memory device of claim 9, wherein the semiconductor memory device further comprises a plurality of input / output blocks, each of the plurality of input / output blocks including the first delay circuit, the first selection circuit, the first circuit, the first output buffer, the first output pad, and the counter; and The delay time can be controlled according to each of the input / output blocks.

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