Chip Testing Device, Chip Testing System and Data Acquisition Method

Abstract

The present invention discloses a chip testing device, which includes a network analyzer and a trigger module. The network analyzer, the trigger module and the chip to be tested are electrically connected. The network analyzer is configured to send a trigger instruction to the trigger module and collect the state switching time of the chip to be tested. The trigger module is configured to send a first trigger signal to the chip to be tested in response to the trigger instruction, where the first trigger signal is a signal for triggering the chip to be tested to perform a state switch. Through the combined action of the network analyzer and the trigger module, the collection of the state switching time of the chip to be tested can be achieved without the need to additionally build a complex test environment, thereby not only improving the efficiency of collecting the state switching time of the chip, but also reducing the test cost.

Description

Technical Field

[0001] The present invention relates to the field of testing technologies, and in particular, to a chip testing device, a chip testing system, and a data acquisition method. Background Art

[0002] With the development of communication technologies, people's requirements for the performance of chips are also getting higher and higher. Exemplarily, in various detections and verifications of radio frequency chips, testing is an important link for inspecting the quality of chips. By testing the performance of a chip, it can be accurately evaluated whether the chip meets the actual application requirements. In the field of testing, for the testing of devices such as chips, an automatic test equipment (ATE) is usually used to implement the testing of different performances of devices such as chips. In some specific application scenarios, when testing different performances of devices such as chips, it is necessary to collect the state switching time of devices such as chips. Currently, the method for collecting the state switching time of devices such as chips is relatively cumbersome, and a relatively complex test environment needs to be built. Not only is the test cost high, but also the efficiency is low, far from meeting the actual needs. Summary of the Invention

[0003] Embodiments of the present invention provide a chip testing device, a chip testing system, and a data acquisition method to solve the problem of low efficiency in collecting the state switching time of a chip.

[0004] A chip testing device includes a network analyzer and a trigger module, and the network analyzer, the trigger module, and the chip to be tested are electrically connected;

[0005] The network analyzer is configured to send a trigger instruction to the trigger module and collect the state switching time of the chip to be tested;

[0006] The trigger module is configured to send a first trigger signal to the chip to be tested in response to the trigger instruction, where the first trigger signal is a signal for triggering the chip to be tested to perform a state switch.

[0007] Further, the sampling period of the network analyzer is equal to or less than one-tenth of the state switching time of the chip to be tested.

[0008] Further, the sampling period of the network analyzer is 10 ns - 1 μs.

[0009] Further, the state switching time of the chip to be tested includes the time for a switch in the chip to be tested to perform a state switch.

[0010] Further, the network analyzer includes L connection ports and a first trigger port; the connection ports are configured to output an excitation signal to the chip under test, and / or receive a response signal output by the chip under test, where the response signal is a signal output by the chip under test based on the excitation signal, and L is a positive integer greater than or equal to 1; the first trigger port is configured to send a trigger instruction to the trigger module.

[0011] Further, the L connection ports include A first connection ports and B second connection ports; the first connection ports are configured to output an excitation signal to the chip under test, and the second connection ports are configured to receive a response signal output by the chip under test, where the response signal is a signal output by the chip under test based on the excitation signal, where A is a positive integer greater than or equal to 1, and B is a positive integer greater than or equal to 1.

[0012] Further, the network analyzer is configured to collect the response signal output by the chip under test within a preset time period to collect the state switching time of the chip under test.

[0013] Further, the network analyzer is configured to start collecting the response signal output by the chip under test when sending a trigger instruction to the trigger module.

[0014] Further, the chip testing device further includes Z radio frequency switch modules, each radio frequency switch module includes a first switching port and M second switching ports, the first switching port of each radio frequency switch module is connected to one of the connection ports in the network analyzer, and each second switching port is coupled to one of the test ports in the chip under test, where Z is a positive integer greater than or equal to 1, and M is a positive integer greater than or equal to 1.

[0015] Further, the chip testing device further includes N isolation switch modules, each isolation switch module includes a moving end, a first fixed end and a second fixed end, the moving end of each isolation switch module is connected to one of the test ports in the chip under test, the first fixed end of each isolation switch module is connected to one of the second switching ports in the radio frequency switch module, and the second fixed end of each isolation switch module is coupled to the ground terminal, where N is a positive integer greater than or equal to 1.

[0016] Further, the isolation switch module further includes an impedance matching unit, the second fixed end of the isolation switch module is connected to the first end of the impedance matching unit, and the second end of the impedance matching unit is connected to the ground terminal.

[0017] The present application also provides a chip testing device, which includes a network analyzer and a trigger module. The network analyzer, the trigger module and the chip to be tested are electrically connected;

[0018] The network analyzer includes L connection ports and a first trigger port; the trigger module includes a first input port and a first output port;

[0019] Each of the connection ports is electrically connected to a test port in the chip to be tested. The connection port is configured to output an excitation signal to the test port of the chip to be tested, and / or receive a response signal output from the test port of the chip to be tested, where the response signal is a signal output by the chip to be tested based on the excitation signal;

[0020] The first trigger port is electrically connected to the first input port of the trigger module and is configured to send a trigger instruction to the trigger module; the first output port of the trigger module is electrically connected to the second trigger port of the chip to be tested and is configured to send a first trigger signal to the chip to be tested, where the first trigger signal is a signal for triggering the chip to be tested to perform a state transition.

[0021] A data acquisition method is applied to a chip testing device. The chip testing device includes a network analyzer and a trigger module. The network analyzer, the trigger module and the chip to be tested are electrically connected;

[0022] The network analyzer sends a trigger instruction to the trigger module and acquires the switching time of a switch in the chip to be tested;

[0023] The trigger module responds to the trigger instruction and sends a first trigger signal to the chip to be tested, where the first trigger signal is a signal for triggering the chip to be tested to perform a state transition.

[0024] The above chip testing device includes a network analyzer and a trigger module. The network analyzer, the trigger module and the chip to be tested are electrically connected; the network analyzer is configured to send a trigger instruction to the trigger module and acquire the state transition time of the chip to be tested; the trigger module is configured to respond to the trigger instruction and send a first trigger signal to the chip to be tested, where the first trigger signal is a signal for triggering the chip to be tested to perform a state transition. In this embodiment, by the combined action of the network analyzer and the trigger module, the state transition time of the chip to be tested can be acquired, and there is no need to additionally build a complex test environment. Therefore, not only the efficiency of acquiring the chip state transition time is improved, but also the test cost is reduced.

[0025] The above chip testing device includes a network analyzer and a trigger module, and the network analyzer, the trigger module and the chip to be tested are electrically connected; the network analyzer includes L connection ports and a first trigger port; the trigger module includes a first input port and a first output port; each of the connection ports is electrically connected to a test port in the chip to be tested, and the connection port is configured to output an excitation signal to the test port of the chip to be tested, and / or receive a response signal output from the test port of the chip to be tested, where the response signal is a signal output by the chip to be tested based on the excitation signal; the first trigger port is electrically connected to the first input port of the trigger module and is configured to send a trigger instruction to the trigger module; the first output port of the trigger module is electrically connected to the second trigger port of the chip to be tested and is configured to send a first trigger signal to the chip to be tested, where the first trigger signal is a signal for triggering the chip to be tested to perform a state transition; in this embodiment, the network analyzer sends a trigger instruction to the trigger module to trigger the trigger module to send a first trigger signal to the chip to be tested, and the chip to be tested realizes a state transition under the action of the first trigger signal, and the network analyzer collects the response signal output from the test port of the chip to be tested to collect the state transition time of the chip to be tested. Thus, it can be seen that in this embodiment, the state transition time of the chip to be tested can be collected under the combined action of the network analyzer and the trigger module without the need to additionally build a complex test environment, thereby not only improving the efficiency of collecting the state transition time of the chip, but also reducing the test cost.

[0026] The above data acquisition method is applied to a chip testing device, where the chip testing device includes a network analyzer and a trigger module, and the network analyzer, the trigger module and the chip to be tested are electrically connected;

[0027] The network analyzer sends a trigger instruction to the trigger module and collects the state transition time of the chip to be tested; the trigger module responds to the trigger instruction and sends a first trigger signal to the chip to be tested, where the first trigger signal is a signal for triggering the chip to be tested to perform a state transition; in this embodiment, the state transition time of the chip to be tested can be collected under the combined action of the network analyzer and the trigger module without the need to additionally build a complex test environment, thereby not only improving the efficiency of collecting the state transition time of the chip, but also reducing the test cost. Description of the Drawings

[0028] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments of the present invention. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0029] Figure 1 is a circuit schematic diagram of a chip testing device in an embodiment of the present invention;

[0030] Figure 2 is another circuit schematic diagram of a chip testing device in an embodiment of the present invention;

[0031] Figure 3 is another circuit schematic diagram of a chip testing device in an embodiment of the present invention;

[0032] Figure 4 is another circuit schematic diagram of a chip testing device in an embodiment of the present invention;

[0033] Figure 5 is another circuit schematic diagram of a chip testing device in an embodiment of the present invention. Detailed implementation manners

[0034] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0035] It should be understood that the present invention can be implemented in different forms and should not be construed as limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout the drawings.

[0036] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Thus, without departing from the teachings of the present invention, the first element, component, region, layer or portion discussed below may be denoted as the second element, component, region, layer or portion.

[0037] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "below" other elements or features will be oriented "on" the other elements or features. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0038] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0039] To fully understand the present invention, detailed structures and steps will be set forth in the following description in order to explain the technical solutions proposed by the present invention. The preferred embodiments of the present invention are described in detail below. However, in addition to these detailed descriptions, the present invention may have other embodiments.

[0040] This embodiment provides a chip testing device, such asFigure 1 As shown, it includes a network analyzer 10 and a trigger module 20, and the network analyzer 10, the trigger module 20 and the chip under test 30 are electrically connected. Among them, the network analyzer (VNA) 10 is a radio frequency test device that can perform scanning measurements within a wide frequency band to determine various parameters of the device under test (such as: radio frequency chip). The network analyzer (VNA) 10 can directly measure the performance parameters of active or passive, reversible or irreversible two-port and one-port devices. The network analyzer 10 in this embodiment is preferably a vector network analyzer, and other radio frequency test instruments such as a signal source (signal generator), a spectrum analyzer and an oscilloscope are integrated inside the network analyzer (VNA). Among them, the trigger module 20 is a module for triggering the chip under test 30 to perform a state switch. For example: through the trigger module 20, the switch in the chip under test 30 can be switched from the off state to the on state, or from the on state to the off state, or through the trigger module 20, the chip under test 30 can be triggered to switch from the original state to the target state. Among them, the original state can be the off state, and the target state can be the on state. Preferably, the trigger module 20 can be a MIPI (Mobile Industry Processor Interface) module, a GPIO (General-purpose input / output) module or other modules that can trigger the chip under test 30 to perform a state switch. The chip under test 30 can be a power amplifier chip, a low noise amplifier chip or a switch chip, etc.

[0041] The network analyzer 10, the trigger module 20 and the chip under test 30 are electrically connected to each other. Optionally, the interconnection between the network analyzer 10, the trigger module 20 and the chip under test 30 can be implemented as a cable, a probe, a fixture, a filter or other electrical components capable of delivering signals.

[0042] Among them, the network analyzer 10 is configured to send a trigger instruction to the trigger module 20 and collect the state switching time of the chip under test 30.

[0043] Among them, the trigger instruction is an instruction for triggering the trigger module 20 to send a trigger signal. Specifically, the trigger instruction in this embodiment is used to trigger the trigger module 20 to send a first trigger signal to the test chip 30 to trigger the test chip 30 to perform a state switch. For example: triggering the switching switch in the trigger test chip 30 to perform a state switch.

[0044] In a specific embodiment, one or more switches are integrated in the chip 30 to be tested. The speed of the state switching time of the chip 30 to be tested is an important indicator for evaluating the overall performance of the chip 30 to be tested. Therefore, it is necessary to collect the state switching time of the chip 30 to be tested. In this application, the network analyzer 10 and the trigger module 20 are used to collect the state switching time of the chip 30 to be tested.

[0045] The network analyzer 10, the trigger module 20, and the chip 30 to be tested are electrically connected to each other. The signal source (SG) in the network analyzer 10 outputs an excitation signal to the chip 30 to be tested. The chip 30 to be tested processes the excitation signal and feeds back and outputs a response signal to the spectrum analyzer (SA) in the network analyzer. The spectrum analyzer (SA) can analyze the response signal to obtain the state switching time of the chip 30 to be tested.

[0046] Exemplarily, when it is necessary to collect the state switching time of the chip to be tested, first control the network analyzer 10 to send a trigger instruction to the trigger module 20, and control the network analyzer 10 to start collecting the response signal fed back and output by the chip 30 to be tested within a preset time period. After receiving the trigger instruction sent by the network analyzer 10, the trigger module 20 responds to the trigger instruction and sends a first trigger signal to the chip 30 to be tested. The chip 30 to be tested receives the first trigger signal to perform a state switch. Among them, the preset time period can be custom-set in advance according to the state switching speed of the chip 30 to be tested. Preferably, the preset time period can be 20 us. Further, after the network analyzer collects the response signal fed back and output by the chip 30 to be tested within the preset time period, by analyzing and processing the response signal, the state switching time of the test chip can be obtained.

[0047] Preferably, in this embodiment, in order to improve the accuracy of the response signal collected by the network analyzer, so as to determine the state switching time of the test chip from the response signal. Set the time point when the network analyzer 10 issues a trigger instruction to the trigger module 20 and the time point when the network analyzer 10 starts collecting the response signal fed back and output by the chip 30 to be tested to be the same time point, that is, the network analyzer 10 starts to execute sending a trigger instruction to the trigger module 20 and collecting the response signal fed back and output by the chip 30 to be tested at the same moment.

[0048] Among them, the trigger module 20 is configured to respond to the trigger instruction and send a first trigger signal to the chip to be tested, where the first trigger signal is a signal for triggering the chip 30 to be tested to perform a state switch.

[0049] In a specific embodiment, the state transition time of the chip under test includes the time for the switch in the chip under test to perform a state transition. For example, the first trigger signal is a signal for triggering the switch in the chip under test 30 to perform a state transition. In a specific embodiment, when the trigger module 20 receives the trigger instruction sent by the network analyzer 10, it immediately sends the first trigger signal to the chip under test to trigger the switch in the chip under test to perform a state transition. Exemplarily, if the original state of the switch in the chip under test is the off state, then under the trigger of the first trigger signal, the switch in the chip under test switches from the off state to the on state; or, if the original state of the switch in the chip under test is the on state, then under the trigger of the first trigger signal, the switch in the chip under test switches from the on state to the off state.

[0050] Exemplarily, the network analyzer 10 sends a trigger instruction to the trigger module 20 at time point T1, starts collecting the response signal output by the chip under test 30 at time point T1, and preset the network analyzer 10 to collect the response signal fed back and output by the chip under test 30 within the time period from T1 to T1 + 20 us. After receiving the trigger instruction sent by the network analyzer 10, the trigger module 20 will respond to the trigger instruction and send a first trigger signal to the chip under test 30, and the chip under test 30 receives the first trigger signal to perform a state switch. If it is determined from the analysis of the response signal collected by the network analyzer 10 that the switch in the chip under test has completed the state switch at time point T1 + 10 us, then the state switch time of the chip under test is 10 us. Preferably, the response signal collected in this embodiment is a continuous analog signal, so the state change of the response signal can be directly seen from the collected response signal, and then the state switch time of the chip under test 30 can be determined according to the state change of the response signal. For example, within a time period, the switch in the chip under test 30 switches from the off state to the on state. The response signal in the off state is a low-level signal (a voltage signal of 0V), and the response signal in the on state is a high-level signal (a voltage signal of 1V). If the response signal is a low-level signal (a voltage signal of 0V) at time point T1 and the response signal converts to a high-level signal (a voltage signal of 1V) at time point T1 + 10 us, then the switch-over time of the switch in the test chip can be determined to be 10 us according to the state change of the response signal. In a specific embodiment, usually ninety percent of the switch completing the state switch can confirm that the switch has completed the state switch. For example, within a time period, if the response signal is a low-level signal (a voltage signal of 0V) at time point T1, then when the response signal converts from a voltage signal of 0V to a voltage signal of 0.9V, it can be determined that the switch has completed the switch from the off state to the on state. If the response signal is a high-level signal (a voltage signal of 1V) at time point T1, then when the response signal converts from a voltage signal of 1V to a voltage signal of 0.1V, it can be determined that the switch has completed the switch from the on state to the off state.

[0051] Preferably, since the trigger module 20 operates in a time-division duplex mode, that is, the operating state of the trigger module 20 is not continuous in time sequence. Therefore, there may be a certain delay in time sequence between the trigger module 20 receiving the trigger instruction sent by the network analyzer 10 and sending the first trigger signal to the chip to be tested. For example, the trigger module 20 receives the trigger instruction sent by the network analyzer 10 at time point T1, and the trigger module 20 may send the first trigger signal to the chip to be tested at time point T1 + 2us for state switching. Therefore, if it is analyzed from the response signal collected by the network analyzer 10 that the response signal is a low-level signal (voltage signal of 0V) at time point T1 and is converted into a high-level signal (voltage signal of 1V) at time point T1 + 10us, then the actual state switching time of the chip to be tested should be 10us - 2us = 8us. It should be noted that the delay time period of the trigger module 20 can be detected in advance for the trigger module 20 and determined in advance. After determining the initial state switching time of the chip to be tested 10, only the initial state switching time of the chip to be tested needs to be subtracted by the delay time period of the trigger module 20 to obtain the actual switching time of the chip to be tested.

[0052] It can be understood that since the response signal in this application is a continuous analog signal within a time period, the actual state switching time of the chip to be tested can be determined according to the change in the voltage of the response signal collected within the preset time period, that is, the actual state switching time of the chip to be tested is determined according to the time required for the voltage of the response signal to be converted from 0V to 1V.

[0053] In this embodiment, the chip testing device includes a network analyzer and a trigger module, and the network analyzer, the trigger module and the chip to be tested are electrically connected; the network analyzer is configured to send a trigger instruction to the trigger module and collect the state switching time of the chip to be tested; the trigger module is configured to send a first trigger signal to the chip to be tested in response to the trigger instruction, where the first trigger signal is a signal for triggering the chip to be tested to perform state switching; in this embodiment, the state switching time of the chip to be tested can be collected through the combined action of the network analyzer and the trigger module, without the need to additionally build a complex test environment, thereby not only improving the efficiency of collecting the state switching time of the chip, but also reducing the test cost.

[0054] In a specific embodiment, the sampling period of the network analyzer 10 is equal to or less than one-tenth of the switching time of the switch in the chip to be tested 30. Preferably, the sampling period of the network analyzer in this embodiment is the sampling period for IQ sampling.

[0055] To ensure that the network analyzer 10 can accurately collect the state transition time of the chip 30 to be tested, it is necessary to ensure that the sampling period of the network analyzer 10 is equal to or less than one-tenth of the state transition time of the chip to be tested. It can be understood that since the state transition time of the chip 30 to be tested is often only a few microseconds, that is, the speed of the chip 30 to be tested for state transition is often very fast. Therefore, if the sampling period of the network analyzer 10 is too large, it is impossible to accurately collect the state transition time of the chip 30 to be tested in an extremely short time.

[0056] Furthermore, the sampling period of the network analyzer is 10 ns - 1 μs. In a specific embodiment, the state transition time of the chip 30 to be tested is usually 100 ns - 10 μs. Therefore, to ensure that the network analyzer 10 can accurately collect the state transition time of the chip 30 to be tested, the sampling period of the network analyzer should be equal to or less than one-tenth of the state transition time of the chip to be tested. In this embodiment, the sampling period of the network analyzer is equal to one-tenth of the state transition time of the chip to be tested, that is, the sampling period of the network analyzer is 10 ns - 1 μs.

[0057] In a specific embodiment, as shown below Figure 2 The network analyzer 10 includes L connection ports ( Figure 2 illustrated by taking 6 connection ports as an example), and 1 first trigger port, where L is a positive integer equal to or greater than 1. The connection ports are configured to output an excitation signal to the chip to be tested and / or receive the response signal output by the chip to be tested, where the response signal is a signal output by the chip to be tested based on the excitation signal. The first trigger port is configured to send a trigger instruction to the trigger module. For example, if the chip to be tested is a power amplifier, the response signal may be a signal obtained by the chip to be tested after amplifying the excitation signal. Since the purpose of this embodiment is to collect the state transition time of the chip to be tested, the response signal is a signal indicating that the test chip performs a state transition.

[0058] In a specific embodiment, if the L connection ports are unidirectional transmission ports, a part of the L connection ports can be used as transmission ports for outputting excitation signals to the chip under test, and another part of the connection ports can be used as receiving ports for receiving the response signals output by the chip under test, where the response signal is a signal output by the chip under test based on the excitation signal. Preferably, the number of transmission ports for outputting excitation signals to the chip under test is equal to the number of receiving ports for receiving the response signals output by the chip under test. Exemplarily, the network analyzer includes two connection ports, namely a first connection port and a second connection port, where the first connection port is a transmission port for outputting excitation signals to the chip under test, and the second connection port is a receiving port for receiving the response signals output by the chip under test.

[0059] In another specific embodiment, if the L connection ports are bidirectional transmission ports, each of the L connection ports can output an excitation signal to the chip under test and can also receive the response signal output by the chip under test. In the actual application process, when it is necessary to test the voltage standing wave ratio (VSWR) of the chip under test, the L connection ports need to be designed as bidirectional transmission ports, that is, each connection port can output an excitation signal to the chip under test and can also receive the response signal output by the chip under test. Exemplarily, the network analyzer includes two connection ports, namely a first connection port and a second connection port, where the first connection port can output an excitation signal to the chip under test and can also receive the response signal output by the chip under test, and the second connection port can output an excitation signal to the chip under test and can also receive the response signal output by the chip under test.

[0060] Refer to the following Figure 3 As shown, in a specific embodiment, the L connection ports include A first connection ports and B second connection ports; the first connection ports are configured to output excitation signals to the chip under test, and the second connection ports are configured to receive the response signals output by the chip under test, where the response signal is a signal output by the chip under test based on the excitation signal.

[0061] In this embodiment, the connection ports are all unidirectional transmission ports. The first connection port is a sending port for outputting an excitation signal to the chip under test, and the second connection port is a receiving port for receiving the response signal output by the chip under test. The excitation signal output by the network analyzer is transmitted to the chip under test through the first connection port. After receiving the excitation signal, the chip under test feeds back and outputs a response signal to be transmitted to the second connection port of the network analyzer. It can be understood that in this embodiment, after a first connection port and a second connection port of the chip under test are respectively connected to the chip under test, a signal transmission loop for testing a certain performance of the chip under test can be formed. Preferably, the number A of the first connection ports and the number B of the second connection ports among the L connection ports are the same, and one first connection port corresponds to one second connection port, so as to form L / 2 signal transmission loops, so as to realize the testing of L / 2 chips under test by one network analyzer, thereby improving the testing efficiency.

[0062] Exemplarily, the network analyzer includes four connection ports, including two first connection ports and two second connection ports. One of the first connection ports is used to output a first excitation signal to the first chip under test, and one of the second connection ports is a receiving port for receiving the first response signal output by the first chip under test. The first response signal is a signal fed back and output by the first chip under test after receiving the first excitation signal. One of the first connection ports and one of the second connection ports form a first signal transmission loop. The other first connection port is used to output a second excitation signal to the second chip under test, and the other second connection port is a receiving port for receiving the second response signal output by the second chip under test. The second response signal is a signal fed back and output by the second chip under test after receiving the second excitation signal. The other first connection port and the other second connection port form a second signal transmission loop, so as to realize the testing of two chips under test by one network analyzer, thereby improving the testing efficiency.

[0063] In a specific embodiment, the network analyzer 10 is configured to collect the response signal output by the chip under test within a preset time period to collect the state switching time of the chip under test.

[0064] Among them, the preset time period is a time period set in advance according to the state switching time of the chip to be tested. For example: the preset time period can be 15us, 20us or 25us, and the user can customize the setting according to the actual situation. In a specific embodiment, before using the network analyzer 10 to collect the state switching time of the chip to be tested, it is necessary to configure the preset time period for the network analyzer 10 to collect in advance. Exemplarily, the network analyzer 10 is configured in advance so that the network analyzer 10 collects the response signal output by the chip to be tested within 20us, and then analyzes and processes the response signal within the collected preset time period, so as to obtain the state switching time of the chip to be tested. It should be noted that the preset time period must include the time period during which the chip to be tested undergoes a state switch, that is, the state switch of the chip to be tested occurs within the preset time period.

[0065] In a specific embodiment, the network analyzer 10 is configured to start collecting the response signal output by the chip to be tested 30 when sending a trigger instruction to the trigger module 20. Since after the network analyzer 10 sends a trigger instruction to the trigger module 20, the trigger module 20 will immediately respond to the trigger instruction to send a trigger signal to the chip to be tested 30, and under the action of this trigger signal, the chip to be tested 30 undergoes a state switch, that is, the time interval between the time point when the network analyzer 10 sends a trigger instruction to the trigger module 20 and the time point when the chip to be tested 30 undergoes a state switch is very short. Therefore, if the network analyzer 10 starts collecting the response signal output by the chip to be tested 30 after sending a trigger instruction to the trigger module 20, it may not be possible to ensure that the collected response signal contains the signal indicating the chip to be tested 30 from before the state switch to after the state switch, that is, the chip to be tested 30 may start collecting the response signal output by the chip to be tested 30 at a certain time point during the state switch of the chip to be tested 3, and then it is impossible to determine the state switching time of the chip to be tested 30 from the collected response signal output by the chip to be tested 30 finally.

[0066] In view of this, the network analyzer 10 of the present application is configured to start collecting the response signal output by the chip to be tested 30 when sending a trigger instruction to the trigger module 20. That is, the time point when the network analyzer issues a trigger instruction to the trigger module 20 and the time point when it starts collecting the response signal fed back and output by the chip to be tested 30 are the same time point, that is, a trigger instruction is issued to the trigger module 20 and the response signal fed back and output by the chip to be tested 30 is collected at the same moment of the chip to be tested 30.

[0067] Refer to the following Figure 4As shown, in a specific embodiment, the chip testing device further includes Z radio frequency switch modules 40. Each radio frequency switch module 40 includes a first switching port and M second switching ports. The first switching port of each radio frequency switch module 40 is connected to a connection port in the network analyzer, and each second switching port is connected to a test port in the chip to be tested. Here, Z is a positive integer greater than or equal to 1, and M is a positive integer greater than or equal to 1. Preferably, in order to expand the ports of each connection port in the network analyzer, the number Z of the radio frequency switch modules 40 is the same as the number M of the connection ports of the network analyzer.

[0068] In an actual application process, the chip 30 to be tested may include multiple different test ports. Different test ports may correspond to different test items, or different test ports correspond to different switches in the chip 30 to be tested. By connecting to different test ports, the switching time of different switches in the chip 30 to be tested can be collected. Preferably, in this embodiment, different test ports can correspond to collecting the switching time of different switches in the chip 30 to be tested. Therefore, in order to improve the test efficiency, in this embodiment, a single-pole M-throw radio frequency switch module 40 is connected between the network analyzer 10 and the chip 30 to be tested. Each radio frequency switch module 40 includes a first switching port and M second switching ports. Among them, the first switching port of the radio frequency switch module 40 is connected to a connection port in the network analyzer 10, and each second switching port of the radio frequency switch module 40 is connected to a test port in the corresponding chip to be tested; thus, during the process of testing the chip to be tested, according to different test requirements, by flexibly adjusting the switching state of the radio frequency switch module 40, different sequencing items of the chip 30 to be tested can be tested, or the switching time of different switches in the chip 30 to be tested can be collected. The chip testing device has stronger versatility, not only improving the test efficiency, but also simplifying the test operation, which is beneficial to the production test of the chip.

[0069] Exemplarily, if the network analyzer 10 includes six connection ports, and every two connection ports form a group for testing one of the chips 30 to be tested. One of the connection ports in each group serves as the first connection port to output an excitation signal to the chip to be tested, and the other connection port serves as the second connection port to receive the response signal output by the chip to be tested, thereby forming three test transmission loops to simultaneously collect the switching times of the switches in three chips 30 to be tested. Since the network analyzer in this embodiment includes six connection ports, six single-pole M-throw RF switch modules 40 are connected between the network analyzer 10 and the chips 30 to be tested. It can be understood that in order to expand each connection port of the network analyzer, the number of RF switch modules 40 is the same as the number of connection ports of the network analyzer.

[0070] Exemplarily, the RF switch module 40 is a single-pole 8-throw switch, that is, each RF switch module 40 includes a first switching port and eight second switching ports. The first switching port of each RF switch module 40 is connected to a connection port of the corresponding network analyzer, and each second switching port of each RF switch module 40 is connected to a test port of the corresponding chip 30 to be tested. It is equivalent to expanding each connection port of the network analyzer to eight ports, and each chip 30 to be tested has 16 test ports. Thus, according to different test requirements, by flexibly adjusting the switching states of the RF switch modules 40, the switching times of different switches in the chips 30 to be tested can be collected, thereby improving the data collection efficiency.

[0071] Refer to the following Figure 5 As shown, in a specific embodiment, the chip testing device further includes N isolation switch modules 50. Each isolation switch module 50 includes a moving end, a first fixed end, and a second fixed end. The moving end of each isolation switch module 50 is connected to a test port in the corresponding chip 30 to be tested. The first fixed end of each isolation switch module 50 is connected to a second switching port in the RF switch module 40, and the second fixed end of each isolation switch module 50 is coupled to the ground terminal.

[0072] As can be seen from the above embodiments, by connecting a radio frequency switch module 40 between the network analyzer 10 and the chip 30 to be tested, it is possible to collect the switching times of different switches in the chip 30 to be tested by flexibly adjusting the switching state of the radio frequency switch module 40 according to different test requirements. However, since the radio frequency switch module 40 is a single-pole M-throw switch, when the first switching port of the radio frequency switch module 40 is switched to be connected to the first second switching port to collect the switching time of a certain switch in the chip 30 to be tested, the remaining second switching ports not connected to the first switching port are all in a floating state, resulting in the signal on the path formed between the first switching port and the first second switching port being easily leaked into other floating second switching ports, thereby affecting the test efficiency and accuracy.

[0073] In view of this, in this embodiment, N isolation switch modules 50 are connected between the radio frequency switch module 40 and the chip 30 to be tested. Preferably, in order to improve the isolation degree between each second switching port in the radio frequency switch module 40, the number N of the isolation switch modules 50 is the same as the number M of the second switching ports of the radio frequency switch module 40. Specifically, the isolation switch module 50 is a single-pole double-throw switch. The moving end of each isolation switch module 50 is connected to a test port of the corresponding chip 30 to be tested. The first fixed end of each isolation switch module 50 is connected to a second switching port in the corresponding radio frequency switch module 40. When the first switching port of the radio frequency switch module 40 is switched to be connected to the first second switching port, the moving end of the isolation switch module 50 connected to the first second switching port is switched to be connected to the first fixed end, and the moving ends of the remaining isolation switch modules 50 are all switched to be connected to the second fixed end. The second fixed end of the isolation switch module 50 is coupled to the ground terminal; thus, while improving the collection efficiency of the switching time of the switch in the chip to be tested, it is also possible to avoid signal interference and leakage phenomena due to the formation of multiple different paths between the radio frequency switch module 40 and the isolation switch module 50, thereby improving the accuracy of the network analyzer in collecting the switching time of the switch in the chip to be tested.

[0074] Preferably, in a specific embodiment, in order to improve the integrated design of the chip test device, all the radio frequency switch modules 40 and all the isolation switch modules 50 in this embodiment are integrated in a radio frequency switch box. By switching the states of the radio frequency switch module 4 and the isolation switch module 50 in the radio frequency switch box, different test requirements can be met, thereby not only realizing the port expansion of the network analyzer 10, but also reducing the occupied area of the chip test device.

[0075] In a specific embodiment, the disconnector module further includes an impedance matching unit. The second fixed end of the disconnector module is connected to the first end of the impedance matching unit, and the second end of the impedance matching unit is connected to the ground terminal.

[0076] Among them, the impedance matching unit is a component for implementing impedance matching. Preferably, the impedance matching unit in this embodiment is a resistor R. In the actual application process, in order to achieve the maximum transmission power of the signal, it is usually necessary to satisfy an impedance matching of 50 ohms. Therefore, the second fixed end of the disconnector module in this application is connected to the ground terminal through a 50-ohm resistor R, which not only ensures the stability of the switch state, but also improves the signal transmission efficiency and reduces the signal loss during the transmission process.

[0077] This embodiment also provides a chip testing device, including a network analyzer 10 and a trigger module 20. The network analyzer 10, the trigger module 20, and the chip to be tested 30 are electrically connected. The network analyzer 10, the trigger module 20, and the chip to be tested 30 are electrically connected to each other. Optionally, the interconnection between the network analyzer 10, the trigger module 20, and the chip to be tested 30 can be implemented as a cable, a probe, a fixing device, a filter, or other electrical components capable of transmitting signals.

[0078] The network analyzer 10 includes L connection ports and a first trigger port, where L is a positive integer greater than or equal to 1. The connection ports are electrically connected to the test ports of the chip to be tested 30. The connection ports are configured to output an excitation signal to the test ports of the chip to be tested 30 and / or receive the response signal output from the test ports of the chip to be tested 30, where the response signal is a signal output by the chip to be tested based on the excitation signal.

[0079] Among them, the connection port is a port for connecting to the chip to be tested 30. The connection port can be a bidirectional transmission port or a unidirectional transmission port. If the connection port is a bidirectional transmission port, the connection port is configured to output an excitation signal to the chip to be tested 30 and receive the response signal output from the test ports of the chip to be tested 30. Exemplarily, the network analyzer includes two connection ports, namely a first connection port and a second connection port. The first connection port can output an excitation signal to the chip to be tested and receive the response signal output by the chip to be tested, and the second connection port can output an excitation signal to the chip to be tested and receive the response signal output by the chip to be tested.

[0080] In another specific embodiment, if the connection port is a unidirectional transmission port, the connection port is configured to output an excitation signal to the chip under test 30, or receive a response signal output from the test port of the chip under test 30. Wherein, the first trigger port is a port connected to the trigger module 20. The network analyzer 10 sends a trigger instruction to the trigger module 20 through the first trigger port. Preferably, the network analyzer 10 can send the trigger instruction to the trigger module 20 by means of backplane triggering. Exemplarily, the network analyzer includes two connection ports, namely a first connection port and a second connection port. Among them, the first connection port is a transmission port for outputting an excitation signal to the chip under test, and the second connection port is a receiving port for receiving the response signal output by the chip under test.

[0081] Refer to the following Figure 3 As shown, in a specific embodiment, the L connection ports include A first connection ports and B second connection ports; the first connection ports are configured to output excitation signals to the chip under test, and the second connection ports are configured to receive the response signals output by the chip under test, wherein the response signal is a signal output by the chip under test based on the excitation signal.

[0082] In this embodiment, the connection ports are all unidirectional transmission ports. The first connection port is a transmission port for outputting an excitation signal to the chip under test, and the second connection port is a receiving port for receiving the response signal output by the chip under test. The excitation signal output by the network analyzer is transmitted to the chip under test through the first connection port. After receiving the excitation signal, the chip under test feeds back and outputs a response signal to be transmitted to the second connection port of the network analyzer. It can be understood that in this embodiment, after a first connection port and a second connection port of the chip under test are respectively connected to the chip under test, a signal transmission loop for testing a certain performance of the chip under test can be formed. Preferably, the number A of the first connection ports and the number B of the second connection ports in the L connection ports are the same, and one first connection port corresponds to one second connection port, so as to form L / 2 signal transmission loops, so as to realize that one network analyzer can test L / 2 chips under test, thereby improving the test efficiency.

[0083] Exemplarily, the network analyzer includes four connection ports, including two first connection ports and two second connection ports. One of the first connection ports is used to output a first excitation signal to a first chip under test, and one of the second connection ports is a receiving port for receiving the first response signal output by the first chip under test. The first response signal is a signal fed back and output by the first chip under test after receiving the first excitation signal. The one first connection port and the one second connection port form a first signal transmission loop. The other first connection port is used to output a second excitation signal to a second chip under test, and the other second connection port is a receiving port for receiving the second response signal output by the second chip under test. The second response signal is a signal fed back and output by the second chip under test after receiving the second excitation signal. The other first connection port and the other second connection port form a second signal transmission loop, so as to enable two chips under test to be tested by one network analyzer, thereby improving the test efficiency.

[0084] The trigger module 20 includes a first input port and a first output port. The first trigger port is electrically connected to the first input port of the trigger module and is configured to send a trigger instruction to the trigger module; the first output port of the trigger module is electrically connected to the second trigger port of the chip under test and is configured to send a first trigger signal to the chip under test. The first trigger signal is a signal for triggering the chip under test to perform a state switch.

[0085] Among them, the first input port is a port for connecting to the network analyzer 10 to receive the trigger instruction sent by the network analyzer 10. The first output port is a port for connecting to the chip under test 30 to send a first trigger signal to the chip under test 30. Optionally, the trigger module 20 may be a MIPI (Mobile Industry Processor Interface) module or a GPIO (General-purpose input / output) module, etc.

[0086] Exemplarily, the network analyzer 10, the trigger module 20, and the chip under test 30 are electrically connected to each other. The signal source (SG) in the network analyzer 10 outputs an excitation signal to the chip under test 30, and the chip under test 30 processes the excitation signal and feeds back and outputs a response signal to the spectrum analyzer (SA) in the network analyzer. Specifically, when it is necessary to collect the state switching time of the chip under test, first, a trigger instruction is sent from the network analyzer to the trigger module 20 by control and the response signal fed back and output by the chip under test 30 within a preset time period is collected. After receiving the trigger instruction, the trigger module 20 immediately responds to the trigger instruction and sends a first trigger signal to the chip under test 30, and the chip under test 30 performs a state switch based on the first trigger signal. Among them, the preset time period can be custom-set in advance according to the state switching speed of the chip under test 30. Preferably, the preset time period is 20 us. After the network analyzer collects the response signal fed back and output by the chip under test 30 within the preset time period, the state switching time of the test chip can be obtained by performing signal processing on the response signal. Preferably, the state switching time of the chip under test includes the time for the switch in the chip under test to perform a state switch.

[0087] In a specific embodiment, the network analyzer is configured to collect the state switching time in the chip under test by collecting the response signal output from the test port of the chip under test within a preset time period.

[0088] Among them, the preset time period is a time period set in advance according to the state switching time of the chip under test. For example: the preset time period can be 15 us, 20 us, or 25 us, and the user can customize the setting according to the actual situation. In a specific embodiment, before using the network analyzer 10 to collect the state switching time of the chip under test, it is necessary to configure the preset time period for the network analyzer 10 to collect in advance. Exemplarily, the network analyzer 10 is configured in advance so that the network analyzer 10 collects the response signal output by the chip under test within 20 us, and then analyzes and processes the response signal within this time period collected, so as to obtain the state switching time in the chip under test. It should be noted that the preset time period must include the time period from before the state of the chip under test switches to after the switch, that is, the state switch of the chip under test occurs within the preset time period.

[0089] This embodiment also provides a chip testing system, which includes a chassis and the chip testing device described in the above embodiment. The chip testing device is integrated in the chassis, that is, the network analyzer, trigger module, RF switch module, and isolation switch module in the chip testing device are all integrated in the chassis, which is conducive to the integrated design of the chip testing system and saves the occupied area of the chip testing system. Further, a power supply module for powering the network analyzer, trigger module, RF switch module, and isolation switch module in the chip testing system is usually also integrated in the chassis. It should be noted that the beneficial effects achievable by the chip testing device in the above embodiment can also be achieved by the chip testing system in this embodiment, and will not be elaborated here.

[0090] This embodiment also provides a data acquisition method, which is applied to a chip testing device. The chip testing device includes a network analyzer 10 and a trigger module 20. The network analyzer 10, the trigger module 20, and the chip under test 30 are electrically connected. The network analyzer 10, the trigger module 20, and the chip under test 30 are electrically connected to each other. Optionally, the interconnection among the network analyzer 10, the trigger module 20, and the chip under test 30 can be implemented as a cable, probe, fixture, filter, or other electrical components capable of transmitting signals.

[0091] The network analyzer 10 sends a trigger instruction to the trigger module 20 and acquires the state switching time of the chip under test 30. Preferably, the state switching time of the chip under test includes the time for the switch in the chip under test to switch states.

[0092] In a specific embodiment, refer to the following Figure 2 As shown, the network analyzer 10 includes L connection ports ( Figure 2 illustrated with 6 connection ports as an example), and 1 first trigger port, where L is a positive integer greater than or equal to 1. The connection ports are configured to output an excitation signal to the chip under test and / or receive the response signal output by the chip under test, where the response signal is the signal output by the chip under test based on the excitation signal. The first trigger port is configured to send a trigger instruction to the trigger module. For example, if the chip under test is a power amplifier, the response signal can be the signal after the chip under test amplifies the excitation signal. Since the purpose of this embodiment is to acquire the state switching time of the chip under test, the response signal is a signal indicating the state switching of the test chip.

[0093] In a specific embodiment, if the L connection ports are unidirectional transmission ports, a part of the L connection ports can be used as transmission ports for outputting excitation signals to the chip under test, and another part of the connection ports can be used as receiving ports for receiving response signals output by the chip under test, where the response signal is a signal output by the chip under test based on the excitation signal. Preferably, the number of transmission ports for outputting excitation signals to the chip under test is equal to the number of receiving ports for receiving response signals output by the chip under test. Exemplarily, the network analyzer includes two connection ports, namely a first connection port and a second connection port, where the first connection port is a transmission port for outputting excitation signals to the chip under test, and the second connection port is a receiving port for receiving response signals output by the chip under test.

[0094] In another specific embodiment, if the L connection ports are bidirectional transmission ports, each of the L connection ports can output an excitation signal to the chip under test and can also receive a response signal output by the chip under test. In actual application, when it is necessary to test the voltage standing wave ratio (VSWR) of the chip under test, the L connection ports need to be designed as bidirectional transmission ports, that is, each of the connection ports can output an excitation signal to the chip under test and can also receive a response signal output by the chip under test. Exemplarily, the network analyzer includes two connection ports, namely a first connection port and a second connection port, where the first connection port can output an excitation signal to the chip under test and can also receive a response signal output by the chip under test, and the second connection port can output an excitation signal to the chip under test and can also receive a response signal output by the chip under test.

[0095] Refer to the following Figure 3 As shown, in a specific embodiment, the L connection ports include A first connection ports and B second connection ports; the first connection ports are configured to output excitation signals to the chip under test, and the second connection ports are configured to receive response signals output by the chip under test, where the response signal is a signal output by the chip under test based on the excitation signal.

[0096] In this embodiment, the connection ports are all unidirectional transmission ports. The first connection port is a transmitting port for outputting an excitation signal to the chip under test, and the second connection port is a receiving port for receiving the response signal output by the chip under test. The excitation signal output by the network analyzer is transmitted to the chip under test through the first connection port. After receiving the excitation signal, the chip under test feeds back and outputs a response signal to be transmitted to the second connection port of the network analyzer. It can be understood that in this embodiment, after a first connection port and a second connection port of the chip under test are respectively connected to the chip under test, a signal transmission loop for testing a certain performance of the chip under test can be formed. Preferably, the number A of the first connection ports and the number B of the second connection ports among the L connection ports are the same, and one first connection port corresponds to one second connection port, so as to form L / 2 signal transmission loops, so as to realize the testing of L / 2 chips under test by one network analyzer, thereby improving the testing efficiency.

[0097] Exemplarily, the network analyzer includes four connection ports, including two first connection ports and two second connection ports. One of the first connection ports is used to output a first excitation signal to the first chip under test, and one of the second connection ports is a receiving port for receiving the first response signal output by the first chip under test. The first response signal is a signal fed back and output by the first chip under test after receiving the first excitation signal. One of the first connection ports and one of the second connection ports form a first signal transmission loop. The other first connection port is used to output a second excitation signal to the second chip under test, and the other second connection port is a receiving port for receiving the second response signal output by the second chip under test. The second response signal is a signal fed back and output by the second chip under test after receiving the second excitation signal. The other first connection port and the other second connection port form a second signal transmission loop, so as to realize the testing of two chips under test by one network analyzer, thereby improving the testing efficiency.

[0098] The trigger module 20 responds to the trigger instruction and sends a first trigger signal to the chip under test 30, where the first trigger signal is a signal for triggering the switch in the chip under test to perform a state switch.

[0099] Among them, the trigger instruction is used to trigger the trigger module 20 to send a first trigger signaling. Specifically, this trigger instruction is used to trigger the trigger module 20 to send a first trigger signal to the chip under test 30 to trigger the chip under test 30 to perform a state transition. Among them, the first trigger signal is a signal used to trigger the chip under test 30 to perform a state transition. Preferably, the first trigger signal is a signal used to trigger the switch in the chip under test 30 to perform a state transition.

[0100] Specifically, while sending the trigger instruction to the trigger module 20, the network analyzer 10 starts to collect the state transition time in the chip under test 30. In this embodiment, the network analyzer 10 collects the state transition time of the chip under test 30 by collecting the response signal fed back and output by the chip under test 30.

[0101] Exemplarily, the network analyzer 10, the trigger module 20, and the chip under test 30 are always in an electrically connected state with each other. The signal source (SG) in the network analyzer 10 outputs an excitation signal to the chip under test 30, and the chip under test 30 processes the excitation signal and feeds back and outputs a response signal to the spectrum analyzer (SA) in the network analyzer. Specifically, when it is necessary to collect the state transition time of the chip under test, first, the network analyzer is controlled to send a trigger instruction to the trigger module 20 and start to collect the response signal fed back and output by the chip under test 30 within a preset time period. After receiving the trigger instruction, the trigger module 20 will immediately respond to the trigger instruction and send a first trigger signal to the chip under test 30, and the chip under test 30 will perform a state transition based on this first trigger signal. Among them, the preset time period can be custom-set in advance according to the state transition speed of the chip under test 30. Preferably, the preset time period is 20 us. After the network analyzer controls to collect the response signal fed back and output by the chip under test 30 within the preset time period, by performing signal processing on this response signal, the state transition time in the test chip can be obtained. In a specific embodiment, before using the network analyzer 10 to collect the state transition time of the chip under test, it is necessary to pre-configure the preset time period for the network analyzer 10 to collect. Exemplarily, the network analyzer 10 is pre-configured so that the network analyzer 10 collects the response signal output by the chip under test within 20 us, and then analyzes and processes the response signal within this preset time period collected, so as to obtain the state transition time of the chip under test. It should be noted that the preset time period must include the time period during which the chip under test undergoes a state transition, that is, the state transition of the chip under test occurs within the preset time period.

[0102] In a specific embodiment, the network analyzer 10 is configured to start collecting the response signal output by the chip under test 30 when sending a trigger instruction to the trigger module 20. Since after the network analyzer 10 sends a trigger instruction to the trigger module 20, the trigger module 20 will immediately respond to the trigger instruction to send a trigger signal to the chip under test 30, and under the action of this trigger signal, the chip under test 30 performs a state switch, that is, the time interval between the time point when the network analyzer 10 sends a trigger instruction to the trigger module 20 and the time point when the chip under test 30 performs a state switch is very short. Therefore, if the network analyzer 10 starts collecting the response signal output by the chip under test 30 after sending a trigger instruction to the trigger module 20, it may not be possible to ensure that the collected response signal contains the signal indicating the chip under test 30 from before the state switch to after the state switch, that is, the chip under test 30 may start collecting the response signal output by the chip under test 30 at a certain time point during the state switch of the chip under test 3, and further makes it impossible to determine the state switch time of the chip under test 30 from the collected response signal output by the chip under test 30 finally.

[0103] In view of this, the network analyzer 10 of the present application is configured to start collecting the response signal output by the chip under test 30 when sending a trigger instruction to the trigger module 20. That is, the time point when the network analyzer issues a trigger instruction to the trigger module 20 and the time point when it starts collecting the response signal fed back and output by the chip under test 30 are the same time point, that is, a trigger instruction is issued to the trigger module 20 and the response signal fed back and output by the chip under test 30 is collected at the same moment of the chip under test 30.

[0104] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A chip testing device, characterized in that, it includes a network analyzer and a trigger module, and the network analyzer, the trigger module and the chip to be tested are electrically connected; the network analyzer is configured to send a trigger instruction to the trigger module and collect the state switching time of the chip to be tested; the trigger module is configured to send a first trigger signal to the chip to be tested in response to the trigger instruction, wherein the first trigger signal is a signal for triggering the chip to be tested to perform a state switch; the chip testing device further includes Z radio frequency switch modules, each radio frequency switch module includes a first switching port and M second switching ports, the first switching port of each radio frequency switch module is connected to a connection port in the network analyzer, and each second switching port is coupled to a test port in the chip to be tested, wherein Z is a positive integer greater than or equal to 1, and M is a positive integer greater than or equal to 1; the chip testing device further includes N isolation switch modules, each isolation switch module includes a moving end, a first fixed end, a second fixed end and an impedance matching unit, the moving end of each isolation switch module is connected to a test port in the chip to be tested, the first fixed end of each isolation switch module is connected to a second switching port in the radio frequency switch module, the second fixed end of each isolation switch module is connected to the first end of the impedance matching unit, and the second end of the impedance matching unit is connected to the ground end, wherein N is a positive integer greater than or equal to 1.

2. The chip testing device according to claim 1, characterized in that, the sampling period of the network analyzer is equal to or less than one tenth of the state switching time of the chip to be tested.

3. The chip testing device according to claim 1, characterized in that, the sampling period of the network analyzer is 10ns - 1us.

4. The chip testing device according to claim 1, characterized in that, the state switching time of the chip to be tested includes the time for the switch in the chip to be tested to perform a state switch.

5. The chip testing device according to claim 1, characterized in that, the network analyzer includes L connection ports and a first trigger port, wherein L is a positive integer greater than or equal to 1; the connection ports are configured to output an excitation signal to the chip to be tested and / or receive a response signal output by the chip to be tested, wherein the response signal is a signal output by the chip to be tested based on the excitation signal; the first trigger port is configured to send a trigger instruction to the trigger module.

6. The chip testing device according to claim 5, characterized in that, The L connection ports include A first connection ports and B second connection ports; the first connection ports are configured to output excitation signals to the chip under test, and the second connection ports are configured to receive response signals output by the chip under test, where the response signals are signals output by the chip under test based on the excitation signals, and where A is a positive integer greater than or equal to 1, and B is a positive integer greater than or equal to 1.

7. The chip testing device according to claim 5, wherein, the network analyzer is configured to collect the response signals output by the chip under test within a preset time period to collect the state switching time of the chip under test.

8. The chip testing device according to claim 7, wherein, the network analyzer is configured to start collecting the response signals output by the chip under test when sending a trigger instruction to the trigger module.

9. A chip testing device, wherein, comprising a network analyzer and a trigger module, the network analyzer, the trigger module and the chip under test are electrically connected; the network analyzer includes L connection ports and a first trigger port; the trigger module includes a first input port and a first output port, where L is a positive integer greater than or equal to 1; each of the connection ports is electrically connected to a test port in the chip under test, and the connection ports are configured to output excitation signals to the test ports of the chip under test, and / or, receive response signals output by the test ports of the chip under test, where the response signals are signals output by the chip under test based on the excitation signals; the first trigger port is electrically connected to the first input port of the trigger module and is configured to send a trigger instruction to the trigger module; the first output port of the trigger module is electrically connected to the second trigger port of the chip under test and is configured to send a first trigger signal to the chip under test, where the first trigger signal is a signal for triggering the chip under test to perform a state switch; the chip testing device further includes Z radio frequency switch modules, each radio frequency switch module includes a first switching port and M second switching ports, the first switching port of each radio frequency switch module is connected to one of the connection ports in the network analyzer, and each second switching port is coupled to one of the test ports in the chip under test, where Z is a positive integer greater than or equal to 1, and M is a positive integer greater than or equal to 1; the chip testing device further includes N isolation switch modules, each isolation switch module includes a moving end, a first fixed end, a second fixed end and an impedance matching unit, the moving end of each isolation switch module is connected to one of the test ports in the chip under test, the first fixed end of each isolation switch module is connected to one of the second switching ports in the radio frequency switch module, the second fixed end of each isolation switch module is connected to the first end of the impedance matching unit, and the second end of the impedance matching unit is connected to the ground terminal, where N is a positive integer greater than or equal to 1.

Images