Bandgap reference circuit and analog integrated circuit

Abstract

The present application discloses a bandgap reference circuit and an analog integrated circuit. The bandgap reference circuit includes a current mode regulator for accessing a power supply voltage; a bandgap reference voltage generation circuit, whose power supply input terminal is connected to the power supply output terminal of the current mode regulator; a fully CMOS bandgap core circuit, whose power supply input terminal is connected to the power supply output terminal of the current mode regulator. The fully CMOS bandgap core circuit is used to generate a bandgap reference current and mirror it to the bandgap reference voltage generation circuit, so that the bandgap reference voltage generation circuit generates a bandgap reference voltage. The present application improves the stability of the bandgap reference circuit and reduces the power consumption of the bandgap reference circuit itself.

Description

Technical Field

[0001] This application relates to the field of analog integrated circuit technology, and particularly to a bandgap reference circuit and an analog integrated circuit. Background Art

[0002] Bandgap reference circuits are widely used in various integrated circuits such as analog, mixed-signal, and power management circuits. The purpose is to establish a DC voltage or current that is independent of the power supply voltage VDD, temperature, and process. The design quality of the bandgap reference circuit directly affects the performance of the chip circuit and even the entire system. Circuits such as data converters, comparators, and error amplifiers all require the bandgap reference circuit to provide an accurate and stable bandgap reference voltage and bandgap reference current. Therefore, the design of the bandgap reference circuit occupies an important position in the entire circuit system. Factors such as the area, power consumption, and PSRR of the bandgap reference circuit are likely to affect stability and reliability. Summary of the Invention

[0003] The main purpose of this application is to propose a bandgap reference circuit and an analog integrated circuit, aiming to overcome the problem that the bandgap reference cannot well meet the design requirements due to the compromise of the bandgap reference area, power consumption, and PSRR performance in the prior art, and to design a new bandgap reference circuit to improve the power supply rejection ratio (PSRR) performance on the basis of reducing power consumption and area.

[0004] To achieve the above object, this application proposes a bandgap reference circuit, which includes a current mode regulator, a fully CMOS bandgap core circuit, and a bandgap reference voltage generation circuit; the current mode regulator is used to connect to the power supply voltage.

[0005] The power input terminal of the bandgap reference voltage generation circuit is connected to the power output terminal of the current mode regulator.

[0006] The fully CMOS bandgap core circuit, whose power input terminal is connected to the power output terminal of the current mode regulator, is used to generate a bandgap reference current and mirror it to the bandgap reference voltage generation circuit, so that the bandgap reference voltage generation circuit generates a bandgap reference voltage.

[0007] Optionally, the fully CMOS bandgap core circuit includes:

[0008] A first MOS transistor and a second MOS transistor, both of which are electrically connected to the current mode regulator;

[0009] A diode-connected third MOS transistor and a fourth MOS transistor, the third MOS transistor is connected in series with the first MOS transistor, and the second MOS transistor is connected in series with the fourth MOS transistor;

[0010] A first resistor, serially arranged between the first MOS transistor and the third MOS transistor;

[0011] A second resistor, arranged in parallel with the third MOS transistor; the third MOS transistor, the first resistor, and the second resistor are used to generate a bandgap reference current, and mirror it to the bandgap reference voltage generation circuit through the second MOS transistor and the fourth MOS transistor, so that the bandgap reference voltage generation circuit generates a bandgap reference voltage.

[0012] Optionally, the third MOS transistor and / or the fourth MOS transistor operate in the weak inversion region.

[0013] Optionally, the bandgap reference circuit further includes:

[0014] A self - biased operational amplifier, the first input terminal of the self - biased operational amplifier is connected to the drain of the first MOS transistor, the second input terminal of the self - biased operational amplifier is connected to the drain of the second MOS transistor, and the output terminal of the self - biased operational amplifier is connected to the controlled terminal of the current mode regulator.

[0015] Optionally, the bandgap reference circuit further includes:

[0016] A power supply rejection ratio enhancement circuit, the controlled terminal of the power supply rejection ratio enhancement circuit is connected to the self - biased operational amplifier, the input terminal of the power supply rejection ratio enhancement circuit is connected to the power supply output terminal VR of the current mode regulator, and the output terminal of the power supply rejection ratio enhancement circuit is connected to the controlled terminal of the bandgap reference voltage generation circuit.

[0017] Optionally, the power supply rejection ratio enhancement circuit includes:

[0018] A fifth MOS transistor and a sixth MOS transistor, the gate of the fifth MOS transistor is the controlled terminal of the power supply rejection ratio enhancement circuit, the source of the fifth MOS transistor is the input terminal of the power supply rejection ratio enhancement circuit, the drain of the fifth MOS transistor is the output terminal of the power supply rejection ratio enhancement circuit, and is interconnected with the source and the gate of the sixth MOS transistor.

[0019] Optionally, the bandgap reference voltage generation circuit includes an eleventh MOS transistor and a twelfth MOS transistor, the source of the eleventh MOS transistor is connected to the power supply output terminal VR of the current mode regulator, the gate of the eleventh MOS transistor is connected to the output terminal of the power supply rejection ratio enhancement circuit, and the source of the eleventh MOS transistor is connected to the source and the gate of the twelfth MOS transistor.

[0020] Optionally, the self - biased operational amplifier includes a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, a first bias MOS transistor, and a second bias MOS transistor;

[0021] The gate of the seventh MOS transistor is the first input terminal of the self - biased operational amplifier 40. The gate of the eighth MOS transistor is the second input terminal of the self - biased operational amplifier 40. The seventh MOS transistor is serially disposed between the ninth MOS transistor and the first bias MOS transistor. The eighth MOS transistor is serially disposed between the tenth MOS transistor and the first bias MOS transistor. The gates of the ninth MOS transistor and the tenth MOS transistor are also connected to the drain of the seventh MOS transistor. The sources of the ninth MOS transistor, the tenth MOS transistor, and the second bias MOS transistor are all connected to the power output terminal VR of the current - mode regulator. The gate of the second bias MOS transistor is connected to the drain of the eighth MOS transistor. The drain of the second bias MOS transistor is the output terminal of the self - biased operational amplifier and is connected to the controlled terminal of the first bias MOS transistor.

[0022] Optionally, the current - mode regulator includes a first current - regulating MOS transistor, a second current - regulating MOS transistor, and a third current - regulating MOS transistor. The sources of the first current - regulating MOS transistor and the second current - regulating MOS transistor are both connected to a DC power supply. The gate and the source of the first current - regulating MOS transistor and the gate of the second current - regulating MOS transistor are both connected to the drain of the third current - regulating MOS transistor. The gate of the third current - regulating MOS transistor is the controlled terminal of the current - mode regulator.

[0023] Optionally, the bandgap reference circuit further includes:

[0024] A startup circuit, the controlled terminal of the startup circuit is connected to the output terminal of the self - biased operational amplifier, and the startup circuit is serially disposed between the controlled terminal of the bandgap reference voltage generating circuit and the first input terminal of the self - biased operational amplifier.

[0025] This application also provides an analog integrated circuit, including the bandgap reference circuit as described above.

[0026] The bandgap reference circuit of this application uses a fully CMOS bandgap core circuit to generate CTAT (inversely proportional to absolute temperature) and PTAT (proportional to absolute temperature) using the power supply voltage VDD isolated by a self-current mode regulator, and mirrors the bandgap reference current to the bandgap reference voltage generation circuit, so that the bandgap reference voltage generation circuit generates a temperature-independent current Iref, and a temperature-independent bandgap reference voltage is obtained from the bandgap reference voltage generation circuit. This application overcomes the problem in the prior art that the trade-off between the area, power consumption, and PSRR performance of the bandgap reference results in the bandgap reference not being able to meet the design requirements well. A new bandgap reference circuit is designed to improve the power supply rejection ratio (PSRR) performance while reducing the power consumption and area. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on the structures shown in these drawings.

[0028] Figure 1 It is a schematic circuit structure diagram of an embodiment of the bandgap reference circuit of this application;

[0029] Figure 2 It is a schematic equivalent circuit structure diagram of an embodiment of the bandgap reference circuit of this application.

[0030] Description of the reference numerals in the drawings:

[0031] Label Name Label Name 10 Current mode regulator M8 The twelfth MOS transistor 20 Full CMOS bandgap core circuit M9 The first MOS transistor 30 Bandgap reference voltage generation circuit M10 The third MOS transistor 40 Self - biased operational amplifier M11 The second MOS transistor 50 Power supply rejection ratio enhancement circuit M12 The fourth MOS transistor 60 Startup circuit MP1 The first current - regulating MOS transistor M1 The seventh MOS transistor MP2 The second current - regulating MOS transistor M2 The eighth MOS transistor MP3 The third current - regulating MOS transistor M3 The ninth MOS transistor MSB1 The first bias MOS transistor M4 The tenth MOS transistor MSB2 The second bias MOS transistor M5 The fifth MOS transistor MST Startup MOS transistor M6 The sixth MOS transistor R1 The first resistor M7 The eleventh MOS transistor R2 The second resistor

[0032] The realization, functional features, and advantages of the objectives of this application will be further described with reference to the embodiments and the drawings. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0033] The following will clearly and completely describe the technical solutions in the embodiments of this application with reference to the drawings in the embodiments of this application. Obviously, the described embodiments are only some embodiments of this application, rather than all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of this application.

[0034] It should be noted that if there are directional indications (such as up, down, left, right, front, back...) involved in the embodiments of this application, the directional indications are only used to explain the relative positional relationship and movement conditions between components in a specific posture (as shown in the drawings). If the specific posture changes, the directional indications will also change accordingly.

[0035] In addition, if there are descriptions such as "first" and "second" in the embodiments of the present application, the descriptions of "first", "second", etc. are only for descriptive purposes and should not be construed as indicating or implying their relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions between various embodiments may be combined with each other, but it must be based on what can be achieved by those of ordinary skill in the art. When the combination of technical solutions results in contradictions or cannot be achieved, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present application.

[0036] The term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this article generally represents an "or" relationship between the associated objects before and after.

[0037] The present application proposes a bandgap reference circuit, which is applied to analog integrated circuits.

[0038] Integrated circuits are divided into three directions: analog circuits, digital circuits, and mixed-signal circuits. The bandgap reference circuit is independent of process, voltage, and temperature (PVT) variations and is a very important circuit module in the field of integrated circuits. Especially in analog circuits, it is one of the core circuits, enabling the system to have stable performance without being affected by external PVT variations. The bandgap reference circuit can be divided into three main functional modules: a voltage proportional to absolute temperature (PTAT), a voltage inversely proportional to absolute temperature (CTAT), and a bias circuit. Based on the characteristic that the bandgap voltage of silicon material is independent of power supply and temperature, the bandgap reference circuit uses the base-emitter voltage VBE of a BJT with a negative temperature coefficient and the thermal voltage VT with a positive temperature coefficient, and obtains an output voltage with a zero temperature coefficient by weighted addition of two voltages with opposite temperature coefficients. In traditional bandgap references, VT has a linear relationship with temperature, while VBE has a certain non-linear relationship with temperature, resulting in the temperature coefficient (TC) being limited to higher than 20 ppm / °C and a relatively low power supply rejection ratio, making it vulnerable to power supply ripple. Most bandgap reference circuits use two nodes and generate CTAT and PTAT currents by using equal-value resistors. Currently, the bandgap part usually uses diodes D1 and D2, which have the disadvantages of large area and high power consumption, do not conform to the development trend of low voltage and low power consumption, and the current source will also introduce additional errors and power consumption.

[0039] Refer to Figure 1 and Figure 2, To solve the above problems, the present application proposes a new bandgap reference circuit to improve the PSRR performance while reducing power consumption and area. The bandgap reference circuit includes a current mode regulator 10, a fully CMOS bandgap core circuit 20, and a bandgap reference voltage generation circuit 30; wherein,

[0040] The current mode regulator 10 is configured to connect to a power supply voltage and isolate the power supply voltage from the fully CMOS bandgap core circuit 20 to improve the power supply rejection ratio;

[0041] The power input terminal of the bandgap reference voltage generation circuit 30 is connected to the power output terminal VR of the current mode regulator 10;

[0042] The power input terminal of the fully CMOS bandgap core circuit 20 is connected to the power output terminal VR of the current mode regulator 10. The fully CMOS bandgap core circuit 20 is configured to generate a bandgap reference current and mirror it to the bandgap reference voltage generation circuit 30, so that the bandgap reference voltage generation circuit 30 generates a bandgap reference voltage.

[0043] In a possible implementation manner of the present application, the fully CMOS bandgap core circuit 20 includes:

[0044] A first MOS transistor M9 and a second MOS transistor M11, both the first MOS transistor M9 and the second MOS transistor M11 are connected to the current mode regulator 10;

[0045] A diode-connected third MOS transistor M10 and a fourth MOS transistor M12, the third MOS transistor M10 is connected in series with the first MOS transistor M9, and the second MOS transistor M11 is connected in series with the fourth MOS transistor M12;

[0046] A first resistor R1 is connected in series between the first MOS transistor M9 and the third MOS transistor M10;

[0047] A second resistor R2 is connected in parallel with the third MOS transistor M10; the third MOS transistor M10, the first resistor R1, and the second resistor R2 are configured to generate a bandgap reference current and mirror it to the bandgap reference voltage generation circuit 30 through the second MOS transistor M11 and the fourth MOS transistor M12, so that the bandgap reference voltage generation circuit 30 generates a bandgap reference voltage.

[0048] In a possible implementation of the present application, the circuit elements of the all-CMOS bandgap core circuit have the following circuit connection relationships: The gates of the first MOS transistor M9 and the second MOS transistor M11 are both connected to the control voltage output terminal of the current mode regulator 10. The sources of the first MOS transistor M9 and the second MOS transistor M11 are respectively connected to the power output terminal of the current mode regulator 10. The drain of the first MOS transistor M9 is interconnected with the first end of the first resistor R1 and the first end of the second resistor R2. The second end of the first resistor R1 is interconnected with the gate and the source of the third MOS transistor M10. The drain of the second MOS transistor is interconnected with the gate and the source of the fourth MOS transistor M12. The drains of the second resistor R2, the third MOS transistor M10, and the fourth MOS transistor M12 are all grounded.

[0049] When the bandgap reference circuit of the present application is applied to a low dropout linear regulator (LDO), the power supply rejection ratio (PSRR) is the most important factor to be considered in circuit design. In a mixed signal system, especially in a data converter, the power supply noise is the most important noise, and a high PSRR configuration is required in a wide frequency range to suppress the coupled power supply noise. For this reason, in this embodiment, the power supply voltage of the bandgap reference circuit is provided by the current mode regulator 10, and the all-CMOS bandgap core circuit 20 is isolated from the power supply voltage VDD to suppress the influence of the change of the power supply voltage VDD on the bandgap reference.

[0050] In a possible implementation of the present application, the bandgap reference voltage generation circuit 30 includes an eleventh MOS transistor M7 and a twelfth MOS transistor M8. The source of the eleventh MOS transistor M7 is connected to the power output terminal VR of the current mode regulator 10. The gate of the eleventh MOS transistor M7 is connected to the output terminal of the power supply rejection ratio enhancement circuit 50. The source of the eleventh MOS transistor M7 is connected to the source and the gate of the twelfth MOS transistor M8.

[0051] The bandgap reference voltage generation circuit 30 adopts a current mirror structure. The size of the eleventh MOS transistor M7 is set to be the same as that of the second MOS transistor M11 in the all-CMOS bandgap core circuit 20. The eleventh MOS transistor M7 is implemented by a PMOS transistor, and the twelfth MOS transistor M8 is implemented by an NMOS transistor. The twelfth MOS transistor M8 is connected by the diode connection method, that is, the gate and the source of the twelfth MOS transistor M8 are interconnected. The twelfth MOS transistor M8 operates in the saturation region. A bandgap reference current is generated by the third MOS transistor M10, the first resistor R1, and the second resistor R2, and is mirrored to the bandgap reference voltage generation circuit 30 through the second MOS transistor M11 and the fourth MOS transistor M12. The bandgap reference voltage is determined by the current I flowing through the twelfth MOS transistor M8ref and the internal resistance of the twelfth MOS transistor M8. The bandgap reference voltage V ref can be expressed by the equation:

[0052]

[0053] In Equation (1), I ref is the current flowing through M8, and k M8 = μCox(WM8 / LM8), where μ, Cox, W, and L represent the carrier mobility of the MOSFET, the gate oxide capacitance per unit area, the width and length of the MOS transistor respectively. It can be seen from Equation (1) that the first term and the second term on the right side of the equal sign are both susceptible to temperature changes and can be completely suppressed by using a bias current proportional to the mobility.

[0054] The first MOS transistor M9 and the second MOS transistor M11 are implemented using PMOS transistors, and the third MOS transistor M10 and the fourth MOS transistor M12 are implemented using NMOS transistors. The third MOS transistor M10 and the fourth MOS transistor M12 are connected using the diode connection method, that is, the gate and source of the third MOS transistor M10 are interconnected, and the gate and source of the fourth MOS transistor M12 are interconnected. The second MOS transistor M11 and the fourth MOS transistor M12 are mirror - set with the bandgap reference voltage generation circuit 30. The first MOS transistor M9, the first resistor R1, and the third MOS transistor M10 are connected in series in sequence, and the second resistor R2 is connected in parallel with the third MOS transistor M10. The second MOS transistor M11 and the fourth MOS transistor M12 are connected in series. Let the common point of the first MOS transistor M9 and the first resistor R1 be X, and the voltage at this common point X be V y , the common point of the second MOS transistor M11 and the fourth MOS transistor M12 be Y, and the voltage at this common point Y be V y , and the voltage V z output from the control voltage output terminal of the current - mode regulator 10. V z is used to control the conduction of the first MOS transistor M9 and the second MOS transistor M11. Let the control current flowing through the first MOS transistor M9 and the third MOS transistor M10 be I1, the control current flowing through the second MOS transistor M11 and the fourth MOS transistor M12 be I2, the current flowing through the first resistor R1 be I R1 , the current flowing through the second resistor R2 be I R2 , and the current flowing through the fourth MOS transistor M12 be I D12 . By adjusting the control currents I1 and I2, V y and V y can be made equal, and V zThen, I1 and I2 can be controlled to be equal. Since the second MOS transistor M11 and the fourth MOS transistor M12 are mirror - set with the band - gap reference voltage generation circuit 30, the control current flowing through the second MOS transistor M11 and the fourth MOS transistor M12 is I2, and the current flowing through the mirror of the band - gap reference voltage generation circuit 30 is I ref is equal. V y , V y , the control currents I1, I2, the current I R1 , I R2 and I D12 have the following relationship:

[0055] V x =V y (2)

[0056] I2 = I R1 +I R2 =I ref =I1 = I D12 (3)

[0057] The leakage current equation of the current flowing through the fourth MOS transistor M12 is expressed as:

[0058]

[0059] In Equation (4), It is a process - related parameter (≈20 nA), n represents the sub - threshold slope factor (≈1.5), k is the Boltzmann constant, q is the charge, and T is the absolute temperature. From Equation (4), the gate - source voltage (Vgs) difference between the third MOS transistor M10 and the fourth MOS transistor M12 can be expressed as:

[0060]

[0061] where M is the ratio of the width - to - length ratio of the third MOS transistor M10 to the fourth MOS transistor M12, and VT represents the thermal voltage. From Figure XX and Equation (5), the current I R1 flowing through the first resistor R1 can be expressed by Equation (6) as:

[0062]

[0063] From Equation (6), it can be obtained that VT has a positive temperature coefficient. Therefore, the current I R1 flowing through the first resistor R1 is proportional to the absolute temperature. On the other hand, the current I R2 flowing through the second resistor R2 is inversely proportional to the absolute temperature and is expressed by Equation (7) as:

[0064]

[0065] In summary, in Equation (4), without considering the body effect of the fourth MOS transistor M12, the gate-source voltage Vgs of the fourth MOS transistor M12 exhibits a characteristic inversely proportional to the absolute temperature. Using the first resistor R1 and the second resistor R2, a current I with a positive temperature coefficient connected to the V y node is generated, and a current I with a negative temperature coefficient R1 . By superimposing these two currents with opposite temperature coefficients, the temperature coefficient of the entire circuit can be eliminated, thereby obtaining a current with a zero temperature coefficient. As shown in Equation (2), the current flowing through the first resistor R1 and the current flowing through the second resistor R2 are mirrored to the bandgap reference voltage generation circuit 30 to generate a temperature-independent current I R2 . From Equation (1), a temperature-independent bandgap reference voltage is obtained. ref

[0066] In the bandgap reference circuit of the present application, a fully CMOS bandgap core circuit is used to generate CTAT (inversely proportional to the absolute temperature) and PTAT (proportional to the absolute temperature) using the power supply voltage VDD isolated by the self-current mode regulator 10, and the bandgap reference current is mirrored to the bandgap reference voltage generation circuit 30, so that the bandgap reference voltage generation circuit 30 generates a temperature-independent current I ref . And a temperature-independent bandgap reference voltage is obtained from the bandgap reference voltage generation circuit 30. The present application overcomes the problem in the prior art that the trade-off among the area, power consumption, and PSRR performance of the bandgap reference results in the bandgap reference not being able to well meet the design requirements. The newly designed bandgap reference circuit can improve the power supply rejection ratio PSRR performance on the basis of reducing the power consumption area, which is beneficial to improving the stability of the bandgap reference circuit.

[0067] Referring to Figure 1 , in an embodiment of the present application, the third MOS transistor M10 and / or the fourth MOS transistor M12 operate in the weak inversion region.

[0068] In this embodiment, when the gate-source voltage of the third MOS transistor M10 and / or the fourth MOS transistor M12 approaches its threshold voltage V th , the third MOS transistor M10 and / or the fourth MOS transistor M12 can operate in the weak inversion region. The current flowing through the channels of the third MOS transistor M10 and / or the fourth MOS transistor M12 will gradually be mainly diffusion current to obtain a lower current, and at the same time, a higher transconductance can also be obtained, thereby reducing the volume of the bandgap reference circuit and reducing the self-power consumption of the bandgap reference circuit.

[0069] Referring to Figure 1 , in an embodiment of the present application, the bandgap reference circuit further includes:

[0070] The self - biasing operational amplifier 40, the first input terminal of the self - biasing operational amplifier 40 is connected to the drain of the first MOS transistor M9, the second input terminal of the self - biasing operational amplifier 40 is connected to the drain of the second MOS transistor M11, and the output terminal of the self - biasing operational amplifier 40 is connected to the controlled terminal of the current - mode regulator 10.

[0071] In this embodiment, the two input terminals of the self - biasing operational amplifier 40 are respectively connected to the common point X and the common point Y. The output terminal of the self - biasing operational amplifier 40 is connected to the controlled terminal of the current - mode regulator 10. A negative feedback is formed between the self - biasing operational amplifier 40 and the current - mode regulator 10. The self - biasing operational amplifier 40 obtains the bias current as a differential input from the first MOS transistor M9 and the second MOS transistor M11 of the fully - CMOS bandgap core circuit 20. By adjusting the voltage output to the controlled terminal of the current - mode regulator 10, the gate - bias voltages of the first MOS transistor M9 and the second MOS transistor M11 in the fully - CMOS bandgap core circuit 20 are adjusted, so that the input voltages (common point X and common point Y) of the self - biasing operational amplifier 40, V y and V y are equal.

[0072] Referring to Figure 1 In an embodiment of the present application, the current - mode regulator 10 includes a first current - regulating MOS transistor MP1, a second current - regulating MOS transistor MP2, and a third current - regulating MOS transistor MP3. The source electrodes of the first current - regulating MOS transistor MP1 and the second current - regulating MOS transistor MP2 are both connected to the DC power supply. The gate electrode and the source electrode of the first current - regulating MOS transistor MP1 and the gate electrode of the second current - regulating MOS transistor MP2 are both connected to the drain of the third current - regulating MOS transistor MP3. The gate electrode of the third current - regulating MOS transistor MP3 is the controlled terminal of the current - mode regulator 10.

[0073] In this embodiment, the first current regulating MOS transistor MP1 and the second current regulating MOS transistor MP2 can be implemented by PMOS transistors, and the third MOS transistor M10 can be implemented by an NMOS transistor. The third MOS transistor M10 is controlled by a bias operational amplifier, and the drain of the second current regulating MOS transistor MP2 is also connected to the power input terminal of the self-bias operational amplifier 40. Since the drain of the first current regulating MOS transistor MP1 forms a low resistance with the power supply of the self-bias operational amplifier 40, the power supply noise of the self-bias operational amplifier 40 can be introduced to the drain of the first current regulating MOS transistor MP1, that is, the drain voltage of the first current regulating MOS transistor MP1 can follow the change of the voltage at the power input terminal of the self-bias operational amplifier 40. Therefore, the voltage difference Vgs between the gate and the source of the second current regulating MOS transistor MP2 is equal to zero. In this way, the current variation range of the second current regulating MOS transistor MP2 is effectively reduced, that is, the power supply rejection ratio of the self-bias operational amplifier 40, the all-CMOS bandgap core circuit 20, and the bandgap reference voltage generating circuit 30 is improved. Since the current mode regulator 10 can follow the change of the power supply voltage VDD of the self-bias operational amplifier 40, the change of the power supply voltage VDD will not affect the self-bias operational amplifier 40, the all-CMOS bandgap core circuit 20, and the bandgap reference voltage generating circuit 30, that is, the current mode regulator 10 improves the power supply rejection ratio of the bandgap reference circuit.

[0074] Referring to Figure 1 , in an embodiment of the present application, the bandgap reference circuit further includes:

[0075] A power supply rejection ratio enhancement circuit 50, the controlled terminal of the power supply rejection ratio enhancement circuit 50 is connected to the self-bias operational amplifier 40, the input terminal of the power supply rejection ratio enhancement circuit 50 is connected to the power output terminal VR of the current mode regulator 10, and the output terminal of the power supply rejection ratio enhancement circuit 50 is connected to the controlled terminals of the current mode regulator 10 and the bandgap reference voltage generating circuit 30.

[0076] In this embodiment, in order to improve the power supply rejection ratio of the bandgap reference circuit, a power supply rejection ratio enhancement circuit 50 is introduced. The current mode regulator 10 receives the gate bias voltage output by the power supply rejection ratio enhancement circuit 50 and provides a stable power supply voltage VDD to the bandgap reference voltage generating circuit 30 and the all-CMOS bandgap core circuit 20.

[0077] In an exemplary embodiment of the present application, the power supply rejection ratio enhancement circuit 50 includes:

[0078] The fifth MOS transistor M5 and the sixth MOS transistor M6, the gate of the fifth MOS transistor M5 is the controlled end of the power supply rejection ratio enhancement circuit 50, the source of the fifth MOS transistor M5 is the input end of the power supply rejection ratio enhancement circuit 50, the drain of the fifth MOS transistor M5 is the output end of the power supply rejection ratio enhancement circuit 50, and is interconnected with the source and gate of the sixth MOS transistor M6.

[0079] In this embodiment, the fifth MOS transistor M5 can be implemented by an NMOS transistor, and the sixth MOS transistor M6 is connected by the diode connection method, that is, the gate and source of the twelfth MOS transistor M8 are interconnected. The fifth MOS transistor M5 is controlled by the self-biased operational amplifier 40. By adjusting the conductance of the fifth MOS transistor M5, the gate bias voltage of the current mode regulator 10 is adjusted, so that the current mode regulator 10 provides a stable power supply voltage VDD to be converted to the bandgap reference voltage generation circuit 30 and the all-CMOS bandgap core circuit 20.

[0080] Refer to Figure 2 , Figure 2 is the equivalent circuit of the current mode regulator 10, the self-biased operational amplifier 40, the power supply rejection ratio enhancement circuit 50, and the bandgap reference voltage generation circuit 30 in the bandgap reference circuit. The first stage is the equivalent circuit of the self-biased operational amplifier 40, the second stage is the equivalent circuit of the power supply rejection ratio enhancement circuit 50, and the third stage is the bandgap reference voltage generation circuit 30. The open-loop gains of the three equivalent circuits are A1, A2, and A3 respectively. Therefore, the open-loop gain of the entire equivalent circuit is A = A1A2A3. The power supply gain A of the current mode regulator 10 R , and the power supply gains A R1 , A R2 , A R3 output to the three equivalent circuits can be expressed as A R = A R3 + A3(1 - (A R2 + A2(1 - A R1 ))), so the power supply rejection ratio PSRR of the CMR of the equivalent network can be expressed as:

[0081]

[0082] In Equation (7), the power supply rejection ratio PSRR1 of the first-stage equivalent circuit can be expressed as:

[0083] PSRR1 = A1 / A R1 = -g m，M1 / (g o，M1 + g o，M4 );

[0084] The power supply rejection ratio PSRR2 of the second-stage equivalent circuit can be expressed as:

[0085] PSRR2 = -A2 / A R2 = -g m5，M5 / g o，M5 ;

[0086] The power supply rejection ratio PSRR3 of the third - stage equivalent circuit can be expressed as:

[0087] PSRR3 = -A3 / A R3 = -g m，M7 / g o，M7 ;

[0088] In the above equations, g m，M1 , g o，M1 represent the transconductance and conductance of the eighth MOS transistor M2 respectively, g o，M4 represents the conductance of the ninth MOS transistor M3, g m5，M5 and g o，M5 represent the transconductance and conductance of the fifth MOS transistor M5 respectively; g m，M7 and g o，M7 represent the transconductance and conductance of the eleventh MOS transistor M7 respectively.

[0089] Substituting PSRR1, PSRR2, and PSRR3 into equation (7), M7 obtains:

[0090]

[0091] In the self - biased operational amplifier 40, the transconductances of the seventh MOS transistor M1 to the tenth MOS transistor have the following relationship

[0092] g o,M1 = g o,M2 = g o,M3 = g o,M4

[0093] In the current - suppression - ratio enhancement circuit, the transconductances of the fifth MOS transistor M5 and the sixth MOS transistor M6 have the following relationship:

[0094] g o,M5 = g o,M6

[0095] According to equation (8), by adjusting the conductance g o,M5 of the fifth MOS transistor M5, the power supply rejection ratio PSRR performance of the band - gap reference voltage generation circuit 30 can be improved well. In addition, the equation of the PSRR of the power supply voltage VDD is expressed as:

[0096]

[0097] Equation (9) shows that by cascading a first - stage current mirror, that is, the power - supply rejection - ratio enhancement circuit 50, to adjust the power - supply voltage VDD for the power - supply rejection - ratio PSRR performance, the conductance g of the seventh MOS transistor M1 in the operational amplifier can be improved. O,MP1 , the conductance g of the eighth MOS transistor M2 0,MP2 The final PSRR expression is expressed as Equation (10) as follows:

[0098]

[0099] Referring to Figure 1 , in an embodiment of the present application, the self - biased operational amplifier 40 includes a seventh MOS transistor M1, an eighth MOS transistor M2, a ninth MOS transistor M3, a tenth MOS transistor M4, a first bias MOS transistor MSB1, and a second bias MOS transistor MSB2;

[0100] The gate of the seventh MOS transistor M1 is the first input terminal of the self - biased operational amplifier 40, the gate of the eighth MOS transistor M2 is the second input terminal of the self - biased operational amplifier 40, the seventh MOS transistor M1 is serially arranged between the ninth MOS transistor M3 and the first bias MOS transistor MSB1, and the eighth MOS transistor M2 is serially arranged between the tenth MOS transistor M4 and the first bias MOS transistor MSB1; the gates of the ninth MOS transistor M3 and the tenth MOS transistor M4 are also connected to the drain of the seventh MOS transistor M1; the sources of the ninth MOS transistor M3, the tenth MOS transistor M4, and the second bias MOS transistor MSB2 are all connected to the power - supply output terminal VR of the current - mode regulator 10; the gate of the second bias MOS transistor MSB2 is connected to the drain of the eighth MOS transistor M2, and the drain of the second bias MOS transistor MSB2 is the output terminal of the self - biased operational amplifier 40 and is connected to the controlled terminal of the first bias MOS transistor MSB1.

[0101] In this embodiment, the seventh MOS transistor M1 and the eighth MOS transistor M2 can be implemented by NMOS transistors; the ninth MOS transistor M3 and the tenth MOS transistor M4 can be implemented by PMOS transistors. The seventh MOS transistor M1 and the eighth MOS transistor M2 form an input differential pair. The seventh MOS transistor M1 serves as the first input terminal of the self-biased operational amplifier 40 and is connected to the power supply voltage VDD through the first MOS transistor M9. The eighth MOS transistor M2 serves as the second input terminal of the self-biased operational amplifier 40 and is connected to the power supply voltage VDD through the second MOS transistor M11. The ninth MOS transistor M3 and the tenth MOS transistor M4 are current mirror loads. The common terminal of the seventh MOS transistor M1 and the ninth MOS transistor M3 is connected as an output terminal of the self-biased operational amplifier 40, which can control the operation of the power supply rejection ratio enhancement circuit 50. The seventh MOS transistor M1 to the tenth MOS transistor M4 form the operational amplifier part. The second bias MOS transistor MSB2 is connected to the common terminal of the seventh MOS transistor M1 and the ninth MOS transistor M3 and is controlled by the output of the operational amplifier part. The source of the second bias MOS transistor MSB2 is connected to the output terminal of the current mode regulator 10 and is connected to the power supply voltage VDD. The source of the second bias MOS transistor MSB2 is connected to the gate of the first bias MOS transistor MSB1 to control the conduction of the first bias MOS transistor MSB1. The source of the second bias MOS transistor MSB2 serves as the output terminal of the self-biased operational amplifier 40 to control the operation of the current mode regulator 10, so that the current mode regulator 10 provides the power supply voltage VDD to turn on two branches of the all-CMOS bandgap core circuit 20. The self-biased operational amplifier 40 obtains voltage negative feedback. When the self-biased operational amplifier 40 has a certain gain, it clamps the voltages at both ends of its input differential pair and makes them consistent. Due to the existence of voltage negative feedback, the bandgap reference circuit gradually operates normally and reaches the final balance of the bandgap reference circuit.

[0102] Referring to Figure 1 , in an embodiment of the present application, the bandgap reference circuit further includes:

[0103] A startup circuit 60, the controlled terminal of the startup circuit 60 is connected to the output terminal of the self-biased operational amplifier 40, and the startup circuit 60 is serially arranged between the controlled terminal of the bandgap reference voltage generation circuit 30 and the first input terminal of the self-biased operational amplifier 40.

[0104] The startup circuit 60 includes a startup MOS transistor MST. The gate of the startup MOS transistor MST is connected to the drain of the second bias MOS transistor MSB2. The source of the startup MOS transistor MST is connected to the gate of the fifth MOS transistor M5. The drain of the startup MOS transistor MST is connected to the public point X.

[0105] In this embodiment, it can be understood that when the open-loop gain of the self-biased operational amplifier 40 is relatively high, the output voltage of the self-biased operational amplifier 40 is relatively independent of the power supply voltage VDD. If the voltage V y at the common point X and the voltage V y at the common point Y are both equal to zero, the bandgap reference circuit will enter a degenerate state and the circuit will never be able to work. Therefore, this embodiment is provided with a startup circuit 60 to remove the degenerate state. In practical applications, the startup circuit 60 receives the bias voltage output by the second bias MOS transistor MSB2 in the self-biased operational amplifier 40. At the beginning of power-on of the power supply, there is no current in the bandgap reference circuit. When the ninth MOS transistor M3 and the tenth MOS transistor M4 in the self-biased operational amplifier 40 are turned on, the drain voltage of the ninth MOS transistor M3 is set high, thereby controlling the second bias MOS transistor MSB2 to turn on, so that the startup MOS transistor MST receives a high level and turns on, and the startup circuit 60 works normally. The gate bias voltage control signal output by the conduction of the startup MOS transistor MST enables the all-CMOS bandgap core circuit 20, the current mode regulator 10, and the bandgap reference voltage generation circuit 30. The current mode regulator 10 isolates the power supply voltage VDD and outputs it. There is current flowing into the first MOS transistor M9 and the second MOS transistor M11 of the all-CMOS bandgap core circuit 20, thereby generating a reference current and mirroring it to the bandgap reference voltage generation circuit 30. When the all-CMOS bandgap core circuit 20 is normally turned on, the second bias MOS transistor MSB2 in the self-biased operational amplifier 40 conducts, so that the startup MOS transistor that outputs a low level is turned off, and the startup circuit 60 automatically shuts down.

[0106] The present application also proposes an analog integrated circuit, including the bandgap reference circuit as described above. The detailed structure of the bandgap reference circuit can be referred to the above embodiment and will not be elaborated here; it can be understood that since the above bandgap reference circuit is used in the inventive analog integrated circuit, therefore, the embodiments of the inventive analog integrated circuit include all the technical solutions of all the above embodiments of the bandgap reference circuit, and the achieved technical effects are also exactly the same, which will not be elaborated here.

[0107] The above are only optional embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structural transformation made by using the specification and drawings of the present application under the inventive concept of the present application, or direct / indirect application in other related technical fields, is included in the patent protection scope of the present application.

Claims

1. A bandgap reference circuit, characterized in that, The bandgap reference circuit includes: A current mode regulator for accessing a power supply voltage; A bandgap reference voltage generation circuit, whose power supply input terminal is connected to the power supply output terminal of the current mode regulator; A fully CMOS bandgap core circuit, whose power supply input terminal is connected to the power supply output terminal of the current mode regulator. The fully CMOS bandgap core circuit is used to generate a bandgap reference current and mirror it to the bandgap reference voltage generation circuit, so that the bandgap reference voltage generation circuit generates a bandgap reference voltage. The fully CMOS bandgap core circuit includes: A first MOS transistor and a second MOS transistor, both the first MOS transistor and the second MOS transistor are electrically connected to the current mode regulator; A diode-connected third MOS transistor and a fourth MOS transistor, the third MOS transistor is serially arranged with the first MOS transistor, and the second MOS transistor is serially arranged with the fourth MOS transistor; A first resistor serially arranged between the first MOS transistor and the third MOS transistor; A second resistor connected in parallel with the third MOS transistor. The third MOS transistor, the first resistor and the second resistor are used to generate a bandgap reference current, and mirror it to the bandgap reference voltage generation circuit through the second MOS transistor and the fourth MOS transistor, so that the bandgap reference voltage generation circuit generates a bandgap reference voltage; The bandgap reference circuit further includes: A self-biased operational amplifier, the first input terminal of the self-biased operational amplifier is connected to the drain of the first MOS transistor, the second input terminal of the self-biased operational amplifier is connected to the drain of the second MOS transistor, and the output terminal of the self-biased operational amplifier is connected to the controlled terminal of the current mode regulator; The current mode regulator includes a first current regulating MOS transistor, a second current regulating MOS transistor and a third current regulating MOS transistor. The sources of the first current regulating MOS transistor and the second current regulating MOS transistor are both connected to a DC power supply. The gate and source of the first current regulating MOS transistor and the gate of the second current regulating MOS transistor are both connected to the drain of the third current regulating MOS transistor. The gate of the third current regulating MOS transistor is the controlled terminal of the current mode regulator.

2. The bandgap reference circuit according to claim 1, wherein The third MOS transistor and / or the fourth MOS transistor operate in the weak inversion region.

3. The bandgap reference circuit according to claim 1, wherein The bandgap reference circuit further includes: A power supply rejection ratio enhancement circuit, the controlled terminal of the power supply rejection ratio enhancement circuit is connected to the self-biased operational amplifier, the input terminal of the power supply rejection ratio enhancement circuit is connected to the power supply output terminal of the current mode regulator, and the output terminal of the power supply rejection ratio enhancement circuit is connected to the controlled terminal of the bandgap reference voltage generation circuit.

4. The bandgap reference circuit according to claim 3, wherein The power supply rejection ratio enhancement circuit includes: A fifth MOS transistor and a sixth MOS transistor, the gate of the fifth MOS transistor is the controlled terminal of the power supply rejection ratio enhancement circuit, the source of the fifth MOS transistor is the input terminal of the power supply rejection ratio enhancement circuit, the drain of the fifth MOS transistor is the output terminal of the power supply rejection ratio enhancement circuit and is interconnected with the source and gate of the sixth MOS transistor.

5. The bandgap reference circuit according to claim 3, wherein The bandgap reference voltage generation circuit includes an eleventh MOS transistor and a twelfth MOS transistor. The source of the eleventh MOS transistor is connected to the power supply output terminal VR of the current mode regulator. The gate of the eleventh MOS transistor is connected to the output terminal of the power supply rejection ratio enhancement circuit. The source of the eleventh MOS transistor is connected to the source and gate of the twelfth MOS transistor.

6. The bandgap reference circuit according to claim 1, wherein The self - biased operational amplifier includes a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, a first bias MOS transistor, and a second bias MOS transistor; The gate of the seventh MOS transistor is the first input terminal of the self - biased operational amplifier 40. The gate of the eighth MOS transistor is the second input terminal of the self - biased operational amplifier 40. The seventh MOS transistor is serially arranged between the ninth MOS transistor and the first bias MOS transistor. The eighth MOS transistor is serially arranged between the tenth MOS transistor and the first bias MOS transistor. The gates of the ninth MOS transistor and the tenth MOS transistor are also connected to the drain of the seventh MOS transistor. The sources of the ninth MOS transistor, the tenth MOS transistor, and the second bias MOS transistor are all connected to the power supply output terminal VR of the current mode regulator. The gate of the second bias MOS transistor is connected to the drain of the eighth MOS transistor. The drain of the second bias MOS transistor is the output terminal of the self - biased operational amplifier and is connected to the controlled terminal of the first bias MOS transistor.

7. The bandgap reference circuit according to any one of claims 1 to 6, characterized in that The bandgap reference circuit further includes: A start - up circuit. The controlled terminal of the start - up circuit is connected to the output terminal of the self - biased operational amplifier. The start - up circuit is serially arranged between the controlled terminal of the bandgap reference voltage generation circuit and the first input terminal of the self - biased operational amplifier.

8. An analog integrated circuit, characterized in that, Comprising the bandgap reference circuit according to any one of claims 1 to 7.

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