Atomicity maintenance method, processor and electronic device

Abstract

The present application provides an atomicity maintenance method, a processor and an electronic device, the method comprising: generating N memory access operations according to a vector memory access instruction, where N is a positive integer greater than or equal to 1; checking whether there is an event during the processing of the N memory access operations that causes the vector memory access instruction to be non-atomic; processing the N memory access operations; in the case of the presence of the event, the processing of any memory access operation in the N memory access operations does not produce any processing effect, or the N memory access operations produce all processing effects. The present application can achieve the maintenance of the atomicity of vector instructions.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to an atomicity preservation method, a processor, and an electronic device. Background Art

[0002] The atomicity of an instruction refers to the property that the process of an instruction from the start to the end of execution will not be interrupted. For example, taking instruction A as an example, if instruction A has atomicity, then once instruction A starts executing, it will not be affected by events such as interrupt events or exception events and suspend the execution of the instruction until instruction A is executed.

[0003] During the execution of instructions, they are usually affected by events such as interrupts or exceptions, causing the execution of instructions to be suspended. For example, if instruction B does not have atomicity, then during the execution of instruction B, when the CPU detects an interrupt event at the same time, it may suspend the execution of instruction B and prioritize the execution of the interrupt event. After the interrupt event is completed, it will return to continue executing instruction B. Due to the influence of interrupt events or exceptions, the atomicity of instructions cannot be maintained.

[0004] In the processing of any vector instruction in the prior art, there are multiple identical or similar operations in a single instruction inside the processor; from the perspective of software developers, a single vector instruction is the smallest operation unit of the CPU, that is, a single vector instruction should be atomic. Therefore, the processor design must ensure the atomicity of vector instruction execution.

[0005] In actual applications, the processor executes multiple operations obtained by splitting a vector instruction concurrently, and the concurrent execution mechanism designed to improve the efficiency of instruction execution poses a challenge to maintaining the atomicity of vector instructions. In addition, the instruction system also includes barrier instructions, which are used to isolate memory access operations before and after the barrier instructions; and inside the processor, the barrier instructions and other vector instructions are split into multiple operations that are also processed concurrently. The above factors bring further difficulties to ensuring the atomicity of vector instructions. Summary of the invention

[0006] The present application provides an atomicity maintenance method, a processor and an electronic device to solve the problem in the prior art that the atomicity of vector instructions cannot be guaranteed due to the multi-operation parallel execution mechanism after vector instructions are split, and the barrier instruction and vector instruction parallel execution mechanism.

[0007] In order to solve the above problems, the present application discloses an atomicity preservation method, which comprises:

[0008] Split the vector memory access instruction into N memory access operations, where N is a positive integer greater than or equal to 1;

[0009] Checking whether there is an event during the processing of the N memory access operations that causes the vector memory access instruction to be non-atomic;

[0010] In the presence of the event, any one of the N memory access operations does not produce any processing effect, or the N memory access operations produce all processing effects.

[0011] In order to solve the above problem, the present application also discloses a processor, including:

[0012] A decoding unit, used for acquiring a vector memory access instruction and generating N memory access operations according to the vector memory access instruction, where N is a positive integer greater than or equal to 1;

[0013] A processing unit is used to check whether there is an event during the processing of the N memory access operations that causes the vector memory access instruction to be non-atomic; if the event exists, any memory access operation among the N memory access operations does not produce any processing effect, or the N memory access operations produce all processing effects.

[0014] In order to solve the above problems, the present application further discloses an electronic device, wherein the electronic device includes a memory and one or more programs, wherein the one or more programs are stored in the memory and are configured to be processed by one or more processors to process one or more atomicity preservation methods in the present application.

[0015] Compared with the prior art, this application has the following advantages:

[0016] The atomicity maintaining method, processor and electronic device provided in the embodiments of the present application generate N memory access operations according to the vector memory access instruction, and check whether there is an event that causes the vector memory access instruction to be non-atomic during the processing of the N memory access operations. When the event exists, the processing of any memory access operation among the N memory access operations does not produce any processing effect, or the N memory access operations produce all processing effects, thereby maintaining the atomicity of the vector instruction. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a flowchart of a method for maintaining atomicity according to Embodiment 1 of the present application;

[0018] Figure 2 is a flowchart of a method for maintaining atomicity according to Embodiment 2 of the present application;

[0019] Figure 3 is a flowchart of a method for maintaining atomicity according to Embodiment 3 of the present application;

[0020] Figure 4is a flowchart of a method for maintaining atomicity according to Embodiment 4 of the present application;

[0021] Figure 5 is a flowchart of a method for maintaining atomicity according to Embodiment 5 of the present application;

[0022] Figure 6-A is a structural block diagram of a processor according to Embodiment 5 of the present application;

[0023] Figure 6-B is a structural block diagram of another processor according to Embodiment 5 of the present application;

[0024] Figure 7 This is a structural block diagram of an electronic device according to Embodiment 6 of the present application. DETAILED DESCRIPTION

[0025] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0026] Embodiment 1

[0027] Reference Figure 1 , showing a step flow chart of an atomicity preservation method according to the first embodiment of the present application.

[0028] The atomicity preservation method provided in the embodiment of the present application may be executed by a CPU (Central Processing Unit), and includes the following steps:

[0029] Step 101: Generate N memory access operations according to a vector memory access instruction, where N is a positive integer greater than or equal to 1.

[0030] The embodiments of the present application can be applied to a scenario in which, during the process of processing vector memory access operation instructions, events that cause vector memory access instructions to be non-atomic are checked, and based on the check results, it is determined whether to execute the vector memory access instructions or submit the execution results of the vector memory access instructions to achieve instruction atomicity.

[0031] The vector memory access instruction can implement the same processing for a group of data at the same time; in practical applications, after receiving the vector memory access instruction, the vector memory access instruction can be decoded to be split into N memory access operations, where N is a positive integer greater than or equal to 1.

[0032] In this example, the vector memory access instruction may be a Load instruction or a Store instruction.

[0033] After N memory access operations are generated according to the vector memory access instruction, step 102 is executed.

[0034] Step 102: Check whether any event occurs during the processing of the N memory access operations that causes the vector memory access instruction to be non-atomic.

[0035] In the prior art, the pipeline for processing vector memory access instructions may include: 1. instruction fetch and decoding, i.e. obtaining vector memory access instructions and decoding the vector memory access instructions; 2. emission, i.e. sending the instructions in the operation queue to the reservation station according to the operation type, and reading the register value and the result status field during the emission process; 3. execution, if all required operands are ready, then execution; 4. write back, transferring the execution result to the result bus and releasing the reservation station; 5. submission, i.e. when the execution result of the instruction in the queue has been written back and no exception has occurred, the execution result of the instruction is written back to the register or memory.

[0036] Based on this, in an embodiment of the present application, processing a vector memory access instruction refers to performing any one or a combination of multiple operations of fetching, decoding, transmitting, executing, writing back and submitting the vector memory access instruction; processing a memory access operation includes any one or a combination of multiple operations of transmitting, executing and submitting the memory access operation.

[0037] The event mentioned in this example refers to an event that will cause the vector memory access instruction to be non-atomic. In this example, the event may include at least one of: an interrupt event, an exception event, and a barrier instruction detection event.

[0038] Among them, an interrupt event (also called an external interrupt) refers to an event that comes from other than the CPU executing instructions.

[0039] Exception events are events that occur within the CPU while executing instructions.

[0040] A barrier instruction is an instruction used to ensure synchronization between different operations; for example, a barrier instruction can be used to complete the synchronization function between load / store memory access operations and indicate the synchronization object and synchronization degree of the load / store memory access operations.

[0041] The atomicity of a vector memory access instruction refers to the property that a vector memory access instruction will not be interrupted from the start of execution to the end of execution until submission.

[0042] Therefore, in this example, after the vector memory access instruction is split into N memory access operations, the N memory access operations can be checked during the processing of the N memory access operations, that is, whether there is an event that causes the vector memory access instruction to be non-atomic during the processing of the N memory access operations. Optionally, when the processing of the memory access operation includes any one of the operations of transmitting, executing and submitting the memory access operation or a combination of multiple operations, the N memory access operations are checked for events that cause the vector memory access instruction to be non-atomic, that is: during the process of transmitting the N memory access operations, the N memory access operations are checked; or, during the process of executing the N memory access operations, the N memory access operations are checked; or, during the process of submitting the N memory access operations, the N memory access operations are checked. The specific stage at which the N memory access operations are checked depends on the type of event (i.e., interrupt event, exception event, barrier instruction, etc.) that causes the vector memory access instruction to be non-atomic.

[0043] After checking whether there is any event that causes the vector memory access instruction to be non-atomic during the processing of the N memory access operations, step 103 is executed.

[0044] Step 103: In the case where the event exists, any memory access operation among the N memory access operations does not produce any processing effect, or the N memory access operations produce all processing effects.

[0045] In the embodiment of the present application, the memory access operation does not produce any processing effect means that the memory access operation is executed but not submitted, or the memory access operation is not executed, or the memory access operation is not emitted; the memory access operation produces all processing effects means that all N memory access operations split by the vector memory access instruction are executed, and the execution results of the N memory access operations are all submitted.

[0046] In the embodiment of the present application, if there is no event that causes the vector memory access instruction to be non-atomic, N memory access operations can be executed according to the above instruction pipeline processing order, and the N memory access operation execution results can be submitted; specifically, when the vector memory access instruction is a Load instruction, an operation of reading the operand of the address indicated by the vector memory access instruction from the memory to the specified general register can be executed. When the vector memory access instruction is a Store instruction, an operation of writing the operand of the address indicated by the vector memory access instruction from the specified general register to the memory can be executed.

[0047] In an embodiment of the present application, when it is detected that there is an event in the process of processing N memory access operations that causes the vector memory access instruction to be non-atomic, the vector memory access instruction may not be processed, that is, the current processing of the vector memory access instruction is abandoned, and the vector memory access instruction may be executed, but the execution result of the vector memory access instruction is not submitted. Specifically, first, when it is detected that the N memory access operations are marked with an interruption mark, it means that there is an interruption event in the processing of the N memory access operations. At this time, the current execution of the vector memory access instruction is abandoned, that is, all the N memory access operations are not executed, or the N memory access operations are not emitted. Second, when there is an exception event in the processing of the N memory access operations, the vector memory access instruction is executed, but the execution result is not submitted. Third, for the barrier instruction, the barrier instruction can be executed first, and all memory access operations are not executed or emitted. After the barrier instruction is processed, the memory access operation is executed and the execution result is submitted. The process will be described in detail from the three dimensions of interruption events, exception events and barrier instructions in combination with Embodiment 2, Embodiment 3 and Embodiment 4, respectively, and this embodiment will not be described in detail here.

[0048] In addition, in an embodiment of the present application, when it is detected that there are events in the process of processing N memory access operations that cause the vector memory access instruction to be non-atomic, all the vector memory access instructions can be executed, and the execution results of the vector memory access instructions can be submitted, and then the above-mentioned events that cause the vector memory access instruction to be non-atomic can be processed. Specifically, first, when it is detected that the N memory access operations are marked with interruption marks, it means that there is an interruption event in the processing of the N memory access operations. At this time, after the N memory access operations are emitted and executed, the execution results of the N memory access operations are submitted, and after all the execution results are submitted, the interruption event is responded to. Second, for the barrier instruction, all memory access operations can be emitted and executed first, and after all the memory access operation execution results are submitted, the barrier instruction is processed. Since the exception event is an event inside the instruction to be processed, once an exception event is encountered during the instruction processing process, there will be no submission of all the execution effects of the instruction. This process will be described in detail from the two dimensions of interruption events and barrier instructions in combination with Embodiment 2, Embodiment 3 and Embodiment 4, respectively, and this embodiment will not be described in detail here.

[0049] The atomicity maintaining method provided in the embodiment of the present application generates N memory access operations according to a vector memory access instruction, and checks whether there is an event that causes the vector memory access instruction to be non-atomic during the processing of the N memory access operations; if there is an event that causes the vector memory access instruction to be non-atomic, then the processing of any memory access operation among the N memory access operations does not produce any processing effect, or the N memory access operations produce all processing effects, thereby achieving the maintenance of the atomicity of the vector instruction; adopting the above technical scheme, for the parallel execution mechanism of vector instructions in the prior art or the concurrent execution mechanism of multiple operations obtained by splitting a barrier instruction and other vector instructions, when encountering an event that causes the vector memory access instruction to be non-atomic, not executing all memory access operations, not submitting the execution results of all memory access operations, or submitting the execution results of all memory access operations, in a vector memory access instruction, there is no situation in which some memory access operations obtained by splitting the vector memory access instruction have produced execution effects, while other memory access operations do not produce execution effects, thereby effectively ensuring the atomicity of the vector instruction.

[0050] Embodiment 2

[0051] Reference Figure 2 , showing a step flow chart of an atomicity preservation method of embodiment 2 of the present application.

[0052] The atomicity preservation method provided in the embodiment of the present application may be executed by a CPU, and the event that causes the vector memory access instruction to be non-atomic is an interrupt event. Based on this, the atomicity preservation method includes the following steps:

[0053] Step 201: Generate N memory access operations according to the vector memory access instruction, where N is a positive integer greater than or equal to 1.

[0054] In an embodiment of the present application, a vector memory access instruction can simultaneously implement the same processing on a group of data. In actual applications, after receiving a vector memory access instruction, the vector memory access instruction can be split into N memory access operations, where N is a positive integer greater than or equal to 1.

[0055] In this example, the vector memory access instruction may be a Load instruction or a Store instruction.

[0056] After N memory access operations are generated according to the vector memory access instruction, step 202 is executed.

[0057] Step 202: After checking that an event occurs during the processing of N memory access operations that causes the vector memory access instruction to be non-atomic, and the event is an interrupt event, a corresponding identifier can be added to the N memory access operations to indicate that an interrupt event occurs during the processing of the N memory access operations.

[0058] In an embodiment of the present application, the step of checking whether there is an interrupt event during the processing of N memory access operations can be performed in the emission phase of the N memory access operations, or in the execution phase of the N memory access operations.

[0059] In a specific implementation of the present application, the interruption marking method may include:

[0060] Step A1: During the processing of the vector memory access instruction, in response to an interruption, an interruption flag is added to one or more of the N memory access operations.

[0061] In practical applications, the number of vector memory access instructions is huge. After obtaining a vector memory access instruction, the vector memory access instruction will be added to the cache and wait for issuance for execution; during the processing of the vector memory access instruction, the vector memory access instruction can be checked for interrupt events to check whether there is an interrupt event that causes the vector memory access instruction to be non-atomic during the processing of the vector memory access instruction; in a specific implementation, since the interrupt event is an external event, the CPU can check in real time whether an interrupt request is received during the processing of the vector memory access instruction to determine whether there is an interrupt event during the processing of the vector memory access instruction based on the check result, that is, when the CPU receives an interrupt request, it determines that the check result is that there is an interrupt event during the processing of the vector memory access instruction.

[0062] Of course, other methods may also be used to check whether there is an interrupt event that causes the vector memory access instruction to be non-atomic during the processing of the vector memory access instruction. Specifically, the method for checking the interrupt event may be determined according to business requirements, and this embodiment does not limit this.

[0063] In an embodiment of the present application, an interrupt flag can be used to indicate that an interrupt event occurs during the processing of N memory access operations; specifically, the form of the interrupt flag can be determined based on business requirements, and this embodiment does not impose any restrictions on this.

[0064] Furthermore, if it is detected that an event causing the vector memory access instruction to be non-atomic occurs during the processing of the N memory access operations, and the event is an interrupt event, an interrupt flag may be added to the memory access operation.

[0065] In the specific implementation, the situations where interrupt flags are added for memory access operations can be divided into the following two situations:

[0066] 1. Add an interrupt flag to any memory access operation among N memory access operations. Specifically, an interrupt flag may be added to the first memory access operation, or to the last memory access operation, or to any memory access operation between the first memory access operation and the last memory access operation (it can be understood that the above descriptions of the first and the last refer to the limitation according to the execution order of the N memory access operations). For example, a vector memory access instruction can be divided into 5 memory access operations, which are sorted from first to last in the execution order of the 5 memory access operations: memory access operation 1, memory access operation 2, memory access operation 3, memory access operation 4 and memory access operation 5. When adding an interrupt flag, an interrupt flag may be added to the first memory access operation (i.e., memory access operation 1), or to the last memory access operation (i.e., memory access operation 5), or to the memory access operation between the first memory access operation and the last memory access operation (i.e., memory access operation 2 or memory access operation 3 or memory access operation 4).

[0067] Preferably, an interrupt flag is added to the first memory access operation among the N memory access operations.

[0068] It can be understood that the above examples are merely examples listed for a better understanding of the technical solutions of the embodiments of the present application, and are not intended to be the sole limitation to the embodiments.

[0069] 2. Add interrupt flags to all N memory access operations, that is, add interrupt flags to all N memory access operations. For example, continuing with the above example, after the vector memory access instruction is split into 5 memory access operations, interrupt flags can be added to these 5 memory access operations, that is, add interrupt flags to memory access operation 1, memory access operation 2, memory access operation 3, memory access operation 4 and memory access operation 5.

[0070] In an embodiment of the present application, by adding an interrupt flag for indicating an interrupt event to N memory access operations, in the subsequent processing of the vector memory access instruction, it is possible to intuitively understand whether the vector memory access instruction is atomic through the interrupt flag to decide how to process the vector memory access instruction.

[0071] Step 203: Check whether the N memory access operations have an interrupt flag.

[0072] In an embodiment of the present application, after adding interrupt flags to N memory access operations in the above manner, the N memory access operations can be checked in sequence to see whether they are marked with interrupt flags to determine whether an interrupt event occurs during the processing of the N memory access operations.

[0073] After adding interrupt flags to N memory access operations, the interrupt flags can be checked in the following two ways.

[0074] First, check in sequence whether N memory access operations are marked with interrupt flags.

[0075] Second, check whether the first memory access operation among the N memory access operations is marked with an interrupt flag.

[0076] After detecting that N memory access operations have interrupt flags, step 204 is executed.

[0077] After checking that the N memory access operations are not marked with an interrupt flag, step 205 is executed.

[0078] Step 204: If the interrupt flag exists, any memory access operation among the N memory access operations does not produce any processing effect, or the N memory access operations produce all processing effects.

[0079] After checking that N memory access operations are marked with interrupt flags, any of the N memory access operations does not produce any processing effect, or the N memory access operations produce all processing effects. Specifically, it can be described in combination with the following four situations.

[0080] In the first case, if it is detected that any of the N memory access operations is marked with an interrupt flag, none of the N memory access operations will be emitted or executed. At this time, none of the N memory access operations will produce any execution processing effect, that is, after responding to the interrupt event, the N memory access operations will continue to be emitted or executed, and the execution results of the N memory access operations will be submitted.

[0081] Optionally, if it is detected in the transmission phase of N memory access operations that any memory access operation among the N memory access operations is marked with an interrupt flag, then none of the N memory access operations are transmitted, or, N memory access operations are transmitted but none of the N memory access operations are executed; if it is detected in the execution phase of N memory access operations that any of the N memory access operations is marked with an interrupt flag, then the execution result of any of the N memory access operations is not submitted.

[0082] In the second case, if it is detected that any of the N memory access operations is marked with an interrupt flag, each of the N memory access operations is submitted and executed, and the execution results of all the N memory access operations are submitted, that is, after all the N memory access operations are executed and the corresponding execution results are submitted, the interrupt event is responded to.

[0083] In the third case, if it is detected that the first memory access operation among N memory access operations is marked with an interrupt flag, none of the N memory access operations will be emitted or executed. At this time, none of the N memory access operations will produce any processing effect, that is, after responding to the interrupt event, N memory access operations will continue to be emitted or executed, and the execution results of the N memory access operations will be submitted.

[0084] Optionally, if it is detected in the transmission phase of N memory access operations that the first memory access operation among the N memory access operations is marked with an interrupt flag, then none of the N memory access operations are transmitted, or, N memory access operations are transmitted but none of the N memory access operations are executed; if it is detected in the execution phase of N memory access operations that the first memory access operation among the N memory access operations is marked with an interrupt flag, then the execution result of any of the N memory access operations is not submitted.

[0085] In the fourth case, if it is detected that the first memory access operation among N memory access operations is marked with an interrupt flag, each of the N memory access operations can be executed and the execution results of all N memory access operations can be submitted, that is, after all N memory access operations are executed and the corresponding execution results are submitted, the interrupt event can be responded to.

[0086] Step 205: If the interrupt flag is not marked in any of the N memory access operations, the N memory access operations are executed, and the execution results of the N memory access operations are submitted.

[0087] If it is detected that the interrupt flag is not marked in any of the N memory access operations, the N memory access operations may be executed to obtain the execution results of the N memory access operations, and then the execution results of the N memory access operations may be submitted.

[0088] The atomicity maintaining method provided in the embodiment of the present application generates N memory access operations according to the vector memory access instruction, and checks whether the N memory access operations are marked with an interrupt flag. When the interrupt flag is checked, the processing of any memory access operation among the N memory access operations does not produce any processing effect, or the N memory access operations produce all processing effects. By adopting the technical solution of the present application, during the processing of the vector memory access operation, once an interrupt event occurs, it can be ensured that the vector memory access instructions are fully processed before responding to the interrupt event, or the vector memory access instructions are processed after the interrupt event is responded to, so that the vector memory access instruction will not submit only the execution results of part of the memory access operation due to the interrupt event, thereby realizing the maintenance of the atomicity of the vector instruction.

[0089] Embodiment 3

[0090] Reference Figure 3 , showing a step flow chart of an atomicity preservation method of embodiment 3 of the present application.

[0091] The atomicity preservation method provided in the embodiment of the present application may be executed by a CPU, and the event that causes the vector memory access instruction to be non-atomic is an exceptional event. Based on this, the atomicity preservation method includes the following steps:

[0092] Step 301: Generate N memory access operations according to the vector memory access instruction, where N is a positive integer greater than or equal to 1.

[0093] In an embodiment of the present application, a vector memory access instruction can simultaneously implement the same processing on a group of data. In actual applications, after receiving a vector memory access instruction, the vector memory access instruction can be split into N memory access operations, where N is a positive integer greater than or equal to 1.

[0094] In this example, the vector memory access instruction may be a Load instruction or a Store instruction.

[0095] After N memory access operations are generated according to the vector memory access instruction, step 302 is executed.

[0096] Step 302: Check whether any memory access operation among the N memory access operations will cause an exception event to occur during the processing, and obtain a check result.

[0097] After generating N memory access operations according to the vector memory access instruction, it is possible to check whether any of the N memory access operations will cause an exception event to occur during the processing to obtain a check result. The check process for the exception event can be described in detail in conjunction with the following specific implementation.

[0098] In the embodiment of the present application, the step of checking whether there are any exceptional events during the processing of the N memory access operations can be performed during the execution phase of the N memory access operations.

[0099] In a specific implementation of the present application, the above step 302 may include:

[0100] Sub-step S1: Obtain a memory access address of each of the N memory access operations.

[0101] In the embodiment of the present application, after N memory access operations are generated according to the vector memory access instruction, the memory access address of each of the N memory access operations can be obtained.

[0102] After the memory access address of each of the N memory access operations is obtained, sub-step S2 is executed.

[0103] Sub-step S2: Check whether each of the memory access addresses satisfies the exception event triggering condition; if so, determine as the check result that any memory access operation among the N memory access operations will cause an exception event to occur during the processing; otherwise, determine as the check result that no memory access operation among the N memory access operations will cause an exception event to occur during the processing.

[0104] After obtaining the memory access address of each of the N memory access operations, it is possible to check whether each memory access address satisfies the exception event triggering condition; if so, the existence of any memory access operation among the N memory access operations will cause an exception event to occur in the processing process, which is determined as the check result; otherwise, the non-existence of any memory access operation among the N memory access operations will cause an exception event to occur in the processing process, which is determined as the check result.

[0105] The exception event triggering conditions include at least one of the following conditions:

[0106] 1. The permission of any memory access operation has an attribute permission violation; among which, the attribute permission violation includes the segment attribute permission violation and the page attribute permission violation, and the attribute permission mainly refers to the read permission, write permission, execute permission, privilege level permission, etc.; the attribute permission violation is mainly used to characterize whether the action of any memory access operation / vector memory access instruction is consistent with the permission corresponding to the address accessed by the any memory access operation / vector memory access instruction. If not, it will be determined that the permission of any memory access operation / vector memory access instruction has an attribute permission violation.

[0107] 2. The address translation table does not contain any memory access address;

[0108] 3. The memory access address of the vector memory access instruction is out of bounds.

[0109] Step 303: Execute the N memory access operations.

[0110] After N memory access operations are generated according to the vector memory access instruction, the N memory access operations may be executed to obtain execution results of the N memory access operations.

[0111] Step 304: If the checking result indicates that there is a memory access operation among the N memory access operations that will cause an exception event to occur during the processing, the execution result of any memory access operation among the N memory access operations is not submitted, and the exception event is reported.

[0112] If the check result of the exception event indicates that there is a memory access operation among the N memory access operations that will cause an exception event to occur during the processing, the execution result of any memory access operation among the N memory access operations is not submitted, and the exception event is reported.

[0113] Step 305: If the checking result indicates that none of the N memory access operations will cause an exception to occur during the processing, then the execution results of the N memory access operations are submitted.

[0114] When the check result of the exception event indicates that none of the N memory access operations will cause an exception event to occur during the processing, the execution results of the N memory access operations may be submitted.

[0115] The atomicity maintenance method provided in the embodiment of the present application generates N memory access operations according to the vector memory access instruction, and checks whether any memory access operation among the N memory access operations will cause an exception event during the processing. If so, the execution result of any memory access operation among the N memory access operations is not submitted, and the exception event is reported. By adopting the technical solution of the present application, during the processing of the vector memory access operation, once an exception event occurs, it can be guaranteed to respond to the exception event, and the vector memory access instruction will not produce any processing effect, so that the vector memory access instruction will not submit only the processing results of part of the memory access operation due to the exception event, thereby realizing the maintenance of the atomicity of the vector instruction.

[0116] Embodiment 4

[0117] Reference Figure 4 , showing a step flow chart of an atomicity preservation method of embodiment 4 of the present application.

[0118] The atomicity preservation method provided in the embodiment of the present application may be executed by a CPU, and the event that causes the vector memory access instruction to be non-atomic is a barrier instruction event. Based on this, the atomicity preservation method includes the following steps:

[0119] Step 401: Generate N memory access operations according to the vector memory access instruction, where N is a positive integer greater than or equal to 1.

[0120] In an embodiment of the present application, a vector memory access instruction can simultaneously implement the same processing on a group of data. In actual applications, after receiving a vector memory access instruction, the vector memory access instruction can be split into N memory access operations, where N is a positive integer greater than or equal to 1.

[0121] In this example, the vector memory access instruction may be a Load instruction or a Store instruction.

[0122] After N memory access operations are generated according to the vector memory access instruction, step 402 is executed.

[0123] Step 402: Check whether there is a barrier instruction during the processing of the N memory access operations.

[0124] After N memory access operations are generated according to the vector memory access instruction, it may be checked whether there is a barrier instruction during the processing of the N memory access operations.

[0125] In the embodiment of the present application, the step of checking whether there are barrier instructions that affect atomicity during the processing of N memory access operations can be performed in the emission phase or the execution phase of the N memory access operations.

[0126] Step 403: in response to obtaining the barrier instruction, when it is confirmed that all the N memory access operations being executed have been completed, processing the barrier instruction; or

[0127] Step 404: In response to obtaining the vector memory access instruction, if there is a barrier instruction that has not been processed yet, cache the N memory access operations generated by the vector memory access instruction without processing, wait for the barrier instruction that has not been processed to be processed to be completed, and then process the N memory access operations.

[0128] If it is detected that there is a barrier instruction in the processing of N memory access operations, the obtained barrier instruction can be responded to; when it is confirmed that all the N memory access operations being executed have been completed and the execution results of the N memory access operations have all been submitted, the barrier instruction is processed; or

[0129] In response to obtaining the vector memory access instruction, if there is a barrier instruction that has not been processed yet, N memory access operations generated by the vector memory access instruction are cached without being issued or executed, and the barrier instruction that has not been processed yet is processed until it is completed before executing N memory access operations.

[0130] Among them, the above-mentioned step 403 and step 404 are parallel optional solutions after the execution of step 402, that is, after executing step 402, any step of step 403 and step 404 can be selected for execution, and step 403 and step 404 are not executed at the same time.

[0131] The atomicity maintaining method provided by the embodiment of the present application is to process the barrier instruction in response to obtaining the barrier instruction after checking and receiving the barrier instruction, and when it is confirmed that all the N memory access operations being processed have been processed, process the barrier instruction, or, in response to obtaining the vector memory access instruction, if there is a barrier instruction that has not been processed, cache the N memory access operations generated by the vector memory access instruction without processing, wait for the barrier instructions that have not been processed to be processed to be completed, and then process the N memory access operations; adopt the technical solution of the present application, first process the barrier instruction, and after the barrier instruction is processed, process the N memory access operations; or, first process the N memory access operations, after the N memory access operations are executed and all the execution results are submitted, then process the barrier instruction, so that the vector memory access instruction will not submit only the execution results of part of the memory access operations due to the barrier instruction, thereby realizing the maintenance of the atomicity of the vector instruction.

[0132] Embodiment 5

[0133] Reference Figure 5 , showing a step flow chart of an atomicity preservation method of Example 5 of the present application.

[0134] The embodiment of the present application provides another atomicity preservation method, which also covers the three events that affect the atomicity of vector memory access instructions described in Embodiments 2 to 4. Based on this, the atomicity preservation method includes the following steps:

[0135] Step 501: Generate N memory access operations according to the vector memory access instruction, where N is a positive integer greater than or equal to 1.

[0136] In the embodiments of the present application, the definition and decoding method of the vector memory access instruction are consistent with those of Embodiments 2 to 4 and will not be repeated here.

[0137] Step 502: In the emission phase of the N memory access operations, check whether there is an interrupt event during the processing of the N memory access operations; if so, execute step 504; otherwise, execute step 503. At the same time, in the emission phase of the N memory access operations, check whether there is a barrier instruction during the processing of the N memory access operations; if so, execute step 505; otherwise, execute step 503.

[0138] Step 503: Send N memory access operations, and during the execution phase of the N memory access operations, check whether any of the N memory access operations has an exception event during the processing; if so, execute step 506; otherwise, execute step 507.

[0139] Step 504: Do not process any memory access operation among the N memory access operations and respond to the interrupt event.

[0140] In the embodiment of the present application, not processing any memory access operation among the N memory access operations includes not transmitting any memory access operation among the N memory access operations, or not executing any memory access operation among the N memory access operations.

[0141] Furthermore, after the interrupt event response is completed, the N memory access operations are processed; that is, if any of the N memory access operations is not transmitted, step 503 is executed after the interrupt event response is completed; if any of the N memory access operations is not executed, after the interrupt event response is completed, the step of checking whether any of the N memory access operations has an exceptional event during the processing process in step 503 is executed during the execution phase of the N memory access operations.

[0142] Step 505: Cache the N memory access operations without processing them, wait for the barrier instructions that have not been processed to be processed to be processed, and then process the N memory access operations.

[0143] In the embodiment of the present application, the processing of the barrier instructions that have not been processed yet is waited for to be completed before processing the N memory access operations, that is, waiting for the processing of the barrier instructions that have not been processed yet to be completed before executing step 503.

[0144] Furthermore, in step 502 and step 504, if there is an interrupt event / barrier instruction, step 503 may be executed first, and after the execution results of N memory access operations are submitted / exceptional events are reported, the interrupt event / barrier instruction is responded to.

[0145] Step 506: Do not submit any memory access operation among the N memory access operations, and report an exception event.

[0146] Step 507: Execute the N memory access operations and submit the execution results of the N memory access operations.

[0147] Embodiment 6

[0148] 6 , there is shown a structural block diagram of a processor according to a sixth embodiment of the present application.

[0149] like Figure 6-A As shown, the processor of the embodiment of the present application includes:

[0150] A decoding unit 61, used for acquiring a vector memory access instruction and generating N memory access operations according to the vector memory access instruction, where N is a positive integer greater than or equal to 1;

[0151] The processing unit 62 is used to check whether there is an event during the processing of the N memory access operations that causes the vector memory access instruction to be non-atomic; if the event exists, any memory access operation among the N memory access operations does not produce any processing effect, or the N memory access operations produce all processing effects.

[0152] The processor unit 62 is specifically used to: check whether there is at least one of an interrupt event, an exception event, and a barrier instruction during the processing of the N memory access operations; if so, determine whether there is an event during the processing of the N memory access operations that causes the vector memory access instruction to be non-atomic.

[0153] like Figure 6-B As shown, the processor includes an instruction memory 63, and the vector memory access instruction of the decoding unit can come from the instruction memory.

[0154] Optionally, the processing unit 62 includes: a transmitting unit 621, an executing unit 622 and a submitting unit 623.

[0155] The transmitting unit 621 is used to check whether there is an event that causes the vector memory access instruction to be non-atomic during the processing of the N memory access operations, and in response to the occurrence of an interrupt event during the processing of the vector memory access instruction, add an interrupt flag to one or more of the N memory access operations; the interrupt flag is used to indicate that an interrupt event has occurred during the processing of the vector memory access instruction.

[0156] Optionally, the transmitting unit 621 is specifically configured to add the interrupt flag to any memory access operation among the N memory access operations.

[0157] Optionally, the transmitting unit 621 is specifically configured to add the interrupt flag to all of the N memory access operations.

[0158] Optionally, the transmitting unit 621 is used to sequentially check whether the N memory access operations are marked with the interrupt flag; if any memory access operation among the N memory access operations is marked with the interrupt flag, any memory access operation of the N memory access operations is not transmitted.

[0159] Optionally, the transmitting unit 621 is used to sequentially check whether the N memory access operations are marked with the interruption flag; if it is determined that any memory access operation among the N memory access operations is marked with the interruption flag, then transmit the N memory access operations;

[0160] The execution unit 622 is used to cache the N memory access operations generated by the vector memory access instruction, but not execute any of the N memory access operations, wait for the interrupt event to be processed, and then execute the N memory access operations.

[0161] Optionally, the transmitting unit 621 is used to sequentially check whether the N memory access operations are marked with the interruption flag; if it is determined that any memory access operation among the N memory access operations is marked with the interruption flag, then transmit the N memory access operations;

[0162] The execution unit 622 is used to execute each memory access operation of the N memory access operations;

[0163] The submitting unit 623 is used to submit the execution results of the N memory access operations;

[0164] When the processor confirms that the execution results of the N memory access operations have all been submitted, the interrupt event is processed.

[0165] Optionally, the transmitting unit 621 is used to check whether the first memory access operation among the N memory access operations is marked with the interrupt flag, and if the first memory access operation is marked with the interrupt flag, no one of the N memory access operations is transmitted.

[0166] Optionally, the transmitting unit 621 is used to check whether the first memory access operation among the N memory access operations is marked with the interruption flag; if it is determined that the first memory access operation is marked with the interruption flag, transmitting the N memory access operations;

[0167] The execution unit 622 is used to cache the N memory access operations generated by the vector memory access instruction, but not execute any of the N memory access operations, wait for the interrupt event to be processed, and then execute the N memory access operations.

[0168] Optionally, the transmitting unit 621 is used to check whether the first memory access operation among the N memory access operations is marked with the interruption flag; if it is determined that the first memory access operation is marked with the interruption flag, transmitting the N memory access operations;

[0169] The execution unit 622 is used to execute each memory access operation of the N memory access operations;

[0170] The submitting unit 623 is used to submit the execution results of the N memory access operations.

[0171] Optionally, the transmitting unit 621 is configured to transmit the N memory access operations if none of the N memory access operations are marked with the interrupt flag;

[0172] The execution unit 622 is used to execute the N memory access operations;

[0173] The submitting unit 623 is used to submit the execution results of the N memory access operations.

[0174] Optionally, the transmitting unit 621 is used to check whether any memory access operation among the N memory access operations will cause an exception event to occur during the processing, obtain a check result, and transmit the N memory access operations;

[0175] The execution unit 622 is used to execute the N memory access operations;

[0176] The submitting unit 623 is configured to not submit the execution result of any memory access operation among the N memory access operations and report the exception event if the checking result indicates that there is a memory access operation among the N memory access operations that will cause an exception event to occur during the processing.

[0177] Optionally, the transmitting unit 621 is used to transmit the N memory access operations;

[0178] The execution unit 622 is used to execute the N memory access operations, and check whether any of the N memory access operations will cause an exception event to occur during the processing, and obtain a check result;

[0179] The submitting unit 623 is used to submit the execution results of each of the N memory access operations and report the exception event if the checking result indicates that there is a memory access operation among the N memory access operations that will cause an exception event to occur during the processing.

[0180] Optionally, the transmitting unit 621 is used to obtain the memory access address of each of the N memory access operations; check whether each of the memory access addresses satisfies the triggering condition of an exception event, and if so, determine that the existence of any memory access operation in the N memory access operations will cause an exception event to occur in the processing process as a check result; otherwise, determine that the existence of any memory access operation in the N memory access operations will cause an exception event to occur in the processing process as a check result;

[0181] The exceptional event triggering condition includes at least one of the following conditions:

[0182] Any of the permissions for the memory access operation has illegal attribute permissions;

[0183] The address conversion table does not contain any of the memory access addresses;

[0184] The memory access address of the vector memory access instruction is an out-of-bounds address.

[0185] Optionally, the submitting unit 621 is configured to submit the execution results of the N memory access operations if the checking result indicates that none of the N memory access operations will cause an exception to occur during the processing.

[0186] Optionally, the processing unit 62 is configured to respond to the barrier instruction when it is determined that the barrier instruction is received; process the barrier instruction when it is confirmed that all the N memory access operations being processed have been completed and the execution results have been submitted; or

[0187] In response to obtaining the vector memory access instruction, if there is a barrier instruction that has not been processed yet, N memory access operations generated by the vector memory access instruction are cached without being executed, and the N memory access operations are executed after the barrier instruction that has not been processed yet is processed.

[0188] Optionally, the vector memory access instruction is a Load instruction or a Store instruction; the processing unit further includes an execution unit; the processor further includes a general register 64;

[0189] When the vector memory access instruction is a Load instruction, the execution unit 622 is specifically used to: execute reading of the operand at the address indicated by the vector memory access instruction from the memory; the commit unit 623 is used to read the operand into the designated general register 64;

[0190] When the vector memory access instruction is a Store instruction, the execution unit 622 is specifically used to execute the fetching of the operand at the address indicated by the vector memory access instruction from the specified general register 64; the commit unit is used to write the operand into the memory.

[0191] The processor in the embodiment of the present application is used to implement the corresponding atomicity maintenance method in the aforementioned method embodiment, and has the beneficial effects of the corresponding method implementation, which will not be repeated here.

[0192] Embodiment 7

[0193] Reference Figure 7 , showing a structural schematic diagram of an electronic device for maintaining atomicity according to embodiment 7 of the present application.

[0194] like Figure 7 As shown, the electronic device may include one or more of the following components: a processing component 702 , a memory 704 , a power component 706 , a multimedia component 708 , an audio component 710 , an input / output (I / O) interface 712 , a sensor component 714 , and a communication component 716 .

[0195] The processing component 702 generally controls the overall operation of the electronic device, such as operations associated with display, data communication, camera operation, and recording operation. The processing component 702 may include one or more processors 720 to process instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 702 may include one or more modules to facilitate the interaction between the processing component 702 and other components. For example, the processing component 702 may include a multimedia module to facilitate the interaction between the multimedia component 708 and the processing component 702.

[0196] The memory 704 is configured to store various types of data to support the operation of the electronic device. Examples of such data include instructions for any application or method operating on the electronic device, contact data, phone book data, messages, pictures, videos, etc. The memory 704 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0197] The power supply component 706 provides power to various components of the electronic device. The power supply component 706 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the terminal 700.

[0198] The multimedia component 708 includes a screen that provides an output interface between the electronic device and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 708 includes a front camera and / or a rear camera. When the electronic device is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0199] The audio component 710 is configured to output and / or input audio signals. For example, the audio component 710 includes a microphone (MIC), and when the terminal is in an operation mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is configured to receive an external audio signal. The received audio signal can be further stored in the memory 704 or sent via the communication component 717. In some embodiments, the audio component 710 also includes a speaker for outputting audio signals.

[0200] I / O interface 712 provides an interface between processing component 702 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: a home button, a volume button, a start button, and a lock button.

[0201] The sensor assembly 714 includes one or more sensors for providing various aspects of status assessment for the electronic device 700. For example, the sensor assembly 714 can detect the open / closed state of the electronic device 700, the relative positioning of the components, such as the display and keypad of the terminal, and the sensor assembly 714 can also detect the position change of the terminal or a component of the terminal, the presence or absence of contact between the user and the electronic device, the orientation or acceleration / deceleration of the electronic device and the temperature change of the electronic device. The sensor assembly 714 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 714 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 714 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor or a temperature sensor.

[0202] The communication component 716 is configured to facilitate wired or wireless communication between the electronic device and other devices. The electronic device can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 716 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 716 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0203] In an exemplary embodiment, the electronic device may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to process the atomicity maintenance methods described in embodiments one to five above.

[0204] The electronic device of the embodiment of the present application is used to implement the corresponding atomicity maintenance methods in the aforementioned multiple method embodiments, and has the beneficial effects of the corresponding method implementation, which will not be repeated here.

[0205] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0206] The above is a detailed introduction to an atomicity maintenance method, processor and electronic device provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

[0207] The algorithm and display provided herein are not inherently related to any particular computer, electronic system or other device. Various general purpose systems can also be used together with the teachings based on this. According to the above description, it is obvious that the structure required for constructing such systems. In addition, the application is not directed to any specific programming language either. It should be understood that various programming languages ​​can be utilized to implement the content of the application described herein, and the description of the specific language above is for the purpose of disclosing the best mode of implementation of the application.

[0208] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0209] Similarly, it should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various inventive aspects, in the above description of the exemplary embodiments of the present application, the various features of the present application are sometimes grouped together into a single embodiment, figure, or description thereof. However, the disclosed method should not be interpreted as reflecting the following intention: the claimed application requires more features than the features explicitly recited in each claim. More specifically, as reflected in the claims below, the inventive aspects lie in less than all the features of the single embodiment disclosed above. Therefore, the claims following the specific embodiment are hereby expressly incorporated into the specific embodiment, wherein each claim itself serves as a separate embodiment of the present application.

[0210] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and in addition they may be divided into a plurality of submodules or subunits or subcomponents. Except that at least some of such features and / or processes or units are mutually exclusive, all features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this manner may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose.

[0211] In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present application and form different embodiments. For example, in the claims below, any one of the claimed embodiments may be used in any combination.

[0212] The various component embodiments of the present application can be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. It should be understood by those skilled in the art that a microprocessor or a digital signal processor (DSP) can be used in practice to implement some or all functions of some or all components in the browser client device according to the embodiment of the present application. The present application can also be implemented as a device or apparatus program (e.g., a computer program and a computer program product) for executing part or all of the methods described herein. Such a program implementing the present application can be stored on a computer-readable medium, or can have the form of one or more signals. Such a signal can be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0213] It should be noted that the above embodiments illustrate the present application rather than limit the present application, and that those skilled in the art may design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets should not be constructed as a limitation to the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "one" or "an" preceding an element does not exclude the presence of multiple such elements. The present application may be implemented by means of hardware including several different elements and by means of a suitably programmed computer. In a unit claim that lists several devices, several of these devices may be embodied by the same hardware item. The use of the words first, second, and third, etc. does not indicate any order. These words may be interpreted as names.

Claims

1. A method for maintaining atomicity, characterized in that: The method comprises: Generate N memory access operations according to the vector memory access instruction, where N is a positive integer greater than or equal to 1; Checking whether there is an event during the processing of the N memory access operations that causes the vector memory access instruction to be non-atomic; In the case where the event exists, any memory access operation among the N memory access operations does not produce any processing effect, or the N memory access operations produce all processing effects; wherein the memory access operation does not produce any processing effect means that the memory access operation is executed but the execution result of the memory access operation is not submitted, or the memory access operation is not executed, or the memory access operation is not emitted; the memory access operation produces all processing effects means that all the N memory access operations are executed, and the execution results of the N memory access operations are all submitted; Checking whether there is an event during the processing of the N memory access operations that causes the vector memory access instruction to be non-atomic includes: Checking whether there is at least one of an interrupt event, an exception event, and a barrier instruction during the processing of the N memory access operations; If so, it is determined that an event occurs during the processing of the N memory access operations that causes the vector memory access instruction to be non-atomic.

2. The method according to claim 1, characterized in that Before checking whether there is an event during the processing of the N memory access operations that causes the vector memory access instruction to be non-atomic, the method further includes: In the process of processing the vector memory access instruction, in response to an interrupt event, adding an interrupt flag to one or more of the N memory access operations; The interrupt flag is used to indicate that an interrupt event occurs during the processing of the vector memory access instruction.

3. The method according to claim 2, characterized in that The adding an interrupt flag to one or more of the N memory access operations includes: The interrupt flag is added to any memory access operation of the N memory access operations.

4. The method according to claim 2, characterized in that: The adding an interrupt flag to one or more of the N memory access operations includes: The interrupt flag is added to all the N memory access operations.

5. The method according to any one of claims 2 to 4, characterized in that: The checking whether there is an event during the processing of the N memory access operations that causes the vector memory access instruction to be non-atomic includes: Checking in sequence whether the N memory access operations are marked with the interrupt flag; In the case where the event occurs, any memory access operation among the N memory access operations does not produce any processing effect, including: If any of the N memory access operations is marked with the interrupt flag, the N memory access operations generated by the vector memory access instruction are cached without executing any of the N memory access operations, and the N memory access operations are executed after the interrupt event is processed.

6. The method according to any one of claims 2 to 4, characterized in that: The checking whether there is an event during the processing of the N memory access operations that causes the vector memory access instruction to be non-atomic includes: Checking in sequence whether the N memory access operations are marked with the interrupt flag; In the case where the event occurs, the N memory access operations produce all processing effects, including: If any memory access operation among the N memory access operations is marked with the interrupt flag, then all of the N memory access operations are executed; and Submitting the execution results of the N memory access operations; When it is confirmed that the execution results of the N memory access operations have all been submitted, the interrupt event is processed.

7. The method according to any one of claims 2 to 4, characterized in that: The checking whether there is an event during the processing of the N memory access operations that causes the vector memory access instruction to be non-atomic includes: Checking whether a first memory access operation among the N memory access operations is marked with the interrupt flag; In the case where the event occurs, any memory access operation among the N memory access operations does not produce any processing effect, including: If the first memory access operation is marked with the interrupt flag, the N memory access operations generated by the vector memory access instruction are cached without executing any of the N memory access operations, and the N memory access operations are executed after the interrupt event is processed.

8. The method according to any one of claims 2 to 4, characterized in that: The checking whether there is an event during the processing of the N memory access operations that causes the vector memory access instruction to be non-atomic includes: Checking whether a first memory access operation among the N memory access operations is marked with the interrupt flag; In the case where the event occurs, the N memory access operations produce all processing effects, including: If the first memory access operation is marked with the interrupt flag, then all of the N memory access operations are executed; and Submitting the execution results of the N memory access operations; When it is confirmed that the execution results of the N memory access operations have all been submitted, the interrupt event is processed.

9. The method according to any one of claims 2 to 4, characterized in that: The method further comprises: If the interrupt flag is not marked in any of the N memory access operations, executing the N memory access operations; and Submit the execution results of the N memory access operations.

10. The method according to any one of claims 1 to 4, characterized in that: The checking whether there is an event during the processing of the N memory access operations that causes the vector memory access instruction to be non-atomic includes: Checking whether any memory access operation among the N memory access operations will cause an exception event to occur during the processing, and obtaining a check result; and Execute the N memory access operations; In the event of the occurrence of the event, any memory access operation among the N memory access operations does not produce any processing effect, including: If the checking result indicates that there is a memory access operation among the N memory access operations that will cause an exception event to occur during the processing, the execution result of any memory access operation among the N memory access operations is not submitted, and the exception event is reported.

11. The method according to claim 10, characterized in that Check whether any of the N memory access operations will cause an exception to occur during the processing, and obtain a check result, including: Obtaining a memory access address of each of the N memory access operations; Checking whether each of the memory access addresses satisfies the triggering condition of an exception event, and if so, determining that any memory access operation among the N memory access operations will cause an exception event to occur during the processing as a check result; otherwise, determining that no memory access operation among the N memory access operations will cause an exception event to occur during the processing as a check result; The exceptional event triggering condition includes at least one of the following conditions: Any of the permissions for the memory access operation has illegal attribute permissions; The address conversion table does not contain any of the memory access addresses; The memory access address of the vector memory access instruction is an out-of-bounds address.

12. The method according to claim 10, characterized in that After executing the N memory access operations, the method further includes: If the checking result indicates that none of the N memory access operations will cause an exception to occur during the processing, the execution results of the N memory access operations are submitted.

13. The method according to any one of claims 1 to 4, characterized in that: The checking whether there is an event during the processing of the N memory access operations that causes the vector memory access instruction to be non-atomic includes: Check whether the barrier command is received; In the presence of the event, any one of the N memory access operations does not produce any processing effect, or the N memory access operations produce all processing effects, including: In response to obtaining the barrier instruction, when it is confirmed that all the N memory access operations being processed have been executed to completion and the execution results have been submitted, processing the barrier instruction; or In response to obtaining the vector memory access instruction, if there is a barrier instruction that has not been processed yet, N memory access operations generated by the vector memory access instruction are cached without being executed, and the N memory access operations are executed after the barrier instruction that has not been processed yet is processed.

14. The method according to any one of claims 1 to 4, characterized in that: The vector memory access instruction is a Load instruction or a Store instruction; When the vector memory access instruction is a Load instruction, executing the N memory access operations includes: Execute an operation of reading the operand at the address indicated by the vector memory access instruction from the memory to a designated general register; When the vector memory access instruction is a Store instruction, executing the N memory access operations includes: An operation of writing the operand at the address indicated by the vector memory access instruction from the designated general register to the memory is executed.

15. A processor, characterized in that: include: A decoding unit, used for acquiring a vector memory access instruction and generating N memory access operations according to the vector memory access instruction, where N is a positive integer greater than or equal to 1; A processing unit, used for checking whether there is an event in the processing of the N memory access operations that causes the vector memory access instruction to be non-atomic; in the case of the presence of the event, any memory access operation of the N memory access operations does not produce any processing effect, or the N memory access operations produce all processing effects; wherein, the memory access operation does not produce any processing effect means that the memory access operation is executed but the execution result of the memory access operation is not submitted, or the memory access operation is not executed, or the memory access operation is not emitted; the memory access operation produces all processing effects means that all the N memory access operations are executed, and the execution results of the N memory access operations are all submitted; The processor unit is specifically used for: Check whether there is at least one of an interrupt event, an exception event, and a barrier instruction during the processing of the N memory access operations; if so, determine whether there is an event during the processing of the N memory access operations that causes the vector memory access instruction to be non-atomic.

16. The processor according to claim 15, characterized in that The processing unit includes a transmitting unit; The transmitting unit is configured to, before checking whether there is an event causing the vector memory access instruction to be non-atomic during the processing of the N memory access operations, add an interrupt flag to one or more of the N memory access operations in response to an interrupt event occurring during the processing of the vector memory access instruction; The interrupt flag is used to indicate that an interrupt event occurs during the processing of the vector memory access instruction.

17. The processor according to claim 16, characterized in that The transmitting unit is specifically configured to add the interrupt flag to any memory access operation among the N memory access operations.

18. The processor according to claim 16, characterized in that The transmitting unit is specifically used to add the interrupt flag to all the N memory access operations.

19. The processor according to any one of claims 16 to 18, characterized in that: The transmitting unit is used to sequentially check whether the N memory access operations are marked with the interruption mark; if any memory access operation among the N memory access operations is marked with the interruption mark, then any memory access operation among the N memory access operations is not transmitted.

20. The processor according to any one of claims 16 to 18, characterized in that: The processing unit also includes an execution unit; The transmitting unit is used to sequentially check whether the N memory access operations are marked with the interruption mark; if it is determined that any memory access operation among the N memory access operations is marked with the interruption mark, then transmit the N memory access operations; The execution unit is used to cache N memory access operations generated by the vector memory access instruction, but not execute any of the N memory access operations, wait for the interrupt event to be processed, and then execute the N memory access operations.

21. The processor according to any one of claims 16 to 18, characterized in that: The processing unit also includes an execution unit and a submission unit; The transmitting unit is used to sequentially check whether the N memory access operations are marked with the interruption mark; if it is determined that any memory access operation among the N memory access operations is marked with the interruption mark, then transmit the N memory access operations; The execution unit is used to execute each memory access operation of the N memory access operations; The submitting unit is used to submit the execution results of the N memory access operations.

22. The processor according to any one of claims 16 to 18, characterized in that: The transmitting unit is used to check whether the first memory access operation among the N memory access operations is marked with the interruption mark, and if the first memory access operation is marked with the interruption mark, any of the N memory access operations is not transmitted.

23. The processor according to any one of claims 16 to 18, characterized in that: The processing unit also includes an execution unit; The transmitting unit is used to check whether the first memory access operation among the N memory access operations is marked with the interruption mark; if it is determined that the first memory access operation is marked with the interruption mark, then transmit the N memory access operations; The execution unit is used to cache N memory access operations generated by the vector memory access instruction, but not execute any of the N memory access operations, wait for the interrupt event to be processed, and then execute the N memory access operations.

24. The processor according to any one of claims 16 to 18, characterized in that: The processing unit also includes an execution unit and a submission unit; The transmitting unit is used to check whether the first memory access operation among the N memory access operations is marked with the interruption mark; if it is determined that the first memory access operation is marked with the interruption mark, then transmit the N memory access operations; The execution unit is used to execute each memory access operation of the N memory access operations; The submitting unit is used to submit the execution results of the N memory access operations.

25. The processor according to any one of claims 16 to 18, characterized in that: The processing unit also includes an execution unit and a submission unit; The transmitting unit is used to transmit the N memory access operations if none of the N memory access operations are marked with the interrupt flag; The execution unit is used to execute the N memory access operations; The submitting unit is used to submit the execution results of the N memory access operations.

26. The processor according to claim 15, characterized in that The processing unit includes an emission unit, an execution unit and a submission unit; The transmitting unit is used to transmit the N memory access operations; The execution unit is used to execute the N memory access operations, and check whether any of the N memory access operations will cause an exception event to occur during the processing, and obtain a check result; The submitting unit is used for not submitting the execution result of any memory access operation among the N memory access operations and reporting the exception event if the checking result indicates that there is a memory access operation among the N memory access operations that will cause an exception event to occur during the processing.

27. The processor according to claim 25, characterized in that The execution unit is used to obtain the memory access address of each of the N memory access operations; check whether each of the memory access addresses meets the exception event triggering condition, and if so, determine that any memory access operation in the N memory access operations will cause an exception event to occur during the processing as a check result; Otherwise, it is determined as a check result that none of the N memory access operations will result in an exception event occurring during the processing; The exceptional event triggering condition includes at least one of the following conditions: Any of the permissions for the memory access operation has illegal attribute permissions; The address conversion table does not contain any of the memory access addresses; The memory access address of the vector memory access instruction is an out-of-bounds address.

28. The processor according to claim 27, characterized in that The submitting unit is used to submit the execution results of the N memory access operations if the checking result indicates that none of the N memory access operations will cause an exception event to occur during the processing.

29. The processor according to claim 15, characterized in that The processing unit is used for: When it is determined that a barrier instruction is received, responding to the barrier instruction; when it is confirmed that all the N memory access operations being processed have been executed and the execution results have been submitted, processing the barrier instruction; or In response to obtaining the vector memory access instruction, if there is a barrier instruction that has not been processed yet, N memory access operations generated by the vector memory access instruction are cached without being executed, and the N memory access operations are executed after the barrier instruction that has not been processed yet is processed.

30. An electronic device, characterized in that: The system comprises a memory and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by one or more processors to execute the atomicity preservation method as claimed in one or more of claims 1-14.

Images