Test vector storage and debugging method, device, equipment and storage medium

Abstract

The present application provides a method, device, equipment and storage medium for storing and debugging test vectors. The method includes: determining multiple test vectors; wherein the multiple test vectors are for the same test problem in the chip, and the test frequencies of the test problems corresponding to any two test vectors in the multiple test vectors are different; dividing each test vector respectively, and obtaining the configuration part and the test port part of each test vector; storing the information of multiple measurement vectors; wherein the information of the multiple test vectors includes the configuration part of each test vector obtained and the test port part of any one of the test vectors. The method of the present application, by dividing the test vector into a configuration part and a test port part for storage, saves the space occupied by the test vector because only one identical test port part is stored, and does not change the properties of the test vector itself, thereby improving the accuracy of the test results.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method, device, equipment and storage medium for storing and debugging test vectors. Background Art

[0002] With the continuous development of integrated circuit design, multi-core chips have been used more and more widely. Due to the large number of cores in multi-core chips, the number of measurement vectors generated by the testability design based on multi-core chips is also increasing. The test vectors occupy a large space, resulting in high testing costs.

[0003] In order to save space and test cost, the prior art directly compresses a large number of test vectors and uses the compressed test vectors for debugging in the chip.

[0004] However, existing technologies reduce the accuracy of test results. Summary of the invention

[0005] The present application provides a test vector storage and debugging method, device, equipment and storage medium, which solves the problem of low accuracy of test results in the prior art.

[0006] In a first aspect, the present application provides a method for storing a test vector, comprising:

[0007] Determine multiple test vectors; wherein the multiple test vectors are for the same test problem in the chip, and the test frequencies of the test problems corresponding to any two test vectors in the multiple test vectors are different, and each test vector is divided respectively to obtain the configuration part and the test port part of each test vector; store information of multiple measurement vectors; wherein the information of the multiple test vectors includes the configuration part of each test vector obtained and the test port part of any one of the test vectors, and the test vectors are divided into the configuration part and the test port part for storage, and only the same test port part in a test vector is stored, thereby reducing the space occupied by the test vector, storing different configuration parts of the test vector, and improving the accuracy of the test result.

[0008] Optionally, the test port part is compressed to obtain a compression result of the test port part; information of multiple measurement vectors is stored, including: storing the configuration part of each acquired test vector; and storing the compression result of the test port part. By compressing the test port part of the test vector, the space occupied by the test vector is further saved while ensuring the accuracy of the test result.

[0009] Optionally, the test port part includes a scanning part and a non-scanning part; the test port part is compressed, including: a first compression process is performed on the scanning part of the test port part; and a second compression process is performed on the non-scanning part of the test port part; wherein the compression multiple used in the second compression process is greater than the compression multiple used in the first compression process, and the test port part is divided into a scanning port and a non-scanning port for compression, which reduces the space occupied by the test vector and further ensures the accuracy of the test results.

[0010] Optionally, the chip is a multi-core chip; information of multiple measurement vectors is stored, including: for homogeneous cores in the multi-core chip, information of multiple test vectors corresponding to a target core is stored, wherein the target core is any one of the homogeneous cores, and only information of the homogeneous cores in one multi-core chip is stored, thereby further saving the space occupied by the test vectors while ensuring the accuracy of the test results.

[0011] In a second aspect, the present application provides a method for storing a test vector, comprising:

[0012] A test port portion of a test vector is compressed to obtain a compression result of the test port portion, wherein the test vector includes a configuration portion and a test port portion; information of a measurement vector is stored, wherein the information of the test vector includes the configuration portion and a compression result of the compressed test port portion, the test port portion of the test vector is compressed, and then the configuration portion and the test port portion of the test vector are stored. Since the compression of the test port portion of the test vector will not affect the test result of the test vector, the accuracy of the test result is improved while the test vector storage space is saved.

[0013] Optionally, the test port portion of the test vector is compressed, including:

[0014] A first compression process is performed on a portion of the test port part corresponding to the scanning port, and a second compression process is performed on a portion of the test port part corresponding to the non-scanning port, wherein a compression multiple used in the second compression process is greater than a compression multiple used in the first compression process, and the test port part is divided into a scanning port and a non-scanning port for compression, and the non-scanning port is compressed at a compression multiple greater than the scanning port, thereby reducing the space occupied by the test vector and further ensuring the accuracy of the test result.

[0015] In a third aspect, the present application provides a test vector debugging method, comprising:

[0016] Acquire information of multiple measurement vectors; wherein the information of the multiple test vectors includes: configuration parts of the multiple test vectors and a test port part of any one of the multiple test vectors, the multiple test vectors are for the same test problem in the chip, and the test frequencies of the test problems corresponding to any two of the multiple test vectors are different; determine multiple test vectors according to the test path, wherein each test vector includes a configuration part and a test port part corresponding to the test vector, and determine the test vector during the debugging process by acquiring a same test port part and configuration parts corresponding to different test vectors, thereby obtaining a test vector that occupies a small space and has a high test result accuracy.

[0017] Optionally, the information of multiple test vectors includes: the configuration parts of the multiple test vectors and the compression results of the test port part of any one of the multiple test vectors; the method also includes: decompressing the compression results of the test port part of any one of the multiple test vectors to obtain the test port part, and obtaining the test port part of the original test vector by decompression, and forming a test vector with the configuration part, thereby further improving the accuracy of the test results.

[0018] Optionally, the test port part includes a scanning part and a non-scanning part; the compression result of the test port part is decompressed, including: a first decompression process is performed on the scanning part in the test port part, and a second decompression process is performed on the non-scanning part in the test port part, wherein the compression multiple used in the second decompression process is greater than the compression multiple used in the first decompression process, and different decompression multiples are performed according to the different compression multiples of the part corresponding to the scanning port and the part corresponding to the non-scanning port of the test port part during compression, thereby further improving the accuracy of the test result.

[0019] Optionally, the chip is a multi-core chip; based on the information of multiple test vectors corresponding to the target core, the information of the test vector that is isomorphic to the target core is obtained.

[0020] In a fourth aspect, the present application provides a test vector debugging method, comprising:

[0021] The test port part of the test vector is compressed to obtain the compression result of the test port part, wherein the test vector includes a configuration part and a test port part; the information of the measurement vector is obtained, wherein the information of the test vector includes the configuration part and the compression result of the compressed test port part; the compression result of the test port part is decompressed to obtain the test port part; the test vector is obtained, wherein the test vector includes a configuration part and a test port part, the test port part of the test vector is compressed to obtain the configuration part of the test vector and the compression result of the compressed test port part, thereby saving the space occupied by the test vector during the debugging process, decompressing the test port part, and obtaining a test vector with high accuracy together with the configuration part, thereby improving the accuracy of the test result.

[0022] Optionally, the compression result of the test port part is decompressed, including: performing a first decompression process on the part corresponding to the scan port of the test port part, and performing a second decompression process on the part corresponding to the non-scan port of the test port part, wherein a compression multiple used in the second decompression process is greater than a compression multiple used in the first decompression process, thereby further improving the accuracy of the test results.

[0023] In a fifth aspect, the present application provides a storage device for a test vector, comprising:

[0024] A first determination module is used to determine a plurality of test vectors; wherein the plurality of test vectors are for the same test problem in the chip, and the test frequencies of the test problem corresponding to any two of the plurality of test vectors are different; each of the test vectors is divided respectively to obtain a configuration part and a model test port part of each of the test vectors;

[0025] The first storage module is used to store the information of the multiple measurement vectors; wherein the information of the multiple test vectors includes the acquired configuration part of each of the test vectors and the test port part of any one of the test vectors.

[0026] Optionally, also include:

[0027] A first compression module, used for compressing the test port part to obtain a compression result of the test port part;

[0028] Accordingly, the first storage module is specifically used for:

[0029] storing the configuration part of each test vector obtained; and storing the compression result of the test port part.

[0030] Optionally, the first compression module is specifically used for:

[0031] A first compression process is performed on the scan part of the test port part; and a second compression process is performed on the non-scan part of the test port part; wherein the compression multiple used in the second compression process is greater than the compression multiple used in the first compression process.

[0032] Optionally, the chip is a multi-core chip; the first storage module is specifically used to: for homogeneous cores in the multi-core chip, store information of multiple test vectors corresponding to a target core, wherein the target core is any one of the homogeneous cores.

[0033] In a sixth aspect, the present application provides a storage device for a test vector, comprising:

[0034] A second compression module is used to compress the test port part of the test vector to obtain a compression result of the test port part, wherein the test vector includes a configuration part and a test port part;

[0035] The second storage module is used to store the information of the measurement vector, where the information of the test vector includes the compression result of the configuration part and the compression test port part.

[0036] Optionally, the second compression module is specifically used to: perform a first compression processing on the part corresponding to the scanning port of the test port part, and perform a second compression processing on the part corresponding to the non-scanning port of the test port part, wherein the compression multiple used in the second compression processing is greater than the compression multiple used in the first compression processing.

[0037] In a seventh aspect, the present application provides a debugging device for a test vector, including:

[0038] A third acquisition module is configured to acquire information of a plurality of measurement vectors, wherein the information of the plurality of test vectors includes: a configuration part of the plurality of test vectors and a model test port part of any one of the plurality of test vectors, the plurality of test vectors are directed to a same test problem in the chip, and any two of the plurality of test vectors have different test frequencies corresponding to the test problem;

[0039] The third determination module is used to determine the multiple test vectors according to the test path, wherein each test vector includes a configuration part of the test vector and the test port part.

[0040] Optionally, a compression result of the configuration part of the multiple test vectors and the test port part of any one of the multiple test vectors;

[0041] The device also includes:

[0042] The third decompression module is used to decompress the compression result of the test port part of any one of the multiple test vectors to obtain the test port part.

[0043] Optionally, the test port part includes a scanning part and a non-scanning part; the third decompression module is specifically used to: perform a first decompression process on the scanning part in the test port part, and perform a second decompression process on the non-scanning part in the test port part, wherein a compression factor used in the second decompression process is greater than a compression factor used in the first decompression process.

[0044] Optionally, the chip is a multi-core chip; based on the information of multiple test vectors corresponding to the target core, the information of the test vector that is isomorphic to the target core is obtained.

[0045] In an eighth aspect, the present application provides a debugging device for a test vector, comprising:

[0046] a fourth compression module, configured to compress a test port portion of a test vector and obtain a compression result of the test port portion, wherein the test vector includes a configuration portion and a test port portion;

[0047] A fourth acquisition module, used to acquire information of a measurement vector, wherein the information of the measurement vector includes a compression result of a configuration part and a compression test port part;

[0048] A fourth decompression module, used for decompressing the compression result of the test port part to obtain the test port part;

[0049] The fifth acquisition module is used to acquire a test vector, where the test vector includes a configuration part and a test port part.

[0050] Optionally, the fourth decompression module is specifically used to: perform a first decompression process on the part corresponding to the scanning port of the test port part, and perform a second decompression process on the part corresponding to the non-scanning port of the test port part, wherein a compression factor adopted by the second decompression process is greater than a compression factor adopted by the first decompression process.

[0051] In a ninth aspect, the present application provides a computer-readable storage medium, in which computer execution instructions are stored. When the computer execution instructions are executed by a processor, they are used to implement the test vector storage method as described in the first aspect or the optional method of the first aspect.

[0052] In a tenth aspect, the present application provides a computer-readable storage medium, which stores computer execution instructions. When the computer execution instructions are executed by a processor, they are used to implement the test vector storage method as described in the first aspect or the optional method of the first aspect.

[0053] In an eleventh aspect, the present application provides a computer-readable storage medium, in which computer execution instructions are stored. When the computer execution instructions are executed by a processor, they are used to implement the debugging method of the test vector as described in the third aspect or the optional method of the third aspect.

[0054] In a twelfth aspect, the present application provides a computer-readable storage medium, which stores computer execution instructions. When the computer execution instructions are executed by a processor, they are used to implement the debugging method of the test vector as described in the fourth aspect or the optional method of the fourth aspect.

[0055] In a thirteenth aspect, the present application provides a computer program product, comprising computer execution instructions, which, when executed by a processor, are used to implement the test vector storage method as described in the first aspect or the optional manner of the first aspect.

[0056] In a fourteenth aspect, the present application provides a computer program product, comprising computer execution instructions, which, when executed by a processor, are used to implement the test vector storage method as described in the second aspect or the optional manner of the second aspect.

[0057] In a fifteenth aspect, the present application provides a computer program product, comprising computer execution instructions, which, when executed by a processor, are used to implement the debugging method of the test vector as described in the third aspect or the optional manner of the third aspect.

[0058] In a sixteenth aspect, the present application provides a computer program product, comprising computer execution instructions, which, when executed by a processor, are used to implement the debugging method of the test vector as described in the fourth aspect or the optional manner of the fourth aspect.

[0059] The present application provides a method, apparatus, device and medium for storing and debugging test vectors, wherein when determining multiple test vectors, the test vectors are split into a configuration part and a test port part, the multiple test vectors are test vectors corresponding to different test frequencies for the same test problem, the multiple test vectors have different configuration parts and the same test port parts; when storing information of multiple measurement vectors, only multiple different configuration parts and one test port part need to be stored, and the test vectors are divided into a configuration part and a test port part for storage. Since only one test port part is stored, the space occupied by the test vector is saved, and the configuration part and test port part of all test vectors can be obtained in the storage without changing the properties of the test vector itself, thereby improving the accuracy of the test results. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0061] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0062] Figure 1 A schematic diagram of an application scenario provided for an embodiment of the present application;

[0063] Figure 2 A schematic diagram of a flow chart of a method for storing test vectors provided in one embodiment of the present application;

[0064] Figure 3 A schematic diagram of a flow chart of another test vector storage method provided in an embodiment of the present application;

[0065] Figure 4a An example table of chip test vector space occupation provided in an embodiment of the present application;

[0066] Figure 4b Another example table of chip module test vector occupancy space provided in an embodiment of the present application;

[0067] Figure 4c An example table of space occupied by another chip module test vector provided in an embodiment of the present application;

[0068] Figure 4d A test vector splitting schematic diagram provided for an embodiment of the present application;

[0069] Figure 5 A schematic diagram of a flow chart of another test vector storage method provided in an embodiment of the present application;

[0070] Figure 6 A flowchart of a test vector debugging method provided in one embodiment of the present application;

[0071] Figure 7 A flowchart of a test vector debugging method provided in one embodiment of the present application;

[0072] Figure 8 A schematic diagram of the structure of a storage device for test vectors provided in one embodiment of the present application;

[0073] Fig. 9A schematic diagram of the structure of another test vector storage device provided in one embodiment of the present application;

[0074] Fig.10 A schematic diagram of the structure of a debugging device for a test vector provided in one embodiment of the present application;

[0075] Fig.11 A schematic diagram of the structure of another test vector debugging device provided in one embodiment of the present application;

[0076] Fig.12 A schematic diagram of the structure of a storage device for test vectors provided in one embodiment of the present application;

[0077] Fig.13 A schematic diagram of the structure of a debugging device for a test vector provided in an embodiment of the present application.

[0078] The above drawings show clear embodiments of the present disclosure, which will be described in more detail below. These drawings and text descriptions are not intended to limit the scope of the present disclosure in any way, but to illustrate the concepts of the present disclosure to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0079] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0080] First, the terms involved in this application are explained:

[0081] Very Large Scale Integration (VLSI) is an integrated circuit that combines a large number of transistors into a single chip, with a higher level of integration than large-scale integrated circuits.

[0082] Design for Testability (DFT): It is an integrated circuit design technology that implants some special structures into the circuit during the design phase so that it can be tested after the design is completed. Circuit testing is sometimes not easy because many internal node signals of the circuit are difficult to control and observe externally. By adding testability design structures, such as scan chains, internal signals can be exposed to the outside of the circuit, so that problems inside the circuit can be located by detecting the internal signals of the circuit outside the circuit.

[0083] Automatic test pattern generation (ATPG): is a tool that can generate test patterns for testing manufactured integrated circuits, that is, it designs and generates test patterns for various fault models.

[0084] Demonstratively, Figure 1 This is a schematic diagram of an application scenario provided by an embodiment of the present application, that is, a test process diagram for testing the digital part of a VLSI circuit. Figure 1 As shown, the DTF of the circuit includes input 101, design test 102, output 103 and comparison 105 with expected output 104, so as to obtain test result 106; the input signal received by input 101 includes test vectors generated by ATPG, so the test vector occupies too much space, which will increase the debugging process of the chip; especially for multi-core chips, there are many test vectors, and a large number of test vectors will greatly increase the debugging time. In order to solve the problem of large space occupied by test vectors during the test process, the prior art usually directly compresses the test vectors. Due to the high complexity of the test vectors of chips, especially multi-core chips, the test vectors will be damaged during the compression process, and the compressed test vectors may not be able to be debugged normally, resulting in the problem of low accuracy of the test results.

[0085] In order to solve the above technical problems, the present application provides a method, device, equipment and medium for storing and debugging test vectors of a chip. The main idea of ​​the present application is: when determining multiple test vectors, each test vector is split into a configuration part and a test port part, and the multiple test vectors are test vectors corresponding to different test frequencies for the same test problem, and the configuration parts of the multiple test vectors are different, and the test port parts are the same; when storing information of multiple measurement vectors, only multiple different configuration parts and one test port part need to be stored.

[0086] The technical solution of this application is described in detail below:

[0087] Figure 2 A flowchart of a test vector storage method provided in one embodiment of the present application. The method is executed by part or all of a test vector storage device, and the test vector storage device may be located in a chip; the so-called part of the test vector storage device may refer to a processor in the test vector storage device. The following describes the test vector storage method of the chip with the test vector storage device as the execution subject. Figure 2 As shown, the method comprises the following steps:

[0088] S201: A test vector storage device determines a plurality of test vectors.

[0089] Among them, multiple test vectors are aimed at the same test problem in the chip, and the test frequencies of the test problems corresponding to any two test vectors in the multiple test vectors are different; each test vector is divided separately to obtain the configuration part and the test port part of each test vector. For each test vector, the configuration part refers to the information used to determine the fault type, and its test frequency is different. The test port part is mainly the description information of the input and output status of the designed logical function. In a specific application, the test port part can be represented by pattern0-n, which refers to the test mode scan chain information generated according to the fault type, and n represents the number of specific scan chains, which is a positive integer; that is, the test port information part can contain information representing n scan chains.

[0090] The above-mentioned multiple test vectors refer to all test vectors for the same test problem.

[0091] The following uses pattern0-n to represent the test port part as an example to introduce the processing flow of the measurement vector.

[0092] S202: A storage device for test vectors of a chip stores information of a plurality of measurement vectors.

[0093] The information of the multiple test vectors includes the configuration part of each acquired test vector and any pattern 0-n part.

[0094] The following description is given for S201 and S202:

[0095] Each test vector includes a configuration part and a pattern0-n part; for the same test problem, multiple test vectors can be used for testing and verification, and the pattern0-n parts of any two test vectors in the multiple test vectors are the same; and different measurement vectors correspond to different test frequencies, and different test frequencies can be represented by the configuration part in the test vector, therefore, the configuration parts of any two different test vectors in the above multiple test vectors are different.

[0096] Optionally, for any test vector, the configuration part and the pattern0-n part can be divided according to the function descriptors corresponding to different parameters in the test vector; wherein the function descriptor is used to identify the function corresponding to each parameter in the test vector. Exemplarily, for any test vector, there are two function descriptors corresponding, namely function descriptor A and function descriptor B, function descriptor A represents the configuration part, and function descriptor B represents the pattern0-n part; the test vector contains parameter 1, parameter 2, parameter 3, parameter 4 and parameter 5, the function descriptor corresponding to parameter 1 is A, the function descriptors corresponding to parameter 1 and parameter 2 are both A, and the function descriptors corresponding to parameter 3, parameter 4 and parameter 5 are all B; it can be seen that parameter 1 and parameter 2 belong to the configuration part, and parameters 3 to 5 belong to the pattern part. This is only an exemplary case, and the number of parameters contained in any test vector in actual application will be greater than that in the above example.

[0097] For the same test problem, multiple test frequencies need to be set, and the multiple test frequencies are combined to realize multiple tests on the same test problem, thereby ensuring the accuracy of chip testing; there is a one-to-one correspondence between test vectors and test frequencies, and for each test frequency, in order to ensure the feasibility and accuracy of the test, the corresponding configuration part is set respectively, that is, different test frequencies correspond to different test vectors, and the configuration parts of different test vectors are different; and for the same test problem, the pattern 0-n parts of different test vectors are the same, so the test vector can be divided into two parts, namely, the configuration part and the pattern 0-n part; when storing test vectors, only one pattern 0-n part and the configuration parts of all test vectors need to be stored to store all test vectors; since only one pattern 0-n part is stored, the space occupied by the test vector is saved, and the configuration parts and pattern 0-n parts of all test vectors can be directly obtained in the storage device, and the properties of the test vector itself are not changed, thereby improving the accuracy of the test results.

[0098] Optionally, the chip is a multi-core chip; for homogeneous cores in the multi-core chip, information of multiple test vectors corresponding to a target core is stored; wherein the target core is any one of the homogeneous cores. For a multi-core chip, there are generally homogeneous cores inside. Homogeneous cores refer to processor cores with the same chip structure and the same trigger pins. Therefore, the test vectors for the same test problems corresponding to the homogeneous cores are the same; when storing homogeneous cores, only the test vector of one processor core needs to be stored, thereby further reducing the space occupied by the test vectors.

[0099] Figure 3 A flowchart of another test vector storage method provided in an embodiment of the present application is shown below. Figure 3 is Figure 2 The method is implemented on the basis of the embodiment; further, before S202, it also includes:

[0100] S2011: The storage device of the test vector compresses the pattern 0-n part to obtain a compression result of the pattern 0-n part.

[0101] Accordingly, S202 includes:

[0102] S202a: The storage device of the test vector stores the configuration part of each acquired test vector and stores the compression result of the pattern 0-n part.

[0103] The following description is given for S2011:

[0104] The configuration part of each test vector includes different configuration parts of multiple different test vectors.

[0105] Before storing the test vectors, each test vector can be processed in the same manner as test vector A: first, the pattern 0-n part of the test vector A is compressed; because during the test process, the configuration part of the test vector A undertakes the main test task, and the pattern 0-n part of the test vector A basically does not affect the test results, therefore compressing the pattern 0-n part of the test vector A can further save the space occupied by the test vector while ensuring the accuracy of the test results.

[0106] Optionally, the compression multiple of pattern 0-n portion of test vector A is determined according to the time frame of the test vector. For test vector A, the number of time frames required for pattern 0-n portion determines the compression rate of pattern0-n portion; for example, a general integrated circuit automatic test equipment (ATE) contains 8 time frames. If pattern0-n portion of test vector A requires 4 time frames, then the pattern 0-n portion can be compressed to a maximum of one-half of the original. This compression multiple can be determined according to the specific situation of the test vector, and this application does not impose specific restrictions on this.

[0107] Optionally, the chip is a multi-core chip; for homogeneous cores in the multi-core chip, information of multiple test vectors corresponding to a target core is stored, wherein the target core is any one of the homogeneous cores. For multi-core chips, there are generally homogeneous cores inside, which refer to processor cores with the same structure and the same trigger pins in the chip. Therefore, the test vectors corresponding to the same test problem of the homogeneous cores are the same. When storing, only one identical test vector is stored, thereby further reducing the space occupied by the test vector.

[0108] Exemplary, Figure 4a This is an example table of chip test vector space occupation provided by an embodiment of the present application. Figure 4b Another example table of chip module test vector occupancy space provided in an embodiment of the present application is as follows: Figure 4c This is an example table of another chip module test vector occupation space provided in an embodiment of the present application. Figure 4a As shown, the CPUIP module is one of the modules of the multi-core chip. The storage process of the above test vectors is introduced by taking the CPUIP module as an example. The CPUIP module has a total of four cores, CPUIP0, CPUIP1, CPUIP2, and CPUIP3. The test vectors generated by each core include three vectors: vector PD, vector TF, and vector SA. Among them, the first column in the figure is the name of the pattern 0-n part in each test vector, the second column is the memory size occupied by the pattern 0-n part in each test vector, and the third column is the space occupied by the unit vector of the pattern 0-n part in each test vector.

[0109] like Figure 4a The space occupied by the test vectors before compression is given. The total space occupied by the CPUIP module test vectors is 25.964M. For example, the CPUIP module is compressed by X2, that is, the same space can store twice the number of compressed test vectors before compression; the space occupied by the compressed test vectors is as follows Figure 4b As shown, at this time, the space occupied by all compressed test vectors becomes half of the original space, and the total space occupied by the CPUIP module test vectors is 12.982M, realizing the compression of the test vectors.

[0110] Optionally, if core 0 and core 2 are isomorphic cores, core 1 and core 3 are also isomorphic cores; since the test vectors for the same test problem in isomorphic cores are the same, for any identical test vector corresponding to the isomorphic cores, only the pattern 0-n part of the test vector can be stored; for example, core 0 and core 2 can only store the pattern 0-n part of any identical test vector, and similarly, core 1 and core 3 can also only store the pattern 0-n part of any identical test vector, thereby obtaining Figure 4c The test vectors shown in the figure take up space. After the homogeneous core test vectors are compressed, the total space occupied by the CPUIP module test vectors is 6.491M.

[0111] This embodiment realizes the compression of the space occupied by the test vector storage. Since the time frame occupied by the pattern 0-n part is relatively characteristic, the time frames of the pattern 0-n parts of different test vectors can be compatible, which is convenient for compression compared to the configuration part. In addition, the space occupied by the pattern 0-n part is relatively large. Therefore, it is easy to compress the pattern 0-n part, and the pattern 0-n part has little effect on the test result after the test point is determined. Therefore, the pattern 0-n part is compressed, which saves the space occupied by the test vector and improves the accuracy of the test result on the basis of saving memory. Furthermore, the test vectors corresponding to the same test problem of the isomorphic core are the same. When storing, only one identical test vector is stored, thereby reducing the space occupied by the test vector on the basis of ensuring the accuracy of the test result.

[0112] Figure 4d A test vector splitting schematic diagram provided in an embodiment of the present application, comprising Figure 4d It can be seen that the test vector is divided into a configuration part and a pattern 0-n part. Compressing the test vector means compressing the pattern 0-n part. The pattern 0-n part can be divided into a scanning part and a non-scanning part for compression of different multiples. The scanning part refers to the port part mainly used in the test process, and in the specific chip debugging process, for different chips, there are some unused port parts, namely the non-scanning part; for the scanning part and the non-scanning part, different compression multiples can be used for compression. The scanning part of the pattern 0-n part of the test vector occupies more time frames, and is generally compressed to one-half of the original at most. The non-scanning part of the pattern 0-n part occupies fewer time frames and has basically no influence on the test results. Therefore, it can be compressed at a larger multiple, thereby further saving the space occupied by the test vector on the basis of ensuring the accuracy of the test results.

[0113] Optionally, the compression method for pattern 0-n may be coding compression, logical transformation compression or other compression methods for test vectors, and this application does not impose any specific restrictions on this.

[0114] Optionally, the pattern 0-n portion is compressed, including: performing a first compression process on the scanned portion in the pattern 0-n portion, and performing a second compression process on the non-scanned portion in the pattern 0-n portion, wherein the compression multiple used in the second compression process is greater than the compression multiple used in the first compression process. In this embodiment, the pattern 0-n portion of the test vector is divided into a scanned portion and a non-scanned portion, and a larger compression multiple is performed on the non-scanned portion having a small impact on the test result, and a smaller compression multiple is performed on the scanned portion, thereby further improving the accuracy of the test result and saving the space occupied by the test vector.

[0115] Figure 5 A flowchart of a method for storing test vectors of another chip provided in an embodiment of the present application is shown as follows: Figure 5 As shown, the method comprises the following steps:

[0116] S501: The storage device of the test vector compresses the pattern 0-n part of the test vector to obtain a compression result of the pattern 0-n part.

[0117] The test vector includes a configuration part and a pattern 0-n part.

[0118] S502: The storage device of the test vector stores the information of the measurement vector, where the information of the test vector includes the compression result of the configuration part and the pattern 0-n part.

[0119] When storing a test vector, the embodiment of the present application first compresses the pattern 0-n part of the test vector to obtain a compression result of the pattern 0-n part, and then stores the compression results of the configuration part and the pattern 0-n part, thereby reducing the space occupied by the test vector; at the same time, as the pattern 0-n part has a smaller impact on the test result, the pattern 0-n part is compressed without changing the configuration part of the test vector, thereby improving the accuracy of the test result.

[0120] Optionally, the compression method for pattern 0-n may be coding compression, logical transformation compression or other compression methods for test vectors, and this application does not impose any specific restrictions on this.

[0121] Optionally, compression processing is performed on the pattern 0-n part, including: performing a first compression processing on the scanning part in the pattern 0-n part, and performing a second compression processing on the non-scanning part in the pattern 0-n part; wherein the compression multiple used in the second compression processing is greater than the compression multiple used in the first compression processing, and the pattern0-n part of the test vector is divided into a scanning part and a non-scanning part, and the non-scanning part having a small impact on the test result is compressed with a larger multiple, and the scanning part is compressed with a smaller multiple, thereby further improving the accuracy of the test result.

[0122] Figure 6 A flowchart of a chip test vector debugging method provided in one embodiment of the present application is provided. The method is executed by part or all of a chip test vector debugging device. The so-called part of the chip test vector debugging device may refer to a processor in the chip test vector debugging device. The following describes the chip test vector debugging method with the chip test vector debugging device as the execution subject. Figure 6 As shown, the method comprises the following steps:

[0123] S601: The debugging device of the test vector obtains information of multiple measurement vectors.

[0124] Among them, the information of multiple test vectors includes: the configuration part of multiple test vectors and the pattern 0-n part of any one of the multiple test vectors; among them, the multiple test vectors are test vectors corresponding to different test frequencies for the same test problem, the configuration parts of every two test vectors in the multiple test vectors are different, and the pattern 0-n parts of the multiple test vectors are the same.

[0125] S602: The debugging device of the test vector determines a plurality of test vectors according to the test path.

[0126] Each test vector includes a configuration part and a pattern 0-n part corresponding to the test vector.

[0127] The test path refers to a circuit path where a test vector is located during the debugging process of a chip; it is understandable that the same test vector can be tested in multiple different test paths.

[0128] The following description is given for S601 and S602:

[0129] The chip needs to call the stored test vectors during the debugging process. When multiple test vectors are used to debug the same batch of pins of the chip, the pattern 0-n parts of the above multiple test vectors are the same. Therefore, when debugging different test frequencies and test problems of the same batch of pins, the pattern 0-n parts of the above multiple test vectors do not need to be repeatedly adjusted, and it can be achieved by adjusting the configuration part of each test vector accordingly; therefore, when calling the test vector, it is only necessary to obtain the pattern 0-n part once, thereby saving running space; and, the test vector is determined by reconstruction, and the original test vector can be obtained according to the same pattern 0-n part and the different configuration parts of multiple test vectors, thereby improving the accuracy of the test result.

[0130] Optionally, the information of the plurality of test vectors includes: a compression result of a plurality of different configuration parts and a pattern 0-n part;

[0131] The debugging method of the chip test vector also includes: the debugging device of the chip test vector decompresses the compression result of the pattern 0-n part to obtain the pattern 0-n part.

[0132] The test vector stored by the test vector storage method of the above-mentioned chip may include a compressed pattern0-n part. In order to ensure the accuracy of the test result, before determining the test vector, the compression result of the pattern 0-n part is decompressed to obtain a test vector that is closer to the original test vector, thereby further improving the accuracy of the test result.

[0133] Optionally, if the test frequency needs to be modified during the debugging process, only the configuration part of the above multiple test vectors can be modified.

[0134] Optionally, the compression results of the pattern 0-n part are decompressed, including: performing a first decompression process on the scanned part in the pattern 0-n part, and performing a second decompression process on the non-scanned part in the pattern 0-n part; wherein the compression multiple adopted by the second decompression process is greater than the compression multiple adopted by the first decompression process, and the compression results of the scanned part and the non-scanned part in the pattern 0-n part are decompressed according to different compression multiples, thereby further improving the accuracy of the test results.

[0135] Optionally, the chip is a multi-core chip; based on the information of multiple test vectors corresponding to the target core, the information of the test vector of the isomorphic core with the target core is obtained. For a multi-core chip, there are generally isomorphic cores inside. Isomorphic cores refer to processor cores with the same structure and trigger pins as the chip's processor cores. Therefore, the information of the test vectors corresponding to the same test problem of the isomorphic cores is the same, and then the test vector can be determined by obtaining the information of the test vector of the isomorphic core for the target core during the debugging process.

[0136] Figure 7 A flowchart of a method for debugging a chip test vector provided by an embodiment of the present application is shown as follows: Figure 7 As shown, the method comprises the following steps:

[0137] S701: The debugging device of the test vector compresses the pattern 0-n part of the test vector, and obtains the compression result of the pattern 0-n part.

[0138] The test vector includes a configuration part and a pattern 0-n part.

[0139] S702: The debugging device of the test vector obtains information of the measurement vector, where the information of the test vector includes compression results of the configuration part and the pattern 0-n part.

[0140] S703: The debugging device of the test vector decompresses the compression result of the pattern 0-n part to obtain the pattern 0-n part.

[0141] S704: The debugging device of the test vector obtains the test vector, where the test vector includes a configuration part and a pattern 0-n part.

[0142] The following are instructions for the above steps:

[0143] Optionally, the compression method for pattern 0-n may be coding compression, logical transformation compression or other compression methods for test vectors, and this application does not impose any specific restrictions on this.

[0144] Before obtaining the test vector, the test vector is divided into a configuration part and a pattern 0-n part, and the pattern0-n part is compressed, which effectively saves the space occupied by the test vector and improves the running speed of the test. At the same time, the configuration part is retained and the pattern 0-n part is decompressed, which improves the accuracy of the test result.

[0145] Optionally, a first decompression process is performed on the scanned part in the pattern 0-n part, and a second decompression process is performed on the non-scanned part in the pattern 0-n part, wherein a compression factor adopted in the second decompression process is greater than a compression factor adopted in the first decompression process, and the compression results of the scanned part and the non-scanned part in the pattern 0-n part are decompressed according to different compression factors, thereby further improving the accuracy of the test results.

[0146] Figure 8 A schematic diagram of a storage device for test vectors of a chip provided in an embodiment of the present application is shown in FIG. Figure 8 As shown, the device of this embodiment includes:

[0147] The first determination module 1101 determines multiple test vectors; wherein the multiple test vectors are for the same test problem in the chip, and the test frequencies of the test problems corresponding to any two test vectors in the multiple test vectors are different; each test vector is divided respectively to obtain the configuration part and the model pattern 0-n part of each test vector.

[0148] The first storage module 1102 is used to store information of multiple measurement vectors; wherein the information of multiple test vectors includes the configuration part of each test vector obtained and the pattern 0-n part of any test vector.

[0149] Optionally, also include:

[0150] The first compression module 1103 is used to compress the pattern 0-n part to obtain the compression result of the pattern 0-n part.

[0151] Accordingly, the first storage module 1102 is specifically used for:

[0152] The configuration part of each acquired test vector is stored; and the compression result of the pattern 0-n part is stored.

[0153] Optionally, the pattern 0-n part includes a scanning part and a non-scanning part, and the first compression module 1103 is specifically used for:

[0154] A first compression process is performed on the scanned portion of the pattern 0-n portion, and a second compression process is performed on the non-scanned portion of the pattern 0-n portion, wherein a compression multiple used in the second compression process is greater than a compression multiple used in the first compression process.

[0155] Fig. 9 A schematic diagram of a storage device for test vectors of another chip provided in an embodiment of the present application is shown in FIG. Fig. 9 As shown, the device of this embodiment includes:

[0156] The second compression module 1201 is used to compress the pattern 0-n part of the test vector to obtain a compression result of the pattern 0-n part, wherein the test vector includes a configuration part and a pattern 0-n part.

[0157] The second storage module 1202 is used to store the information of the measurement vector, where the information of the measurement vector includes the compression result of the configuration part and the compression pattern 0-n part.

[0158] Optionally, the second compression module 1201 is specifically used to: perform a first compression process on the part corresponding to the scan port of the pattern 0-n part, and perform a second compression process on the part corresponding to the non-scan port of the pattern 0-n part, wherein the compression multiple used in the second compression process is greater than the compression multiple used in the first compression process.

[0159] Fig.10 A schematic diagram of a chip test vector debugging device provided in an embodiment of the present application, such as Fig.10 As shown, the device of this embodiment includes:

[0160] The third acquisition module 1301 is used to acquire information of multiple measurement vectors; wherein the information of the multiple test vectors includes: a configuration part of the multiple test vectors and a model pattern 0-n part of any one of the multiple test vectors, the multiple test vectors are aimed at the same test problem in the chip, and the test frequencies of the test problems corresponding to any two of the multiple test vectors are different;

[0161] The third determination module 1302 is used to determine a plurality of test vectors according to the test path, wherein each test vector includes a configuration part and a pattern 0-n part of the test vector.

[0162] Optionally, a compression result of a configuration portion of multiple test vectors and a pattern 0-n portion of any one of the multiple test vectors.

[0163] The device also includes:

[0164] The third decompression module 1303 is used to decompress the compression result of the pattern 0-n part of any test vector among the multiple test vectors to obtain the pattern 0-n part.

[0165] Optionally, the pattern 0-n part includes a scanning part and a non-scanning part; the third decompression module 1303 is specifically used to: perform a first decompression process on the scanning part in the pattern 0-n part, and perform a second decompression process on the non-scanning part in the pattern 0-n part, wherein a compression factor used in the second decompression process is greater than a compression factor used in the first decompression process.

[0166] Optionally, the chip is a multi-core chip; based on the information of multiple test vectors corresponding to the target core, the information of the test vector that is isomorphic to the target core is obtained.

[0167] Fig.11 A schematic diagram of the structure of another chip test vector debugging device provided in an embodiment of the present application, such as Fig.11 As shown, the device of this embodiment includes:

[0168] The fourth compression module 1401 is used to compress the pattern 0-n part of the test vector, and the compression result of the pattern 0-n part, wherein the test vector includes the configuration part and the pattern 0-n part;

[0169] A fourth acquisition module 1402 is used to acquire information of a measurement vector, where the information of the measurement vector includes a configuration part and a compression result of a compression pattern 0-n part;

[0170] The fourth decompression module 1403 is used to decompress the compression result of the pattern 0-n part to obtain the pattern 0-n part;

[0171] The fifth acquisition module 1404 is used to acquire a test vector, where the test vector includes a configuration part and a pattern 0-n part.

[0172] Optionally, the fourth decompression module 1403 is specifically used to: perform a first decompression process on the part corresponding to the scanning port of the pattern 0-n part, and perform a second decompression process on the part corresponding to the non-scanning port of the pattern 0-n part, wherein a compression factor used in the second decompression process is greater than a compression factor used in the first decompression process.

[0173] Fig.12 A schematic diagram of a storage device for chip test vectors provided in an embodiment of the present application. Fig.12 As shown, the storage device of the test vector of the chip includes: a processor 121 and a memory 122.

[0174] The memory 122 stores computer executable instructions.

[0175] The processor 121 executes the computer execution instructions stored in the memory 122, so that the processor 122 executes the above-mentioned method for storing the test vectors of the chip.

[0176] Optionally, the storage device for the test vector of the chip also includes: a transceiver 123 for communicating with other network devices or terminal devices.

[0177] The storage device of the test vector of the chip in the embodiment of the present application can be used to execute the technical solutions in the above-mentioned method embodiments of the present application. Its implementation principles and technical effects are similar and will not be repeated here.

[0178] An embodiment of the present application also provides a computer-readable storage medium, which stores computer execution instructions. When the computer execution instructions are executed by a processor, they are used to implement the storage method of test vectors of any of the chips described above.

[0179] An embodiment of the present application also provides a computer program product, which includes computer execution instructions, and when the computer execution instructions are executed by a processor, they are used to implement the storage method of test vectors of any of the chips described above.

[0180] Fig.13 A schematic diagram of the structure of a debugging device for a chip test vector provided in an embodiment of the present application. Fig.13 As shown, the debugging device of the test vector of the chip includes: a processor 131 and a memory 132.

[0181] The memory 132 stores computer executable instructions.

[0182] The processor 131 executes the computer execution instructions stored in the memory 132, so that the processor 132 executes the above-mentioned debugging method of the chip test vector.

[0183] Optionally, the debugging device for the test vector of the chip also includes: a transceiver 133 for communicating with other network devices or terminal devices.

[0184] The debugging device for the test vector of the chip in the embodiment of the present application can be used to execute the technical solutions in the above-mentioned method embodiments of the present application. Its implementation principles and technical effects are similar and will not be repeated here.

[0185] An embodiment of the present application also provides a computer-readable storage medium, which stores computer execution instructions. When the computer execution instructions are executed by a processor, they are used to implement a debugging method for a test vector of any of the chips described above.

[0186] An embodiment of the present application also provides a computer program product, which includes computer execution instructions. When the computer execution instructions are executed by a processor, they are used to implement the debugging method of the test vector of any of the chips described above.

[0187] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0188] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0189] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0190] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0191] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A method for storing test vectors, applied to a chip, characterized in that: include: Determine a plurality of test vectors; wherein the plurality of test vectors are for the same test problem in the chip, and any two of the plurality of test vectors correspond to different test frequencies of the test problem; Divide each of the test vectors respectively to obtain a configuration part and a test port part of each of the test vectors; wherein the configuration part of each of the test vectors is different, and the test port part of each of the test vectors is the same; The information of the plurality of measurement vectors is stored; wherein the information of the plurality of test vectors includes a configuration part of each of the test vectors and a test port part of any one of the test vectors.

2. The method according to claim 1, characterized in that Also includes: Performing compression processing on the test port portion to obtain a compression result of the test port portion; The storing of the information of the plurality of measurement vectors comprises: storing the configuration portion of each test vector obtained; as well as The compression result of the test port portion is stored.

3. The method according to claim 2, characterized in that The test port part includes a scanning part and a non-scanning part; and the compressing process on the test port part includes: performing a first compression process on a scan portion in the test port portion; and performing a second compression process on a non-scanning portion in the test port portion; The compression factor used in the second compression process is greater than the compression factor used in the first compression process.

4. The method according to any one of claims 1 to 3, characterized in that: The chip is a multi-core chip; Storing information of the plurality of measurement vectors, including: For homogeneous cores in a multi-core chip, information of multiple test vectors corresponding to a target core is stored, wherein the target core is any one of the homogeneous cores.

5. A test vector debugging method, applied to a chip, characterized in that: include: Acquire information of a plurality of measurement vectors; wherein the information of the plurality of test vectors includes a configuration part of the plurality of test vectors and a model test port part of any one of the plurality of test vectors, the plurality of test vectors are directed to a same test problem in the chip, and the test frequencies of the test problem corresponding to any two of the plurality of test vectors are different; wherein the configuration part of each of the test vectors is different, and the test port part of each of the test vectors is the same; The plurality of test vectors are determined according to the test path, wherein each test vector includes a configuration portion of the test vector and the test port portion.

6. The method according to claim 5, characterized in that The information of the plurality of test vectors includes: a compression result of a configuration part of the plurality of test vectors and a test port part of any one of the plurality of test vectors; The method further comprises: A compression result of the test port part of any one of the multiple test vectors is decompressed to obtain the test port part.

7. The method according to claim 6, characterized in that The test port part includes a scanning part and a non-scanning part; decompressing the compression result of the test port part includes: performing a first decompression process on the scan part in the test port part; and performing a second decompression process on a non-scanned portion of a portion of the test port; The compression factor used in the second decompression process is greater than the compression factor used in the first decompression process.

8. The method according to any one of claims 5 to 7, characterized in that: The chip is a multi-core chip; based on the information of multiple test vectors corresponding to the target core, the information of the test vector that is isomorphic to the target core is obtained.

9. A storage device for test vectors, characterized in that: include: A first determination module determines a plurality of test vectors; wherein the plurality of test vectors are for the same test problem in the chip, and any two of the plurality of test vectors correspond to different test frequencies of the test problem; Divide each of the test vectors respectively to obtain a configuration part and a test port part of each of the test vectors; wherein the configuration part of each of the test vectors is different, and the test port part of each of the test vectors is the same; The first storage module is used to store the information of the multiple measurement vectors; wherein the information of the multiple test vectors includes the acquired configuration part of each of the test vectors and the test port part of any one of the test vectors.

10. A debugging device for a test vector, characterized in that: include: A third acquisition module is used to acquire information of a plurality of measurement vectors; wherein the information of the plurality of test vectors includes: a configuration part of the plurality of test vectors and a model test port part of any one of the plurality of test vectors, the plurality of test vectors are directed to the same test problem in the chip, and the test frequencies of the test problem corresponding to any two of the plurality of test vectors are different; wherein the configuration part of each of the test vectors is different, and the test port part of each of the test vectors is the same; The third determination module is used to determine the multiple test vectors according to the test path, wherein each test vector includes a configuration part of the test vector and the test port part.

11. A storage device for test vectors, comprising: Memory and processor; The memory is used to store computer instructions; The processor is used to execute the computer instructions stored in the memory to implement the test vector storage method described in any one of claims 1 to 4.

12. A debugging device for a test vector, comprising: Memory and processor; The memory is used to store computer instructions; The processor is used to execute the computer instructions stored in the memory to implement the debugging method of the test vector according to any one of claims 5 to 8.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the test vector storage method according to any one of claims 1 to 4.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, which are used to implement the debugging method of the test vector according to any one of claims 5 to 8 when executed by a processor.

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