A method for storing and updating sensitive data of Internet of Vehicles equipment

Abstract

The present invention discloses a method for preserving and updating sensitive data of an Internet of Vehicles device. By establishing a mapping relationship between a physical page address and a logical page address of a target storage area, an online address fast search mode is adopted when reading and writing data to avoid memory overhead and software delay caused by initializing a physical page scan to establish a mapping table; when writing data, a rolling write and an incrementing sequence number method are adopted to support access to any logical address space that is smaller than the physical address space, and for high-frequency data updates, the physical space can be effectively utilized to increase the write life; an atomicity identifier is added to the physical page information to support the consistency of writing to multiple discontinuous address spaces generated by a single transaction write; through the detection of a physical page frame header, a frame tail, an incrementing sequence number and an atomic mark, the introduction of a backup page for multiple data exchanges is avoided, and a rapid integrity check is performed on the data during the power-on process to implement abnormal power-off protection for data.

Description

Technical Field

[0001] The present invention belongs to the technical field of vehicle networking, and in particular, relates to a method for storing and updating sensitive data of vehicle networking equipment. Background Art

[0002] With the rapid promotion of 5G technology, the Internet of Vehicles, as the most mature and connected field in the high-speed field of the Internet of Things, has rapidly penetrated the Internet of Vehicles industry and the scale of the industry has continued to expand. Consumers have higher and higher requirements for the intelligence of in-vehicle wireless terminals, and the security and reliability of vehicle information storage are becoming more and more worthy of attention. Especially in various Internet of Vehicles applications such as T-BOX, ETC, and V2X, in addition to basic vehicle information, there will also be vehicle diagnostic information, payment information, user identity information, positioning information, etc., which involve vehicle safety, user sensitive information, and financial data, and other data with higher security requirements. In the face of the complex application environment of automotive electronics, data needs to be processed in a highly reliable manner.

[0003] The reliability requirements for chips in automotive electronics are higher than those in consumer electronics, and they are easily affected by harsh environments such as high temperature, high humidity, vibration, and electromagnetic interference. Some important data needs to be stored on non-volatile storage media, such as EEPROM, Flash, MTP and other types of memory. Flash is widely used due to its higher integration density and efficient read and write performance. For application scenarios where embedded flash memory is integrated inside the chip, traditional storage management methods or file systems often require large resources. When mounted on an embedded chip, they often encounter problems such as insufficient memory, slow processing performance, lack of atomic characteristics, and poor exception handling capabilities. Summary of the invention

[0004] The purpose of the present invention is to provide a method for preserving and updating sensitive data of Internet of Vehicles equipment, which can realize the functions of data atomicity (consistency, integrity) protection, rolling balance, and power-off protection, and has the characteristics of small resources, high reliability, and long life.

[0005] To solve the above problems, the technical solution of the present invention is:

[0006] A method for storing and updating sensitive data of an Internet of Vehicles device, comprising:

[0007] Use embedded chip storage management system to save and update sensitive data of connected car devices, and establish mapping relationship between physical page address and logical page address of target storage area;

[0008] Recording the physical pages of the target storage area in a field format including a frame header, a logical page number, an increasing sequence number, an atomicity flag, data content, and a frame trailer, wherein the frame header and the frame trailer are used to confirm the integrity of the frame data, the logical page number corresponds to the target logical address, the increasing sequence number is used to record the number of data updates, and the atomicity flag is used to record the number of associated physical pages and the sequence number of each physical page included in each data update;

[0009] Obtain the target data to be updated, calculate the number of logical pages required to write the target data to be updated, quickly locate the physical page address where the target data is located according to the target logical address, load the target data to be updated into the internal cache, and update the field information of the physical page at the same time; write the target data to be updated in the internal cache into the logistics page address.

[0010] According to an embodiment of the present invention, the use of an embedded chip storage management system to save and update sensitive data of an Internet of Vehicles device further includes:

[0011] The embedded chip storage management system includes a processor, a data register, an SRAM buffer, a DMA controller, a Flash controller and a Flash memory;

[0012] The processor is used to initiate data saving and / or updating instructions;

[0013] The data register is used to store the target logical address, buffer location and data length information of the data;

[0014] The SRAM buffer is used to temporarily store target data;

[0015] The DMA controller is used to transfer data between the SRAM buffer and the Flash memory according to the data structure in the data register;

[0016] The Flash controller is used to initiate the read, write or erase operation of the Flash memory, control the signal and timing, and protect;

[0017] The Flash memory is used to store target data.

[0018] According to an embodiment of the present invention, a group of elements in the data register corresponds to a piece of data in the SRAM buffer, wherein the group of elements in the data register includes a target logical address, a buffer location and a data length.

[0019] According to one embodiment of the present invention, the DMA controller sends the target data to be updated to the Flash controller in sequence according to the data information in the data register and the data information in the SRAM buffer, and then the Flash controller updates the target data to be updated to the Flash memory according to the timing of reading, writing or erasing.

[0020] According to an embodiment of the present invention, when the target data to be updated includes multiple data blocks, the DMA controller processes the data blocks in a forward-to-backward order according to the target logical address;

[0021] When the data block crosses pages, the DMA controller splits the data block in a page boundary aligned manner, processes the data of the data block on the previous page first, and then processes the data of the data block on the next page;

[0022] When data blocks are adjacent, spaced or overlapping, the DMA controller pre-fetches the data in the target physical page address to the internal cache, and then directly overwrites the data in the internal cache with the target data to be updated in the SRAM buffer; wherein the overlapping data blocks are processed in order from front to back according to the target logical address.

[0023] According to an embodiment of the present invention, the Flash memory writes data to a physical address in a rolling write combined with an incrementing sequence number;

[0024] The rolling write adopts an index method to quickly locate an empty address in a physical page according to a target logical address. The location of the index is the physical address that can be written at present. After each data update, the index will search for the next empty address in sequence. When the index reaches the tail address of the Flash memory, it will scroll to the head address.

[0025] After each data update, the value of the incremental sequence number is increased by 1.

[0026] According to an embodiment of the present invention, the method of quickly locating the physical page address where the target data is located according to the target logical address further includes:

[0027] According to the target logical address, the current logical page number is matched with the logical page number corresponding to the target logical address in order from front to back. If the match is successful, the physical page address corresponding to the current logical page number is returned.

[0028] According to an embodiment of the present invention, when the embedded chip is powered on, it enters an initialization process; the initialization process is as follows:

[0029] Scan the physical pages quickly, skip empty pages directly, and erase pages with incomplete headers and footers directly;

[0030] For valid physical pages, record the value of the incremental sequence number of the physical page, set the variable MaxSeq to record the value of the maximum incremental sequence number, and set the variable Cnt to record the number of physical pages; compare whether the variable Cnt is less than the atomicity identifier in the physical page corresponding to the variable MaxSeq, if so, erase all physical pages whose incremental sequence numbers are equal to the variable MaxSeq; if not, erase all physical pages whose logical page numbers overlap with the new data and whose incremental sequence numbers are less than the variable MaxSeq.

[0031] According to one embodiment of the present invention, when reading data stored in an embedded chip, the physical page address where the target data is located is first quickly located according to the target logical address, then a modulo operation is performed on the target logical address and the logical page size to obtain an offset, and then the read address of the target data is obtained by adding the offset to the physical page address.

[0032] According to an embodiment of the present invention, when the address of the target data to be read exceeds the range of a logical page, the data is read in segments with the logical page as a unit.

[0033] Due to the adoption of the above technical solution, the present invention has the following advantages and positive effects compared with the prior art:

[0034] The method for preserving and updating sensitive data of a connected vehicle device in an embodiment of the present invention establishes a mapping relationship between the physical page address and the logical page address of the target storage area, and adopts an online address fast search mode when reading and writing data, avoiding the memory overhead and software delay caused by initializing the physical page scan to establish the mapping table, and realizing the requirement of fast device startup; when writing data, a rolling write and an incrementing sequence number are adopted to support access to any logical address space smaller than the physical address space, and for high-frequency data updates, the physical space can be effectively utilized to increase the write life; an atomicity identifier is added to the physical page information to support the consistency of multiple discontinuous address space writes generated by a transaction write; by detecting the physical page frame header, frame tail, incrementing sequence number and atomic mark, the introduction of backup pages for multiple data exchanges is avoided, and the data is quickly checked for integrity during the power-on process to realize data abnormal power-off protection. The above method can be applied to chips with memory resources less than 2KB. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A hardware block diagram of an embedded chip storage management system in one embodiment of the present invention;

[0036] Figure 2 A data structure diagram of an embedded chip storage management buffer in an embodiment of the present invention;

[0037] Figure 3A data structure diagram of a Flash physical storage area for embedded chip storage management in one embodiment of the present invention;

[0038] Figure 4 A flowchart of fast search for embedded chip storage management in one embodiment of the present invention;

[0039] Figure 5 This is a flowchart of power-on initialization of embedded chip storage management in one embodiment of the present invention;

[0040] Figure 6 This is a flow chart of embedded chip storage management data reading in one embodiment of the present invention;

[0041] Figure 7 The present invention is a flowchart of embedded chip storage management data writing in one embodiment of the present invention. DETAILED DESCRIPTION

[0042] The following is a further detailed description of a method for storing and updating sensitive data of a connected vehicle device proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and claims.

[0043] The purpose of the present invention is to solve the technical difficulties encountered in the fast and efficient use of the flash memory inside the current embedded chip under the high reliability requirements in the field of the Internet of Vehicles, and to provide a safe and reliable data storage, update and backup solution. For embedded flash memory, it has a higher cost-effectiveness than EEPROM, but its inability to directly read and write by byte brings inconvenience to users. At the same time, in the process of data update, the physical page needs to be erased before the new data can be written again, which easily leads to the risk of data loss in the case of abnormal power failure. Traditional flash-based storage management or file systems often require a large amount of memory to establish complex address mapping tables and lookup tables, and consume a lot of software overhead to implement physical block scanning, fragmentation management and backup mechanisms. For embedded chips such as security chips or ESAM modules in Internet of Vehicles devices, resources are often insufficient and the efficiency is relatively low. For some battery-powered Internet of Vehicles devices, such as ETC devices, it is necessary to consider the requirements of low power consumption and fast response. The chip will enter the sleep mode in the standby state at ordinary times, and needs to respond quickly during the wake-up process. The traditional storage management method has a large overhead in the initialization process, which affects the startup time of the device. In addition, the data characteristics of ETC equipment are high update frequency, small data volume, and high data reliability requirements.

[0044] In order to solve the above technical difficulties, the present invention provides a method for storing and updating sensitive data of Internet of Vehicles equipment, comprising:

[0045] Use embedded chip storage management system to save and update sensitive data of connected car devices, and establish mapping relationship between physical page address and logical page address of target storage area;

[0046] Recording the physical pages of the target storage area in a field format including a frame header, a logical page number, an increasing sequence number, an atomicity flag, data content, and a frame trailer, wherein the frame header and the frame trailer are used to confirm the integrity of the frame data, the logical page number corresponds to the target logical address, the increasing sequence number is used to record the number of data updates, and the atomicity flag is used to record the number of associated physical pages and the sequence number of each physical page included in each data update;

[0047] Obtain the target data to be updated, calculate the number of logical pages required to write the target data to be updated, quickly locate the physical page address where the target data is located according to the target logical address, load the target data to be updated into the internal cache, and update the field information of the physical page at the same time; write the target data to be updated in the internal cache into the logistics page address.

[0048] Specifically, Figure 1 The embedded chip storage management system in this embodiment is composed of a processor 1, a data register 2, an SRAM buffer 3, a DMA controller 4, a Flash controller 5, and a Flash memory 6. The processor 1 is the core unit of the embedded system, which initiates various instruction operations; the data register 2 stores data parameters, including the target logical address of the data, the buffer location, the length and other information; the SRAM buffer 3 stores the target data; the DMA controller 4 is responsible for data transfer between the buffer data and the Flash memory according to the data structure in the data register; the Flash controller 5 is responsible for initiating the read, write, and erase operations of the Flash, signal and timing control, and protection functions; the Flash memory 6 is the physical medium for actually storing non-volatile data. The processor initiates the data save and update instructions, and the modules operate in conjunction, so that in the embedded chip system, the sensitive data can be updated quickly, efficiently, and reliably with as little resource overhead as possible.

[0049] like Figure 2, the data structure between data register 2 and SRAM buffer 3 represents the address and content of the target data to be updated. The parameters of the Info area are stored in data register 2, representing the logical address (LA) of the target data, the data pointer (Ptr) of the SRAM buffer, and the data length (Len). Each group of elements (LA, Ptr, Len) corresponds to Data1, Data2, Data3, ... in the Body area. The Data in the Body area represents the entity of the data to be updated, which is located in the SRAM buffer 3. It supports multiple data blocks to exist in the Info area and the Body area at the same time. This can easily realize the simultaneous update and cancellation of multiple related data blocks, so as to achieve the purpose of data atomicity protection.

[0050] like Figure 3 , the DMA controller 4 sends the target data to be updated to the Flash controller 5 in order according to the data Info information in the data register 2 and the data Body information in the SRAM buffer 3, and then the Flash controller 5 updates the data to the Flash memory 6 according to the read, write, and erase timing of the Flash. Since the writing of the Flash can be performed in the form of words, half words, bytes, etc., and erasing is usually performed in the form of physical pages (Phy Page) as the minimum unit, the Flash controller 5 will pre-fetch the data of the target page into the internal cache buffer before writing to the Flash memory 6, and then erase and write the target page uniformly after updating the target data into the cache buffer. The whole process is completed by the Flash controller 5 without the intervention of the processor 1, which reduces the software overhead and improves the efficiency of data updating. This embodiment does not limit whether the Flash controller 5 has the pre-fetch buffer function. If it does not have this function, the data of the target physical page will be pre-fetched into the SRAM buffer 3 first, and then the DMA controller 4 will be responsible for sending the data to the Flash controller 5.

[0051] For the update of multiple data blocks, DMA controller 4 will consider whether the data blocks span pages, whether the data blocks are adjacent, spaced, or overlapped. DMA controller 4 processes the data blocks in a front-to-back order according to the logical address (LA). When the data blocks span pages, DMA controller 4 will split the data blocks according to page boundary alignment, that is, the data of the data block falling on the previous page will be processed first, and then the data of the data block falling on the next page will be processed. For the situation where the data blocks are adjacent, spaced, or overlapped, the data in the target physical page can be pre-fetched into the internal cache buffer, and then the new data in the SRAM buffer 3 can be directly overwritten with the old data in the cache buffer, wherein the overlapping data blocks will be processed in a front-to-back order according to the logical address (LA), that is, the data blocks with the later logical addresses overwrite the data blocks with the earlier logical addresses.

[0052] Figure 3 The format of the physical page (Phy Page) is composed of a frame header (H), a logical page number (LP), an increasing sequence number (Seq), an atomicity identifier (a / n), data content (Data), and a frame tail (T). The size of each field is determined by the physical characteristics of the Flash. For example, if the Flash physical page (Phy Page) is 512 bytes and the minimum write unit is 4 bytes, then the frame header (H) and frame tail (T) each occupy 4 bytes, and the logical page number (LP), sequence number (Seq) and atomicity identifier (a / n) are also set to 4 bytes as needed. The effective length of the data content (Data) is 512-4*5=492, and this effective length value is also recorded as the logical page size. The effective utilization rate of the memory is 492 / 512=96%, which is very high.

[0053] The frame header (H) and frame trailer (T) are used to confirm the integrity of the frame data. Only the physical page (Phy Page) with both the frame header (H) and frame trailer (T) is valid. The logical page number (LP) corresponds to the logical address (LA) of the target data in data register 2. The logical address (LA) divided by the logical page size is the logical page number (LP). The physical page address where the target data is located can be quickly located through fast search. The fast search method will be described in detail later. The role of the incrementing sequence number (Seq) can distinguish between new and old data. After each data update, the value of the incrementing sequence number (Seq) is increased by 1. The atomicity identifier (a / n) is used to mark the number of associated physical pages (n) contained in each data update operation, as well as the sequence number (a) of each physical page, a=1...n.

[0054] Figure 4 The figure shows the process of online address fast search, which quickly locates the physical page address where the target data is located according to the target logical address (LA). Since the size of each physical page is the same, the size of each logical page is also the same, making the search process very simple. It only needs to perform a cyclic matching in the order from front to back, and each time only matches the logical page number corresponding to the current logical page number (LP) and the target logical address (LA). If it matches, the physical address of the current logical page is returned, otherwise the next page is searched. When the match is successful, the Flash controller 5 can directly load the data into the internal cache buffer to prepare for subsequent operations. The fast search mode can avoid the memory overhead and software delay caused by initializing the physical page scan to establish the mapping table, reduce the initialization time, and achieve the requirement of fast startup of the device.

[0055] The writing method of Flash memory 6 is rolling writing and increasing serial number, supporting access of any logical address space smaller than the physical address space, avoiding repeated writing of the same address and high-frequency use of backup page data, effectively solving the requirements of products with high data update frequency for erase and write life. Figure 3 The current index (CurIdx) in represents the physical address that the Flash memory 6 can currently write to. After each data update, the current index (CurIdx) will search for the next empty page in order from front to back. The search method is similar to the process of quick search, except that the target address becomes an empty address. According to the characteristics of Flash, the default empty address is usually recorded as 0xFFFFFFFF. If the current index (CurIdx) reaches the tail address of the Flash memory 6, it will scroll to the first address to continue. The increasing sequence number (Seq) continues to increase with each data update. The bit width of the increasing sequence number (Seq) is set according to the application scenario so that it will not overflow during its life cycle. For example, the increasing sequence number (Seq) selects a bit width of 32 bits, which means that the maximum number of updates is 4.2 billion times, which is much greater than the erase and write life of Flash. Compared with complex balancing algorithms, the rolling write method is easier to implement and makes better use of physical space. It is suitable for embedded chips with limited resources and can meet the requirements of vehicle-mounted equipment for high data reliability.

[0056] The atomicity identifier (a / n) in the physical page information is used to mark the number of associated physical pages (n) included in each data update operation, as well as the serial number (a) of each physical page, a=1…n, which can support the consistency of multiple discontinuous address space writes generated by a transaction write. This feature is very necessary in some application scenarios involving transactions. A transaction may involve the update of multiple data blocks. Using these data blocks as an atomic data update can ensure that the transaction is either successful or failed, without any intermediate state, eliminating the complexity of software maintenance.

[0057] like Figure 5, shows the power-on initialization process of embedded chip storage management. It will monitor the integrity of the data. If the updated data is complete, the old data will be cleared; if it is incomplete, the new data will be cleared and the old data will be retained. This process plays a key role in data power-off protection. Since the power-on initialization process is mainly to determine whether there is data loss caused by abnormal conditions, it does not need to consume memory to establish complex address mapping tables, lookup tables or data block linked lists in traditional storage management, making the whole process faster and shortening the response time of the entire product. After the chip is powered on, it first enters the fast scanning process. If an empty page is encountered, it will be skipped directly. If a page with incomplete frame header (H) and frame tail (T) is encountered, the page will be erased directly. The rest are valid pages. For valid pages, record the value of their incrementing sequence number (Seq), and set variables MaxSeq and Cnt to record the maximum Seq value and the corresponding number of physical pages respectively. This data is very important because it represents the number of physical pages involved in the most recent data update. By obtaining the atomicity identifier (a / n) in the physical page corresponding to MaxSeq and comparing it with the value of Cnt, if Cnt is less than n, it means that the atomicity of the new data is incomplete and all physical pages with incrementing sequence numbers (Seq) equal to MaxSeq need to be erased; otherwise, it means that the atomicity of the new data is complete and all physical pages with logical page numbers (LP) that repeat with the new data and incrementing sequence numbers (Seq) less than MaxSeq need to be erased. After the entire initialization is completed, the value of MaxSeq will be used as the starting value of the incrementing sequence number (Seq) when the next data is updated.

[0058] like Figure 6 , shows the data reading process of embedded chip storage management. First, according to the fast search process, the physical page address where the target data is located is quickly located according to the target logical address (LA), and then the offset is obtained by performing a modulo operation on the target logical address (LA) and the logical page size. Finally, the read address of the target data is obtained by adding the offset to the physical page address. If the data to be read spans pages, that is, the address of the target data exceeds the range of a logical page, it is read in segments, and the excess part returns to the fast search part for further processing.

[0059] like Figure 7, shows the data writing process of embedded chip storage management. First, according to the address and content of the target data to be updated in the data register 2 and the SRAM buffer 3, the total number of logical pages covered by the data block to be written is calculated, and then the logical pages are processed one by one in order from front to back. The update process of each logical page is the same. First, according to the fast search process, the physical page address where the target data is located is quickly located according to the target logical address (LA), and the data is loaded into the internal cache buffer. At this time, the data in the cache buffer is the old data of the old physical page. The new data in the SRAM buffer 3 is updated to the internal cache buffer through the DMA controller 4, and the physical page frame format information is updated at the same time, including the frame header (H), the frame tail (T), the logical page number (LP), the incrementing sequence number (Seq), and the atomicity identifier (a / n). The atomic identifier a indicates the current logical page number, and the atomic identifier n indicates the total number of logical pages to be processed. At this time, the data in the cache buffer is new data, and then the new data is written to the new physical page in the Flash memory 6 through the Flash controller 5. Finally, the old physical page is erased through the Flash controller 5. After each logical page is processed, the atomic mark a is increased by 1, and after all atomic data is written, the sequence number (Seq) is increased by 1.

[0060] In summary, the present invention can be applied to chips with memory resources less than 2KB, as traditional storage management or file systems occupy large resources and are not suitable for embedded chips with small memory resources. As the erase and write life of flash memory is usually lower than that of EEPROM, the present invention can support access to any logical address space that is smaller than the physical address space, and adopts rolling write and increasing serial number methods to effectively solve the erase and write life requirements of products with high data update frequency. In addition, the storage management loading efficiency of the present invention is high, and it supports atomic data protection under abnormal power failure, without the need for data maintenance at the user level, meeting the high reliability requirements of Internet of Vehicles equipment.

[0061] The embodiments of the present invention are described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, if these changes fall within the scope of the claims of the present invention and their equivalents, they still fall within the protection scope of the present invention.

Claims

1. A method for storing and updating sensitive data of a vehicle networking device, characterized in that: include: Use embedded chip storage management system to save and update sensitive data of connected car devices, and establish mapping relationship between physical page address and logical page address of target storage area; Recording the physical pages of the target storage area in a field format including a frame header, a logical page number, an increasing sequence number, an atomicity flag, data content, and a frame trailer, wherein the frame header and the frame trailer are used to confirm the integrity of the frame data, the logical page number corresponds to the target logical address, the increasing sequence number is used to record the number of data updates, and the atomicity flag is used to record the number of associated physical pages and the sequence number of each physical page included in each data update; Obtain the target data to be updated, calculate the number of logical pages required to write the target data to be updated, quickly locate the physical page address where the target data is located according to the target logical address, load the target data to be updated into the internal cache, and update the field information of the physical page at the same time; write the target data to be updated in the internal cache into the physical page address.

2. The method for storing and updating sensitive data of a vehicle networking device according to claim 1, characterized in that: The method of using the embedded chip storage management system to save and update the sensitive data of the Internet of Vehicles device further includes: The embedded chip storage management system includes a processor, a data register, an SRAM buffer, a DMA controller, a Flash controller and a Flash memory; The processor is used to initiate data saving and / or updating instructions; The data register is used to store the target logical address, buffer location and data length information of the data; The SRAM buffer is used to temporarily store target data; The DMA controller is used to transfer data between the SRAM buffer and the Flash memory according to the data structure in the data register; The Flash controller is used to initiate the read, write or erase operation of the Flash memory, control the signal and timing, and protect; The Flash memory is used to store target data.

3. The method for storing and updating sensitive data of a vehicle networking device as claimed in claim 2, characterized in that: A group of elements in the data register corresponds to a piece of data in the SRAM buffer, wherein the group of elements in the data register includes a target logical address, a buffer location and a data length.

4. The method for storing and updating sensitive data of a vehicle networking device as claimed in claim 2, characterized in that: The DMA controller sends the target data to be updated to the Flash controller in sequence according to the data information in the data register and the data information in the SRAM buffer, and then the Flash controller updates the target data to be updated to the Flash memory according to the timing of reading, writing or erasing.

5. The method for storing and updating sensitive data of a vehicle networking device as claimed in claim 4, characterized in that: When the target data to be updated includes multiple data blocks, the DMA controller processes the data blocks in a forward-to-backward order according to the target logical address; When the data block crosses pages, the DMA controller splits the data block in a page boundary aligned manner, processes the data of the data block on the previous page first, and then processes the data of the data block on the next page; When data blocks are adjacent, spaced or overlapping, the DMA controller pre-fetches the data in the target physical page address to the internal cache, and then directly overwrites the data in the internal cache with the target data to be updated in the SRAM buffer; wherein the overlapping data blocks are processed in order from front to back according to the target logical address.

6. The method for storing and updating sensitive data of a vehicle networking device as claimed in claim 2, characterized in that: The Flash memory writes data into the physical address in a rolling write combined with an increasing sequence number; The rolling write uses an index method to quickly locate an empty address in a physical page according to the target logical address. The location of the index is the physical address that can be written at present. After each data update, the index will search for the next empty address in order. When the index reaches the end address of the Flash memory, scroll to the beginning address; After each data update, the value of the incremental sequence number is increased by 1.

7. The method for storing and updating sensitive data of a vehicle networking device as claimed in claim 1, characterized in that: The method of quickly locating the physical page address where the target data is located according to the target logical address further includes: According to the target logical address, the current logical page number is matched with the logical page number corresponding to the target logical address in order from front to back. If the match is successful, the physical page address corresponding to the current logical page number is returned.

8. The method for storing and updating sensitive data of a vehicle networking device as claimed in claim 1, characterized in that: When the embedded chip is powered on, it enters the initialization process; the initialization process is as follows: Scan the physical pages quickly, skip empty pages directly, and erase pages with incomplete headers and footers directly; For valid physical pages, record the value of the incremental sequence number of the physical page, set the variable MaxSeq to record the value of the maximum incremental sequence number, and set the variable Cnt to record the number of physical pages; compare whether the variable Cnt is less than the atomicity identifier in the physical page corresponding to the variable MaxSeq, if so, erase all physical pages whose incremental sequence numbers are equal to the variable MaxSeq; if not, erase all physical pages whose logical page numbers overlap with the new data and whose incremental sequence numbers are less than the variable MaxSeq.

9. The method for storing and updating sensitive data of a vehicle networking device as claimed in claim 1, characterized in that: When reading data stored in an embedded chip, first quickly locate the physical page address of the target data according to the target logical address, then perform a modulo operation on the target logical address and the logical page size to obtain an offset, and then add the offset to the physical page address to obtain the read address of the target data.

10. The method for storing and updating sensitive data of a vehicle networking device as claimed in claim 9, characterized in that: When the address of the target data to be read exceeds the range of a logical page, the data is read in segments in units of logical pages.

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