Interface of semiconductor device and interface method for arranging and combining semiconductor devices

Abstract

The present invention provides an interface of a semiconductor device and an interface method for arranging and combining semiconductor devices. The interface of the semiconductor device includes a master device and a plurality of slave devices. The interface includes a master interface and a slave interface. The master interface is implemented in the master device and includes a master combination pattern formed by master combination members arranged in a first array. The slave interface is implemented in each slave device and includes a slave combination pattern formed by slave combination members arranged in a second array. The first array of master combination members includes a first center row and a first group of data rows divided into two parts, and the two parts are completely symmetrical with respect to the first center row. The second array of slave combination members includes a second center row and a second group of data rows divided into two parts, and the two parts are completely symmetrical with respect to the second center row. The first center row is aligned with the second center row in a chip bonding connection, and the first group of data rows is connected to the second group of data rows.

Description

Technical Field

[0001] The present invention relates to the manufacture of semiconductor devices, and more particularly to an interface of a semiconductor device and an interface method for arranging and combining semiconductor devices. Background Art

[0002] Digital electronic devices based on semiconductor integrated circuits, such as mobile phones, digital cameras, personal digital assistants (PDAs), etc., are designed to have more powerful functions to adapt to various applications in the modern digital world. However, as a trend in semiconductor manufacturing, digital electronic devices are intended to be smaller and lighter, with improved functions and higher performance. Semiconductor devices can be packaged into three-dimensional (3D) semiconductor devices, in which several circuit chips can be stacked and integrated into a larger integrated circuit, in which bonding pieces and through-silicon vias (TSVs) are used for connection between chips.

[0003] System-on-integrated-chip (SoIC) packaging, wafer-on-wafer (WoW) packaging, and die-to-chip-to-substrate (CoWoS) packaging technologies have been proposed to package a plurality of chips stacked in height.

[0004] However, the communication between the master chip and multiple slave chips as a 3D stack is still under development to have better performance and compact structure. In addition, the bonding pattern between the two chips needs to be arranged to be easy to connect to adapt to the 3D stacking of multiple chips. Summary of the invention

[0005] The present invention provides an interface of a 3D semiconductor device, wherein a plurality of slave chips are stacked on a single master chip to form a 3D package structure. The interface allows communication between a single master chip and the slave chips in an efficient manner. A binding pattern is included in the interface between the master chip and each slave chip respectively. The interface between the stacked master chip and all the slave chips can transmit or receive signals through the binding pattern.

[0006] In an embodiment, the present invention provides an interface of a semiconductor device, the semiconductor device comprising a master device and a plurality of slave devices. The interface comprises a master interface and a slave interface of each slave device. The master interface is implemented in the master device and comprises a master binding member pattern formed by master binding members arranged in a first array. The slave interface is implemented in each of the slave devices and comprises a slave binding member pattern formed by slave binding members arranged in a second array. The first array of the master binding members comprises a first center row and a first group of data rows divided into two parts, the two parts being completely symmetrical with respect to the first center row. The second array of the slave binding members comprises a second center row and a second group of data rows divided into two parts, the two parts being completely symmetrical with respect to the second center row. The first center row is aligned with the second center row in a chip connection, and the first group of data rows is connected to the second group of data rows.

[0007] In an embodiment, the present invention also provides a method for arranging an interface of a semiconductor device, the semiconductor device comprising a master device and a plurality of slave devices, the method comprising: providing a master interface, the master interface being implemented in the master device and comprising a master binder pattern formed by master binders arranged in a first array; and providing a slave interface, the slave interface being implemented in each of the slave devices and comprising a slave binder pattern formed by slave binders arranged in a second array. The first array in which the master binders are arranged comprises a first center row and a first group of data rows divided into two parts, the two parts being completely symmetrical with respect to the first center row. The second array in which the slave binders are arranged comprises a second center row and a second group of data rows divided into two parts, the two parts being completely symmetrical with respect to the second center row. The first center row is aligned with the second center row in a chip connection, and the first group of data rows is connected to the second group of data rows.

[0008] In order to make the above contents more easily understood, several embodiments with accompanying drawings will be described in detail below. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure.

[0010] Figure 1 is a diagram schematically showing a cross-sectional stacking structure of a 3D semiconductor device according to an embodiment of the present invention;

[0011] Figure 2 is a diagram schematically showing a cross-sectional stacking structure of a 3D semiconductor device with an interface according to an embodiment of the present invention;

[0012] Figure 3is a diagram schematically showing a perspective stacking structure of a 3D semiconductor device having a communication mechanism of an interface according to an embodiment of the present invention;

[0013] Figure 4 is a diagram schematically illustrating a communication mechanism of an interface between a master chip and a slave chip according to an embodiment of the present invention;

[0014] Figure 5 is a diagram schematically illustrating a 3D communication mechanism of an interface between a master chip and a slave chip according to an embodiment of the present invention;

[0015] Figure 6 is a diagram schematically showing a circuit structure of an interface between a master chip and a slave chip according to an embodiment of the present invention;

[0016] Figure 7 is a diagram schematically showing a system circuit structure of an interface between a master chip and a slave chip according to an embodiment of the present invention;

[0017] Figure 8 is a diagram schematically illustrating a communication mechanism of an interface having a binding pattern according to an embodiment of the present invention;

[0018] Fig. 9 is a diagram schematically showing a 3D packaging structure of a master chip and a slave chip connected face-to-face, face-to-back, and back-to-back according to an embodiment of the present invention;

[0019] Fig.10 is a diagram schematically showing an arrangement of bonding members in a group of bonding members serving as a bonding tile corresponding to a main interface according to an embodiment of the present invention;

[0020] Fig.11 is a diagram schematically showing an arrangement of bonding members in a group of bonding members as a bonding sheet corresponding to a slave interface according to an embodiment of the present invention;

[0021] Fig.12 is a diagram schematically showing the arrangement of voltage bonding members in a bonding sheet according to an embodiment of the present invention;

[0022] Fig.13 is a diagram schematically showing an output mechanism of a bonded sheet with flip control according to an embodiment of the present invention;

[0023] Fig.14 is a diagram schematically illustrating an input mechanism of a combined sheet with flip control according to an embodiment of the present invention;

[0024] Fig.15is a diagram schematically showing a bonding structure involved in data communication between a master interface and a slave interface in a direct manner from the bonding structure according to an embodiment of the present invention;

[0025] Fig.16 According to an embodiment of the present invention, schematically illustrating a Fig.15 A diagram of a combination structure involved in data communication between a master interface and a slave interface in a flipping manner of a slave combination structure;

[0026] Fig.17 is a diagram schematically showing a circuit structure of an interface incorporating a double data rate (DDR) mechanism and a flip mechanism according to an embodiment of the present invention;

[0027] Fig.18 is a diagram schematically showing an application of flipping the entire chip relative to the X-axis according to an embodiment of the present invention;

[0028] Fig.19 FIG. 1 is a diagram schematically showing an application of flipping the entire chip relative to the Y-axis according to an embodiment of the present invention.

[0029] [Explanation of Symbols]

[0030] 10: 3D semiconductor devices

[0031] 20, 30: substrate

[0032] 22, 32: Circuit layer

[0033] 24, 34: Circuit chip / chip

[0034] 26, 36: TSV structure

[0035] 38M_CMD[1:0]、M_DID[3:0]、RDQS_R / F、S_CMD[1:0]、S_DID[3:0]:Combination

[0036] 40: Interface area

[0037] 100: Main chip

[0038] 102: From chip

[0039] 104, 104M, 104S: combined structure

[0040] 110: CPU block

[0041] 112: Cache block

[0042] 120: SRAM block / SRAM

[0043] 130: Logic Circuits

[0044] 132: Fifth trigger block

[0045] 150, 150S, 150M, 170: Combined sheet

[0046] 152: Binding parts / data binding parts

[0047] 154M, 154S, 156M, 156S: Voltage combination

[0048] 158M, 158S: Functional combination

[0049] 160: Arrow

[0050] 180, 192: Axis of symmetry

[0051] 200. Glink-3D: Interface

[0052] 200M: Main interface

[0053] 200S: Slave interface

[0054] 202, 210: Flip-flop (FF) block

[0055] 204: Trigger unit

[0056] 204A: First-In-First-Out (FIFO) Block

[0057] 206: Multiplexer

[0058] 208: Main joint pattern / joint pattern

[0059] 220: From the pattern of the binding parts / the pattern of the binding parts

[0060] 222: Third trigger block / trigger block

[0061] 222a, 222b: Trigger block

[0062] 224: Trigger block / Fourth trigger block

[0063] 224a: Enable trigger block

[0064] 226: From the multiplexer

[0065] 228a, 228b: Output control block

[0066] 230: Circuit block

[0067] 230a, 230b, DLLf, DLLr: Delay locked loop block

[0068] 230c, CACd: Delay control unit

[0069] 240: Inverter

[0070] 300: Command / Flip Multiplexer / Mux

[0071] 302, 306: Control signal

[0072] 304: Flip Multiplexer / Mux

[0073] C_LR, T_LR: Redundant connectors

[0074] clk: clock / clock signal / original clock

[0075] CLK, clk_in: clock

[0076] command: command

[0077] CS / RD / WR: Command / Read_Data / Write_Data

[0078] Flip: Control signal

[0079] M_PAR: Master command parity

[0080] MUX: Flip Multiplexer

[0081] N: North

[0082] R_D0~R_D15, T_D0~T_D15: data combination

[0083] rd_data: data

[0084] rx_data: command / data

[0085] S: South side

[0086] S_PAR: Slave command parity

[0087] T_PAR: Data parity

[0088] tx_data: data / data cluster / input data / command data

[0089] tx_data[31:0]: command data

[0090] tx_en: enable signal

[0091] VDD: System high voltage / voltage combination

[0092] VSS: Ground voltage / voltage combination

[0093] X, Y: Axis DETAILED DESCRIPTION

[0094] The present invention relates to an interface of a 3D semiconductor device, wherein the interface is also made based on 3D packaging technology. The interface can link a single master chip (such as a processor) with multiple slave chips (such as static random access memory (SRAM)).

[0095] In the present invention, the interface allows communication between the master chip and the plurality of slave chips. The communication signal may include a command from the master chip and a response message from one of the selected slave chips. The interface provides reliable communication. In addition, the signal latency between the master chip and each of the slave chips may be stabilized to be approximately constant and predictable. Due to the control of the latency, the trigger edge of the valid clock may be appropriately set corresponding to the data packet (also referred to as the data eye).

[0096] A number of embodiments are provided below to illustrate the present invention, but the present invention is not limited to the embodiments.

[0097] Figure 1 FIG. 1 is a diagram schematically showing the structure of a 3D semiconductor device in a cross-sectional view according to an embodiment of the present invention. Figure 1 The 3D semiconductor device 10 includes a plurality of chips 24, 34, which are vertically stacked in addition to the horizontal distribution of the chips. Thus, a 3D semiconductor device including the chips is formed.

[0098] In the example, the circuit chip 24 can be regarded as a master chip, which generally includes a substrate 20 and a circuit layer 22. Several other circuit chips 34 (for example, used as slave chips) will be stacked on the circuit chip 24, wherein based on the packaging process, a through-hole structure (for example, a TSV structure 26 with a bonding member) can be formed between the circuit chip 24 and the circuit chip 34. The circuit chip 34 includes a substrate 30 and a circuit layer 32 and may also include a TSV structure 36 at a corresponding position to be electrically connected to the circuit chip 24. In addition, a bonding member 38 may also be formed at the outermost surface corresponding to the TSV structure 36.

[0099] 3D packaging technology has been proposed in various stacking structures such as System-on-Integrated-Chip (SoIC) packaging, Wafer-on-Wafer (WoW) packaging, and Die-on-Chip-on-Substrate (CoWoS). The present invention is based on 3D packaging, but is not limited to the type of 3D packaging.

[0100] Figure 2 FIG. 1 is a diagram schematically showing a cross-sectional stacking structure of a 3D semiconductor device having an interface according to an embodiment of the present invention. Figure 2Based on the 3D packaging structure, in an embodiment, the 3D semiconductor device 10 may further include an interface area 40, wherein an interface in each circuit chip 24, 34 is formed at the interface area 40. The interface may link the circuit chip 24 used as a master chip to all of the circuit chips 34 used as slave chips. Communication between the circuit chip 24 and the circuit chip 34 may pass through the interface at the interface area 40.

[0101] The circuits of the interface implemented in the interface region 40 will be described in detail later. It should also be noted that in the embodiment, a plurality of interface regions 40 may be formed in the circuit chip according to actual needs, and is not limited to a single interface region.

[0102] Figure 3 is a diagram schematically illustrating a perspective stacking structure of a 3D semiconductor device having a communication mechanism of an interface according to an embodiment of the present invention.

[0103] Reference Figure 3 From the perspective of the 3D stacking structure in the operation of the slave interface, a master chip 100 (e.g., a processor chip) is included in the semiconductor device as a basic chip. A plurality of slave chips 102 (e.g., SRAM chips) are stacked on the master chip 100. The master chip 100 includes a master interface and each slave chip includes a slave interface. The master interface and the slave interface form an interface 200, which may also be referred to as Glink-3D. The master chip 100 is linked to the slave chip 102 through the interface 200 to communicate using information / data / signals.

[0104] In the operation as an example, the main chip 100 of the processor has a command for accessing data stored in the slave chip 102 of the SRAM chip. Due to the implemented interface, the read latency can be controlled to be approximately constant and small, such as 2ns or 5ns in the example. A single clock is used in the interface to distribute to all slave chips, and the path length from the main chip 100 to each slave chip 102 is approximately the same and reliable. The latency can be adjusted to a predictable constant value.

[0105] Figure 4 1 is a diagram schematically showing a communication mechanism of an interface between a master chip and a slave chip according to an embodiment of the present invention. Figure 4 , describing the communication mechanism between the master chip 100 having the master interface 200M and the slave chip 102 having the slave interface 200S connected by the bonding structure 104 in the 3D package. Figure 3As described in the above, the master interface 200M and the slave interface 200S form the interface 200. Inside the master chip 100, a central processing unit (CPU) block 110 having a cache block 112 in the example forms a processor. The processor is connected to the master interface 200M to transmit or receive signals at the master interface 200M, with the intention of communicating with the slave chip 102.

[0106] Inside the slave chip 102, it also includes an SRAM block 120 and a slave interface 200S. The SRAM block 120 is connected to the slave interface 200S for communicating with the master chip 100. In communication, the master interface 200M is connected to the slave interface 200S through a bonding structure 104. Depending on the packaging process, the bonding structure 104 may include a TSV with a mixed bonding pattern. The connection is bidirectional. The bonding pattern may generally correspond to a data bus. All signals are transmitted or received in parallel. In an example, the clock rate may be 2.5GHz. The signal waiting time of the interface between the master chip 100 and the slave chip 102 through the master interface 200M and the slave interface 200S is reliable, and may be about 2ns as an example.

[0107] Figure 5 FIG. 1 is a diagram schematically showing a 3D communication mechanism of an interface between a master chip and a slave chip according to an embodiment of the present invention. Figure 5 , based on the operating mechanism as described above, the master chip 100 and the slave chip 102 in the 3D structure are shown in more detail as examples. The master chip 100 (e.g., a processor) includes a master interface 200M, and the master interface 200M includes a binding structure 104M. The binding structure 104M in the example includes a binding pattern, and the binding pattern is composed of a plurality of bindings in the example. Therefore, depending on the data size of the bus, the binding is formed into an array, in which one binding piece 150 corresponds to a set of binary data (e.g., 16-bit data with a voltage binding piece, a clock binding piece, and other specified binding pieces). A plurality of binding pieces 150 form the entire binding pattern of the master interface 200M. As described above, the data from the processor communicates bidirectionally with the master interface 200M.

[0108] Similarly, the slave chip 102 may include an SRAM and a slave interface 200S. The SRAM communicates with the slave interface 200S, and the slave interface 200S communicates with the main interface 200M through the connection of the binding structure 104S, and the binding structure 104S is also composed of a plurality of binding members arranged in an array into a binding member pattern, and each of the plurality of binding members is represented by a square unit. Similarly, the binding member pattern is also divided into a plurality of binding sheets 150. In 3D packaging technology, the main interface 200M is connected to the slave interface 200S by the binding structure 104M and the binding structure 104S with a matching binding member pattern. Therefore, based on 3D packaging technology, the main interface 200M is connected to the slave interface 200S as a complete interface, so as to have communication between the master chip 100 and the slave chip 102. As described above, a plurality of slave chips 102 are stacked on the top of the master chip 100, wherein the main interface 200M is connected to the slave interface 200S in a vertical direction.

[0109] The circuits of the master interface 200M and the slave interface 200S are described as follows. Figure 6 is a diagram schematically showing a circuit structure of an interface between a master chip and a slave chip according to an embodiment of the present invention.

[0110] Reference Figure 6 , using the implemented circuit to illustrate the master interface 200M of the master chip 100 and the slave interface 200S of the slave chip 102. For the master interface 200M, it includes a flip-flop (FF) block 202 to receive the command intended by the core circuit of the master chip 100. The command as input in the example may include a data cluster tx_data and / or command, without specific restrictions. The number of flip-flop blocks 202 may be one unit (FF) or more units (FFs) according to actual needs, and there is no restriction here. The command from the master chip 100 in the example may include a command and a data cluster to be transmitted. The command may also include a selection slave identifier, which is used to select the slave chip 102 to implement the command from the master chip 100.

[0111] The multiplexer 206 receives the output of the flip-flop block 202. The multiplexer 206 in the example is of a double data rate (DDR) type according to the input data at the flip-flop block 202. The output of the multiplexer 206 is transmitted to the corresponding binder of the binder pattern 208 in the master interface 200M.

[0112] As described above, a single clock clk is provided to the slave chip 102 through the master interface 200M and the slave interface 200S. The flip-flop block 202 and the multiplexer 206 are controlled in timing by the clock clk_in. In the master interface 200M, the flip-flop block 202 and the master multiplexer 206 form a transmission path to transmit commands to the slave chip 102.

[0113] The master interface 200M also includes a receiving path to receive a response from the slave chip 102 through the slave interface 200S and the master interface 200M having a corresponding binding member portion of the binding member pattern 208. A first-in-first-out (FIFO) block 204A receives a response from the slave interface 200S. The FIFO block 204A in the example includes a plurality of trigger units 204. The output of the FIFO block 204A is provided to another trigger block 210, and then the output is transmitted inward to the core of the master chip 100. The trigger block 210 is controlled by a clock clk_in in timing. The FIFO block 204A is controlled by a feedback clock from the slave chip 102, and the slave chip 102 has an enable control corresponding to the response data from the slave chip 102.

[0114] In the example of a read operation, the command of the master chip 100 is received by the trigger block 202 of the master interface 200M. The selected slave chip 102 responds with the requested data to the FIFO block 204A of the master interface 200M.

[0115] In the slave interface 200S of the chip 102, the binding pattern 220 corresponds to the binding pattern 208. The command of the master chip 100 is then received by the trigger block 222, which also controls the clock clk. The trigger block 222 in the slave interface 200S then further transmits commands, such as rx_data and / or command, to the SRAM of the slave chip 102. In the example, the master chip 100 sends a command to read data from the SRAM of the slave chip 102.

[0116] Then, the slave chip 102 provides the data group requested from the master chip 100 to the circuit block 230, which is also indicated by the tx_data arriving at the slave chip 102 in the example. The circuit block 230 is also controlled by the clock clk and the enable signal tx_en. The circuit block 230 includes a trigger block 224, an enable trigger block 224a, a slave multiplexer 226, and output control blocks 228a, 228b.

[0117] The clock signal clk for control in each slave interface 200S is also provided to the third flip-flop block 222, the fourth flip-flop block 224, the slave multiplexer 226, the enable flip-flop block 224a, and the output control block 228a.

[0118] The trigger block 224 outputs the data to the slave multiplexer 226 and then to the output control block 228b. The enable trigger block 224a receives the enable signal tx_en and the clock signal clk and provides a control signal to control the output control block 228a. Then, the data provided by the slave chip 102 is transmitted to the master chip 100 through the bonding part of the bonding pattern 220.

[0119] In order to perform proper timing control on the clock signal clk to respond to the master chip 100, another output control block 228b also receives the original clock clk and is controlled by the enable signal from the enable flip-flop block 224a.

[0120] The data output from the slave interface 200S is then received by the FIFO block 204A in the master interface 200M. For the master interface 200M, the data rx_data is a response from the slave chip 102 to a command (eg, command).

[0121] In an embodiment, there are multiple slave chips 102 stacked on the master chip 100. Commands from the master chip 100 are sent to all of the slave chips 102. In this case, the command of the master chip 100 also includes selecting a slave identification, and the command is used to select the slave chip 102 to implement the command from the master chip 100. The slave interface 200S also includes the ability to identify the selected slave identification code. Each slave interface 200S has its own identification code. One of the slave interfaces 200S that matches the selected slave identification code will be activated to respond to the command from the master chip 100 at the time slot allocated by the master command. Interference between the slave chips can be effectively avoided.

[0122] Figure 7 2 is a diagram schematically showing a circuit structure of an interface between a master chip and a slave chip according to an embodiment of the present invention. Figure 7 , further illustrating the connection between the slave interface 200S and the SRAM 120 in the example.

[0123] In an example, the command 300 may include a command, an address, write data, and a select slave identifier. The data rx_data from the trigger block 222 of the slave interface 200S is output to the SRAM 120. However, the slave interface 200S may also include a logic circuit 130 and a fifth trigger block 132. The logic circuit 130 also receives a command output from the third trigger block 222, such as data rx_data, to determine the type signal of command / read_data / write_data (CS / RD / WR) and also generates an initial enable signal to the fifth trigger block 132, and the fifth trigger block 132 outputs an enable signal to the enable trigger block 224a accordingly. The SRAM 120 receives the type signal of CS / RD / WR to respond to the command from the master chip 100. Once the slave chip 102 (such as SRAM 120) completes the command, the result of the read command (such as data rd_data) is responded to the slave interface 200S as the input data tx_data of the slave interface 200S.

[0124] As further shown, in the structure of the present invention including an interface connected to a plurality of slave chips 102 (e.g., 16 slave chips), write commands and read commands can overlap and then be executed simultaneously. In addition to some reserved bits, the size of the data bus can have 256 bits. The master binding member pattern 208 and the slave binding member pattern 220 have many binding members required for transmitting data signals in the master interface 200M and the slave interface 200S, and the many binding members are grouped into a plurality of binding pieces 150S, 150M, as will be described later. Figure 8 In addition, it can also include Figure 8 The bonding pad 170 shown in FIG. 1 is used to transmit other control signals for actual operation.

[0125] Since 3D packaging technology allows multiple chips to be stacked, the bonding piece is located at the front surface of the chip. However, the TSV structure is included to extend the bonding piece at the front surface to the back surface of the chip. In order to form a stacked chip, two chips can be electrically connected at the bonding piece pattern in a face-to-face manner, a face-to-back manner, or a back-to-back manner.

[0126] Figure 8 FIG. 1 is a diagram schematically illustrating a communication mechanism of an interface having a binding pattern according to an embodiment of the present invention. Figure 8 And also refer to Figure 5 , the main interface 200M main bonding element pattern 208 includes a plurality of bonding elements 152. The bonding elements 152 may be as follows: Figure 5As seen in the figure, the plurality of bonding pads 150 are grouped, wherein the bonding pad 150 belonging to the master interface 200M may also be referred to as the bonding pad 150M and the bonding pad 150 belonging to the slave interface 200S may also be referred to as the bonding pad 150S. Taking the bonding pad 150M as an example, one bonding pad 150M includes a group of bonding members, and in the example, the group of bonding members is used to transmit a group of data signals, voltage signals, data parity signals and control signals. The data signal in the example includes 16-bit data, but is not limited thereto. The voltage bonding members 154M and 156M may include a system high voltage (e.g., VDD) and a ground voltage (e.g., VSS). A bonding member having a constant function of transmitting a voltage signal, a data parity signal and a control signal may be referred to as a functional bonding member 158M, and the functional bonding member 158M includes the voltage bonding members 154M and 156M and is located at the center row in one bonding pad 150M. In other words, one bonding sheet 150S may include a central row of bonding elements with functional bonding elements 158S, and the functional bonding elements 158S include voltage bonding elements 154S, 156S. The data bonding element 152 for transmitting data signals may be divided into two parts of the data row, and the two parts are symmetrical with respect to the central row in geometric positions. The details will be explained later.

[0127] In an embodiment, depending on the operation of the interface, a bonding sheet 170 may also be included for transmitting or receiving various control signals as needed in the operation between the master chip 100 and the slave chip 102, wherein a clock signal indicated by a thin arrow may be included in the bonding sheet 170 for transmitting or receiving. Arrow 160 represents the vertical connection at the bonding piece pattern 208 of the master interface 200M and the bonding piece pattern 220 of the slave interface 200S, and the vertical connection is used to communicate between the master chip 100 and the slave chip 102 through the bonding piece pattern 208 in the master interface 200M and the bonding piece pattern 220 in the slave interface 200S. For the master interface 200M, the inward thick arrow represents a command issued from a master device (e.g., a processor). The command is vertically transmitted downward to the slave device through the bonding piece pattern 208 of the master interface 200M and the bonding piece pattern 220 of the slave interface 200S. The output thick arrow represents that the command is transmitted to the slave device, such as an SRAM. The slave interface 200S then receives data from the slave device according to the command, and then transmits the data to the master interface 200M, which provides the data to the master device as indicated by the thick arrow having an output direction.

[0128] The bonding pieces 150M, 150S are configured to have a center row and a data row divided into two parts, the two parts being located at both sides of the center row in symmetrical positions. This configuration of the bonding piece allows the master chip to be easily packaged with the plurality of slave chips in a face-to-face, face-to-back, and back-to-back manner, wherein the bonding piece of the bonding piece pattern 208, 220 can be flipped or not flipped to adapt to the face-to-face, face-to-back, or back-to-back manner.

[0129] Fig. 9 FIG. 1 is a diagram schematically showing a 3D packaging structure of a master chip and a slave chip connected face-to-face, face-to-back, and back-to-back according to an embodiment of the present invention. Fig. 9 , the 3D packaging structure in the example includes a master chip (indicated as chip) and multiple slave chips (indicated as chip 0, chip 1, chip 2 and chip 3 as an example). Here, some slave chips 0 to 3 shown are only examples, but the present invention is not limited to this. The master chip can be adapted to more other chips in different areas of the chip, not limited to Fig. 9 In the example, the connection between the master chip and the slave chip 0 is face-to-face, the connection between the slave chip 0 and the slave chip 1 is face-to-back, the connection between the slave chip 1 and the slave chip 2 is back-to-back, and the connection between the slave chip 2 and the slave chip 3 is face-to-face. However, the present invention is not limited to the example.

[0130] Due to the configuration of the data binders in the binding sheet as described above, the data binders are symmetrical with respect to the center row. In the production, the data binders can be freely connected between the binder pattern 208 and the binder pattern 220, and the two center rows of the binder pattern 208 and the binder pattern 220 are aligned and connected. During operation, in an example, the data binders of the binder pattern 208 of the master interface 200M can be mapped to the data binders of the binder pattern 220 of the slave interface 200S by a multiplexer. In this case, the binders of the binder patterns 208, 220 can be arranged in a compact manner and can adapt to face-to-face, face-to-back and back-to-back modes.

[0131] Fig.10 FIG. 1 is a diagram schematically showing an arrangement of a set of bonding members in a bonding sheet corresponding to a main interface according to an embodiment of the present invention. Fig.10, taking the bonding piece 150M as an example, the voltage bonding piece 154M and another voltage bonding piece 156M for VSS in the embodiment are part of the functional bonding piece 158M set at the center row of the bonding piece 150M. In addition, according to the actual needs in the embodiment, the voltage bonding piece of VDD and the voltage bonding piece of VSS can be set at the peripheral rows. The center row may also include data parity T_PAR and redundant bonding piece T_LR. However, when the voltage bonding piece is set at the peripheral rows, the voltage bonding piece of VDD and the voltage bonding piece of VSS at the center row may be replaced by other signals. The present invention is not particularly limited to the embodiment. The bonding pieces arranged in the center row are general signals other than data signals. The middle row serves as the axis of symmetry. The data bonding pieces are located at both sides of the center row and in symmetrical positions. Therefore, when the bonding piece 150M is flipped along the axis of symmetry, the structure can remain unchanged. In other words, when the bonding piece 150M is flipped, the bonding piece at the center row will not change. However, when the bonding sheet 150M is flipped, the positions of the data binding elements T_D0 to T_D15 in the two parts are interchanged. In an embodiment, a flip case can be used to adapt to the face-to-back stacking structure. The data binding element can be connected to the bonding sheet 150S by direct connection or flip connection, which may involve a multiplexer to map the data in the connection.

[0132] Fig.11 FIG. 1 is a diagram schematically showing an arrangement of a set of coupling members in a coupling sheet corresponding to a slave interface according to an embodiment of the present invention. Fig.11 , for the slave interface 200S combined with the sheet 150S, it is similar to Fig.10 The functional binding piece is located at the center row or additionally at the peripheral row. Therefore, the functional binding piece can be globally located at the same position and can be directly connected. When the chip is turned upside down, the data binding piece will change. However, the binding piece configured in the present invention may help to easily adapt to the stacking structure.

[0133] In addition, the definition of the data binding piece is only an example, depending on the data to be transmitted or received from the master device or the slave device. As an example, the number of bits to be transmitted or received in one binding piece is 16, but it is not limited. In order to make the data rows symmetrical with respect to the center row, the total number of binding rows in one binding piece is an odd number. In an embodiment, the binding piece includes 7 binding rows, wherein the center row does not change when the binding piece is flipped.

[0134] Fig.12 FIG. 1 is a diagram schematically showing the arrangement of voltage bonding members in a bonding sheet according to an embodiment of the present invention. Fig.12In the embodiment of defining the binding element, a binding sheet 150M having 28 binding elements as an array is shown, in which 10 voltage binding elements are involved. The definition of the binding element is listed in Table 1 as an example. According to the configuration, 28 binding elements for various signals are involved in one binding sheet. In an embodiment, the voltage binding elements VSS and VDD are distributed in the center row and the peripheral rows. The center row is used as a symmetry axis and also includes a redundant binding element C_LR, and the clock CLK is set in the center row. Commands, data, parity and chip identification (identification, ID) are set to be symmetrical. However, the definition of the binding element is not limited to the embodiments provided for illustration.

[0135] Table 1

[0136] Combination Number of joints direction Function Master command, M_CMD[1:0] 2 M->S Command symmetry Master chip ID to slave chip ID, M_DID[3:0] 4 M->S Chip ID: Symmetrical Master command parity, M_PAR 1 M->S Parity: Symmetric Slave command, S_CMD[1:0] 2 M->S Command: Symmetric From chip ID to master chip ID, S_DID[3:0] 4 M->S Chip ID: Symmetrical Slave command parity S_PAR 1 M->S Parity: Symmetric Redundant coupling, C_LR 1 M->S Redundancy: Center Row Clock, CLK 1 M->S Clock: Center Row Read DQS, RDQS_R / F 2 S->M Read DQS: Symmetric

[0137] Fig.13 FIG. 1 is a diagram schematically showing an output mechanism for a bonded sheet with flip control according to an embodiment of the present invention. Fig.13 , describing the flipping mechanism for transmitting read data from the interface. The binding position of the left binding sheet is in an unflipped or direct state and the binding position of the right binding sheet is in a flipping state required in the packaging process. Taking the data binding members R_D0 to R_D15 as an example, the data binding members R_D0 to R_D15 are arranged to have symmetrical properties. When the left binding sheet is flipped as shown in the right binding sheet, the lower part of the data binding members R_D0 to R_D7 in the right binding sheet corresponds to the upper part of the data binding members R_D0 to R_D7 in the left binding sheet. Similarly, the upper part of the data binding members R_D8 to R_D15 in the right binding sheet corresponds to the lower part of the data binding members R_D8 to R_D15 in the left binding sheet. The voltage binding members VDD and VSS will not change. When flipped, the functional binding members at the middle row will not change.

[0138] In an embodiment, in order to obtain appropriate output data from the slave device, the output side of the master / slave interface can be further implemented using a flip multiplexer MUX with a 2:1 multiplexing capability to output data according to a flip state or a direct state. For direct output, the control signal Flip is set to Flip=0. For flip output, the control signal Flip is set to Flip=1.

[0139] In the example, the bindings are defined in different assignments depending on whether they are flipped or not. Table 2 shows the defined bindings associated with the original data bits in the straight view or flipped view.

[0140] Table 2

[0141]

[0142] Fig.14 is a diagram schematically illustrating an input mechanism for a combined sheet with flip control according to an embodiment of the present invention. Fig.14 ,for Fig.12 In the example of different types of bonding sheets, the left bonding sheet is in a direct state of transmitting commands from the main device. However, if a flip state is required to adapt to the packaging process, the upper bonding piece in the right bonding sheet corresponds to the lower bonding piece in the left bonding sheet, and the lower bonding piece in the right bonding sheet corresponds to the upper bonding piece in the left bonding sheet. The flip multiplexer at the input side of the left bonding sheet is set to Flip=0, and the flip multiplexer at the input side of the right bonding sheet is set to Flip=1. As described above, the defined bonding pieces can be changed according to actual needs without being limited to the described embodiments.

[0143] Fig.15 FIG. 1 is a diagram schematically showing a bonding structure involved in data communication between a master interface and a slave interface in a direct manner from the bonding structure according to an embodiment of the present invention. Fig.15 , which is a direct view of the bonding pattern in direct connection. Taking the 128-bit data size transmitted between the master device and the slave device as an example, the bonding pattern 208 of the master interface 200M and the bonding pattern 220 of the slave interface 200S may include multiple bonding pads to transmit various command data, operating voltages, bit data, etc. Make the bonding in the bonding pattern 208 and the bonding in the bonding pattern 220 compatible.

[0144] The master device intends to transmit data (indicated as tx_data) to the slave device. In the absence of a direct view of the combination flip, the flip multiplexer 304 is controlled by the control signal 306 to be set in the state of Flip=0. Similarly, the data tx_data responded from the slave device (such as SRAM) can first pass through the flip multiplexer 300, and the control signal 302 of the flip multiplexer 300 is also set in the state of Flip=0. The data will be returned to the main circuit of the master device.

[0145] Fig.16 According to an embodiment of the present invention, schematically illustrating a Fig.15 FIG. 1 is a diagram of a coupling structure involved in data communication between a master interface and a slave interface in a flipping manner of a slave coupling structure.

[0146] Reference Fig.16As an example, when the slave chip is stacked on the master chip according to the need to flip the bonding pattern of the slave interface 200S, the bonding elements in the bonding pattern 220 are flipped. As described above with respect to the flip mechanism, the bonding definition is flipped. However, the original data bits from the slave device need to be flipped by the flip multiplexers 300, 304, wherein the control signals 302, 306 are set to the state Flip=1 according to the flipped bonding pattern.

[0147] Therefore, the chips can be stacked in a face-to-face, back-to-back or face-to-back manner, wherein the flipped bonding pattern is flexibly redefined. As described above, there is no need to flip a portion of the bonding including voltage bonding, parity bonding, etc.

[0148] Fig.17 FIG. 1 is a diagram schematically showing a circuit structure of an interface combining a DDR mechanism and a toggle mechanism according to an embodiment of the present invention.

[0149] Reference Fig.17 as well as Figure 7 For one command data from the master chip 100 , for example, tx_data[31:0], the data tx_data as the command may include 32 bits of data in the example. The data tx_data is first controlled by the flip multiplexer 300 .

[0150] For further operation based on the DDR mechanism, in an embodiment, the 32-bit data may be divided into two groups of 16-bit data, and the two groups of 16-bit data are respectively input to the trigger block 202. The master multiplexer 206 also operates under the DDR mechanism. After the command data tx_data is transmitted to the slave chip 102, the two parts of the data enter the trigger block 222a and the trigger block 222b respectively through two paths. The trigger block 222a and the trigger block 222b correspond to Figure 6 The trigger block 222 in the circuit. The clock clk also controls the trigger block 222a and the trigger block 222b.

[0151] However, in order to correctly decode the data cluster (since the shape of the data cluster is usually represented as an eye-like shape in the data train, the data cluster is also called a data eye), several delay lock loop (DLL) blocks can be used, such as DLLr 230a and DLLf 230b shown. In addition, a delay control unit 230c indicated by CACd 230c is also used to modify the clock clk to control the flip-flop blocks 222a, 222b. Then, the bits in the data cluster are correctly decoded. Due to the DDR mechanism, the inverter 240 is used to invert the voltage level at DLLf 230b before providing it to the flip-flop blocks 222a, 222b. The DDR bus then provides the data rx_data in the slave interface 200S of the slave chip 102.

[0152] In order to output from the slave chip 102 according to the stacking of the chips, the flip multiplexer 304 is also included in the example of the reverse flip operation, thereby obtaining the data rx_data to enter the stacked slave chip. In other words, the flip multiplexer can be assisted to implement to adapt to the flip combination pattern, so as to correctly map the connection of the data combination.

[0153] As further shown, in an embodiment, flip multiplexer 300 and flip multiplexer 304 are used to map data combination pieces into the original sequence according to the stacking mode. In an embodiment, the two multiplexers 300, 304 can be set only in the slave interface 200S because each slave chip can flip or not flip. The slave chip knows whether it is flipped and can set the FLIP control of the multiplexer accordingly. In an example further modified in the embodiment, the slave interface 200S can include flip multiplexer 300 at the input side to locate the two parts of the input data row. The slave interface 200S then also includes another flip multiplexer 304 at the output side to locate the two parts of the output data row.

[0154] Further from the perspective of the entire combination pattern having a flipping property, the flipping axis can be the X-axis or the Y-axis. Fig.18 FIG. 1 is a diagram schematically illustrating an application of flipping the entire chip relative to the X-axis according to an embodiment of the present invention. Fig.19 FIG. 1 is a diagram schematically showing an application of flipping the entire chip relative to the Y-axis according to an embodiment of the present invention.

[0155] Reference Fig.18, the symmetry axis 180 may be the X axis as the horizontal axis. The bonding pattern having a plurality of bonding pieces extends along the symmetry axis 180. Taking the bonding pattern 208 of the main chip 100 as an example, the bonding pattern 208 in the south side S is symmetrical with the bonding pattern in the north side N, and then may be flipped based on the flipping mechanism as described above. Fig.19 In another configuration, the symmetry axis 192 may be set to be a Y-axis extending along the south side S to the north side N. The binder pattern 208 may then be flipped between east and west relative to the symmetry axis 192 .

[0156] According to the foregoing description, in an embodiment, the present invention provides an interface of a semiconductor device, the semiconductor device comprising a master device and a plurality of slave devices. The interface comprises a master interface and a slave interface of each of the slave devices. The master interface is implemented in the master device and comprises a master binding member pattern formed by master binding members arranged in a first array. The slave interface is implemented in each of the slave devices and comprises a slave binding member pattern formed by slave binding members arranged in a second array. The first array of the master binding members comprises a first center row and a first group of data rows divided into two parts, the two parts being symmetrical relative to the first center row. The second array of the slave binding members comprises a second center row and a second group of data rows divided into two parts, the two parts being symmetrical relative to the second center row. The first center row is aligned with the second center row in connection, and the first group of data rows is connected to the second group of data rows.

[0157] In an embodiment, the present invention also provides a method for arranging an interface of a semiconductor device, the semiconductor device comprising a master device and a plurality of slave devices, the method comprising: providing a master interface, the master interface being implemented in the master device and comprising a master binder pattern formed by master binders arranged in a first array; and providing a slave interface, the slave interface being implemented in each of the slave devices and comprising a slave binder pattern formed by slave binders arranged in a second array. The first array of the arranged master binders comprises a first center row and a first group of data rows divided into two parts, the two parts being symmetrical with respect to the first center row. The second array of the arranged slave binders comprises a second center row and a second group of data rows divided into two parts, the two parts being symmetrical with respect to the second center row. The first center row is aligned with the second center row in connection, and the first group of data rows is connected to the second group of data rows.

[0158] The configuration of the data binding element is symmetrical with respect to the axis of symmetry. Among these features of the binding element pattern, the data binding element can be easily flipped to adapt to the 3D stacking structure in the packaging process. In order to further control the data binding element in the flipping operation, a flip multiplexer can also be implemented in the interface to adapt to the operation of whether to flip the binding element, thereby allowing the chips to be stacked in various ways by face-to-face, back-to-back or face-to-back.

[0159] It will be apparent to those skilled in the art that various modifications and variations may be made to the disclosed embodiments without departing from the scope or spirit of the present disclosure. In view of the foregoing, the present disclosure is intended to cover modifications and variations provided within the scope of the above claims and their equivalents.

Claims

1. An interface of a semiconductor device, the semiconductor device comprising a master device and a plurality of slave devices, characterized in that: The interface includes: a master interface implemented in the master device and comprising a master bonding element pattern formed by master bonding elements arranged in a first array; and a slave interface implemented in each of the slave devices and comprising a slave binding element pattern formed by slave binding elements arranged in a second array; The first array formed by the main combination comprises a first central row and a first group of data rows divided into two parts, the two parts are completely symmetrical with respect to the first central row, wherein the second array formed from the combined elements comprises a second central row and a second set of data rows divided into two parts, the two parts being completely symmetrical with respect to the second central row, The first center row is aligned with the second center row in chip connection, and the first group of data rows is connected to the second group of data rows.

2. The semiconductor device interface according to claim 1, characterized in that: The first array further comprises two peripheral rows symmetrical with respect to the first central row, wherein the second array further comprises two peripheral rows symmetrical with respect to the second central row.

3. The interface of a semiconductor device according to claim 1, characterized in that: wherein the slave interface further comprises a first flip multiplexer at the input side to position the two parts of the first set of data rows, and The slave interface further comprises a second flip multiplexer at the output side to position the two parts of the second set of data rows.

4. The semiconductor device interface according to claim 1, wherein: The master bonds of the first center row and the slave bonds of the second center row are identical to transmit global signals.

5. The interface of a semiconductor device according to claim 4, characterized in that: The global signal includes a high voltage, a ground voltage, a clock signal, and / or data parity information, and / or a redundant signal.

6. The semiconductor device interface according to claim 1, characterized in that: A through silicon via is included in the connection with the master bonding component or the slave bonding component to stack the master device and the slave device with connection pads facing each other or facing each other.

7. The interface of a semiconductor device according to claim 1, characterized in that: A flip multiplexer is also included in the master device or the slave device to restore the original data bits defined internally in the master device or the slave device.

8. The interface of a semiconductor device according to claim 1, characterized in that: The first center row and the first set of data rows form a first signal group, and a plurality of the first signal groups form a master bonding element pattern.

9. The interface of a semiconductor device according to claim 8, characterized in that: The second center row and the second set of data rows form a second signal group, and a plurality of the second signal groups form a total slave coupling element pattern.

10. The semiconductor device interface according to claim 1, wherein: The master device and the slave device are stacked by electrical connection between the master bonding pattern and the slave bonding pattern.

11. The semiconductor device interface according to claim 1, characterized in that: The master device transmits a signal to all the slave interfaces through the master binding pattern and the slave binding pattern, and the slave device responds a signal to the master interface through the master binding pattern and the slave binding pattern.

12. The interface of a semiconductor device according to claim 1, characterized in that: The first central row is configured to transmit a first part of a global signal, wherein the first array further includes two first peripheral rows symmetrical with respect to the first central row for transmitting a system voltage and a second part of the global signal.

13. The interface of a semiconductor device according to claim 12, characterized in that: In each of the slave devices, the second central row is configured to transmit the first portion of the global signal, wherein the second array further includes two second peripheral rows symmetrical with respect to the second central row for transmitting the system voltage and the second portion of the global signal.

14. A method for arranging interfaces of a semiconductor device, the semiconductor device comprising a master device and a plurality of slave devices, characterized in that: The method comprises: providing a host interface implemented in the host device and comprising a host bonding element pattern formed by host bonding elements arranged in a first array; and providing a slave interface implemented in each of the slave devices and comprising a slave binding element pattern formed by slave binding elements arranged in a second array; The first array formed by the arranged main combining elements includes a first central row and a first group of data rows divided into two parts, the two parts are completely symmetrical with respect to the first central row, The second array of the slave combining elements arranged therein comprises a second central row and a second group of data rows divided into two parts, wherein the second group of data rows is completely symmetrical with respect to the second central row, The first center row is aligned with the second center row in chip connection, and the first group of data rows is connected to the second group of data rows.

15. The method for arranging interfaces of semiconductor devices according to claim 14, characterized in that: The first array further comprises two peripheral rows symmetrical with respect to the first central row, wherein the second array further comprises two peripheral rows symmetrical with respect to the second central row.

16. The method for arranging interfaces of semiconductor devices according to claim 14, characterized in that: The slave interface is arranged to further include a first flip multiplexer at the input side to position the two parts of the first set of data lines, and The slave interface is arranged to further comprise a second flip multiplexer at the output side to position the two parts of the second set of data lines.

17. The method for arranging interfaces of semiconductor devices according to claim 14, characterized in that: The master binding members of the first center row and the slave binding members of the second center row are identical for transmitting global signals.

18. The method for arranging interfaces of semiconductor devices according to claim 17, characterized in that: The global signal includes a high voltage, a ground voltage, a clock signal, and / or data parity information, and / or a redundant signal.

19. The method for arranging interfaces of semiconductor devices according to claim 14, characterized in that: A through silicon via is included in the connection with the master bonding component or the slave bonding component to stack the master device and the slave device with connection pads facing each other or facing each other.

20. The method for arranging interfaces of semiconductor devices according to claim 14, characterized in that: A flip multiplexer is also included in the master device or the slave device to restore the original data bits defined internally in the master device or the slave device.

21. The method for arranging interfaces of semiconductor devices according to claim 14, characterized in that: The first center row and the first set of data rows form a first signal group, and a plurality of the first signal groups form a master bonding element pattern.

22. The method for arranging interfaces of semiconductor devices according to claim 21, characterized in that: The second center row and the second set of data rows form a second signal group, and a plurality of the second signal groups form a total slave coupling element pattern.

23. The method for arranging interfaces of semiconductor devices according to claim 14, characterized in that: The master device and the slave device are stacked by electrical connection between the master bonding pattern and the slave bonding pattern.

24. The method for arranging interfaces of semiconductor devices according to claim 14, characterized in that: The master device transmits a signal to all the slave interfaces through the master bonding pattern and the slave bonding pattern, and the slave device responds a signal to the master interface through the master bonding pattern and the slave bonding pattern.

25. The method for arranging interfaces of semiconductor devices according to claim 14, characterized in that: The first central row is configured to transmit a first part of a global signal, wherein the first array further includes two first peripheral rows symmetrical with respect to the first central row for transmitting a system voltage and a second part of the global signal.

26. The method for arranging interfaces of semiconductor devices according to claim 25, characterized in that: In each of the slave devices, the second central row is configured to transmit the first portion of the global signal, wherein the second array further includes two second peripheral rows symmetrical with respect to the second central row for transmitting the system voltage and the second portion of the global signal.

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