Method, apparatus, electronic device and storage medium for security protection

Abstract

The present application relates to the technical field of memory, and discloses a method for security protection, including: when receiving a memory access request, verifying a bus control signal; when the bus control signal verification is passed, triggering a plurality of data error detection modules to respectively obtain corresponding comparison check codes according to the memory address to be accessed; determining whether each data error detection module fails according to each comparison check code; when it is determined that none of the data error detection modules fails, determining whether the memory address to be accessed passes the verification by using the comparison check code; when the memory address to be accessed passes the verification, storing the data to be stored in the memory access request into a target memory; or, triggering the target memory to read target data according to the memory access request. In this way, the security of accessing the memory can be improved. The present application also discloses a device, an electronic device and a storage medium for security protection.

Description

Technical Field

[0001] This application relates to the technical field of memory, and for example, relates to a method, device, electronic device and storage medium for security protection. Background Art

[0002] Before a bus master, such as a central processing unit (CPU), reads data stored in a memory, erases data stored in the memory, or stores data to be stored in the memory, in order to achieve secure access to the memory data, it is necessary to verify the address information sent by the bus master.

[0003] In the process of implementing the embodiments of the present disclosure, it is found that at least the following problems exist in the related art:

[0004] Since the prior art can only verify the address information sent by the bus master and cannot determine whether the module for verifying the address information has failed, the access to the memory is not secure enough. Summary of the Invention

[0005] To provide a basic understanding of some aspects of the disclosed embodiments, a simple summary is given below. This summary is not an extensive review, nor is it intended to identify key / important elements or delineate the scope of protection of these embodiments. Instead, it serves as a preamble to the detailed description that follows.

[0006] Embodiments of the present disclosure provide a method, device, electronic device and storage medium for security protection, so as to improve the security of accessing a memory.

[0007] In some embodiments, the method for security protection includes: when receiving a memory access request sent by a bus, verifying a bus control signal in the memory access request; when the bus control signal passes the verification, triggering a plurality of data error detection modules to respectively obtain corresponding comparison verification codes according to a memory address to be accessed in the memory access request; determining whether each of the data error detection modules has failed according to each of the comparison verification codes; when it is determined that none of the data error detection modules has failed, determining whether the memory address to be accessed passes the verification by using any one of the comparison verification codes; when the memory address to be accessed passes the verification, storing the data to be stored in the memory access request into the target memory; or, triggering the target memory to read target data according to the memory access request.

[0008] In some embodiments, the device for security protection includes: a bus control signal verification module configured to verify the bus control signal in the memory access request when receiving the memory access request sent by the bus; a trigger module configured to trigger a plurality of data error detection modules to respectively obtain corresponding verification codes to be compared according to the memory address to be accessed in the memory access request when the verification of the bus control signal is passed; a first determination module configured to determine whether each of the data error detection modules fails according to each of the verification codes to be compared; a second determination module configured to determine whether the memory address to be accessed passes the verification by using any one of the verification codes to be compared when it is determined that none of the data error detection modules fails; a secure access module configured to store the data to be stored in the memory access request in the target memory when the memory address to be accessed passes the verification; or, trigger the target memory to read target data according to the memory access request.

[0009] In some embodiments, the device for security protection includes a processor and a memory storing program instructions, and the processor is configured to execute the above-mentioned method for security protection when running the program instructions.

[0010] In some embodiments, the electronic device includes the above-mentioned device for security protection.

[0011] In some embodiments, the storage medium stores program instructions, and the program instructions execute the above-mentioned method for security protection when running.

[0012] The method, device, electronic device, and storage medium for security protection provided by the embodiments of the present disclosure can achieve the following technical effects: by triggering a plurality of data error detection modules to respectively obtain corresponding verification codes to be compared according to the memory address to be accessed when the verification of the bus control signal is passed; and determining whether each data error detection module fails according to each verification code to be compared; then, when none of the data error detection modules fails, using any one of the verification codes to be compared to verify the memory address to be accessed; and when the memory address to be accessed passes the verification, storing the data to be stored in the memory access request in the target memory; or, triggering the target memory to read target data according to the memory access request. In this way, it is possible to determine whether a data error detection module fails, and thus improve the security of accessing the memory.

[0013] The above general description and the following description are only exemplary and explanatory, and are not used to limit this application. Description of the Drawings

[0014] One or more embodiments are exemplarily illustrated by corresponding accompanying drawings. These exemplary illustrations and the accompanying drawings do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements. The drawings do not constitute a scale limitation, and wherein:

[0015] Figure 1 is a schematic diagram of the first method for security protection provided by an embodiment of the present disclosure;

[0016] Figure 2 is a schematic diagram of the second method for security protection provided by an embodiment of the present disclosure;

[0017] Figure 3 is a schematic diagram of the third method for security protection provided by an embodiment of the present disclosure;

[0018] Figure 4 is a schematic diagram of a device for security protection provided by an embodiment of the present disclosure;

[0019] Figure 5 is a schematic diagram of an actual application system of a method for security protection provided by an embodiment of the present disclosure;

[0020] Figure 6 is a schematic diagram of another device for security protection provided by an embodiment of the present disclosure. Detailed implementation manners

[0021] In order to be able to more thoroughly understand the features and technical content of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. The attached accompanying drawings are only for reference and illustration purposes and are not used to limit the embodiments of the present disclosure. In the following technical descriptions, for the sake of explanation, multiple details are provided to provide a full understanding of the disclosed embodiments. However, one or more embodiments can still be implemented without these details. In other cases, well-known structures and devices can be shown in a simplified manner.

[0022] In the specification and claims of the embodiments of the present disclosure and the above accompanying drawings, terms such as "first", "second", etc. are used to distinguish similar objects and do not have to be used to describe a specific order or sequence. It should be understood that such data used can be interchanged under appropriate circumstances so as to implement the embodiments of the present disclosure described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion.

[0023] Unless otherwise specified, the term "plurality" means two or more.

[0024] In the embodiments of the present disclosure, the character " / " indicates that the objects before and after are in an "or" relationship. For example, A / B means: A or B.

[0025] The term "and / or" describes the relationship between objects and indicates that there can be three relationships. For example, A and / or B means: A or B, or, the three relationships of A and B.

[0026] The term "corresponding" can refer to a relationship of association or a binding relationship. A corresponding to B means that there is a relationship of association or a binding relationship between A and B.

[0027] Combine Figure 1 As shown, an embodiment of the present disclosure provides a method for security protection, including:

[0028] Step S101, when receiving a memory access request sent by the bus, verify the bus control signal in the memory access request;

[0029] Step S102, when the bus control signal verification passes, trigger multiple data error detection modules to respectively obtain corresponding comparison check codes according to the memory address to be accessed in the memory access request;

[0030] Step S103, determine whether each data error detection module has a fault according to each comparison check code;

[0031] Step S104, when it is determined that none of the data error detection modules have a fault, use any one of the comparison check codes to determine whether the memory address to be accessed passes the verification;

[0032] Step S105, when the memory address to be accessed passes the verification, store the data to be stored in the memory access request into the target memory; or, trigger the target memory to read the target data according to the memory access request.

[0033] The method for security protection provided by the embodiment of the present disclosure, by triggering multiple data error detection modules to respectively obtain corresponding comparison check codes for the memory address to be accessed when the bus control signal verification passes; and determining whether each data error detection module has a fault according to each comparison check code; then, when none of the data error detection modules have a fault, using any one of the comparison check codes to determine whether the memory address to be accessed passes the verification; and when the memory address to be accessed passes the verification, storing the data to be stored in the memory access request into the target memory; or, triggering the target memory to read the target data according to the memory access request. In this way, it is possible to determine whether the data error detection module has a fault, and thus improve the security of accessing the memory.

[0034] In some embodiments, the target memory is a static random access memory.

[0035] In some embodiments, there are two data error detection modules.

[0036] Optionally, the memory access request in the bus is obtained in the following manner: the bus master sends the memory access request to the bus. In some embodiments, the bus master is a CPU (Central Processing Unit) or a DMA (Direct Memory Access).

[0037] Optionally, after verifying the bus control signal in the memory access request, it further includes: when the verification of the bus control signal fails, sending a first prompt message indicating the error in the verification of the bus control signal to the bus master. In this way, the user can modify the memory access request according to the first prompt message and send the modified memory access request again through the bus master.

[0038] Optionally, after verifying the bus control signal in the memory access request, it further includes: when the verification of the bus control signal fails, recording the address information when the verification of the bus control signal fails. This facilitates tracing the error information.

[0039] Optionally, the memory address to be accessed in the memory access request includes row address information and column address information; triggering the target memory to read the target data according to the memory access request includes: triggering the target memory to read the target data according to the row address information and the column address information.

[0040] Optionally, after triggering the target memory to read the target data according to the memory access request, it further includes: triggering the target memory to feedback the target data and the third parity check code corresponding to the target data to the data error detection module, and triggering the data error detection module to obtain a fourth parity check code by using the target data; determining whether the target data passes the verification according to the third parity check code and the fourth parity check code.

[0041] Optionally, determining whether the target data passes the verification according to the third parity check code and the fourth parity check code includes: when the third parity check code and the fourth parity check code are the same, determining that the target data passes the verification; and / or, when the third parity check code and the fourth parity check code are different, determining that the target data fails the verification.

[0042] Optionally, after determining that the target data fails the verification, it further includes: determining whether the error of the target data is a correctable error. When the error of the target data is a correctable error, correcting the error in the target data and then feeding it back to the bus master; and / or, when the error of the target data is an uncorrectable error, sending a fourth prompt message indicating the error of the target data to the bus master.

[0043] Optionally, determining whether an error in the target data is a correctable error includes: when only one value of the third parity code and the fourth parity code is different, determining the error in the target data corresponding to the fourth parity code as a correctable error; and / or when two or more values of the third parity code and the fourth parity code are different, determining the error in the target data corresponding to the fourth parity code as an uncorrectable error.

[0044] Optionally, after determining that the target data fails the check, it further includes: recording the address information when the target data fails the check. This facilitates tracing the error information.

[0045] Optionally, after determining that the target data passes the check, it further includes: adding a corresponding fifth parity code to the target data; and sending the target data and the fifth parity code to the bus master. Optionally, the data error detection module sends a bypass signal including the fifth parity code to the bus master.

[0046] Optionally, the memory access request includes a first parity code corresponding to the bus control signal; checking the bus control signal in the memory access request includes: obtaining a second parity code using the bus control signal; comparing the second parity code with the first parity code; when the second parity code is the same as the first parity code, determining that the bus control signal passes the check; and / or when the second parity code is different from the first parity code, determining that the bus control signal fails the check.

[0047] In some embodiments, the memory access request includes a bypass signal, and the first parity code corresponding to the bus control signal is stored in the bypass signal.

[0048] Optionally, the memory access request includes a target check code corresponding to the memory address to be accessed; checking the memory address to be accessed according to any check code to be compared includes: comparing the target check code with the check code to be compared; when the target check code is the same as the check code to be compared, determining that the memory address to be accessed passes the check; and / or when the target check code is different from the check code to be compared, determining that the memory address to be accessed fails the check. In this way, when it is determined that the data error detection module does not malfunction, using the data error detection module to check the memory address to be accessed can improve the accuracy of the check result of the memory address to be accessed.

[0049] Optionally, before storing the data to be stored in the memory access request into the target memory, it further includes: triggering the data error detection module to verify the data to be stored in the memory access request; and in the case where the data to be stored passes the verification, storing the data to be stored in the memory access request into the target memory. In this way, in the case where it is determined that the data error detection module has not failed, using the data error detection module to verify the data to be stored can improve the accuracy rate of the verification result of the data to be stored.

[0050] Combined with Figure 2 As shown, an embodiment of the present disclosure provides a method for security protection, including:

[0051] Step S201, when receiving a memory access request sent by the bus, verifying the bus control signal in the memory access request;

[0052] Step S202, in the case where the bus control signal passes the verification, triggering multiple data error detection modules to respectively obtain corresponding comparison check codes according to the memory address to be accessed in the memory access request;

[0053] Step S203, determining whether each data error detection module has failed according to each comparison check code;

[0054] Step S204, in the case where it is determined that none of the data error detection modules has failed, determining whether the memory address to be accessed passes the verification by using any one of the comparison check codes;

[0055] Step S205, in the case where the memory address to be accessed passes the verification, triggering the data error detection module to verify the data to be stored in the memory access request;

[0056] Step S206, in the case where the data to be stored passes the verification, storing the data to be stored in the memory access request into the target memory.

[0057] The method for security protection provided by the embodiment of the present disclosure triggers multiple data error detection modules to respectively obtain corresponding comparison check codes according to the memory address to be accessed in the case where the bus control signal passes the verification; and determines whether each data error detection module has failed according to each comparison check code; then, in the case where none of the data error detection modules has failed, determines whether the memory address to be accessed passes the verification by using any one of the comparison check codes; and uses the data error detection module to detect the data to be stored, and in the case where both the memory address to be accessed and the data to be stored pass the verification, stores the data to be stored in the memory access request into the target memory. In this way, it can be determined whether the data error detection module has failed, and thus the security of accessing the memory can be improved.

[0058] Optionally, after determining that the memory address access to be verified fails, it further includes: sending a second prompt message for characterizing the address verification error to the bus master device.

[0059] Optionally, after determining that the memory address access to be verified fails, it further includes: recording the address information when the memory address access to be verified fails. This facilitates tracing of error information.

[0060] Optionally, after triggering the data error detection module to verify the data to be stored in the memory access request, it further includes: in the case where the verification of the data to be stored fails, sending a third prompt message for characterizing the data verification error to the bus master device.

[0061] Optionally, after triggering the data error detection module to verify the data to be stored in the memory access request, it further includes: in the case where the verification of the data to be stored fails, recording the address information when the verification of the data to be stored fails.

[0062] Optionally, determining whether each data error detection module fails according to each comparison verification code to be compared includes: in the case where all the comparison verification codes to be compared are the same, determining that none of the data error detection modules fails; and / or, in the case where there are differences among the comparison verification codes to be compared, determining that each data error detection module fails, and determining each data error detection module as an alternative failed data error detection module. Since when each data error detection module does not fail, each data error detection module calculates using the same memory address to be accessed, and the obtained multiple comparison verification codes should be the same, therefore, it is possible to determine whether the data error detection module fails by determining whether the multiple comparison verification codes are the same.

[0063] Optionally, after determining each data error detection module as an alternative failed data error detection module, it further includes: sending the detection verification code corresponding to the original data information and the detection data information obtained after injecting error data information into the first preset position of the original data information to each alternative failed data error detection module, triggering each alternative failed data error detection module to respectively obtain corresponding detection comparison codes according to the detection data information; determining whether the comparison value to be compared in the second preset position of each detection comparison code is the same as the target value in the third preset position of the detection verification code; determining the alternative failed data error detection module corresponding to the comparison value to be compared that is the same as the target value as the target failed data error detection module. In this way, by determining whether the comparison value to be compared in the second preset position is the same as the target value in the third preset position, it is possible to determine whether the alternative failed data error detection module can detect the error data information in the detection data information; and further determine the target failed data error detection module from the alternative failed data error detection modules.

[0064] Combined Figure 3 As shown, an embodiment of the present disclosure provides a method for security protection, including:

[0065] Step S301, when receiving a memory access request sent from the bus, verify the bus control signal in the memory access request;

[0066] Step S302, when the bus control signal verification passes, trigger multiple data error detection modules to respectively obtain corresponding comparison check codes according to the memory addresses to be accessed in the memory access request;

[0067] Step S303, determine whether each data error detection module fails according to each comparison check code;

[0068] Step S304, when there are differences among the comparison check codes, determine that each data error detection module fails, and determine each data error detection module as an alternative faulty data error detection module;

[0069] Step S305, send the detection check code corresponding to the original data information and the detection data information obtained after injecting error data information into the first preset position of the original data information to each alternative faulty data error detection module, and trigger each alternative faulty data error detection module to respectively obtain corresponding detection comparison codes according to the detection data information;

[0070] Step S306, determine whether the value to be compared in the second preset position of each detection comparison code is the same as the target value in the third preset position of the detection check code;

[0071] Step S307, determine the alternative faulty data error detection module corresponding to the value to be compared that is the same as the target value as the target faulty data error detection module.

[0072] The method for security protection provided by the embodiment of the present disclosure, when the bus control signal verification passes, triggers multiple data error detection modules to respectively obtain corresponding comparison check codes according to the memory addresses to be accessed; and determines whether each data error detection module fails according to each comparison check code; in this way, it can be determined whether there is a faulty module among the multiple data error detection modules; at the same time, by sending the detection data information including error data information to the data detection module and using the data detection module to detect the detection data information, by determining whether the data detection module can detect that the detection data information includes error data information, the target faulty data error detection module can be determined among multiple alternative faulty data error detection modules.

[0073] Combined Figure 4As shown in the figure, an embodiment of the present disclosure provides a device for security protection, including a bus control signal verification module 401, a trigger module 402, a first determination module 403, a second determination module 404, and a secure access module 405; the bus control signal verification module 401 is configured to verify the bus control signal in the memory access request when receiving the memory access request sent by the bus; the trigger module 402 is configured to trigger a plurality of data error detection modules to respectively obtain corresponding comparison verification codes according to the memory address to be accessed in the memory access request when the bus control signal verification is passed; the first determination module 403 is configured to determine whether each data error detection module fails according to each comparison verification code; the second determination module 404 is configured to determine whether the memory address to be accessed passes the verification by using any one of the comparison verification codes when it is determined that none of the data error detection modules fails; the secure access module 405 is configured to store the data to be stored in the memory access request into the target memory when the memory address to be accessed passes the verification; or, trigger the target memory to read the target data according to the memory access request.

[0074] The device for security protection provided by the embodiment of the present disclosure triggers a plurality of data error detection modules to respectively obtain corresponding comparison verification codes according to the memory address to be accessed when the bus control signal verification is passed by the trigger module; and determines whether each data error detection module fails according to each comparison verification code; then determines whether the memory address to be accessed passes the verification by using any one of the comparison verification codes when none of the data error detection modules fails; and stores the data to be stored in the memory access request into the target memory by using the secure access module when the memory address to be accessed passes the verification; or, triggers the target memory to read the target data according to the memory access request. In this way, it is possible to determine whether the data error detection module fails, and thus improve the security of accessing the memory.

[0075] Optionally, the bus control signal verification module is configured to verify the bus control signal in the memory access request in the following manner: obtain a second parity check code with the bus control signal; compare the second parity check code with the first parity check code; determine that the bus control signal verification is passed when the second parity check code is the same as the first parity check code; and / or, determine that the bus control signal verification fails when the second parity check code is different from the first parity check code.

[0076] Optionally, the second determination module is configured to determine whether the memory address to be accessed passes the verification by using any verification code to be compared in the following manner, including: comparing the target verification code with the verification code to be compared; determining that the memory address to be accessed passes the verification when the target verification code is the same as the verification code to be compared; and / or determining that the memory address to be accessed fails to pass the verification when the target verification code is different from the verification code to be compared.

[0077] Optionally, the trigger module is further configured to trigger the data error detection module to verify the data to be stored in the memory access request before storing the data to be stored in the memory access request into the target memory.

[0078] Optionally, the secure access module is configured to store the data to be stored in the memory access request into the target memory when the memory address to be accessed passes the verification and the data to be stored passes the verification.

[0079] Optionally, the first determination module is configured to determine whether each data error detection module fails according to each verification code to be compared in the following manner: determining that none of the data error detection modules fails when all the verification codes to be compared are the same; and / or determining that each data error detection module fails and determining each data error detection module as an alternative faulty data error detection module when there are differences among the verification codes to be compared.

[0080] Optionally, the device for security protection further includes an error injection module, and the error injection module is configured to send the detection verification code corresponding to the original data information and the detection data information obtained after injecting error data information into the first preset position of the original data information to each alternative faulty data error detection module, trigger each alternative faulty data error detection module to respectively obtain the corresponding detection comparison code according to the detection data information; determine whether the value to be compared in the second preset position of each detection comparison code is the same as the target value in the third preset position of the detection verification code; and determine the alternative faulty data error detection module corresponding to the value to be compared that is the same as the target value as the target faulty data error detection module.

[0081] Optionally, the error injection module is further configured to send the detection verification code corresponding to the original data information and the detection data information to each error detection module, and trigger each error detection module to perform self-checking by using the detection verification code corresponding to the original data information and the detection data information.

[0082] Optionally, the device for security protection further includes an error address recording module, which is configured to record the address information when the target data fails to pass the verification, record the address information when the memory address to be accessed fails to pass the verification, and record the address information when the data to be stored fails to pass the verification.

[0083] Optionally, the device for security protection further includes a register redundancy check module, which sets redundancy for the registers in the bus control signal check module, the registers in the data error detection module, and the registers in the error injection module. This can improve the functional reliability of the bus control signal check module, the data error detection module, and the error injection module.

[0084] Combined with Figure 5 As shown, an embodiment of the present disclosure provides a method for security protection, including: a bus master 501 sends a memory access request to a first bus 502. When the first bus 502 receives the memory access request, it sends the memory access request to a bus control signal check module 503. When the bus control signal check module 503 receives the memory access request, it checks the bus control signal in the memory access request. When the bus control signal check passes, the bus control signal check module 503 sends the memory access request to a trigger module 504. When the trigger module 504 receives the memory access request, it triggers two data error detection modules 505 to respectively check the memory address to be accessed in the memory access request. When the memory address to be accessed passes the check, the trigger module 504 sends the memory access request to a static random access memory 506 corresponding to the memory address to be accessed. When the static random access memory 506 receives the memory access request, it stores the data to be stored in the memory access request, or reads the target data according to the memory access request.

[0085] Combined with Figure 6 As shown, an embodiment of the present disclosure provides a device for security protection, including a processor 600 and a memory 601. Optionally, the device may further include a communication interface 602 and a second bus 603. Among them, the processor 600, the communication interface 602, and the memory 601 can complete mutual communication through the second bus 603. The communication interface 602 can be used for information transmission. The processor 600 can call the logical instructions in the memory 601 to execute the method for security protection in the above embodiment.

[0086] The device for security protection provided by the embodiments of the present disclosure can achieve the following technical effects: When the bus control signal verification passes, trigger multiple data error detection modules to respectively obtain corresponding verification codes to be compared for the memory addresses to be accessed; and determine whether each data error detection module has a fault according to each verification code to be compared; then, when none of the data error detection modules has a fault, use any one of the verification codes to be compared to determine whether the memory address to be accessed passes the verification; and when the memory address to be accessed passes the verification, store the data to be stored in the memory access request into the target memory; or, trigger the target memory to read the target data according to the memory access request. In this way, it is possible to determine whether a data error detection module has a fault, and thus improve the security of accessing the memory.

[0087] In addition, when the logical instructions in the above-mentioned memory 601 are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium.

[0088] The memory 601, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as the program instructions / modules corresponding to the methods in the embodiments of the present disclosure. The processor 600 executes functional applications and data processing by running the program instructions / modules stored in the memory 601, that is, implements the method for security protection in the above embodiments.

[0089] The memory 601 may include a program storage area and a data storage area. Among them, the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory 601 may include high-speed random access memory and may also include non-volatile memory.

[0090] The embodiments of the present disclosure provide an electronic device including the above-mentioned device for security protection.

[0091] The electronic device for security protection provided by the embodiments of the present disclosure can achieve the following technical effects: When the bus control signal verification passes, trigger multiple data error detection modules to respectively obtain corresponding comparison check codes for the memory addresses to be accessed; and determine whether each data error detection module fails according to each comparison check code; then, when none of the data error detection modules fails, use any one of the comparison check codes to determine whether the memory address to be accessed passes the verification; and when the memory address to be accessed passes the verification, store the data to be stored in the memory access request into the target memory; or, trigger the target memory to read the target data according to the memory access request. In this way, it is possible to determine whether a data error detection module fails, and thus improve the security of accessing the memory.

[0092] Optionally, the electronic device includes a computer, a mobile phone or a tablet computer.

[0093] The embodiments of the present disclosure provide a storage medium storing program instructions, and when the program instructions are running, they execute the above-mentioned method for security protection.

[0094] The embodiments of the present disclosure provide a computer program product, the computer program product includes a computer program stored on a computer-readable storage medium, the computer program includes program instructions, and when the program instructions are executed by a computer, the computer is made to execute the above-mentioned method for security protection.

[0095] The above-mentioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transient computer-readable storage medium.

[0096] The technical solution of the embodiments of the present disclosure can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiments of the present disclosure. The foregoing storage medium may be a non-transient storage medium, including: various media such as a USB flash drive, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk, or an optical disc that can store program codes, or may also be a transient storage medium.

[0097] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure, enabling those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, process, and other changes. Embodiments merely represent possible variations. Unless explicitly required, individual components and functions are optional, and the order of operations may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terms used in this application are only for describing embodiments and do not limit the claims. As used in the description of the embodiments and the claims, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to also include the plural forms. Similarly, as used in this application, the term "and / or" refers to any and all possible combinations of one or more of the associated listed items. Additionally, when used in this application, the term "comprise" and its variants "comprises" and / or "comprising" etc. mean the presence of the stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, or apparatus comprising the element. Herein, each embodiment may focus on the differences from other embodiments, and the same or similar parts among the embodiments may be referred to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method parts disclosed in the embodiments, the relevant parts may refer to the description of the method parts.

[0098] Those skilled in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner may depend on the specific application and design constraints of the technical solution. The technician can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of the embodiments of the present disclosure. The technician can clearly understand that for the convenience and conciseness of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments, and will not be elaborated herein.

[0099] In the embodiments disclosed herein, the disclosed methods, products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units may be only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the shown or discussed couplings or direct couplings or communication connections to each other may be through some interfaces. The indirect couplings or communication connections of devices or units may be in electrical, mechanical, or other forms. The units described as separate components may or may not be physically separated. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to implement this embodiment. In addition, in the embodiments of the present disclosure, the various functional units may be integrated in one processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit.

[0100] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, and the module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description. Sometimes, there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. Each block in the block diagram and / or flowchart, as well as combinations of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system that performs the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A method for safety protection, characterized in that, Including: When receiving a memory access request sent by the bus, verifying the bus control signal in the memory access request; When the bus control signal passes the verification, triggering multiple data error detection modules to respectively obtain corresponding verification codes to be compared according to the memory address to be accessed in the memory access request; Determining whether each of the data error detection modules has a fault according to each of the verification codes to be compared; When it is determined that none of the data error detection modules has a fault, using any one of the verification codes to be compared to determine whether the memory address to be accessed passes the verification; When the memory address to be accessed passes the verification, storing the data to be stored in the memory access request into the target memory; Or, triggering the target memory to read target data according to the memory access request.

2. The method according to claim 1, wherein The memory access request includes a first parity check code corresponding to the bus control signal; verifying the bus control signal in the memory access request includes: Obtaining a second parity check code by using the bus control signal; Comparing the second parity check code with the first parity check code; When the second parity check code is the same as the first parity check code, determining that the bus control signal passes the verification; and / or, When the second parity check code is different from the first parity check code, determining that the bus control signal fails the verification.

3. The method according to claim 1, wherein The memory access request includes a target check code corresponding to the memory address to be accessed; using any one of the verification codes to be compared to determine whether the memory address to be accessed passes the verification includes: Comparing the target check code with the verification code to be compared; When the target check code is the same as the verification code to be compared, determining that the memory address to be accessed passes the verification; and / or, When the target check code is different from the verification code to be compared, determining that the memory address to be accessed fails the verification.

4. The method according to claim 1, wherein Before storing the data to be stored in the memory access request into the target memory, further including: Triggering the data error detection module to verify the data to be stored in the memory access request; When the data to be stored passes the verification, storing the data to be stored in the memory access request into the target memory.

5. The method according to claim 1, wherein Determining whether each of the data error detection modules has a fault according to each of the verification codes to be compared includes: When all of the verification codes to be compared are the same, determining that none of the data error detection modules has a fault; and / or, When there are differences among the verification codes to be compared, determining that each of the data error detection modules has a fault, and determining each of the data error detection modules as an alternative faulty data error detection module.

6. The method according to claim 5, characterized in that, After determining each of the data error detection modules as an alternative faulty data error detection module, further including: Send the detection verification code corresponding to the original data information and the detection data information obtained after injecting error data information into the first preset position of the original data information to each of the alternative fault data error detection modules, and trigger each of the alternative fault data error detection modules to respectively obtain corresponding detection comparison codes according to the detection data information; Determine whether the value to be compared in the second preset position of each of the detection comparison codes is the same as the target value in the third preset position of the detection verification code; Determine the alternative fault data error detection module corresponding to the value to be compared that is the same as the target value as the target fault data error detection module.

7. A device for safety protection, characterized in that, Comprising: A bus control signal verification module configured to verify the bus control signal in the memory access request when receiving the memory access request sent by the bus; A trigger module configured to trigger a plurality of data error detection modules to respectively obtain corresponding comparison verification codes according to the memory address to be accessed in the memory access request when the bus control signal verification passes; A first determination module configured to determine whether each of the data error detection modules has a fault according to each of the comparison verification codes; A second determination module configured to determine whether the memory address to be accessed passes the verification by using any one of the comparison verification codes when it is determined that none of the data error detection modules has a fault; A secure access module configured to store the data to be stored in the memory access request in the target memory when the memory address to be accessed passes the verification; Or, trigger the target memory to read target data according to the memory access request.

8. A device for safety protection, comprising a processor and a memory storing program instructions, characterized in that, The processor is configured to execute the method for security protection according to any one of claims 1 to 6 when running the program instructions.

9. An electronic device, characterized in that, Comprising the device for security protection according to claim 8.

10. A storage medium stores program instructions, characterized in that, When the program instructions are running, execute the method for security protection according to any one of claims 1 to 6.

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