A pre-packing method based on VPR

Through the VPR-based pre-boxing method, the FPGA packing failure caused by the primitives where the input or output pins are not connected to the CLB is solved, and the packing success rate is improved through packaging and rejudgment.

CN114329659BActive Publication Date: 2025-07-11SHANDONG XINHUI MICROELECTRONICS TECH CO LTD
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Patent Information

Application Number
CN202111530820.8
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2021-12-14
Publication Date
2025-07-11
Estimated Expiration
2041-12-14

AI Technical Summary

Technical Problem

In the prior art, the primitives whose input or output pins are not connected to the CLB lead to the problem of FPGA packing failure.

Method used

Through the VPR-based pre-boxing method, the primitives in the structure description file are read, and the primitives that meet the conditions are packaged into molecules according to custom constraints, and whether they are qualified is determined. If they fail, further judgment and repackage are made based on the input and output pins until all molecules can be connected to the external CLB.

Benefits of technology

It reduces the coupling between molecules, increases the degree of freedom of molecules when packing, and reduces the rate of packing failure.

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Abstract

The present invention relates to a pre-packing method based on VPR, and belongs to the field of electronic design automation technology. The method performs the following steps: 1) VPR reads the primitives that come with the system in the structure description file; 2) According to the custom constraints in the structure description file, the primitives that meet the custom constraints are packaged into molecules; 3) It is judged whether each molecule is qualified; 4) When all molecules are qualified molecules, the pre-packing is completed. The pre-packing algorithm of the present invention performs pre-packing processing, which can reduce the coupling between molecules, thereby increasing the degree of freedom of molecules when packing and reducing the failure rate during packing.
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Description

Technical Field

[0001] The present invention relates to a pre-packing method based on VPR, belonging to the technical field of electronic design automation. Background Technique

[0002] A Field Programmable Gate Array (FPGA) consists of several Configurable Logic Blocks (CLBs) and routing resources. The CLB contains the FPGA functional circuit units, which are controlled by programming points and can be configured into different logics. The basic logic units in the FPGA include Look Up Tables (LUTs), Multiplexers (MUXs), flip-flops, etc., and among the flip-flops, D Flip-Flops (DFFs) are the most common.

[0003] The CAD process of FPGA usually consists of multiple steps. The steps in the traditional process are synthesis, technology mapping, packaging, placement, and routing. The combination of these steps is called the implementation process, and the generated circuit is called the implementation design. When a user designs an actual circuit using an FPGA, the technology mapping step can be further divided into two processes: mapping and packing. The goal of the sub-step of mapping is to convert the basic gate-level netlist into a netlist composed of circuit functional elements such as LUTs, MUXs, and flip-flops. The goal of the packing sub-step is to combine circuit functional elements such as LUTs, MUXs, and flip-flops and place them in the same logic block as much as possible while considering constraints (such as the number of LUTs, different input signals, and clocks that can be accommodated in a logic block, etc.). The FPGA dedicated synthesis tool can directly synthesize the circuit netlist into the circuit netlist at the FPGA element level. Therefore, there is a partial overlap between technology mapping and logic synthesis in the mapping part. The technology mapping studied in this paper specifically refers to packing.

[0004] The research on FPGA packing mostly focuses on aspects such as the area, timing, or power consumption of the circuit after packing. Different from the commercial FPGA structure, academic research mostly adopts the BLE (Basic Logic Element) academic model. For the packing sub-step, the existing packing algorithm T-VPack can effectively handle the packing problem of logic blocks with a cluster structure composed of BLEs. Combining with the VPR (Versatile Place and Route) academic model platform, it provides an academic model solution. The T-VPack algorithm first pairs and packs the LUTs and DFFs in the user netlist processed by the mapping sub-step into BLEs one by one, and then packs multiple BLEs into a logic block with a cluster structure.

[0005] As a sub-step of boxing, FPGA pre-boxing is mainly used to pack primitives in pairs to reduce the amount of calculation during boxing. As the structure of FPGA becomes more and more complex, the structure of BLE also becomes more complex, and the types of primitives are also increasing. For primitives whose input or output pins are not connected to CLB, if they are boxed separately, the boxing will fail. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a pre-binning method for avoiding the situation where the input or output pins are not connected to the primitives of the CLB.

[0007] In order to solve the above technical problems, the technical solution proposed by the present invention is: a pre-packing method based on VPR, performing the following steps:

[0008] 1) VPR reads the system's own primitives in the structure description file;

[0009] 2) According to the custom constraints in the structure description file, the primitives that meet the custom constraints are packaged into molecules;

[0010] 3) Determine whether each molecule is qualified;

[0011] If qualified, the molecule completes the pre-packing;

[0012] If it fails, further judgment is made based on the input and output pins of the molecule, and the two connected failed molecules are packaged and judged again;

[0013] The judgment condition is that if some or all of the input and output pins are connected to the external CLB, the molecule is qualified, otherwise it is unqualified;

[0014] 4) When all molecules are qualified, the pre-packing is completed.

[0015] The beneficial effect of the present invention is that the pre-packing algorithm of the present invention performs pre-packing processing, which can reduce the coupling between molecules, thereby increasing the freedom of molecules during packing and reducing the failure rate during packing. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a flowchart of a VPR-based prepackaging method according to an embodiment of the present invention.

[0017] Figure 2 The present invention is a flowchart of a VPR-based prepacking method for determining whether a molecule is qualified.

[0018] Figure 3 This is one of the example diagrams of the embodiment of the present invention.

[0019] Figure 4 This is the second example diagram of the embodiment of the present invention. DETAILED DESCRIPTION Example

[0020] A VPR-based prepackaging method in this embodiment, such as Figure 1 As shown, perform the following steps:

[0021] 1) VPR reads the system's own primitives in the structure description file;

[0022] 2) According to the custom constraints in the structure description file, the primitives that meet the custom constraints are packaged into molecules;

[0023] 3) Determine whether each molecule is qualified;

[0024] If qualified, the molecule completes the pre-packing;

[0025] If it fails, further judgment is made based on the input and output pins of the molecule, and the two connected failed molecules are packaged and judged again;

[0026] The judgment condition is that if some or all of the input and output pins are connected to the external CLB, the molecule is qualified, otherwise it is unqualified;

[0027] 4) When all molecules are qualified, pre-packing is completed.

[0028] Use VPR to read the structure description file. After synthesis, the user-designed circuit generates a user netlist. Find all primitives in the netlist, where name represents LUT, LATCH represents trigger, SUBCKT represents custom primitive, and there are also default INPUT and OUTPUT primitives in VPR. After all primitives are found, you can prepare for pre-packaging.

[0029] Find custom constraints in the structure description file, where custom constraints are expressed as PACK_PATTERN, which instructs the CAD tool to group primitives (such as LUTs, FFs, carry chains) in certain netlists together during the CAD flow. This allows designers to help CAD tools identify structures with limited flexibility so that netlist atoms that fit into these structures are kept together as if they were a single unit. Find primitives in the user netlist that match the PACK_PATTERN and pack them.

[0030] Determine whether there are molecules in the netlist that have no wires that can connect to the external CLB, find the input and output pins of the molecule, and determine whether they are connected to the CLB pins through the structure description file. <complete> 、 <direct>or <mux>Connection: If a part or all of the input and output pins are connected to the external CLB, then this molecule is qualified; otherwise, it is unqualified. If the molecule has only input or only output pins, only the existing pins need to be judged.

[0031] Repackage the unqualified molecules, find the pins of the unqualified molecules that are not connected to the outside, find the molecules connected to the corresponding pins from the user netlist. If this molecule is also connected to the unqualified molecule in the structure description file, then repackage the two until the recombined molecule can be connected to the external pins of its corresponding CLB. If the input pins are not connected to the external CLB, find the atoms connected to the input pins in the structure description file and package them to judge whether they are qualified. If there is a problem with the connection of the output pins, find the atoms connected to the output pins. The flowchart is as Figure 3 shown.

[0032] Take Figure 3 and Figure 4 as an example. If there is only a structure as shown in Figure 3 in the general logic unit of the FPGA, VPR will first read the primitives in the structure description file and those provided by the system, including LUTs and FFs. Then, it will package the primitives in the netlist that conform to the PACK_PATTERN. If the LUTs and FFs are connected together through the PACK_PATTERN, the molecule they form meets the conditions, and the pre-packing of this molecule is completed. Otherwise, the present invention will find the molecules that do not meet the conditions, such as LUTs. Since the output of the LUT is not connected to the external pins of the CLB, the LUT cannot be used as a molecule for packing alone. Therefore, find the primitive connected to the output port of the LUT. After finding the LUT in the netlist, the following FF can be found. It can also be found from the structure description file that the primitive following the LUT is the FF. After packing the LUT and the FF into a molecule, the input and output of this molecule meet the conditions. Therefore, pack the LUT and the FF together to avoid packing errors.

[0033] If the general logic unit of the FPGA is as shown in Figure 4 As shown, VPR first reads the primitives in the structure description file and those provided by the system, and then packs the primitives in the netlist that conform to PACK_PATTERN. If OBUF and OUTPUT are connected together through PACK_PATTERN, the molecule they form meets the conditions, and the pre-packing of this molecule is completed. Otherwise, the present invention will find molecules that do not meet the conditions, such as OUTPUT. Since OUTPUT only has input pins, only need to pay attention to whether its input pins are connected to external IOBs. If not, then OUTPUT cannot be used as a molecule for packing alone. So find the primitives connected to the input port of OUTPUT, find the OBUF preceding OUTPUT in the netlist, which can also be found from the structure description file. Therefore, pack OBUF and OUTPUT into a molecule.

[0034] In actual use, if all the connectable molecules or atoms within the CLB are traversed and none of them can be packed into a qualified molecule, it indicates that there is a problem with the structure described in the structure description file and the pre-packing fails.

[0035] The present invention is not limited to the specific technical solutions described in the above embodiments. In addition to the above embodiments, the present invention can also have other implementation manners. For those skilled in the art, any technical solutions formed by making any modifications, equivalent replacements, improvements, etc. within the spirit and principle of the present invention shall be included within the protection scope of the present invention.< / mux> < / direct> < / complete>

Claims

1. A pre-packing method based on VPR, characterized in that Perform the following steps: 1) The VPR reads the primitives provided by the system in the structure description file; 2) According to the custom constraints in the structure description file, the primitives that meet the custom constraints are packed into molecules; 3) For each molecule, find the input and output pins of the molecule and determine whether it is connected to the CLB pins in the structure description file through <complete> 、 <direct>Or <mux>Connect. If some or all of the input and output pins are connected to the external CLB, then this molecule is qualified, otherwise it is unqualified; < / mux> < / direct> < / complete> If qualified, the molecule completes pre-packing; If unqualified, further judgment is made based on the input and output pins of the molecule, and the two connected unqualified molecules are packed and judged again; 4) When all molecules are qualified, pre-packing is completed.

Citation Information

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