Design method

Abstract

An embodiment of the present invention provides a design method, which is applied to a capacitor array composed of multiple preset capacitor units. The preset capacitor unit includes multiple unit capacitors, and the method includes: obtaining a unit simulation model of the preset capacitor unit; based on the arrangement mode of the preset capacitor units in the capacitor array and the unit simulation models of the respective preset capacitor units, obtaining a first simulation model of the capacitor array; based on the arrangement mode of the preset capacitor units, obtaining the arrangement direction of the preset capacitor units, and establishing a parasitic resistance equivalent test structure for a group of preset capacitor units in the same arrangement direction; based on the parasitic resistance equivalent test structure, obtaining the parasitic resistance of each preset capacitor unit; based on the parasitic resistance of each preset capacitor unit and the first simulation model, establishing a second simulation model characterizing the capacitor array; An embodiment of the present invention provides an accurate capacitor device model to improve the accuracy and reliability of the simulation results of semiconductor memories.

Description

Technical Field

[0001] The present invention relates to the field of memories, and particularly to a design method. Background Art

[0002] Semiconductor memories are indispensable components in modern electronic systems. A semiconductor memory is provided with a plurality of unit capacitors. The unit capacitors in the same row are coupled to the same word line structure, and the unit capacitors in the same column are coupled to the same bit line structure. The performance of the unit capacitors is crucial for the performance of the formed semiconductor memory.

[0003] Currently, for a designed semiconductor memory, circuit pre-simulation and layout post-simulation need to be performed to ensure the performance parameters of the formed semiconductor memory.

[0004] However, currently, the capacitance simulation model in a semiconductor memory is an inaccurate device model, resulting in large errors in the simulation results of the semiconductor memory. Summary of the Invention

[0005] An embodiment of the present invention provides a design method, which provides an accurate capacitor device model to improve the accuracy and reliability of the simulation results of a semiconductor memory.

[0006] To solve the above technical problems, an embodiment of the present invention provides a design method, which is applied to a capacitor array composed of a plurality of preset capacitor units. The preset capacitor units include a plurality of unit capacitors, and the method includes: obtaining a unit simulation model of the preset capacitor units, where the unit simulation model is used to characterize the capacitance value of the preset capacitor units; based on the arrangement manner of the preset capacitor units in the capacitor array and the unit simulation models of the preset capacitor units, obtaining a first simulation model of the capacitor array, where the first simulation model is used to characterize the capacitance values of the preset capacitor units in the capacitor array and the arrangement manner of the preset capacitor units; based on the arrangement manner of the preset capacitor units, obtaining the arrangement direction of the preset capacitor units, and establishing a parasitic resistance equivalent test structure for a group of preset capacitor units in the same arrangement direction; obtaining the parasitic resistance of each preset capacitor unit based on the parasitic resistance equivalent test structure; and establishing a second simulation model characterizing the capacitor array based on the parasitic resistance of each preset capacitor unit and the first simulation model.

[0007] Compared with the related art, by obtaining a first simulation model of a capacitor array, the first simulation model is used to characterize the capacitance value of a preset capacitor unit in the capacitor array and the arrangement manner of the preset capacitor units. Based on the arrangement manner of the preset capacitor units, a parasitic resistance equivalent test structure of the preset capacitor units is established to obtain the parasitic resistance of the preset capacitor units. Based on the parasitic resistance of each preset capacitor unit and the first simulation model, a second simulation model is obtained. The second simulation model combines the parasitic resistance of the preset capacitor units and the first simulation model. Since the performance influence brought by the parasitic resistance is considered in the newly designed simulation model, the accuracy and reliability of the simulation result of the semiconductor memory are improved.

[0008] In addition, a parasitic resistance equivalent test structure of a group of preset capacitor units in the same arrangement direction is established, including: establishing a wire layer, the wire layer being coupled to the lower electrode of the preset capacitor unit; establishing a conductive layer, the preset capacitor unit being arranged in the conductive layer, and the conductive layer serially coupling the upper electrodes of a group of preset capacitor units in the same arrangement direction to each other; based on the conductive layer and the wire layer, taking the wire layers of each preset capacitor unit in a group of preset capacitor units as endpoints respectively, a parasitic resistance equivalent test structure is obtained. A method for establishing a parasitic resistance equivalent test structure provided by the present invention.

[0009] In addition, the preset capacitor units in the capacitor array are distributed in a matrix.

[0010] In addition, based on the parasitic resistance equivalent test structure, the parasitic resistance of each preset capacitor unit is obtained, including: selecting one of the preset capacitor units as a target preset capacitor unit, using the preset interface of the conductive layer where the adjacent preset capacitor unit is located as a separation boundary to define the equivalent conductive layer of the preset capacitor unit; respectively obtaining the minimum distance between the boundary of the target preset capacitor unit and the boundary of its equivalent conductive layer; in the arrangement direction of the preset capacitor unit and in the direction perpendicular to the arrangement direction of the preset capacitor unit, obtaining the characteristic quantities of the capacitor units in the target preset capacitor unit, the characteristic quantities including the number of capacitor units, the spacing between capacitor units, and the line width of each capacitor unit; based on the minimum distance and the characteristic quantities, obtaining the parasitic resistance of the target preset capacitor unit; a specific method for calculating and obtaining the parasitic resistance of the preset capacitor unit based on the parasitic resistance equivalent test structure provided by the present invention.

[0011] In addition, respectively obtaining the minimum distance between the edge of the target preset capacitor unit and the edge of its equivalent conductive layer includes: obtaining the first-side minimum distance and the second-side minimum distance between the boundary of the target preset capacitor unit and the separation boundary, the first-side minimum distance being close to the endpoint and the second-side minimum distance being far from the endpoint; obtaining the minimum distance between the boundary of the target preset capacitor unit and the two-side boundaries of the equivalent conductive layer in the direction perpendicular to the arrangement direction of the preset capacitor unit.

[0012] In addition, based on the minimum distance and the characteristic quantity, the parasitic resistance of the target preset capacitor unit is obtained, including: obtaining the parasitic resistance of the target preset capacitor unit based on the following formula: R = Rtcp * (L_nc * nc / 2 + b / 2 + f - d) / (L_nr * nr + a + c - e); defining the arrangement direction of the preset capacitor unit as the X direction, and the Y direction is perpendicular to the arrangement direction of the preset capacitor unit; R is the parasitic resistance, Rtcp is the resistivity of the equivalent conductive layer; b is the minimum distance on the first side, f is the minimum distance on the second side; nc is the number of unit capacitors in the X direction, L_nc is the line width of the unit capacitors in the X direction, d is the spacing of the unit capacitors in the X direction; nr is the number of unit capacitors in the Y direction, L_nr is the line width of the unit capacitors in the Y direction, e is the spacing of the unit capacitors in the Y direction; a and c are respectively the minimum distances from the boundaries of the target preset capacitor unit in the Y direction to the boundaries of the capacitor array; the specific calculation method for calculating the preset capacitor unit given in the embodiments of the present invention.

[0013] In addition, the preset interface is the midline interface of the conductive layer where adjacent preset capacitor units are located; taking the midline interface of the conductive layer as the preset interface makes the obtained parasitic resistance of the preset capacitor unit more accurate.

[0014] In addition, multiple unit capacitors are distributed in a matrix.

[0015] In addition, obtaining the unit simulation model of the preset capacitor unit includes: obtaining the unit simulation model based on the number of unit capacitors in the preset capacitor unit and the ideal capacitance of the unit capacitor.

[0016] In addition, based on the parasitic resistance of each preset capacitor unit and the first simulation model, a second simulation model representing the capacitor array is established, including: connecting the parasitic resistances corresponding to each preset capacitor unit in series in the first simulation model to obtain the second simulation model. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] One or more embodiments are illustrated by way of example in the accompanying drawings, and unless otherwise stated, the figures in the drawings do not constitute a scale limitation.

[0018] Figure 1 It is a schematic structural diagram of the capacitor array provided by the embodiments of the present invention;

[0019] Figure 2 It is a schematic flow diagram of the design method provided by the embodiments of the present invention;

[0020] Figure 3 It is a schematic structural diagram of the first simulation model provided by the embodiments of the present invention;

[0021] Figure 4 It is a schematic structural diagram of the parasitic resistance equivalent test structure provided by the embodiments of the present invention;

[0022] Figure 5 This is a schematic structural diagram of a capacitor array used to calculate parasitic resistance in an embodiment of the present invention;

[0023] Figure 6 This is a schematic parameter diagram of a capacitor array used to calculate parasitic resistance in an embodiment of the present invention;

[0024] Figure 7 This is a schematic structural diagram of a second simulation model provided by an embodiment of the present invention. Detailed implementation manners

[0025] Currently, the capacitor simulation model in semiconductor memories is an inaccurate device model, resulting in large errors in the simulation results of semiconductor memories.

[0026] An embodiment of the present invention provides an accurate capacitor device model to improve the accuracy and reliability of the simulation results of semiconductor memories.

[0027] To solve the above problems, an embodiment of the present invention provides a design method, which is applied to a capacitor array composed of multiple preset capacitor units. The preset capacitor units include multiple unit capacitors, and the method includes: obtaining a unit simulation model of the preset capacitor unit, where the unit simulation model is used to characterize the capacitance value of the preset capacitor unit; based on the arrangement manner of the preset capacitor units in the capacitor array and the unit simulation models of the respective preset capacitor units, obtaining a first simulation model of the capacitor array, where the first simulation model is used to characterize the capacitance values of the respective preset capacitor units in the capacitor array and the arrangement manner of the preset capacitor units; based on the arrangement manner of the preset capacitor units, obtaining the arrangement direction of the preset capacitor units, and establishing a parasitic resistance equivalent test structure for a group of preset capacitor units in the same arrangement direction; based on the parasitic resistance equivalent test structure, obtaining the parasitic resistance of each preset capacitor unit; and based on the parasitic resistance of each preset capacitor unit and the first simulation model, establishing a second simulation model characterizing the capacitor array.

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will elaborate on the embodiments of the present invention with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present invention, many technical details are provided to help readers better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented. The following division of each embodiment is for convenience of description and should not constitute any limitation on the specific implementation manner of the present invention. The various embodiments can be combined with each other and cross-referenced under the premise of not conflicting with each other.

[0029] This embodiment is applied to a capacitor array composed of multiple preset capacitor units, and each preset capacitor unit includes multiple unit capacitors.

[0030] In one example, referring to Figure 1 , the unit capacitors 203 are distributed in a matrix. Specifically, a matrix array of 3 columns and 3 rows is formed to constitute a preset capacitor unit 202. The preset capacitor unit 202 couples the unit capacitors 203 into a whole through the conductive layer 201; the preset capacitor units 202 are distributed in a matrix. Specifically, a matrix array of 6 columns and 5 rows is formed to constitute a capacitor array 200. The capacitor array 200 couples the preset capacitor units 202 into a whole through the conductive layer 201. The conductive wire 204 is connected to the lower electrode of the preset capacitor unit 202 and is used to simulate the capacitor array 200 as a whole capacitor.

[0031] In this embodiment, referring to Figure 5 , the unit capacitors 203 are distributed in a matrix. Specifically, a matrix array of 3 columns and 3 rows is formed to constitute a preset capacitor unit 202. The preset capacitor unit 202 couples the unit capacitors 203 into a whole through the conductive layer 201; the capacitor array 200 includes two preset capacitor units 202. The capacitor array 200 couples the preset capacitor units 202 into a whole through the conductive layer 201. The conductive wire 204 is connected to the lower electrode of the preset capacitor unit 202 and is used to simulate the capacitor array 200 as a whole capacitor.

[0032] It should be noted that in this embodiment, the unit capacitors 203 distributed in a matrix form the preset capacitor unit 202, and the preset capacitor units 202 distributed in a matrix form the capacitor array 200, which is only an introduction to the capacitor array 200 and the preset capacitor unit 202, and does not constitute a limitation on the capacitor array 200 and the preset capacitor unit 202. Based on a specific structure, the specific calculation method of the design method in this embodiment is described to facilitate those skilled in the art to understand the implementation manner of this embodiment. In specific applications, a corresponding first simulation model can be established according to the actual arrangement of the unit capacitors 203 and the preset capacitor units 202.

[0033] Figure 2 FIG. is a schematic flowchart of the design method provided by the embodiment of the present invention. The design method of this embodiment will be specifically described below.

[0034] Referring to Figure 2 and combining with Figure 5 , the design method includes:

[0035] Step 101, obtain the unit simulation model of the preset capacitor unit 202.

[0036] Obtain the unit simulation model of the preset capacitor unit 202, where the unit simulation model is used to characterize the capacitance value of the preset capacitor unit 202. Specifically, based on the number of unit capacitors 203 in the preset capacitor unit 202 and the ideal capacitance of the unit capacitor 203, obtain the unit simulation model.

[0037] In this embodiment, referring to Figure 5 , one preset capacitor unit 202 includes 9 unit capacitors, and the capacitance values of the 9 unit capacitors 203 are the same. The unit simulation model is used to characterize that the capacitance value of one preset capacitor unit 202 is 9 times the ideal capacitance of the unit capacitor 203; in other embodiments, if the capacitance values of the 9 unit capacitors are different, the unit simulation model is used to characterize that the capacitance value of one preset capacitor unit 202 is the sum of the ideal capacitances of the 9 unit capacitors.

[0038] Step 102, obtain the first simulation model of the capacitor array.

[0039] Based on the arrangement mode of the preset capacitor units 202 in the capacitor array 200 and the unit simulation models of the respective preset capacitor units 202, obtain the first simulation model of the capacitor array 200. The first simulation model is used to characterize the capacitance values of the respective preset capacitor units 202 in the capacitor array 200 and the arrangement mode of the preset capacitor units 202.

[0040] Specifically, according to the arrangement mode of the preset capacitor units 202 in the capacitor array 200, obtain the connection relationships of the respective preset capacitor units 202. Based on the connection relationships of the respective preset capacitor units 202 and the unit simulation models of the preset capacitor units 202, obtain the first simulation model of the capacitor array 200.

[0041] Referring to Figures 3 to 6 , in this embodiment, taking the capacitor array 200 composed of two preset capacitor units 202 as an example to establish the first simulation model and the second simulation model. It should be noted that the capacitor array 200 composed of two preset capacitor units 202 is only an example for establishing the first simulation model and the second simulation model in this embodiment, and does not constitute a limitation to this embodiment. In other embodiments, the first simulation model and the second simulation model can be established according to the number of preset capacitor units in the actual capacitor array.

[0042] In this embodiment, define the arrangement direction of the preset capacitor unit 202 as the X direction, and the Y direction is perpendicular to the arrangement direction of the preset capacitor unit 202.

[0043] Specifically, referring to Figure 3, obtain the unit simulation models of each preset capacitor unit 202 in the capacitor array 200, and connect the unit simulation models of two preset capacitor units 202 in series to form the first simulation model of the capacitor array 200. The first simulation model includes a first preset capacitor unit Cap1 and a second preset capacitor unit Cap2. The first preset capacitor unit Cap1 is used to represent the capacitance value of the first preset capacitor unit, and the second preset capacitor unit Cap2 is used to represent the capacitance value of the second preset capacitor unit.

[0044] It should be noted that in other embodiments, if the preset capacitor units in the capacitor array are arranged in multiple rows and columns, it is necessary to determine the arrangement direction of the preset capacitors according to the connection direction of the conductive wires, that is, to determine the X direction and the Y direction. In the X direction, the unit simulation models of the preset capacitor units are connected in series and coupled; in the Y direction, the simulation models of the preset capacitor units are connected in parallel and coupled.

[0045] Continue to refer to Figure 2 , step 103, establish an equivalent test structure for the parasitic resistance of the preset capacitor unit.

[0046] Based on the arrangement mode of the preset capacitor units 202, obtain the arrangement direction of the preset capacitor units 202, that is, the X direction, and establish an equivalent test structure for the parasitic resistance of a group of preset capacitor units 202 in the same arrangement direction, that is, establish an equivalent test structure for the parasitic resistance of a group of preset capacitor units 202 in the X direction.

[0047] Specifically, refer to Figure 4 and Figure 5 , establish a conductive wire layer 204. The conductive wire layer 204 is coupled to the lower electrode 206 of the preset capacitor unit 202. In this embodiment, the conductive layer 204 is coupled to the lower electrode 206 of the preset capacitor unit 202 through a bottom conductive layer 207. The bottom conductive layer 207 is the capacitor contact pad (landing pad) structure in the memory used to change the arrangement mode of the unit capacitors.

[0048] Establish a conductive layer 201. The preset capacitor units 202 are arranged in the conductive layer 201, and the conductive layer 201 serially couples the upper electrodes 205 of a group of preset capacitor units 202 in the same arrangement direction to each other.

[0049] Refer to Figure 4 , it should be noted that in a specific capacitor structure, there is also a capacitor dielectric layer between the upper electrode 205 and the lower electrode 206. However, the capacitor dielectric layer has no relation to the inventive content of this embodiment, so it is not marked in the drawings. Those skilled in the art are aware that if it is a complete capacitor structure, there is also a capacitor dielectric layer between the upper electrode 205 and the lower electrode 206.

[0050] Based on the conductive layer 201 and the wire layer 204, taking the wire layer 204 of each preset capacitor unit 202 in a group of preset capacitor units 202 as endpoints respectively, a parasitic resistance equivalent test structure is obtained.

[0051] Continue to refer to Figure 2 , step 104, to obtain the parasitic resistance of each preset capacitor unit.

[0052] Based on the parasitic resistance equivalent test structure, the parasitic resistance of the preset capacitor unit 202 is obtained.

[0053] Specifically, refer to Figure 5 , in the capacitor array 200, one of the preset capacitor units 202 is selected as the target preset capacitor unit, and the preset interface of the conductive layer 201 where the adjacent preset capacitor unit 202 is located is used as the separation interface (shown as the dotted line in the figure) to define the equivalent conductive layer of the preset capacitor unit 202.

[0054] It should be noted that if the number of a group of preset capacitor units 202 in the X direction is greater than or equal to 3, then except for the two preset capacitor units 202 at the edges, the remaining preset capacitor units 2020 define the equivalent conductive layer through the separation interfaces on both sides. For the equivalent conductive layers on both edges, the equivalent conductive layer is defined by one of the separation interfaces and the edge of the conductive layer 201.

[0055] In this embodiment, the preset interface is the midline interface of the conductive layer 201 where the adjacent preset capacitor unit 202 is located. Taking the midline interface of the conductive layer 201 as the preset interface makes the obtained parasitic resistance of the preset capacitor unit 202 more accurate.

[0056] Refer to Figure 6 , this embodiment takes the left preset capacitor unit 202 as the target preset capacitor unit as an example for specific introduction.

[0057] Based on the arrangement direction of the preset capacitor unit 202, that is, based on the X direction, the minimum distance between the boundary of the target preset capacitor unit and the boundary of its equivalent conductive layer is obtained respectively.

[0058] In the arrangement direction of the preset capacitor unit 202, the first minimum distance b and the second minimum distance f between the boundary of the target preset capacitor unit and the separation boundary are obtained. The first minimum distance b is close to the left endpoint A, and the second minimum distance is far from the left endpoint A. In this embodiment, since this embodiment takes the capacitor array 200 composed of two preset capacitor units 202 as an example for specific introduction, there is no separation boundary on the side of the target preset capacitor unit close to the endpoint A, but the boundary of the equivalent conductive layer. At this time, the boundary of the equivalent conductive layer is used as the separation boundary to obtain the first minimum distance b.

[0059] Based on the direction perpendicular to the arrangement direction of the preset capacitor unit 202, that is, based on the Y direction, obtain the minimum distance between the boundary of the target preset capacitor unit and the boundary of the equivalent conductive layer.

[0060] In the direction perpendicular to the arrangement direction of the preset capacitor unit 202, obtain the first minimum distance a between the upper boundary of the target preset capacitor unit and the upper boundary of the equivalent conductive layer, and obtain the second minimum distance b between the lower boundary of the target preset capacitor unit and the lower boundary of the equivalent conductive layer.

[0061] In the arrangement direction of the preset capacitor unit 202 and in the direction perpendicular to the arrangement direction of the preset capacitor unit 202, obtain the characteristic quantities of the capacitor units in the target preset capacitor unit, where the characteristic quantities include the number of capacitor units, the distance between capacitor units, and the line width of capacitor units.

[0062] Specifically, refer to Figure 6 , the characteristic quantities include nc, L_nc, nr, L_nr, d, and e.

[0063] Among them, nc is the number of unit capacitors in the X direction, L_nc is the line width of the unit capacitors in the X direction, and d is the distance between the unit capacitors in the X direction; nr is the number of unit capacitors in the Y direction, L_nr is the line width of the unit capacitors in the Y direction, and e is the distance between the unit capacitors in the Y direction.

[0064] Based on the minimum distance and the characteristic quantities, obtain the parasitic resistance R of the target preset capacitor unit.

[0065] Specifically, obtain the parasitic resistance of the target preset capacitor unit based on the following formula:

[0066] R = R tcp *(L_nc * nc / 2 + b / 2 + f - d) / (L_nr * nr + a + c - e);

[0067] Among them, R is the parasitic resistance, and R tcp is the resistivity of the equivalent conductive layer, that is, the circuit rate of the conductive layer 201; b is the first side minimum distance, f is the second side minimum distance; nc is the number of unit capacitors in the X direction, L_nc is the line width of the unit capacitors in the X direction, and d is the distance between the unit capacitors in the X direction; nr is the number of unit capacitors in the Y direction, L_nr is the line width of the unit capacitors in the Y direction, and e is the distance between the unit capacitors in the Y direction; a and c are respectively the minimum distances between the boundaries of the target preset capacitor unit in the Y direction and the boundaries of the capacitor array.

[0068] Based on the minimum distances defined in the X and Y directions and the characteristic quantities, the formula for obtaining the parasitic capacitance R is made applicable to the capacitor array 200 in any arrangement. In the capacitor array 200 in any arrangement, since there are only two wire layers 204, the parasitic resistance equivalent test structure is determined through the wire layers 204, thereby determining the X and Y directions, ensuring that there is only one X direction and one Y direction in the capacitor array 200, and thus ensuring the applicability of the formula for obtaining the parasitic capacitance R.

[0069] Repeat the above steps to obtain the parasitic resistance of each preset capacitor unit 202 in the capacitor array 200, and construct a second simulation model of the capacitor array 200.

[0070] Continue to refer to Figure 2 , step 105, to establish a second simulation model representing the capacitor array.

[0071] Based on the parasitic resistances of the respective preset capacitor units 202 and the first simulation model, establish a second simulation model representing the capacitor array.

[0072] Specifically, each preset capacitor unit 202 in the first simulation model is serially coupled with the corresponding parasitic resistance to obtain the second simulation model.

[0073] Refer to Figure 7 , based on Figure 3 the obtained first simulation model, the first simulation model includes a first preset capacitor unit Cap1 and a second preset capacitor unit Cap2. The first resistor R1 is the parasitic resistance obtained by the first preset capacitor unit Cap1 according to the calculation in step 104, and the second resistor R2 is the parasitic resistance obtained by the second preset capacitor unit Cap2 according to the calculation in step 104. The first preset capacitor Cap1 is serially coupled with the first resistor R1, and the second preset capacitor unit Cap2 is serially coupled with the second resistor R2 to form the second simulation model. The second simulation model takes into account the performance impact of the parasitic resistance of the preset capacitor unit 202 on the formed memory, improving the accuracy and reliability of the simulation results of the semiconductor memory.

[0074] Compared with the related technology, by obtaining the first simulation model of the capacitor array, the first simulation model is used to characterize the capacitance value of the preset capacitor unit in the capacitor array and the arrangement of the preset capacitor units. Based on the arrangement of the preset capacitor units, a parasitic resistance equivalent test structure of the preset capacitor unit is established to obtain the parasitic resistance of the preset capacitor unit. Based on the parasitic resistances of the respective preset capacitor units and the first simulation model, a second simulation model is obtained. The second simulation model combines the parasitic resistance of the preset capacitor unit and the first simulation model. Since the newly designed simulation model takes into account the performance impact brought by the parasitic resistance, the accuracy and reliability of the simulation results of the semiconductor memory are improved.

[0075] The above division of various steps is only for clear description. When implemented, they can be combined into one step or some steps can be split into multiple steps. As long as the same logical relationship is included, it is within the protection scope of this patent; making insignificant modifications to the process or introducing insignificant designs, but without changing the core design of the process, are all within the protection scope of this patent.

[0076] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present invention. In actual applications, various changes can be made to them in form and details without departing from the spirit and scope of the present invention.

Claims

1. A design method is applied to a capacitor array composed of multiple preset capacitor units, and the preset capacitor unit includes multiple unit capacitors. Characterized in that, It includes: Obtain the unit simulation model of the preset capacitor unit, and the unit simulation model is used to characterize the capacitance value of the preset capacitor unit; Based on the arrangement mode of the preset capacitor units in the capacitor array and the unit simulation models of the preset capacitor units, obtain the first simulation model of the capacitor array, and the first simulation model is used to characterize the capacitance values of the preset capacitor units in the capacitor array and the arrangement mode of the preset capacitor units; Based on the arrangement mode of the preset capacitor units, obtain the arrangement direction of the preset capacitor units, and establish a parasitic resistance equivalent test structure for a group of the preset capacitor units in the same arrangement direction; Based on the parasitic resistance equivalent test structure, obtain the parasitic resistance of each preset capacitor unit; Based on the parasitic resistance of each preset capacitor unit and the first simulation model, establish a second simulation model characterizing the capacitor array.

2. The design method according to claim 1, Characterized in that, The parasitic resistance equivalent test structure for a group of the preset capacitor units in the same arrangement direction includes: Establish a wire layer, and the wire layer is coupled to the lower electrode of the preset capacitor unit; Establish a conductive layer, the preset capacitor unit is arranged in the conductive layer, and the conductive layer serially couples the upper electrodes of a group of the preset capacitor units in the same arrangement direction to each other; Based on the wire layer and the conductive layer, take the wire layers of the preset capacitor units in the group as endpoints respectively to obtain the parasitic resistance equivalent test structure.

3. The design method according to claim 2, Characterized in that, The preset capacitor units in the capacitor array are distributed in a matrix.

4. The design method according to claim 3, Characterized in that, Based on the parasitic resistance equivalent test structure, obtaining the parasitic resistance of each preset capacitor unit includes: Select one of the preset capacitor units as the target preset capacitor unit, and define the equivalent conductive layer of the preset capacitor unit with the preset interface of the conductive layer where the adjacent preset capacitor unit is located as the separation boundary; Respectively obtain the minimum distance between the boundary of the target preset capacitor unit and the boundary of its equivalent conductive layer; In the arrangement direction of the preset capacitor unit and perpendicular to the arrangement direction of the preset capacitor unit, obtain the characteristic quantities of the capacitor units in the target preset capacitor unit, and the characteristic quantities include the number of the capacitor units, the distance between the capacitor units and the line width of each capacitor unit; Based on the minimum distance and the characteristic quantities, obtain the parasitic resistance of the target preset capacitor unit.

5. The design method according to claim 4, Characterized in that, The respectively obtaining the minimum distance between the edge of the target preset capacitor unit and the edge of its equivalent conductive layer includes: Obtain the minimum distance from the boundary of the target preset capacitor unit to the first side of the separation boundary and the minimum distance to the second side of the separation boundary, where the first side is close to the end point of the target preset capacitor unit and the second side is far from the end point of the target preset capacitor unit; Obtain the minimum distance from the boundary of the target preset capacitor unit to the two side boundaries of the equivalent conductive layer in the direction perpendicular to the arrangement direction of the preset capacitor unit.

6. According to the design method described in claim 5, wherein, the obtaining of the parasitic resistance of the target preset capacitor unit based on the minimum distance and the characteristic quantity includes: Obtain the parasitic resistance of the target preset capacitor unit based on the following formula: R = Rtcp * (L_nc * nc / 2 + b / 2 + f - d) / (L_nr * nr + a + c - e); Define the arrangement direction of the preset capacitor unit as the X direction, and the Y direction is perpendicular to the arrangement direction of the preset capacitor unit; R is the parasitic resistance, and Rtcp is the resistivity of the equivalent conductive layer; b is the minimum distance of the first side, and f is the minimum distance of the second side; nc is the number of unit capacitors in the X direction, L_nc is the line width of the unit capacitors in the X direction, and d is the spacing of the unit capacitors in the X direction; nr is the number of unit capacitors in the Y direction, L_nr is the line width of the unit capacitors in the Y direction, and e is the spacing of the unit capacitors in the Y direction; a and c are respectively the minimum distances from the boundary of the target preset capacitor unit in the Y direction to the boundary of the capacitor array.

7. According to the design method described in claim 4, wherein, the preset interface is the midline interface of the conductive layer where adjacent preset capacitor units are located.

8. According to the design method described in claim 1, wherein, the multiple unit capacitors are distributed in a matrix.

9. According to the design method described in claim 1, wherein, the obtaining of the unit simulation model of the preset capacitor unit includes: Obtain the unit simulation model based on the number of unit capacitors in the preset capacitor unit and the ideal capacitance of the unit capacitors.

10. According to the design method described in claim 1, wherein, establishing a second simulation model representing the capacitor array based on the parasitic resistance of each preset capacitor unit and the first simulation model includes: Connecting the parasitic resistances corresponding to each preset capacitor unit in series in the first simulation model to obtain the second simulation model.

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