A path determination method, device and terminal device

Abstract

The embodiment of the present invention discloses a path determination method, device and terminal device, which can determine that certain paths between ICG and registers have high power consumption risks, so that the design strategy can be adjusted in advance before the long clock tree to optimize the chip design. It includes: determining M paths from the first integrated clock gate ICG to the M registers driven by the first ICG; determining the distance values ​​of the M paths; according to the distance values ​​of the M paths, determining N high power consumption risk paths from the M paths, where M is greater than or equal to 2 and N is less than or equal to M.

Description

Technical Field

[0001] The present invention relates to the field of audio technology, and in particular to a path determination method, device and terminal equipment. Background Art

[0002] Currently, an integrated clock gate (ICG) can be added before the clock input of the register. This method can make the register have no clock when it does not need to flip, thereby reducing the power consumption of the chip. The synthesis tool (i.e., a chip synthesis software for designing chips) can determine which registers are controlled by an integrated clock gate through an internal algorithm. However, since the result obtained by the synthesis tool does not have a long clock tree, there is no method to measure the power consumption of the clock tree in the synthesis stage (i.e., the stage of using the synthesis tool to design the chip). When the clock tree is long at the back end, the synthesis tool will make the paths from the ICG to all registers as long as possible. At this time, if the distance from the ICG to a register it drives is very long, the synthesis tool will insert an extra buffer (i.e., buffer memory) between the ICG and the register to make the paths of all registers the same length, which will cause unnecessary power consumption, making the power consumption of some paths between the designed ICG and the registers higher. Summary of the invention

[0003] The embodiments of the present invention provide a path determination method, apparatus and terminal device, which can determine that certain paths between ICG and registers have high power consumption risks, so that the design strategy can be adjusted in advance before the long clock tree to optimize the chip design and avoid the occurrence of high power consumption paths.

[0004] In order to solve the above technical problems, the embodiment of the present invention is implemented as follows:

[0005] In a first aspect, an embodiment of the present invention provides a path determination method, including:

[0006] Determine M paths from the first integrated clock gate ICG to the M registers driven by the first ICG;

[0007] Determine the distance values ​​of M paths;

[0008] According to the distance values ​​of the M paths, N high power consumption risk paths are determined from the M paths, where M is greater than or equal to 2 and N is less than or equal to M.

[0009] In a second aspect, a path determination device is provided, comprising:

[0010] A processing module, configured to determine M paths from a first integrated clock gate ICG to M registers driven by the first ICG;

[0011] Determine the distance values ​​of M paths;

[0012] According to the distance values ​​of the M paths, N high power consumption risk paths are determined from the M paths, where M is greater than or equal to 2 and N is less than or equal to M.

[0013] In a third aspect, a terminal device is provided, comprising: a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein when the computer program is executed by the processor, the path determination method of the first aspect is implemented.

[0014] In a fourth aspect, a terminal device is provided, comprising: a path determination device as in the second aspect.

[0015] In a sixth aspect, a computer-readable storage medium is provided, comprising: a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the path determination method of the first aspect is implemented.

[0016] In an embodiment of the present invention, M paths from a first ICG to M registers driven by the first ICG can be determined; the distance values ​​of the M paths can be determined; and according to the distance values ​​of the M paths, N high power consumption risk paths can be determined from the M paths, where M is greater than or equal to 2 and N is less than or equal to M. Through this solution, between long clock trees, according to the distance values ​​of the M paths from the first integrated clock gate ICG to the M registers driven by the first ICG, N high power consumption risk paths can be determined, so that the design strategy can be adjusted in advance to optimize the chip design and avoid the occurrence of high power consumption paths. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments and the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and other drawings can be obtained based on these drawings.

[0018] Figure 1 FIG. 1 is a schematic diagram of a path determination method provided by an embodiment of the present invention. Figure 1 ;

[0019] Figure 2 FIG. 1 is a schematic diagram of an ICG driving register provided by an embodiment of the present invention;

[0020] Figure 3 FIG. 1 is a schematic diagram of calculating the distance value from ICG to DFF provided by an embodiment of the present invention;

[0021] Figure 4 FIG. 1 is a schematic diagram of a group of ICG clock trees provided by an embodiment of the present invention;

[0022] Figure 5 FIG. 1 is a schematic diagram of a path determination method provided by an embodiment of the present invention. Figure 2 ;

[0023] Figure 6 FIG. 1 is a schematic diagram of dividing an ICG and a corresponding register into different Bounds provided by an embodiment of the present invention;

[0024] Figure 7 FIG. 1 is a schematic diagram of a path determination method provided by an embodiment of the present invention. Figure 2 ;

[0025] Figure 8 Shown is a schematic diagram of the hardware structure of a terminal device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] In the embodiments of the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete way. In addition, in the description of the embodiments of the present invention, unless otherwise specified, the meaning of "multiple" refers to two or more.

[0028] The term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0029] Usually, a synthesis tool (i.e., a chip synthesis software for designing chips) can be installed in a computer, and the chip design can be performed through the synthesis tool installed in the computer. The synthesis tool can add an ICG before the clock input of the register (digital flip flop, DFF). In this way, the register does not have a clock when it does not need to flip, which can reduce the power consumption of the chip. The synthesis tool can determine which registers are controlled by an ICG through an internal algorithm. However, since the result obtained by the synthesis tool does not have a long clock tree, there is no method to measure the power consumption of the clock tree in the synthesis stage. When the clock tree is grown at the back end, the synthesis tool will make the path from the ICG to all registers as long as possible. At this time, if the distance from the ICG to a register driven by it is very long, the synthesis tool will insert an extra buffer memory between the ICG and the register it drives to make the path of all registers the same length, which will cause unnecessary power consumption. Therefore, the existing technology can only see whether the original path design between the ICG and the register it drives is reasonable after the clock tree is grown at the back end.

[0030] Currently, as a user, no matter which synthesis tool is used, you can only set an estimated value for the ICG clock path delay to let the synthesis tool optimize the ICG path.

[0031] The synthesis tool may also consider the fanout of the ICG and adopt methods such as cloning the clock_gate to handle registers that are too far away.

[0032] In the above solution, the synthesis tool in the synthesis stage considers ICG more based on function and timing considerations, and has no foresight on the power consumption of the ICG clock tree. This may cause the backend to find that the power consumption is too high after the clock tree is grown, and then perform multiple iterations based on power consumption optimization, which increases the complexity of chip design.

[0033] Furthermore, since the synthesis tool determines which registers are driven by ICG based on the content algorithm, it will only provide timing reports and fanout parameters to the user, or the synthesis tool will consider using the ICG clone method to handle registers that are too far away. However, the synthesis tool cannot provide a quantitative indicator to help determine whether the insertion of ICG is reasonable and whether there is a risk in power consumption.

[0034] In order to solve the above problems, an embodiment of the present invention also provides a path determination method, a path determination device and a terminal device, which can be used for chip design. The technical solution can determine that certain paths between ICG and registers have high power consumption risks, so that the design strategy can be adjusted in advance before the long clock tree to optimize the chip design.

[0035] In the embodiment of the present invention, the path determination device may be a terminal device, or a functional module or functional entity in the terminal device.

[0036] The terminal devices in the embodiments of the present invention may include: tablet computers, laptop computers, ultra-mobile personal computers (UMPCs), handheld computers, netbooks, personal digital assistants (PDAs), and the like. The embodiments of the present application do not impose any special restrictions on the specific form of the terminal devices.

[0037] Optionally, in an embodiment of the present invention, a synthesis tool (i.e., a chip synthesis software for designing chips) may be installed in a terminal device, and the path determination method in an embodiment of the present invention may be implemented in the synthesis stage of chip design through the synthesis tool.

[0038] Figure 1 FIG. 1 is a schematic diagram of a path determination method provided in an embodiment of the present invention. Exemplarily, the execution subject of the method may be a terminal device, or a functional module or functional entity in the terminal device. In the following embodiments, the terminal device is used as the execution subject for exemplary description.

[0039] The following is a detailed description of this method. Figure 1 As shown, the method includes:

[0040] 101. Determine M paths from a first ICG to M registers driven by the first ICG.

[0041] Wherein, M is greater than or equal to 2.

[0042] Usually, when designing a chip, one ICG drives multiple registers, so that a path is formed between the one ICG and each register, thereby forming multiple paths.

[0043] Optionally, a synthesis tool in the terminal device may count all M registers driven by the first ICG.

[0044] 102. Determine the distance values ​​of the M paths.

[0045] For example, Figure 2 FIG. 1 is a schematic diagram of an ICG driving register. An ICG drives a group of registers, including register DFF1, register DFF2, and register DFF3, etc., and the distances between these registers and the ICG are different.

[0046] Further, combined with Figure 2 ,like Figure 3As shown, it is a schematic diagram of calculating the distance value from ICG to DFF, wherein the distance value distance1 from ICG to DFF1, the distance value distance2 from ICG to DFF2, and the distance value distance3 from ICG to DFF3 can be calculated.

[0047] The technical idea of ​​the present invention is: after the synthesis tool completes the synthesis, all registers driven by each ICG are counted, and the distance from the ICG to each register it drives is calculated. An ICG drives a group of registers, and their distances to the ICG are not the same. The distance from the ICG to each register is counted, and these distance parameters are used as parameters to measure the power consumption of the clock tree of this group of ICGs.

[0048] The basic principle of the technical idea of ​​the present invention is as follows Figure 4 As shown, Figure 4 This is a diagram of an ICG clock tree. The farther the ICG is from the register it drives, the more buffer memory is needed between the ICG and the register. Figure 4 This means that more power consumption will be incurred on this clock path.

[0049] 103. According to the distance values ​​of the M paths, N high power consumption risk paths are determined from the M paths.

[0050] Wherein, N is less than or equal to M.

[0051] In the embodiment of the present invention, the high power consumption risk path refers to a path with higher power consumption after a long clock tree.

[0052] In an optional implementation manner, the above 103 may be implemented by the following steps:

[0053] 1031. Compare the distance values ​​of the M paths with preset distance values ​​respectively to determine N high power consumption risk paths from the M paths.

[0054] 1032. The distance values ​​of the N high power consumption risk paths are greater than a preset distance value.

[0055] Assume that there are three paths, including path 1, path 2 and path 3. The distance values ​​corresponding to these three paths are D1, D2 and D3 respectively. The preset distance value is Y. Then D1 can be compared with Y respectively. If D1 is greater than Y, path 1 is determined to be a high power consumption risk path; D2 is compared with Y. If D2 is greater than Y, path 2 is determined to be a high power consumption risk path; D3 is compared with Y. If D3 is greater than Y, path 3 is determined to be a high power consumption risk path.

[0056] In the above optional implementation, by comparing the distance value of each path with a preset distance value, a path with a distance value greater than the preset distance value can be determined as a high power consumption risk path.

[0057] In another optional implementation manner, the above 103 can be implemented by the following steps:

[0058] 1033. Determine the distance value of the shortest path among the M paths.

[0059] 1034. Calculate the difference between the distance values ​​of M-1 paths other than the shortest path among the M paths and the distance value of the shortest path to obtain M-1 distance differences.

[0060] 1035. Compare the M-1 distance differences with the preset differences respectively to determine N high power consumption risk paths from the M-1 paths.

[0061] When the distance difference is greater than the preset difference, it can be determined that the path corresponding to the distance difference is a high power consumption risk path.

[0062] In the above optional implementation, the difference between the distance value of the path and the distance of the shortest path is compared with a preset difference, and the corresponding path with a distance difference greater than the preset difference is determined as a high power consumption risk path.

[0063] Exemplarily, there are three paths, including path 1, path 2 and path 3. The distance values ​​corresponding to these three paths are D1, D2 and D3 respectively. Assuming that path 3 is the shortest path, that is, D3 is the minimum value, then the difference Da between D1 and D3 and the difference Db between D2 and D3 can be calculated. Then Da and Db can be compared with the preset differences respectively. When Da is greater than the preset difference, it is determined that path 1 corresponding to Da is a high power consumption risk path; when Db is greater than the preset difference, it is determined that path 2 corresponding to Db is a high power consumption risk path.

[0064] 1036. The distance difference corresponding to the N high power consumption risk paths is greater than a preset difference.

[0065] Optionally, in an embodiment of the present invention, after the above 103, an analysis report may be output, the analysis report including information indicating that N of the M paths are high power consumption risk paths. In this way, the user can check the analysis report to know that N of the M paths are high power consumption risk paths, thereby improving the comprehensive strategy in chip design.

[0066] In an embodiment of the present invention, M paths from a first ICG to M registers driven by the first ICG can be determined; the distance values ​​of the M paths can be determined; and according to the distance values ​​of the M paths, N high power consumption risk paths can be determined from the M paths, where M is greater than or equal to 2 and N is less than or equal to M. Through this solution, between long clock trees, according to the distance values ​​of the M paths from the first integrated clock gate ICG to the M registers driven by the first ICG, N paths can be determined to be high power consumption risk paths, and these paths may have high power consumption after the long clock tree, so that the design strategy can be adjusted in advance to optimize the chip design and avoid the occurrence of high power consumption paths.

[0067] Figure 5 FIG. 1 is a schematic diagram of a path determination method provided by an embodiment of the present invention, the method comprising:

[0068] 501. Determine M paths from a first ICG to M registers driven by the first ICG.

[0069] 502. Determine distance values ​​of M paths.

[0070] 503. Determine N high power consumption risk paths from the M paths according to the distance values ​​of the M paths.

[0071] For the description of 501 to 503, please refer to the relevant description of 101 to 103 above, which will not be repeated here.

[0072] 504. Determine N registers in N high power consumption risk paths.

[0073] 505. Set the first ICG and the N registers in different partitions so that the first ICG does not drive the N registers.

[0074] Optionally, K registers other than the N registers among the M registers may be set in the same partition as the first ICG, so that the first ICG drives the K registers.

[0075] Further, the N registers and the second ICG may be arranged in the same partition, so that the second ICG drives the N registers.

[0076] In the embodiment of the present invention, the synthesis strategy can be improved accordingly according to the statistical results of the determined high power consumption risk paths, such as by placing the ICG and the corresponding register in the high-risk path in different partitions (i.e. bound), so that the synthesis tool cannot use the ICG to drive the corresponding register. Thus, the high power consumption risk path can be eliminated from the root, thereby achieving the purpose of optimizing the power consumption of the clock tree in the synthesis stage.

[0077] For example, Figure 6 As shown, it is a schematic diagram of dividing the ICG and the corresponding register into different partitions (Bound). Assuming that when the first ICG drives the register DFF2, the path between the first ICG and DFF2 is a high power consumption risk path, then the first ICG and the corresponding DFF2 can be set in different partitions, wherein the first ICG is in partition 1 (i.e. Bound1), and the synthesis tool will not use the first ICG to drive DFF2, and the second ICG and DFF2 are in the same partition 2 (i.e. Bound2). In this way, such a high power consumption risk path (i.e. the path between the first ICG and DFF2) is eliminated from the root, thereby achieving the purpose of optimizing the power consumption of the clock tree in the synthesis stage.

[0078] like Figure 7 As shown, an embodiment of the present invention provides a path determination device, the device comprising:

[0079] The processing module 701 is used to determine M paths from the first ICG to the M registers driven by the first ICG;

[0080] Determine the distance values ​​of M paths;

[0081] According to the distance values ​​of the M paths, N high power consumption risk paths are determined from the M paths, where M is greater than or equal to 2 and N is less than or equal to M.

[0082] Optionally, the processing module 701 is specifically configured to compare the distance values ​​of the M paths with preset distance values ​​respectively, so as to determine N high power consumption risk paths from the M paths;

[0083] The distance values ​​of the N high power consumption risk paths are greater than the preset distance value.

[0084] Optionally, the processing module 701 is specifically configured to determine a distance value of the shortest path among the M paths;

[0085] Calculate the distance values ​​of M-1 paths other than the shortest path among the M paths, and the difference between the distance value of the shortest path to obtain M-1 distance differences;

[0086] The M-1 distance differences are compared with the preset differences respectively to determine N high power consumption risk paths from the M-1 paths;

[0087] The distance differences corresponding to the N high power consumption risk paths are greater than the preset difference.

[0088] Optionally, the processing module 701 is further configured to determine N registers in the N high power consumption risk paths after N high power consumption risk paths are determined from the M paths;

[0089] The first ICG and the N registers are arranged in different partitions so that the first ICG does not drive the N registers.

[0090] Optionally, the processing module 701 is further configured to, after determining N high power consumption risk paths from the M paths, set K registers other than the N registers among the M registers in the same partition as the first ICG, so that the first ICG drives the K registers;

[0091] The N registers are arranged in the same partition as the second ICG, so that the second ICG drives the N registers.

[0092] Optionally, the processing module 701 is further used to output an analysis report after determining N high power consumption risk paths from the M paths according to the distance values ​​of the M paths, wherein the analysis report includes information indicating that N paths among the M paths are high power consumption risk paths.

[0093] like Figure 8 The figure shows a schematic diagram of the hardware structure of a terminal device provided by an embodiment of the present invention. The terminal device may include: a radio frequency (RF) circuit 810, a memory 820, an input unit 830, a display unit 840, a sensor 850, an audio circuit 860, a wireless fidelity (WiFi) module 870, a processor 880, and a power supply 890. Among them, the RF circuit 810 includes a receiver 811 and a transmitter 812. Those skilled in the art can understand that Figure 8 The terminal device structure shown in the figure does not constitute a limitation on the terminal device, and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0094] The RF circuit 810 can be used for receiving and sending signals during information transmission or calls. In particular, after receiving the downlink information of the base station, it is sent to the processor 880 for processing; in addition, the designed uplink data is sent to the base station. Generally, the RF circuit 810 includes but is not limited to an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier (LNA), a duplexer, etc. In addition, the RF circuit 810 can also communicate with the network and other devices through wireless communication. The above wireless communication can use any communication standard or protocol, including but not limited to the global system of mobile communication (GSM), general packet radio service (GPRS), code division multiple access (CDMA), wideband code division multiple access (WCDMA), long term evolution (LTE), email, short messaging service (SMS), etc.

[0095] The memory 820 can be used to store software programs and modules. The processor 880 executes various functional applications and data processing of the terminal device by running the software programs and modules stored in the memory 820. The memory 820 can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc.; the data storage area can store data created according to the use of the terminal device (such as audio data, a phone book, etc.), etc. In addition, the memory 820 can include a high-speed random access memory, and can also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0096] The input unit 830 can be used to receive input digital or character information, and to generate key signal input related to the user settings and function control of the terminal device. Specifically, the input unit 830 may include a touch panel 831 and other input devices 832. The touch panel 831, also known as a touch screen, can collect the user's touch operation on or near it (such as the user's operation on the touch panel 831 or near the touch panel 831 using any suitable object or accessory such as a finger, stylus, etc.), and drive the corresponding connection device according to a pre-set program. Optionally, the touch panel 831 may include two parts: a touch detection device and a touch controller. Among them, the touch detection device detects the user's touch orientation, detects the signal brought by the touch operation, and transmits the signal to the touch controller; the touch controller receives the touch information from the touch detection device, converts it into contact coordinates, and then sends it to the processor 880, and can receive and execute commands sent by the processor 880. In addition, the touch panel 831 can be implemented in various types such as resistive, capacitive, infrared, and surface acoustic waves. In addition to the touch panel 831, the input unit 830 may also include other input devices 832. Specifically, the other input devices 832 may include but are not limited to one or more of a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, a joystick, etc.

[0097] The display unit 840 can be used to display information input by the user or information provided to the user and various menus of the terminal device. The display unit 840 may include a display panel 841. Optionally, the display panel 841 may be configured in the form of a liquid crystal display (LCD), an organic light-emitting diode (OLED), etc. Further, the touch panel 831 may cover the display panel 841. When the touch panel 831 detects a touch operation on or near it, it is transmitted to the processor 880 to determine the type of touch event. Subsequently, the processor 880 provides a corresponding visual output on the display panel 841 according to the type of touch event. Although in Figure 8 In the embodiment, the touch panel 831 and the display panel 841 are used as two independent components to implement the input and output functions of the terminal device, but in some embodiments, the touch panel 831 and the display panel 841 can be integrated to implement the input and output functions of the terminal device.

[0098] The terminal device may also include at least one sensor 850, such as a light sensor, a motion sensor, and other sensors. Specifically, the light sensor may include an ambient light sensor and a proximity sensor, wherein the ambient light sensor may adjust the brightness of the display panel 841 according to the brightness of the ambient light, and the proximity sensor may turn off the display panel 841 and / or the backlight when the terminal device is moved to the ear. As a type of motion sensor, the accelerometer sensor can detect the magnitude of acceleration in each direction (generally three axes), and can detect the magnitude and direction of gravity when stationary. It can be used for applications that identify the posture of the terminal device (such as horizontal and vertical screen switching, related games, magnetometer posture calibration), vibration recognition related functions (such as pedometer, tapping), etc.; as for other sensors that can be configured in the terminal device, such as gyroscopes, barometers, hygrometers, thermometers, infrared sensors, etc., they will not be repeated here.

[0099] The audio circuit 860, the speaker 861, and the microphone 862 can provide an audio interface between the user and the terminal device. The audio circuit 860 can transmit the received audio data to the speaker 861 after converting the received audio data into an electrical signal, which is converted into a sound signal for output; on the other hand, the microphone 862 converts the collected sound signal into an electrical signal, which is received by the audio circuit 860 and converted into audio data, and then the audio data is output to the processor 880 for processing, and then sent to another terminal device through the RF circuit 810, or the audio data is output to the memory 820 for further processing.

[0100] WiFi is a short-range wireless transmission technology. The terminal device can help users send and receive emails, browse web pages and access streaming media through the WiFi module 870. It provides users with wireless broadband Internet access. Figure 8 A WiFi module 870 is shown, but it is understandable that it is not a necessary component of the terminal device and can be omitted as needed without changing the essence of the invention.

[0101] The processor 880 is the control center of the terminal device. It uses various interfaces and lines to connect various parts of the entire mobile phone. By running or executing software programs and / or modules stored in the memory 820, and calling data stored in the memory 820, it executes various functions of the mobile phone and processes data, thereby monitoring the mobile phone as a whole. Optionally, the processor 880 may include one or more processing units; preferably, the processor 880 may integrate an application processor and a modem processor, wherein the application processor mainly processes the operating system, user interface, and application programs, and the modem processor mainly processes wireless communications. It is understandable that the above-mentioned modem processor may not be integrated into the processor 880.

[0102] The terminal device also includes a power supply 890 (such as a battery) for supplying power to each component. Preferably, the power supply can be logically connected to the processor 880 through a power management system, so that the power management system can manage charging, discharging, and power consumption management. Although not shown, the mobile phone can also include a camera, a Bluetooth module, etc., which will not be repeated here.

[0103] Although not shown, the terminal device may also include other functional modules, which will not be described in detail here.

[0104] In an embodiment of the present invention, the processor 880 is used to determine M paths from the first ICG to the M registers driven by the first ICG; determine distance values ​​of the M paths; and determine N high power consumption risk paths from the M paths based on the distance values ​​of the M paths, where M is greater than or equal to 2 and N is less than or equal to M.

[0105] Optionally, the processor 880 is specifically configured to compare the distance values ​​of the M paths with preset distance values ​​respectively, so as to determine N high power consumption risk paths from the M paths;

[0106] The distance values ​​of the N high power consumption risk paths are greater than the preset distance value.

[0107] Optionally, the processor 880 is specifically configured to determine a distance value of the shortest path among the M paths;

[0108] Calculate the distance values ​​of M-1 paths other than the shortest path among the M paths, and the difference between the distance value of the shortest path to obtain M-1 distance differences;

[0109] The M-1 distance differences are compared with the preset differences respectively to determine N high power consumption risk paths from the M-1 paths;

[0110] The distance differences corresponding to the N high power consumption risk paths are greater than the preset difference.

[0111] Optionally, the processor 880 is further configured to determine N registers in the N high power consumption risk paths after determining N high power consumption risk paths from the M paths;

[0112] The first ICG and the N registers are arranged in different partitions so that the first ICG does not drive the N registers.

[0113] Optionally, the processor 880 is further configured to, after determining N high power consumption risk paths from the M paths, set K registers other than the N registers among the M registers in the same partition as the first ICG, so that the first ICG drives the K registers;

[0114] The N registers are arranged in the same partition as the second ICG, so that the second ICG drives the N registers.

[0115] Optionally, the processor 880 is further used to output an analysis report after determining N high power consumption risk paths from the M paths based on the distance values ​​of the M paths, wherein the analysis report includes information indicating that N paths among the M paths are high power consumption risk paths.

[0116] An embodiment of the present invention further provides a path determination system, which can implement the path determination method in the above method embodiment.

[0117] An embodiment of the present invention further provides a computer-readable storage medium, including: a computer program stored on the computer-readable storage medium, and when the computer program is executed by a processor, the path determination method in the above method embodiment is implemented.

[0118] In order to make the technical personnel in the technical field better understand the scheme of the present invention, the technical scheme in the embodiment of the present invention will be described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all the embodiments. Based on the embodiments in the present invention, they should all belong to the scope of protection of the present invention.

[0119] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0120] In the several embodiments provided by the present invention, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0121] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0122] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0123] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0124] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A path determination method, characterized in that: include: Determine M paths from a first integrated clock gate ICG to M registers driven by the first ICG before the long clock tree; Determine the distance values ​​of the M paths; According to the distance values ​​of the M paths, N high power consumption risk paths are determined from the M paths to adjust the chip design strategy, wherein M is greater than or equal to 2 and N is less than or equal to M; Determine N registers in N high power consumption risk paths; The first ICG and the N registers are arranged in different partitions so that the first ICG does not drive the N registers; Setting K registers of the M registers, except the N registers, and the first ICG in the same partition so that the first ICG drives the K registers; The N registers and a second ICG are arranged in a same partition so that the second ICG drives the N registers.

2. The method according to claim 1, characterized in that The determining N high power consumption risk paths from the M paths according to the distance values ​​of the M paths includes: Comparing the distance values ​​of the M paths with preset distance values ​​respectively, so as to determine N high power consumption risk paths from the M paths; The distance values ​​of the N high power consumption risk paths are greater than the preset distance value.

3. The method according to claim 1, characterized in that The determining N high power consumption risk paths from the M paths according to the distance values ​​of the M paths includes: Determine the distance value of the shortest path among the M paths; Calculate the difference between the distance values ​​of M-1 paths among the M paths except the shortest path and the distance value of the shortest path to obtain M-1 distance differences; Comparing the M-1 distance differences with preset differences respectively, so as to determine N high power consumption risk paths from the M-1 paths; The distance difference corresponding to the N high power consumption risk paths is greater than the preset difference.

4. The method according to any one of claims 1 to 3, characterized in that: After determining N high power consumption risk paths from the M paths according to the distance values ​​of the M paths, the method further includes: An analysis report is output, wherein the analysis report includes information indicating that N paths among the M paths are high power consumption risk paths.

5. A path determination device, characterized in that: include: A processing module, configured to determine, before the long clock tree, M paths from a first ICG to M registers driven by the first ICG; Determine the distance values ​​of the M paths; According to the distance values ​​of the M paths, N high power consumption risk paths are determined from the M paths to adjust the chip design strategy, wherein M is greater than or equal to 2 and N is less than or equal to M; The processing module is further used to determine N registers in N high power consumption risk paths; The first ICG and the N registers are arranged in different partitions so that the first ICG does not drive the N registers; Setting K registers of the M registers, except the N registers, and the first ICG in the same partition so that the first ICG drives the K registers; The N registers and a second ICG are arranged in a same partition so that the second ICG drives the N registers.

6. A terminal device, characterized in that: It comprises the path determination device as described in claim 5.

7. A terminal device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program implements the path determination method according to any one of claims 1 to 4 when executed by the processor.

8. A computer-readable storage medium, characterized in that: include: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the path determination method according to any one of claims 1 to 4 is implemented.

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