Storage Devices

Abstract

The present invention provides a storage device, comprising a storage cell array and a voltage generating circuit. The voltage generating circuit is electrically connected to the storage cell array and comprises an active voltage circuit and a sensing circuit. The active voltage circuit is used to output an operating voltage to the storage cell array when the storage device is in an active mode. The sensing circuit is used to sense the operating voltage when the storage device is in a standby mode and to temporarily activate the active voltage circuit to pull up the operating voltage after the operating voltage drops below a critical value.

Description

Technical Field

[0001] The present invention relates to an electronic circuit, and in particular to a storage device. Background Art

[0002] With the development of electronic technology, non-volatile storage that can provide long-term and large-scale data storage has become the main data storage medium, among which flash memory is one of the mainstream storage devices. In order to improve the energy efficiency of electronic devices, flash memory not only enables electronic devices to have an active mode when accessing data, but also has a low-power standby mode.

[0003] However, in order for the flash memory to switch from the standby mode back to the active mode quickly, in the standby mode, the voltage generator circuit still needs to work to provide a high voltage to the word line coupled to the memory array.

[0004] In order to save power, the flash memory circuit is usually equipped with two voltage generating circuits for the active mode and the standby mode, wherein the voltage generating circuit for the standby mode has lower power consumption. In this way, although the power consumption of the flash memory can be reduced, the additional voltage generating circuit causes the storage circuit area to increase and the number of electronic components required to be used to increase. Summary of the invention

[0005] In view of this, the present invention provides a storage device having the advantages of reduced circuit area, simplified circuit components and reduced standby current.

[0006] An embodiment of the present invention provides a memory device, comprising a memory array and a voltage generating circuit. The voltage generating circuit is electrically connected to the memory cell array and comprises an active voltage circuit and a sensing circuit. The active voltage circuit is used to output an operating voltage to the memory cell array when the memory device is in an active mode. The sensing circuit is used to sense the operating voltage when the memory device is in a standby mode and to temporarily activate the active voltage circuit to pull up the operating voltage after the operating voltage drops below a critical value.

[0007] Based on the above, the memory device provided in the embodiment of the present invention has a sensing circuit to detect the change of the operating voltage in the standby mode. Whenever the operating voltage drops below the critical value, the sensing circuit briefly activates the active voltage circuit to pull up the operating voltage. Therefore, the circuit of the above memory device can be simplified, and the circuit area can be reduced.

[0008] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1is a schematic diagram of a storage device according to an embodiment of the present invention;

[0010] Figure 2 is a circuit diagram of a voltage generating circuit according to an embodiment of the present invention;

[0011] Figure 3 FIG. 4 is a schematic diagram of signal waveforms of a voltage generating circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0012] Figure 1 is a schematic diagram of a storage device according to an embodiment of the present invention. Figure 1 , the memory device 100 may be a NOR flash memory, but the present invention is not limited thereto. The memory device 100 at least includes a memory cell array 102, a controller 104, and a voltage generating circuit 106. The controller 104 is electrically connected to the memory cell array 102 and the voltage generating circuit 106. The controller 104 may control the memory cell array 102 to execute an active mode or a standby mode. The voltage generating circuit 106 provides an operating voltage to the word line of the memory cell array 102 according to the active mode or the standby mode. The memory device 100 may also include a memory cell array 102, which is not shown in FIG. Figure 1 The word line decoding circuit, bit line decoding circuit, driving circuit and sensing amplifier circuit, etc., those skilled in the art should be able to understand the configuration relationship and implementation methods between the above components.

[0013] Figure 2 is a circuit diagram of a voltage generating circuit according to an embodiment of the present invention. Figure 2 , Figure 2 The circuit structure of can be used to illustrate the voltage generating circuit 106. The voltage generating circuit 106 includes an active voltage circuit 110 and a sensing circuit 120. The active voltage circuit 110 is used to output the operating voltage RV to the memory cell array 102 when the memory device 100 is in the active mode. The operating voltage RV is taken as a read voltage here. When the memory device 100 is in the standby mode, the active voltage circuit 110 will also output the operating voltage RV, but the difference is that the active voltage circuit 110 is continuously in an enabled state in the active mode to stably output the operating voltage RV, but the active voltage circuit 110 is only intermittently in the enabled state in the standby mode, so that power can be saved. In the standby mode, the sensing circuit 120 senses the operating voltage RV and briefly activates the active voltage circuit 110 to pull up the operating voltage RV after the operating voltage RV drops below a critical value.

[0014] The active voltage circuit 110 includes a charge pump 112 and a voltage regulator 114. The charge pump 112 is electrically connected to the voltage regulator 114. The charge pump 112 outputs an operating voltage RV, and the voltage regulator 114 is used to maintain the voltage value of the operating voltage RV.

[0015] Figure 2 The voltage regulating circuit 114 includes a high-voltage switch HVSW, a transistor T, a voltage divider circuit 116 including a plurality of resistors and at least one transistor, a bandgap reference circuit BGR, and a voltage comparison amplifier 118. The high-voltage switch HVSW is coupled between the output terminal of the active voltage circuit 110 and the control terminal of the transistor T. The transistor T and the voltage divider circuit 116 are connected in series between the output terminal of the active voltage circuit 110 and ground. The voltage comparison amplifier 118 receives the output signal of the bandgap reference circuit BGR and the divided voltage of the voltage divider circuit 116 to output a boost enable signal EN_PUMP. The charge pump 112 boosts the operating voltage RV according to the boost enable signal EN_PUMP.

[0016] It is explained here that the voltage regulating circuit 114 Figure 2 The circuit architecture is only an example, and the present invention does not limit the implementation of the voltage regulating circuit 114.

[0017] The sensing circuit 120 includes a capacitor C, a sensing transistor DT, a start transistor AT, and a switch transistor ST. One end of the capacitor C is coupled to the output end of the active voltage circuit 110 to receive the operating voltage RV, and the other end is coupled to a sensing node D. One end of the sensing transistor DT receives the reference voltage VDD through the transistor P1, the other end is coupled to the reaction node A, and the control end is coupled to the sensing node D. In other words, the voltage at one end of the capacitor C is the operating voltage RV, and the other end is coupled to the control end of the sensing transistor DT, so that during the sensing period, the voltage on the sensing node D changes with the operating voltage RV, and when the operating voltage RV is lower than the critical value, the sensing transistor is turned on and the sensing period ends.

[0018] One end of the start transistor AT receives the reference voltage VDD through the transistor P2, the other end is coupled to the reaction node A, and the control end is coupled to the sensing node D. One end of the switch transistor ST is coupled to the sensing node D, the other end is coupled to the reaction node A, and the control end thereof receives the control signal PG0 together with the control end of the transistor P2. In the present embodiment, the sensing transistor DT, the start transistor AT, the switch transistor ST, the transistor P1 and the transistor P2 are all PMOS transistors, but are not limited thereto.

[0019] After the sensing period ends, the sensing circuit 120 enters the startup period. During the startup period, the switch transistor ST is turned on to correspondingly turn on the startup transistor AT and cut off the sensing transistor DT, and the active voltage circuit 110 is also activated to pull the operating voltage RV back to the target voltage value.

[0020] The sensing circuit 120 further includes a discharge switch 122 and a pull-down circuit 124. One end of the discharge switch 122 is coupled to the reaction node A, and the other end is grounded, wherein the discharge switch 122 is turned on during the startup period to output the leakage current, and is turned off during the sensing period. One end of the pull-down circuit 124 is coupled to the reaction node A, and the other end is grounded, wherein the pull-down circuit 124 is turned off during the startup period and turned on during the sensing period to pull down the voltage of the reaction node A.

[0021] Specifically, in the present embodiment, the discharge switch 122 includes a transistor NB and a transistor N0. The transistor NB and the transistor N0 are connected in series between the reaction node A and the ground, wherein the control terminals of the transistor NB and the transistor N0 receive the control signal NBIAS and the control signal NG0 respectively. Those skilled in the art can determine the current magnitude of the leakage current by selecting an appropriate transistor NB. The pull-down circuit 124 of the present embodiment is implemented with a single transistor. The control terminal of the pull-down circuit 124 receives the control signal NG1. The transistor NB, the transistor N0 and the pull-down circuit 124 are all NMOS transistors here, but are not limited thereto.

[0022] Figure 3 FIG. 4 is a schematic diagram of signal waveforms of a voltage generating circuit according to an embodiment of the present invention. Figure 3 The signal waveform diagram is suitable for Figure 1 and 2 In the embodiment, the following collocation Figure 2 Reference Figure 3 The implementation method will be described.

[0023] The period between time point t1 and time point t2 is a sensing period DETECT. At time point t1, the operating voltage RV has been boosted to the target voltage value V0 by the charge pump 112. During the sensing period DETECT, the active voltage circuit 110 is not started, that is, in a disabled state, so the operating voltage RV gradually starts to decrease. The sensing circuit 120 monitors the change of the operating voltage RV.

[0024] In addition, during the sensing period DETECT, the switch transistor ST, the start transistor AT, the transistor P2, the discharge switch 122 and the pull-down circuit 124 are in the off state. The capacitor C couples the operating voltage RV to the sensing node D, so the voltage of the sensing node D changes with the operating voltage RV. At the beginning (time point t1), the sensing transistor DT is in the off state. The absolute value of the threshold voltage of the sensing transistor DT is represented by Vth1. At time point t2, the voltage of the sensing node D drops below VDD-Vth1, so the sensing transistor DT is turned on, which also means that the operating voltage RV is lower than a critical value at this moment.

[0025] Between time t2 and time t3, the voltage of the reaction node A is pulled up by the reference voltage VDD through the sensing transistor DT and the transistor P1. The switch transistor ST, the start transistor AT, the transistor P2, the discharge switch 122 and the pull-down circuit 124 are all still in the off state at this time.

[0026] The time period between time point t3 and time point t4 is the start-up period ACT. During the start-up period ACT, the voltage of the corresponding reaction node A rises, the control signal PG0, the control signal NBIAS and the control signal NG0 are all switched to the enabled state, and the switch transistor ST, the transistor P2 and the discharge switch 122 are turned on. The pull-down circuit 124 still maintains the cut-off state. Since the switch transistor ST is turned on, the reaction node A and the sensing node D have a common potential, and the start-up transistor AT and the sensing transistor DT are connected in the form of a diode connection. The absolute value of the threshold voltage of the start-up transistor AT is represented by Vth2. It is particularly noted that the absolute value Vth1 of the threshold voltage of the sensing transistor DT of the present embodiment is greater than the absolute value Vth2 of the threshold voltage of the start-up transistor AT, so the start-up transistor AT is turned on, and the sensing transistor DT is not turned on. The voltage of the reaction node A and the sensing node D is maintained at the start-up voltage VDD-Vth2 by the start-up transistor AT. At the same time, the discharge switch 122 allows the reaction node A to output leakage current to the ground.

[0027] During the startup period ACT, the reaction node A outputs an enable signal EN through the inverter INV. The enable signal EN is used to start the active voltage circuit 110, such as the charge pump 112 and the voltage divider circuit 116, the voltage comparison amplifier 118 and the bandgap reference circuit BGR in the voltage regulation circuit 114. The voltage regulation circuit 114 is activated to play a voltage stabilization role. The voltage comparison amplifier 118 outputs a boost enable signal EN_PUMP to enable the charge pump 112 to pull the operating voltage RV back to the target voltage value V0. In other words, by starting the transistor AT, the voltage of the reaction node A and the sensing node D is changed to the startup voltage VDD-Vth2 to start the active voltage circuit 110.

[0028] In short, the operating voltage RV starts to decay from the target voltage value V0. When the operating voltage RV is lower than the critical value, the active voltage circuit 110 raises the operating voltage RV back to the target voltage value V0. The ripple size of the operating voltage RV is determined by the difference ΔVth between the threshold voltages of the sensing transistor DT and the start-up transistor AT, where ΔVth=Vth1-Vth2. The critical value is V0-ΔVth.

[0029] The sensing period DETECT returns to the time point t4 and the time point t5. At the beginning of the sensing period DETECT (time point t4), the discharge switch 122 is turned off and the pull-down circuit 124 is turned on in the initial period In. Figure 3 The initial period In represents the enabling period of the control signal NG1. The initial period In is shorter than the sensing period DETECT. The discharge switch 122 pulls the voltage of the reaction node A down to the ground during the initial period In to initialize the voltage of the reaction node A. After the initial period In, the discharge switch 122 is turned off again.

[0030] When the operating voltage RV rises to be substantially equal to the target voltage value V0 (time point t4), the control signal PG0, the control signal NBIAS and the control signal NG0 are switched back to the disabled state, so that the discharge switch 122 is turned off, and the switch transistor ST, the transistor P2 and the discharge switch 122 are also switched to the cut-off state. Then, the above implementation of the sensing period DETECT and the activation period ACT is repeated. Whether to re-enter the activation period ACT to activate the active voltage circuit 110 is determined by whether the sensing transistor DT is turned on or not.

[0031] It is particularly noted that the activation period ACT is shorter than the sensing period DETECT. In addition, the on-time of the sensing transistor DT is also very short, which is also shorter than the sensing period DETECT.

[0032] In the standby mode, since the sensing circuit 120 only briefly activates the active voltage circuit 110, and the active voltage circuit 110 is not activated for most of the time, the overall power consumption is not too much, and the power saving requirement can be achieved. In addition, the sensing circuit 120 does not need to have circuit components with higher power consumption such as a voltage comparison amplifier or a charge pump, nor does it need to have a voltage divider circuit composed of multiple resistors, so it has the advantages of reducing the standby current and reducing the circuit area.

[0033] In summary, an embodiment of the present invention provides a storage device. The above storage device does not need to configure a low-power voltage generating circuit for the standby mode, but can achieve the effect of low-power output operation voltage by intermittently starting the voltage generating circuit in the active mode through the sensing circuit, so that the original voltage generating circuit can also be applied to the standby mode. The storage device of the embodiment of the present invention has the advantages of reducing the circuit area, simplifying the circuit components and reducing the standby current.

[0034] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the following claims.

Claims

1. A storage device, comprising: A memory cell array; as well as A voltage generating circuit is electrically connected to the memory cell array and includes: an active voltage circuit for outputting an operating voltage to the memory cell array when the memory device is in an active mode; and A sensing circuit is used to sense the operating voltage when the storage device is in a standby mode and to briefly activate the active voltage circuit to pull up the operating voltage after the operating voltage drops below a critical value, wherein the sensing circuit comprises: a capacitor having one end coupled to the output end of the active voltage circuit and the other end coupled to the sensing node; and A sensing transistor, one end of which is used to receive a reference voltage, the other end of which is coupled to a reaction node, and a control end of which is coupled to the sensing node. In the sensing period, the voltage on the sensing node varies with the operating voltage, and when the operating voltage is lower than the critical value, the sensing transistor is turned on.

2. The memory device according to claim 1, wherein the sensing circuit comprises: A start-up transistor, one end of which is used to receive the reference voltage, the other end of which is coupled to the reaction node, and the control end of which is coupled to the sensing node; A switch transistor, one end of which is coupled to the sensing node, and the other end of which is coupled to the reaction node, In the startup period, the switch transistor is turned on to correspondingly turn on the startup transistor and turn off the sensing transistor, and the active voltage circuit is activated to pull the operating voltage back to the target voltage value. 3 . The memory device according to claim 2 , wherein an absolute value of a threshold voltage of the sensing transistor is greater than an absolute value of a threshold voltage of the start-up transistor.

4. The memory device according to claim 2, wherein during the startup period, the voltages of the reaction node and the sensing node are changed to a startup voltage through the startup transistor to start the active voltage circuit, and during the sensing period, the active voltage circuit is not started.

5. The memory device according to claim 2, wherein the sensing circuit further comprises: a discharge switch, one end of which is coupled to the reaction node and the other end of which is grounded, wherein the discharge switch is turned on during the startup period to output the leakage current and is turned off during the sensing period; as well as A pull-down circuit has one end coupled to the reaction node and the other end grounded, wherein the pull-down circuit is disconnected during the startup period and turned on during the sensing period to pull down the voltage of the reaction node. 6 . The memory device according to claim 5 , wherein at the beginning of the sensing period, the discharge switch is turned off and the pull-down circuit is turned on during an initial period, wherein the initial period is shorter than the sensing period. The memory device according to claim 2 , wherein the activation period is shorter than the sensing period. 8 . The memory device according to claim 2 , wherein when the memory device is in the standby mode, a ripple size of the operating voltage is determined by a difference between a threshold voltage of the sensing transistor and a threshold voltage of the start-up transistor. 9 . The memory device according to claim 8 , wherein the critical value is the target voltage value minus the difference value.

Images