Memory self-checking device and method

Abstract

The present invention provides a memory self-checking device and method, including a control module for generating a target input signal according to an input start enable signal, and respectively generating a first selection control signal and a second selection control signal; a first selection module for receiving the first selection control signal and the target input signal, and outputting a first selection output signal to a storage module to be tested; a second selection module for receiving the second selection control signal and a first storage output signal, and performing data selection on an initial signal and the first storage output signal to generate a second selection output signal; a receiving module for receiving the first storage output signal and a detection control signal; wherein, the receiving module detects the first storage output signal according to the detection control signal to obtain a detection result, and the control module outputs a target output signal according to the detection result. The present invention can effectively check the memory, improve the detection efficiency, and reduce the occupation of logic resources.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor chips, and in particular to a memory self-checking device and method. Background Art

[0002] During the chip production process, defects are very likely to be introduced, resulting in product failures. Therefore, semiconductor manufacturers must conduct comprehensive tests on devices before they are launched on the market to exclude faulty chips and shorten the early failure period of the failure rate curve. During normal use, without an external tester, the product also needs an internal test circuit to check its own faults.

[0003] Complementary Metal Oxide Semiconductor (CMOS) refers to a technology used to manufacture large-scale integrated circuit chips or chips manufactured using this technology. A CMOS image sensor (CIS) chip integrates multiple memories, including a Random Access Memory (RAM) that can be read and written repeatedly and a Read-Only Memory (ROM), such as DataRAM for storing image data, a startup chip required for the startup of a Microcontroller Unit (MCU), and a memory required for an Image Signal Processing (ISP) chip. Defects in the memory chip will directly affect the image quality. Therefore, it is necessary to check the memory during chip startup.

[0004] Therefore, it is necessary to provide a new type of memory self-checking device and method to solve the above problems existing in the prior art. Summary of the Invention

[0005] The object of the present invention is to provide a memory self-checking device and method, which can effectively check the memory, improve the detection efficiency, and reduce the occupation of logic resources.

[0006] To achieve the above object, the memory self-checking device of the present invention includes:

[0007] A control module, configured to generate a target input signal according to an input startup enable signal, and respectively generate a first selection control signal and a second selection control signal;

[0008] A first selection module, communicatively connected to the control module, configured to receive the first selection control signal and the target input signal, and perform data selection on an input external control signal and the target input signal and generate a first selection output signal to output to a storage module to be tested;

[0009] A second selection module, communicatively connected to the control module and the memory module under test, is configured to receive the second selection control signal and the first memory output signal generated by the memory module under test, and perform data selection on the input initial signal and the first memory output signal output by the memory module under test to generate a second selection output signal;

[0010] A receiving module, communicatively connected to the control module and the memory module under test, is configured to receive the first memory output signal output by the memory module under test and the detection control signal sent by the control module;

[0011] Wherein, the receiving module detects the first memory output signal according to the detection control signal to obtain a detection result, and the control module outputs a target output signal according to the detection result.

[0012] The beneficial effect of the memory self-checking device of the present invention is that: after receiving an external start enable signal through the control module, the memory self-checking device generates a first selection control signal, a second selection control signal and a target input signal, so that subsequently the first selection module performs data selection according to the first selection control signal and outputs a first selection output signal to the memory module under test. After the memory module under test generates a first memory output signal according to the first selection output signal, the receiving module receives the detection control signal sent by the control module and then detects the first memory output signal, and the control module outputs a target output signal according to the detection result, so as to obtain a final detection result according to the target output signal. The algorithm of the entire memory self-checking device is fixed and the logic is simple, so that compared with the currently JTAG interface-compatible memory self-checking device, fewer logic devices are used, and while realizing the self-checking of the memory, the overall logic resource consumption is reduced.

[0013] Optionally, the memory module under test is a RAM memory module, and the control module includes a processing unit and a sending unit. The processing unit is configured to output a write control signal to the sending unit after receiving the start enable signal, and send a target address signal and a first selection control signal to the first selection module. The sending unit is configured to send write data to the first selection module according to the write control signal. The first selection module performs data selection on the write data, the target address signal and the external control signal according to the first selection control signal and outputs a first selection output signal to the RAM memory module, and the RAM memory module outputs a first memory output signal according to the first selection output signal.

[0014] Optionally, the processing unit is further configured to send a reception enable signal and the read / write control signal to the receiving module. After receiving the first memory output signal, the receiving module detects the first memory output signal according to the read / write control signal, and the processing unit outputs a target output signal according to the detection result of the receiving module.

[0015] Optionally, the period of the continuous high level of the start enable signal is at least greater than four times the clock period of the address depth of the RAM memory module.

[0016] Optionally, the memory module to be tested is a ROM memory module, the target input signal is a read address signal, the receiving module is further configured to receive an externally input detection comparison signal, and the control module outputs a read address signal and a first selection control signal to the first selection module after receiving the start enable signal. The first selection module selects the read address signal as the first selection output signal according to the first selection control signal and outputs it to the ROM memory module.

[0017] Optionally, the control module is configured to send a reception enable signal to the receiving module. After receiving the reception enable signal, the receiving module detects the first memory output signal and the detection comparison signal and generates a detection result, and the control module outputs a target output signal according to the detection result.

[0018] Optionally, the period of the continuous high level of the start enable signal is at least greater than the clock period of the address depth of the ROM memory module.

[0019] Optionally, after the control module receives the start enable signal, the second selection module outputs the initial signal as the second selection output signal outward.

[0020] The present invention also provides a memory self-checking method, including:

[0021] Applied to the above-mentioned memory self-checking device;

[0022] Input a start enable signal to the control module, and output a target input signal and a first selection control signal to the first selection module through the control module;

[0023] The first selection module performs signal selection according to the first selection control signal and outputs the first selection output signal to the memory module to be tested;

[0024] Send a detection control signal to the receiving module through the control module. The receiving module receives the detection control signal and the first memory output signal generated by the memory module to be tested and detects the first memory output signal to obtain a detection result;

[0025] The control module outputs a target output signal according to the detection result of the receiving module to complete the detection.

[0026] The beneficial effect of the memory self-checking method of the present invention is that: after the control module receives an external start enable signal, it generates a first selection control signal, a second selection control signal, and a target input signal, so that the subsequent first selection module can perform data selection according to the first selection control signal and output a first selection output signal to the storage module to be tested. After the storage module to be tested generates a first storage output signal according to the first selection output signal, the receiving module receives the detection control signal sent by the control module and then detects the first storage output signal, and the control module outputs a target output signal according to the detection result, so as to obtain a final detection result according to the target output signal. The whole self-checking method is simple, can detect different defects of the memory, and while realizing the memory self-checking, reduces the overall logical resource consumption and effectively improves the detection efficiency of the memory.

[0027] Optionally, the control module includes a processing unit and a sending unit, the storage module to be tested is a RAM storage module, the processing unit is configured to receive the start enable signal and output a write control signal to the sending unit, send a target address signal and a first selection control signal to the first selection module, and the first selection module performs signal selection according to the first selection control signal and outputs a first selection output signal to the storage module to be tested, including:

[0028] The sending unit generates write data after receiving the write control signal and sends it to the first selection module;

[0029] The processing unit sends the target address signal and the first selection control signal to the first selection module;

[0030] The first selection module performs data selection according to the first selection control signal and then performs data selection on the write data, the target address signal, and an external control signal and outputs a first selection output signal to the RAM storage module;

[0031] The control module sends a detection control signal to the receiving module, and the receiving module receives the detection control signal and the first storage output signal generated by the storage module to be tested and detects the first storage output signal, including:

[0032] The processing unit sends a receive enable signal and the read / write control signal to the receiving module;

[0033] After the receiving module receives the first storage output signal, it detects the first storage output signal according to the read-write control signal.

[0034] Optionally, the storage module to be tested is a ROM storage module. The first selection module performs signal selection according to the first selection control signal and outputs a first selection output signal to the storage module to be tested, including:

[0035] The control module outputs a read address signal and a first selection control signal to the first selection module according to the start enable signal;

[0036] The first selection module performs data selection according to the first selection control signal and uses the read address signal as the first selection output signal to output to the ROM storage module;

[0037] The control module sends a detection control signal to the receiving module. The receiving module receives the first storage output signal sent by the storage module to be tested and detects the first storage output signal, including:

[0038] The control module sends a receive enable signal to the receiving module;

[0039] The receiving module receives the first storage output signal sent by the ROM storage module and detects the first storage output signal by comparing it with a pre-stored detection comparison signal.

[0040] Optionally, the method further includes, after the detection is completed, stopping inputting the start enable signal. The first selection module outputs an external control signal as the first selection output signal to the storage module to be tested. The storage module to be tested generates a second storage output signal according to the external control signal. The second selection module performs data selection on the second storage output signal and the initial signal and outputs the second storage output signal externally. Description of the Drawings

[0041] Figure 1 It is a structural block diagram of the memory self-checking device according to an embodiment of the present invention;

[0042] Figure 2 It is a structural block diagram of the memory self-checking device according to an embodiment of the present invention when the storage module to be tested is a RAM storage module;

[0043] Figure 3 In an embodiment of the present invention Figure 2 The timing diagram of the memory self-checking device;

[0044] Figure 4 It is a structural block diagram of the memory self-checking device according to an embodiment of the present invention when the storage module to be tested is a ROM storage module;

[0045] Figure 5 In the embodiments of the present invention Figure 4 The timing diagram of the memory self - checking device in

[0046] Figure 6 The flowchart of the memory self - checking method described in the embodiments of the present invention. Detailed implementation manners

[0047] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention. Obviously, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings as understood by those of ordinary skill in the art to which the present invention pertains. The words such as "including" used herein mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items.

[0048] In view of the problems existing in the prior art, embodiments of the present invention provide a memory self - checking device, as Figure 1 shown, including:

[0049] A control module 101, configured to generate a target input signal according to an input start - enable signal, and respectively generate a first selection control signal and a second selection control signal;

[0050] A first selection module 102, communicatively connected to the control module 101, configured to receive the first selection control signal and the target input signal, and perform data selection on an input external control signal input and the target input signal and generate a first selection output signal for output to a storage module 103 to be tested;

[0051] A second selection module 104, communicatively connected to the control module 101 and the storage module 103 to be tested, configured to receive the second selection control signal and a first storage output signal generated by the storage module to be tested, and perform data selection on an input initial signal B and the first storage output signal output by the storage module to be tested and generate a second selection output signal output;

[0052] A receiving module 105, communicatively connected to the control module 101 and the storage module 103 to be tested, configured to receive the first storage output signal output by the storage module 103 to be tested and a detection control signal sent by the control module 101;

[0053] Among them, the receiving module 105 detects the first storage output signal according to the detection control signal and obtains a detection result, and the control module 101 outputs a target output signal according to the detection result.

[0054] By connecting the storage module 103 to be tested to the above-mentioned memory self-checking device, under normal circumstances, when it is not necessary to detect the storage module 103 to be tested, the control module 101 sends a first selection control signal to the first selection module 102, and the first selection module 102 outputs the external control signal as the first selection output signal to the storage module 103 to be tested. Then, the storage module 103 to be tested outputs a first storage output signal corresponding to the external control signal. At the same time, the control module 101 sends a second selection control signal to the second selection module 104, so that the second selection module 104 outputs the first storage output signal outward. Thus, when the memory self-checking device does not detect the storage module 103 to be tested, the storage module 103 to be tested can normally generate an output.

[0055] When the memory self-checking device is detecting the storage module 103 to be tested, after inputting a start enable signal to the control module 101, the control module 101 generates a target input signal and a first selection control signal to the first selection module 102, so that the first selection module 102 selects the target input signal as the first selection output signal and outputs it to the storage module 103 to be tested. Then, the storage module 103 to be tested generates a first storage output signal according to the target input signal, and the control module 101 sends a second selection control signal to the second selection module 104, so that the second selection module 104 outputs the initial signal as the second selection output signal, thus realizing the shielding effect on external signals during the self-checking process. Then, the receiving module 105 detects the first storage output signal according to the detection control signal sent by the control module 101, thereby realizing the detection process of the storage module 103 to be tested and obtaining a detection result. Then, the control module 101 generates a corresponding target output signal according to the detection result, so as to obtain the final detection result.

[0056] In some embodiments, refer to Figure 2, the storage module 103 to be measured is the RAM storage module 1031. The control module 101 includes a processing unit 1011 and a sending unit 1012. The processing unit 1011 is configured to output a write control signal to the sending unit 1012 after receiving the start enable signal, and send a target address signal and a first selection control signal to the first selection module 102. The sending unit 1012 is configured to send write data to the first selection module 102 according to the write control signal. The first selection module 102 performs data selection on the write data, the target address signal, and the external control signal RAM_input according to the first selection control signal and outputs a first selection output signal to the RAM storage module 1031. The RAM storage module 1031 outputs a first storage output signal according to the first selection output signal.

[0057] In this embodiment, since the detection object of the memory self-checking device is the RAM storage module 1031, and RAM is a Random Access Memory with read and write functions, it is necessary to perform read and write detection on the RAM storage module 1031.

[0058] In some other embodiments, the processing unit 1011 is further configured to send a receive enable signal and the read / write control signal to the receiving module 105. After receiving the first storage output signal, the receiving module 105 detects the first storage output signal according to the read / write control signal. The processing unit 1011 outputs a target output signal according to the detection result of the receiving module 105.

[0059] Among them, the target address signal includes a read address signal and a write address signal to respectively control the RAM storage module 1031 to perform data reading and data writing at corresponding addresses.

[0060] Specifically, referring to Figure 3 , during detection, after sending a high-level start enable signal bist_en to the processing unit 1011, the processing unit 1011 enters the detection process according to the received start enable signal. The processing unit 1011 sends a second selection control signal to the second selection module 104, so that the second selection module 104 outputs the initial signal to the outside, enabling the external system to obtain the output of the initial signal, thereby shielding the influence of the storage module 103 to be measured on the outside; at the same time, the processing unit 1011 generates a corresponding address signal and sends it to the first selection module 102.

[0061] Optionally, the initial signal is fixed to 0 to ensure that during the detection of the RAM storage module 1031, the signal output to the outside is always 0.

[0062] The post-processing unit 1011 outputs a write control signal to the transmission unit 1012, where the write control signal corresponds to two data writing modes, namely the writing mode of the 01 cyclic sequence and the writing mode of the 10 cyclic sequence, so as to perform data writing detection in two different modes on the storage module 103 to be tested.

[0063] Optionally, when the write control signal is at a low level, data of the 01 cyclic sequence is written. For example, when the data width is D_WIDTH = 8, the corresponding written number is 01010101; when the write control signal is at a high level, data of the 10 cyclic sequence is written. For example, when the data width is D_WIDTH = 8, the corresponding written number is 10101010.

[0064] In some embodiments, the write control signal includes a write mode signal test_mode and a transmission enable signal tx_en. After the transmission unit 1012 receives the write mode signal test_mode and the transmission enable signal tx_en, it determines the corresponding data writing mode, generates the data to be written according to the corresponding data writing mode, and then the transmission unit 1012 sends the generated data to be written to the first selection module 102 according to the transmission enable signal. One data selection terminal of the first selection module 102 inputs an external control signal as an input signal, and the other data selection terminal inputs the data to be written and the target address signal bist_ADR as another input signal. Then, the first selection module 102 selects the data to be written and the target address signal as the first selection output signal according to the first selection control signal and outputs it to the RAM storage module 1031, so as to write the data to be written into the address corresponding to the target address signal in the RAM storage module 1031, thereby completing the data writing to the RAM storage module 1031, and the RAM storage module 1031 outputs the first storage output signal.

[0065] The post-processing unit 1011 generates a high-level reception enable signal, and sends the reception enable signal and the write mode signal in the read-write control signal to the reception module 105, so that the reception module 105 receives the first storage output signal sent by the RAM storage module 1031, and detects the first storage output signal according to the data writing mode corresponding to the write mode signal, so as to determine whether the data written at the target address in the RAM storage module 1031 corresponds to the data writing mode corresponding to the write mode signal, thereby completing the detection process of one of the data writing and reading modes of the RAM storage module 1031.

[0066] In this embodiment, during the process of the receiving module 105 detecting the first storage output signal, the current data writing mode corresponds to a 01 cyclic sequence. After the receiving module 105 receives the first storage output signal, it detects the first storage output signal. When all the data at the addresses corresponding to the first storage output signal do not have a matching error, that is, the data reading and writing of the RAM storage module 1031 are correct, the first output level bist_done of the processing unit 1011 is pulled high, and the second output level bist_fail remains unchanged; when any one of the data at the addresses corresponding to the first storage output signal has a matching error, that is, the data reading and writing of the RAM storage module 1031 are incorrect, both the first output level bist_done and the second output level bist_fail of the processing unit 1011 are pulled high in advance.

[0067] In some other embodiments, the processing unit 1011 sends a write control signal of another write mode to the sending unit 1012 to facilitate the detection of another write mode of the RAM storage module 1031, so as to ensure that all fixed-type faults (Stuck-At Fault, SAF) of the RAM storage module 1031 that fixedly output a high level 1 or a low level 0 can be detected, thereby facilitating the detection of the faults where the RAM storage module 1031 is fixed at a high level or a low level, and improving the accuracy of the detection result.

[0068] Since the detection processes of the two data reading and writing modes are basically the same, they will not be elaborated here.

[0069] In some embodiments, the period of the continuous high level of the start enable signal is at least greater than four times the clock period of the address depth DEPTH of the RAM storage module, so as to ensure that during the detection period of one start enable signal, the detection of the two data reading and writing modes of the RAM storage module 1031 can be completed, so as to timely discover the defects existing in 0 and 1 in the RAM storage module 1031 and avoid missing detections.

[0070] In some embodiments, referring to Figure 4 , the storage module 103 to be tested is the ROM storage module 1032, the target input signal is a read address signal, the receiving module 105 is further configured to receive an externally input detection comparison signal, the control module 101 outputs a read address signal and a first selection control signal to the first selection module 102 after receiving the start enable signal, and the first selection module 102 selects the read address signal as the first selection output signal according to the first selection control signal and outputs it to the ROM storage module 1032.

[0071] In some embodiments, the control module 101 is configured to send a receive enable signal to the receive module 105. After receiving the receive enable signal, the receive module 105 detects the first storage output signal and the detection comparison signal and generates a detection result. The control module 101 outputs a target output signal according to the detection result.

[0072] When the storage module 103 to be tested is the ROM storage module 1032, since the ROM is a read-only memory (Read-Only Memory), only data reading detection is required.

[0073] Specifically, during the detection process, refer to Figure 5 , after the control module 101 receives the high-level start enable signal, it generates a read address signal bist_ADR and a first selection control signal to the first selection module 102. The first selection module 102 receives an external control signal as the input signal of one data input terminal, and uses the read address signal as the input signal of the other data input terminal. The first selection module 102 then selects data between the read address signal and the external control signal according to the first selection control signal, and outputs the read address signal as the first selection output signal to the ROM storage module 1032, so as to read the data corresponding to the address of the read address signal in the ROM storage module 1032. After that, the ROM storage module 1032 outputs the address corresponding to the read address signal as the first storage output signal.

[0074] After that, after the receive module 105 receives the receive enable signal, it detects the register check_sum calculated according to the first storage output signal and the detection comparison signal check_result. When the first storage output signal does not correspond to the detection comparison signal, it indicates that an error occurs in the detection of the ROM storage module 1032, and both the first output level bist_done and the second output level bist_fail of the control module 101 are pulled high; when the first storage output signal corresponds to the detection comparison signal, it indicates that the detection of the ROM storage module 1032 is correct, and the first output level bist_done of the processing unit 1011 is pulled high, and the second output level bist_fail remains unchanged, thus completing the storage detection process of the ROM storage module 1032.

[0075] In this embodiment, since the ROM storage module 1032 cannot be rewritten, when the storage module 103 to be tested is the ROM storage module 1032, the external control signal ROM_ADR input to the first selection module 102 is an address signal.

[0076] It should be noted that the detection and comparison signal can be either input into the receiving module 105 through the input interface or pre-stored in the receiving module 105, which will not be elaborated here.

[0077] In some embodiments, the period of the continuous high level of the start enable signal is at least greater than the clock period of the address depth DEPTH of the ROM storage module 1032, so as to facilitate the detection of the data in each storage address of the ROM storage module 1032.

[0078] In some embodiments, after the receiving module 105 receives the first storage output signal, during the process of detecting the first storage output signal and the detection and comparison signal, the read address signal output by the control module 101 increases from 0 each time. Each address in the first storage output signal output by the ROM storage module 1032 reads data only once, and the data read at address i is denoted as q_out_i. An internal register check_sum is set inside the receiving module 105, and the processing process of the receiving module 105 for the data q_out_i corresponding to address i is as follows:

[0079] When address i is 0, that is, the starting address of the ROM storage module 1032, the corresponding data is q_out_0. Let the internal register check_sum = q_out_0, so that the internal register can save the corresponding data for comparison with the detection and comparison signal.

[0080] After that, for each address i, let the current internal register check_sum = check_sum ^ q_out_i + 1'b1, that is, the previous internal register check_sum and the data q_out_i read corresponding to the current address i are bitwise XOR calculated, and the calculation result obtained after the XOR calculation is incremented by 1, so as to obtain the new internal register check_sum corresponding to address i, so as to compare the new internal register check_sum with the detection and comparison signal, so as to judge whether the first storage output signal output by the ROM storage module 1032 is correct, so as to perform storage detection on the ROM storage module 1032.

[0081] In some embodiments, after the control module 101 receives the start enable signal, the second selection module 104 outputs the initial signal as the second selection output signal, so as to output the initial signal as the second selection output signal during the detection process of the ROM storage module 1032.

[0082] In some other embodiments, the above-mentioned memory self-checking device is applied to the memory detection in a CIS chip. During the chip startup phase, the memory self-checking device can detect faults in the internal memory of the CIS chip in a timely manner, so as to discover the storage faults that occur inside the CIS chip in time, facilitate the timely elimination of the faults, and reduce the impact of defects in the storage chip on the image.

[0083] The above-mentioned memory self-checking device is used to detect the storage module 103 to be tested. Since the entire device uses fewer logic functions and does not need to be compatible with the Joint Test Action Group (JTAG) interface, the difficulty of layout and wiring of the entire device is reduced, and it can detect different types of memories, so as to facilitate the timely elimination of faults in the memory and effectively improve the detection efficiency.

[0084] The present invention also provides a memory self-checking method, as Figure 6 shown, including the following steps:

[0085] S601: Apply it to the above-mentioned memory self-checking device;

[0086] S602: Input a startup enable signal to the control module, and the control module outputs a target input signal and a first selection control signal to the first selection module;

[0087] S603: The first selection module selects signals according to the first selection control signal and outputs a first selection output signal to the storage module to be tested;

[0088] S604: Send a detection control signal to the receiving module through the control module. The receiving module receives the detection control signal and the first storage output signal generated by the storage module to be tested and detects the first storage output signal to obtain a detection result;

[0089] S605: The control module outputs a target output signal according to the detection result of the receiving module to complete the detection.

[0090] In the above process, after the control module receives the start enable signal, the control module sends a target input signal and a first selection control signal value to the first selection module. The first selection module performs signal selection according to the first selection control signal and outputs a first selection output signal to the storage module under test, thereby completing the internal control of the storage module under test. Then, the control module sends a detection control signal to the receiving module. After the receiving module receives the detection control signal, it receives the first storage output signal sent by the storage module under test and performs detection with the detection comparison signal to obtain a detection result. Then, the control module outputs target output signals of different levels according to the detection result of the receiving module, thereby completing the storage detection process of the storage module under test.

[0091] In some embodiments, when the storage module under test is a RAM storage module, since the RAM storage module needs to perform read and write detection, the control module includes a processing unit and a sending unit. The processing unit is configured to receive the start enable signal and output a write control signal to the sending unit, and send a target address signal and a first selection control signal to the first selection module. The first selection module performs signal selection according to the first selection control signal and outputs a first selection output signal to the storage module under test, including:

[0092] After receiving the write control signal, the sending unit generates write data and sends it to the first selection module; then the processing unit sends the target address signal and the first selection control signal to the first selection module; after the first selection module performs data selection according to the first selection control signal, it performs data selection on the write data, the target address signal, and the external control signal and outputs a first selection output signal to the RAM storage module.

[0093] Specifically, the first selection module sends the write data and the target address signal as the first selection output signal to the RAM storage module according to the first selection control signal, so as to write the write data into the target address of the RAM storage module. The RAM storage module then outputs the written data as the first storage output signal.

[0094] The control module sends a detection control signal to the receiving module, and the receiving module receives the detection control signal and the first storage output signal generated by the storage module under test and performs detection on the first storage output signal, including:

[0095] The processing unit sends a receive enable signal and the read / write control signal to the receiving module;

[0096] After receiving the first storage output signal, the receiving module performs detection on the first storage output signal according to the read / write control signal.

[0097] Since the detection process of the RAM storage module has been described in the aforementioned memory self - testing device, it will not be elaborated here.

[0098] In some embodiments, the storage module to be tested is a ROM storage module. The first selection module performs signal selection according to the first selection control signal and outputs a first selection output signal to the storage module to be tested, including:

[0099] The control module outputs a read address signal and a first selection control signal to the first selection module according to the start enable signal;

[0100] The first selection module performs data selection according to the first selection control signal and uses the read address signal as the first selection output signal to output to the ROM storage module;

[0101] The control module sends a detection control signal to the receiving module. The receiving module receives the first storage output signal sent by the storage module to be tested and detects the first storage output signal, including:

[0102] The control module sends a receive enable signal to the receiving module;

[0103] The receiving module receives the first storage output signal sent by the ROM storage module and detects the first storage output signal by comparing it with a pre - stored detection comparison signal.

[0104] Since the detection process of the ROM storage module has been described in the aforementioned memory self - testing device, it will not be elaborated here.

[0105] In some embodiments, the method further includes, after the detection is completed, stopping the input of the start enable signal. The first selection module outputs an external control signal as the first selection output signal to the storage module to be tested. The storage module to be tested generates a second storage output signal according to the external control signal. The second selection module performs data selection on the second storage output signal and the initial signal and outputs the second storage output signal outward. After stopping the input of the start enable signal, it is ensured that the external control signal can control the storage module to be tested.

[0106] Although the embodiments of the present invention have been described in detail above, it is obvious to those skilled in the art that various modifications and changes can be made to these embodiments. However, it should be understood that such modifications and changes fall within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein can have other embodiments and can be implemented or realized in various ways.

Claims

1. A memory self-checking device, characterized in that, Comprising: A control module, configured to generate a target input signal according to an input start enable signal, and respectively generate a first selection control signal and a second selection control signal; A first selection module, communicatively connected to the control module, configured to receive the first selection control signal and the target input signal, and perform data selection on an input external control signal and the target input signal and generate a first selection output signal for output to a storage module under test; A second selection module, communicatively connected to the control module and the storage module under test, configured to receive the second selection control signal and a first storage output signal generated by the storage module under test, and perform data selection on an input initial signal and the first storage output signal output by the storage module under test and generate a second selection output signal; A receiving module, communicatively connected to the control module and the storage module under test, configured to receive the first storage output signal output by the storage module under test and a detection control signal sent by the control module; Wherein, the receiving module detects the first storage output signal according to the detection control signal and obtains a detection result, and the control module outputs a target output signal according to the detection result.

2. The memory self-checking device according to claim 1, wherein The storage module under test is a RAM storage module. The control module includes a processing unit and a sending unit. The processing unit is configured to output a write control signal to the sending unit after receiving the start enable signal, and send a target address signal and a first selection control signal to the first selection module. The sending unit is configured to send write data to the first selection module according to the write control signal. The first selection module performs data selection on the write data, the target address signal and the external control signal according to the first selection control signal and outputs a first selection output signal to the RAM storage module. The RAM storage module outputs a first storage output signal according to the first selection output signal.

3. The memory self-checking device according to claim 2, wherein The processing unit is further configured to send a receive enable signal and a read / write control signal to the receiving module. After receiving the first storage output signal, the receiving module detects the first storage output signal according to the read / write control signal. The processing unit outputs a target output signal according to the detection result of the receiving module.

4. The memory self-checking device according to claim 2, wherein The period of continuous high level of the start enable signal is at least greater than four times the clock period of the address depth of the RAM storage module.

5. The memory self-checking device according to claim 1, wherein The storage module under test is a ROM storage module. The target input signal is a read address signal. The receiving module is further configured to receive an externally input detection comparison signal. The control module outputs a read address signal and a first selection control signal to the first selection module after receiving the start enable signal. The first selection module selects the read address signal as the first selection output signal according to the first selection control signal and outputs it to the ROM storage module.

6. The memory self-checking device according to claim 5, wherein, The control module is used to send a receive enable signal to the receiving module. After receiving the receive enable signal, the receiving module detects the first storage output signal and the detection comparison signal and generates a detection result. The control module outputs a target output signal according to the detection result.

7. The memory self-checking device according to claim 5, wherein The period of the continuous high level of the start enable signal is at least greater than the clock period of the address depth of the ROM storage module.

8. The memory self-checking device according to claim 2 or 5, characterized in that After the control module receives the start enable signal, the second selection module outputs the initial signal as the second selection output signal.

9. A method for self-checking memory, characterized in that, Including: Applied to the memory self-checking device according to any one of claims 1 to 8; Input a start enable signal to the control module, and output a target input signal and a first selection control signal to the first selection module through the control module; The first selection module performs signal selection according to the first selection control signal and outputs a first selection output signal to the storage module to be tested; Send a detection control signal to the receiving module through the control module. The receiving module receives the detection control signal and the first storage output signal generated by the storage module to be tested and detects the first storage output signal to obtain a detection result; The control module outputs a target output signal according to the detection result of the receiving module to complete the detection.

10. The memory self-checking method according to claim 9, characterized in that, The control module includes a processing unit and a sending unit. The storage module to be tested is a RAM storage module. The processing unit is used to receive the start enable signal and output a write control signal to the sending unit, send a target address signal and a first selection control signal to the first selection module. The first selection module performs signal selection according to the first selection control signal and outputs a first selection output signal to the storage module to be tested, including: After receiving the write control signal, the sending unit generates write data and sends it to the first selection module; The processing unit sends the target address signal and the first selection control signal to the first selection module; After the first selection module performs data selection according to the first selection control signal, it performs data selection on the write data, the target address signal and the external control signal and outputs a first selection output signal to the RAM storage module; Sending a detection control signal to the receiving module through the control module. The receiving module receives the detection control signal and the first storage output signal generated by the storage module to be tested and detects the first storage output signal, including: Send a receive enable signal and a read / write control signal to the receiving module through the processing unit; After receiving the first storage output signal, the receiving module detects the first storage output signal according to the read / write control signal.

11. The memory self-checking method according to claim 9, wherein The storage module to be tested is a ROM storage module. The first selection module performs signal selection according to the first selection control signal and outputs a first selection output signal to the storage module to be tested, including: The control module outputs a read address signal and a first selection control signal to the first selection module according to the start enable signal; The first selection module performs data selection according to the first selection control signal and outputs the read address signal as the first selection output signal to the ROM storage module; The control module sends a detection control signal to the receiving module, and the receiving module receives the first storage output signal sent by the storage module to be tested and detects the first storage output signal, including: The control module sends a receiving enable signal to the receiving module; The receiving module receives the first storage output signal sent by the ROM storage module and detects the first storage output signal with a pre-stored detection comparison signal.

12. The memory self-checking method according to any one of claims 9 to 11, characterized in that The method further includes, after the detection is completed, stopping the input of the start enable signal, the first selection module outputs an external control signal as the first selection output signal to the storage module to be tested, the storage module to be tested generates a second storage output signal according to the external control signal, and the second selection module performs data selection on the second storage output signal and the initial signal and outputs the second storage output signal outward.

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