Functional testing device with relay system and testing method using the same

Abstract

The present disclosure provides a functional test device for an electronic component and a test method for the electronic component. The functional test device has a first power supply, a second power supply and a relay system. The first power supply is configured to generate a first supply voltage. The second power supply is configured to generate a second supply voltage, which is different from the first supply voltage. The relay system is configured to electrically couple the first power supply or the second power supply to the electronic component, wherein the first supply voltage is applied to the electronic component for a first duration, and the second supply voltage is applied to the electronic component for a second duration, which is less than the first duration.

Description

Technical Field

[0001] This disclosure claims priority to and the benefit of U.S. regular application No. 17 / 035,028, filed on September 28, 2020, the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a functional testing device and a method for testing an electronic component using the functional testing device. In particular, the present disclosure provides a functional testing device having a relay system and a testing method using the functional testing device. Background Art

[0003] Electronics have become ubiquitous in everyday life. In addition to a personal computer at home, many people carry more than one productivity tool for a variety of purposes. Most personal productivity electronics include some form of non-volatile memory. Cell phones use non-volatile memory to store and retain user-programmed phone numbers and configurations when the power is turned off.

[0004] As non-volatile memories become larger, denser, and more complex, testers must be able to handle the increased size and complexity without significantly increasing the time it takes to test them. Many memory testers run continuously, and test time is considered a major factor in the cost of the finished product. As memory technology evolves and improves, testers must be able to easily adapt to changes made to the device. Another problem unique to testing non-volatile memories is the repeated writing of each unit cell of a memory, which reduces the overall life performance of the component. Non-volatile memory manufacturers address many testing issues by building many specific test patterns into each memory component. The purchaser of the memory does not use these test patterns, but the manufacturer can use these test patterns to test all or significant portions of the memory as effectively as possible in the shortest possible time. Some non-volatile memories can also be repaired during the testing process. Therefore, the tester should be able to determine: the need for repair, the location of the repair, and the type of repair required; in addition, the tester must be able to perform appropriate repairs. Such a repair process requires a tester that is capable of detecting and isolating specific defective portions of the memory. In order to take full advantage of the special multiple test modes and multiple repair functions, it is beneficial for the tester to be able to execute a test program that supports conditional branching based on an expected response from the device.

[0005] The above description of “prior art” only provides background technology, does not admit that the above description of “prior art” discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of the present disclosure. Summary of the invention

[0006] One embodiment of the present disclosure provides a functional test device for an electronic component. The functional test device includes a first power supply, a second power supply, and a relay system. The first power supply is configured to generate a first supply voltage. The second power supply is configured to generate a second supply voltage, which is different from the first supply voltage. The relay system is configured to electrically couple the first power supply or the second power supply to the electronic component, wherein the first supply voltage is applied to the electronic component for a first duration, and the second supply voltage is applied to the electronic component for a second duration, and the second duration is less than the first duration.

[0007] In some embodiments, the functional testing device is provided with a plurality of data lines, a plurality of address lines, and a plurality of control lines, and the plurality of data lines, the plurality of address lines, and the plurality of control lines are electrically coupled to the electronic component.

[0008] In some embodiments, the relay system includes a relay and a microcontroller, the relay is composed of a relay switch and a magnetizing coil, the magnetizing coil is magnetically coupled to the relay switch, and the microcontroller is configured to control multiple operations of the relay switch.

[0009] In some embodiments, the relay system further includes a power source and a control switch, the control switch being inserted between the power source and the magnetizing coil, wherein the microcontroller is configured to close or open the control switch to control the operation of the relay switch.

[0010] In some embodiments, the microcontroller is configured to control a first time interval of an off state of the control switch and a second time interval of an on state of the control switch.

[0011] In some embodiments, the functional testing device also includes a power management capacitor, wherein one terminal of the power management capacitor is electrically coupled to the relay switch and the electronic component, and the other terminal of the power management capacitor is grounded, wherein when the relay system couples the first power supply to the electronic component, the power management capacitor is charged by the first supply voltage; when the relay system couples the second power supply to the electronic component, the power management capacitor is charged by the second supply voltage; and when the relay system does not couple the first power supply or the second power supply to the electronic component, the power management capacitor is discharged to power the electronic component.

[0012] In some embodiments, the relay switch includes a common contact point, a normally closed contact point, a normally open contact point, and a switch arm, the common contact point is electrically coupled to the electronic component, the normally closed contact point is electrically coupled to the first power supply, and the normally open contact point is electrically coupled to the second power supply, wherein the switch arm is spring-pressed by the common contact point and connects the common contact point to the normally closed contact point.

[0013] In some embodiments, when the switch arm connects the common contact point to the normally closed contact point, the first supply voltage is applied to the electronic component.

[0014] In some embodiments, when the switch arm connects the common contact point to the normally open contact point, the second supply voltage is applied to the electronic component.

[0015] In some embodiments, when the switch arm connects the common contact to the normally closed contact, the power management capacitor is charged by the first power supply; and when the switch arm connects the common contact to the normally open contact, the power management capacitor is charged by the second power supply.

[0016] In some embodiments, when the switch arm does not connect the common contact to any one of the normally closed contact and the normally open contact, the power management capacitor is discharged to power the electronic component.

[0017] In some embodiments, the power management capacitor has a capacitance value between 20 microfarads and 220 microfarads.

[0018] Another embodiment of the present disclosure provides a method for testing an electronic component. The method includes coupling the electronic component to a functional test device, the functional test device including a first power supply, a second power supply, a power management capacitor, and a relay switch, the relay switch is coupled to the electronic component, wherein the first power supply is used to provide a first supply voltage, and the second power supply is used to provide a second supply voltage, and the second supply voltage is different from the first supply voltage; operating the relay switch in a first closed state to apply the first supply voltage to the electronic component; and operating the relay switch in a second closed state to apply the second supply voltage to the electronic component; wherein the first supply voltage is applied to the electronic component for a first duration, and the second supply voltage is applied to the electronic component for a second duration, and the second duration is less than the first duration.

[0019] In some embodiments, the method further includes: when the relay switch operates in the first closed state, charging the power management capacitor with the first supply voltage; when the relay switch operates in the second closed state, charging the power management capacitor with the second supply voltage; and when the relay switch operates in an open state, the power management capacitor is discharged to power the electronic component.

[0020] In some embodiments, the relay switch operates in the open state for a third duration that is shorter than the first duration.

[0021] In some embodiments, the third duration is less than the second duration.

[0022] In some embodiments, when the relay switch is operated in the open state, the electronic component is not powered by the first supply voltage or the second supply voltage.

[0023] In some embodiments, the relay changes from the first closed state via the open state to the second closed state, and the relay changes from the second closed state via the open state to the first closed state.

[0024] In some embodiments, the first duration and the second duration are controlled by a microcontroller, and the microcontroller is coupled to a relay, the relay includes a relay switch and a magnetizing coil, and the magnetizing coil is magnetically coupled to the relay switch.

[0025] The testing of components is very important. Because ATE usually provides a relatively stable power supply compared to the power supply provided to each component installed in an electronic device such as a computer or a mobile phone, the existing automatic test equipment (ATE) cannot accurately reflect the voltage changes in the power supply input to the electronic component. Therefore, the existing ATE cannot screen out problematic electronic components during the verification stage. The present disclosure provides a functional test device having a relay system and a pair of power supplies. In addition, the pair of power supplies provides a pair of different supply voltages to an electronic component (DUT), and the electronic component is placed in the functional test device. The combination of the relay system and the pair of power supplies provides a test of the electronic component to simulate multiple conditions, which are various conditions that a memory chip may encounter in actual use. Furthermore, the artificial power reduction provided to the DUT is to verify the robustness of the DUT. Therefore, according to the present disclosure, a more realistic simulation when testing the DUT can be achieved.

[0026] The above has been a fairly broad overview of the technical features and advantages of the present disclosure, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those skilled in the art to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used quite easily to modify or design other structures or processes to achieve the same purpose as the present disclosure. It should also be understood by those skilled in the art to which the present disclosure belongs that such equivalent constructions cannot depart from the concept and scope of the present disclosure as defined by the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] A more comprehensive understanding of the disclosure of the present invention may be obtained by referring to the embodiments and claims in conjunction with the accompanying drawings, in which the same reference numerals refer to the same elements.

[0028] Figure 1 A schematic diagram of a single-pole-double-throw (SPDT) type switch illustrating some embodiments of the present disclosure.

[0029] Figure 2 A schematic diagram illustrating a test fixture according to some embodiments of the present disclosure.

[0030] Figure 3 A schematic diagram illustrating a test device according to some embodiments of the present disclosure.

[0031] Figure 4 Some embodiments of the present disclosure are illustrated in Figure 3 A graph showing the relationship between a test supply voltage (V) and time (t) during operation of the test equipment.

[0032] Figure 5 A block diagram of an electronic component illustrating some embodiments of the present disclosure.

[0033] Figure 6 Some embodiments of the present disclosure are illustrated in Figure 5 A graph showing the relationship between a supply voltage (V) and time (t) during operation of the electronic component.

[0034] Figure 7 A schematic diagram illustrating a functional testing device according to some embodiments of the present disclosure.

[0035] Figure 8 Some embodiments of the present disclosure are used in Figure 7 A flow chart of a testing method of the functional testing device in FIG.

[0036] Figures 9 to 12 In some embodiments of the present disclosure, Figure 7 Schematic diagram of different operating states of the functional test equipment.

[0037] Figure 13 to Figure 15 In some embodiments of the present disclosure, Figure 8 Schematic diagram of different operating states of the test method.

[0038] Explanation of symbols

[0039] 40: Coil

[0040] 50: Switch

[0041] 52: Shared contact points

[0042] 54: Normally closed contact

[0043] 56: Normally open contact

[0044] 58: Switch arm

[0045] 70: Electronic components

[0046] 72: Ground wire

[0047] 74: Data cable

[0048] 76: Address line

[0049] 78: Control Line

[0050] 80: Memory chips

[0051] 82: Central Processing Unit

[0052] 84: Cache memory

[0053] 86: Graphics card

[0054] 100: Landing Point

[0055] 100A: Landing Point

[0056] 102: Electronic components

[0057] 104: Data cable

[0058] 106: Address line

[0059] 108: Control Line

[0060] 110: Power

[0061] 112: Control switch

[0062] 120: Magnetizing coil

[0063] 122: Shared contact points

[0064] 124: Normally closed contact

[0065] 126: Normally open contact

[0066] 128: Switch arm

[0067] 200: Test Methods

[0068] CC: Power Management Capacitor

[0069] CL: Relay circuit

[0070] E1: Test equipment

[0071] E2: Electronic components

[0072] F1: Test fixture

[0073] I1: First current

[0074] I 1a : Current

[0075] I 1b : Current

[0076] I c : Current

[0077] I2: Second current

[0078] I 2a : Current

[0079] I 2b : Current

[0080] MC: microcontroller

[0081] P1: The first power supply

[0082] P2: Second power supply

[0083] R1: Relay

[0084] RL: Relay

[0085] RS: Relay system

[0086] S1: Power supply falling slope

[0087] S2: Power supply rising slope

[0088] SW: Relay switch

[0089] t0: time

[0090] t0': time

[0091] t1: time

[0092] t1': time

[0093] T1: Functional test equipment

[0094] t2: time

[0095] t2': time

[0096] t3: time

[0097] t3': time

[0098] t4: time

[0099] t4': time

[0100] t5: time

[0101] t5': time

[0102] t6: time

[0103] t6': time

[0104] t7: time

[0105] t7': time

[0106] t a : First duration

[0107] t a ': First duration

[0108] t a1 : Duration

[0109] t a2 : Duration

[0110] t a3 : Duration

[0111] tb : Second duration

[0112] t b ': Second duration

[0113] t b1 : Duration

[0114] t b2 : Duration

[0115] t b3 : Duration

[0116] t c : Second duration

[0117] Vdd: test supply voltage

[0118] Vdd-1: First supply voltage

[0119] Vdd-2: Second supply voltage

[0120] Vdd': Partial supply voltage

[0121] S101: Steps

[0122] S103: Steps

[0123] S105: Steps DETAILED DESCRIPTION

[0124] The following description of the present disclosure is accompanied by the accompanying drawings which are incorporated into and constitute a part of the specification, and illustrates an embodiment of the present disclosure, but the present disclosure is not limited to the embodiment. In addition, the following embodiments can be appropriately integrated to complete another embodiment.

[0125] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe different elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Therefore, the "first element", "component", "region", "layer" or "section" discussed below may be referred to as a second element, component, region, layer or portion without departing from the teachings herein.

[0126] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, these terms specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the above.

[0127] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0128] A relay is an electrically-operated switch used to control a circuit based on an independent signal input to the relay. Relays are one of the most important electronic components because they allow low-power electronic devices such as computers or microcontrollers to control high-power devices such as industrial machinery. The operating principle of the relay of the present disclosure is described in detail below. Each relay is composed of a coil and a switch. Depending on the type of switch included, the relays have different architectures.

[0129] Figure 1 A schematic diagram of a single-pole-double-throw (SPDT) type switch illustrating some embodiments of the present disclosure. Figure 1 , a relay R1 having a coil 40 and a SPDT type switch 50 is shown. The SPDT type switch 50 has a common (COM) contact 52, a normally closed (NC) contact 54, a normally open (NO) contact 56, and a switch arm 58, and the switch arm 58 is spring-loaded through the common contact 52. The switch arm 58 can selectively connect the common contact 52 to the normally closed contact 54 or the normally open contact 56.

[0130] Synchronous dynamic random-access memory (SDRAM) is a new type of memory device that mainly uses a synchronous clock to control the input and output signals of the memory. Many computing devices use various types of SDRAM, such as double data rate (DDR) SDRAM. DDR SDRAM is a type of DRAM that supports double data rate, which means that data is transmitted on both the rising and falling edges of the DQ data strobe (DQS) signal to increase the data rate. As technology advances, the capacity of DDR SDRAM devices in such computing devices has been greatly improved. The earlier DDR SDRAM is retroactively called DDRx SDRAM. DDR SDRAM has evolved into DDR2, DDR3, and even DDR4 SDRAM, where the data rate has increased from 333 / 400MHz for DDR to 800MHz for DDR2 and above 1333MHz for DDR3, with higher data rates expected in the near future. Newer memory devices use relatively new standards. For example, DDR4 SDRAM uses a lower supply voltage and a larger bandwidth than DDR3 SDRAM or DDR2 SDRAM. Since the voltage standards and physical interfaces are not consistent, different standards are incompatible with each other. In addition, as the frequency increases, a tester with a high test speed should be prepared to test the corresponding memory accordingly.

[0131] In semiconductor testing, an electronic device under test (DUT) is a manufactured component that is tested during manufacturing or later in the life cycle as part of ongoing functional testing and calibration checks. The electronic component can be mounted on a landing pad of an automatic test equipment (ATE) and connected to the ATE via a connection system. The ATE powers the electronic component, provides a stimulus signal, and then measures or evaluates the resulting output from the component. In this way, the ATE determines whether a particular electronic component meets the device specifications. Generally speaking, ATE includes a variety of different test fixtures that are specially designed according to different testing needs or purposes.

[0132] Figure 2 A schematic diagram of a test fixture F1 illustrating some embodiments of the present disclosure. In some embodiments, the test fixture F1 can be designed to have up to 64 landing points 100A, each of which can accommodate an electronic component for testing purposes. Figure 2In FIG. 1 , eight landing points 100A are mounted on the test fixture F1.

[0133] Figure 3 A schematic diagram of a test device E1 illustrating some embodiments of the present disclosure. In some embodiments, the test device E1 may be an automatic test device. In some embodiments, the test device E1 may provide a test supply voltage Vdd. In addition, the test device E1 provides a ground line 72, a plurality of data lines 74, a plurality of address lines 76, and a plurality of control lines 78. In some embodiments, when an electronic component 70 needs to be tested, the electronic component 70 may be placed in the test device E1 during the test and electrically coupled to the test supply voltage Vdd, the ground line 72, the data lines 74, the address lines 76, and the control lines 78. In some embodiments, the electronic component 70 may be a memory chip, such as a DDRx SDRAM. Generally speaking, when the electronic component 70 is tested, the test supply voltage Vdd provided by the test device E1 is dedicated to the test process. Therefore, the test supply voltage Vdd applied to the electronic component 70 is a relatively stable power supply.

[0134] Figure 4 Some embodiments of the present disclosure are illustrated in Figure 3 A graph showing the relationship between a test supply voltage (V) and time (t) during operation of the test equipment in FIG. Figure 4 As shown, the x-axis represents time (milliseconds), and the y-axis represents the test supply voltage Vdd (volts). The horizontal dashed line shows an exemplary test supply voltage Vdd of 1.2V applied to the electronic component 70. Generally speaking, during the test process, the deviation of the test supply voltage Vdd from 1.2V is less than 30mV. That is, when a specific test supply voltage Vdd is set, the change of the test supply voltage Vdd is usually small.

[0135] However, the power supply systems in automatic test equipment and actual electronic components are very different, because the power supply in electronic components may be distributed to multiple electronic components running simultaneously. Figure 5A block diagram of an electronic component E2 illustrating some embodiments of the present disclosure. In some embodiments, the electronic component E2 may include multiple electronic components, such as a memory chip 80, a central processing unit (CPU) 82, a cache memory 84, and a graphics card 86. In some embodiments, the electronic component E2 is provided with a supply voltage Vdd', and the supply voltage Vdd' can be distributed to all the aforementioned electronic components at the same time. Therefore, in the actual use of the electronic component E2, only a portion of the supply voltage Vdd" diverted from the supply voltage Vdd' is used to power the memory chip 80. Generally, different electronic components have different power consumption levels in different operating modes. For example, when in a standby mode, the central processing unit 82 consumes a small amount of power, while in normal operating mode, the central processing unit 82 requires a large amount of power. Therefore, part of the supply voltage Vdd" supplied to the memory chip 80 may fluctuate, especially when other electronic components switch their operating modes. Compared to the supply voltage Vdd" applied to Figure 3 The test supply voltage Vdd of the memory electronic component 70, and the partial supply voltage Vdd" applied to the memory chip 80 are relatively unstable.

[0136] Figure 6 Some embodiments of the present disclosure are illustrated in Figure 5 Another diagram showing the relationship between supply voltage (V) and time (t) during the operation of electronic component E2 in FIG. Figure 6 As shown, the horizontal dashed line shows an exemplary partial supply voltage Vdd of 1.2V applied to the memory chip 80. The partial supply voltage Vdd" may vary over time, but is relatively Figure 4 In the test supply voltage Vdd, the partial supply voltage Vdd” changes more significantly. In some examples, for example, the partial supply voltage Vdd” may suddenly drop to 1.0V or 0.9V. Sometimes, the partial supply voltage Vdd” may spike and exceed 1.2V. Since some memory elements are very sensitive to sudden voltage changes, a 200 or 300mV change in the partial supply voltage Vdd” applied to the memory chip 80 of the electronic component E2 may cause signal distortion or malfunction of the memory chip 80.

[0137] Existing automatic test equipment cannot accurately test such sudden voltage changes in power supplies because automatic test equipment usually provides a relatively stable power supply. In a simulation mode, the speed at which the supply voltage of an automatic test equipment drops or rises is not fast enough. Therefore, existing automatic test equipment may not be able to screen out problematic memory chips during the test phase.

[0138] The present disclosure provides a functional testing device, which is a test fixture used in the verification of the memory chips. Figure 7 A schematic diagram of a functional test device T1 illustrating some embodiments of the present disclosure. In some embodiments, the functional test device T1 mainly includes a landing site 100, a relay system RS, a first power supply P1, and a second power supply P2. In some embodiments, the functional test device T1 is provided with a plurality of data lines 104, a plurality of address lines 106, and a plurality of control lines 108. In some embodiments, an electronic component 102 can be placed on the landing site 100 in the functional test device T1 to determine whether the electronic component 102 meets the component specifications. In addition, the electronic component 102 can be electrically coupled to the data line 104, the address line 106, and the control line 108 during the test. In some embodiments, the electronic component 102 can be a memory chip, such as a DDRx SDRAM, but is not limited thereto.

[0139] Please refer to Figure 7, the relay system RS is electrically coupled to the landing point 100. In some embodiments, the relay system RS includes at least a relay switch SW, a relay circuit CL, and a power management capacitor CC, the relay circuit CL is magnetically coupled to the relay switch SW for controlling various operations of the relay switch SW, and the power management capacitor CC is electrically connected to the relay switch SW and the electronic component 102. In particular, the relay switch SW and the relay circuit CL are electrically insulated from each other so that current cannot flow between the relay switch SW and the relay circuit CL. In some embodiments, the relay switch SW can be a single-pole-double-throw (SPDT) type switch having a common contact point 122, a normally closed contact point 124, a normally open contact point 126, and a switch arm 128, wherein the switch arm 128 is spring-loaded through the common contact point 122. In some embodiments, the relay circuit CL includes at least a power source 110, a control switch 112, a magnetizing coil 120, and a microcontroller MC. In some embodiments, the power source 110 may be a DC power source, for example, it provides a 3V power source. Furthermore, the microcontroller MC is used to switch the control switch 112 between off and on, thereby determining whether the magnetizing coil 120 is energized. In some embodiments, the magnetically coupled magnetizing coil 120 and the relay switch SW form a relay RL in the relay system RS. In some embodiments, the relay RL is a normally closed relay, which means that the relay switch SW is usually in a closed state. In particular, before the relay circuit CL becomes a closed circuit, no current flows through the magnetizing coil 120. Because it is not energized, the magnetizing coil 120 will not affect the relay switch SW. Therefore, the relay switch SW is in a first closed state, in which Figure 7 As shown, when the magnetizing switch 120 is not energized, the switch arm 128 connects the common contact point 122 to the normally closed contact point 124. When energized, as shown in FIG. Fig.11As shown, the magnetizing switch 120 becomes an electromagnet, which generates an axial magnetic field (not shown) to magnetically push the switch arm 128 of the relay switch SW, thereby connecting the common contact point 122 to the normally open contact point 126. As a result, the relay switch SW enters a second closed state. Once the power is off (denergized), the magnetic field generated by the magnetizing coil 120 disappears, and the switch arm 128 returns to its original position. In some embodiments, when the relay circuit CL is an open circuit, the relay switch SW is in a first closed state, and when the relay circuit CL is a closed circuit, the relay switch SW is in a second closed state. In some embodiments, the microcontroller MC can be electrically coupled to the control switch 112 and used to control a time interval of the on state or off state of the control switch 112. In addition, multiple instructions can be given to the microcontroller MC to control a duration of the on or off state of the relay switch SW according to the time interval of the on state or off state of the control switch 112.

[0140] Please refer to Figure 7 In some embodiments, the first power supply P1 and the second power supply P2 are connected to the relay system RS and electrically coupled to the landing point 100 via the relay system RS. In particular, the normally closed contact 124 and the normally open contact 126 are connected to the first power supply P1 and the second power supply P2, respectively, and the common contact 122 is connected to the landing point 100. Therefore, when the electronic component 102 located on the landing point 100 is tested, the electronic component 102 can be electrically coupled to the first power supply P1 or the second power supply P2 according to the control of the relay system RS. In some embodiments, the first power supply P1 can provide a first supply voltage Vdd-1 to the electronic component 102, and the second power supply P2 can provide a second supply voltage Vdd-2 to the electronic component 102. In some embodiments, the first supply voltage Vdd-1 can be greater than the second supply voltage Vdd-2.

[0141] Please still refer to Figure 7In some embodiments, one terminal of the power management capacitor CC is connected to the common contact point 122 and the electronic component 102, and the other terminal of the power management capacitor CC is grounded. When the relay switch SW mechanically changes between the first closed state and the second closed state, there is a moment when the common contact point 122 is not connected to the normally closed contact point 124 or the normally open contact point 126, that is, the relay switch SW is substantially in an open state, which may cause the electronic component 102 to be powered off. In some embodiments, the duration of the relay switch SW operating in the open state is less than the duration of the relay switch SW operating in the first closed state and the second closed state.

[0142] Therefore, the power management capacitor CC electrically coupled to the common contact point 122 is required to maintain a basic power supply to the electronic component 102 while the relay switch SW changes between the first closed state and the second closed state. In some embodiments, when the switch arm 128 connects the common contact point 122 to the normally closed contact point 124, that is, when the electronic component 102 is electrically coupled to the first power supply P1, the power management capacitor CC is charged through the first power supply P1. In some embodiments, when the switch arm 128 connects the common contact point 122 to the normally open contact point 126, that is, when the electronic component 102 is electrically coupled to the second power supply P2, the power management capacitor CC is charged through the second power supply P2. In some embodiments, during the time when the switch arm 128 does not connect the common contact point 122 to any of the normally closed contact point 124 or the normally open contact point 126, the power management capacitor CC is discharged to power the electronic component 102. Therefore, it is possible to avoid a very short time when no power is supplied to the electronic component 102. In some embodiments, the capacitance of the power management capacitor CC can be obtained according to the following formula: τ=RC, where τ represents the time constant, R represents the resistance value (mainly from the electronic component 102), and C represents the capacitance of the power management capacitor CC. In some embodiments, the power management capacitor CC can have a capacitance value between about 22 and about 220 microfarads (μF), which is sufficient to power the electronic component 102.

[0143] Figure 8 Some embodiments of the present disclosure are used in Figure 7 FIG. 2 is a flow chart of a testing method 200 for a functional testing device T1 in FIG. Figures 9 to 12 In some embodiments of the present disclosure, Figure 7 Schematic diagram of the different operating states of the functional test device T1 in. Please refer to Figure 8 The testing method 200 starts with step S101 , which is coupling the electronic component 102 to the functional testing equipment T1 .

[0144] Please refer to Figure 8 and Fig. 9 , in step S103, the relay system RS enters a closed state to apply the first power supply P1 to the electronic component 102. In particular, the relay switch SW is maintained in a first closed state because the magnetizing coil 120 does not affect the relay switch SW when the relay circuit CL is open. Therefore, the electronic component 102 is connected to the first power supply P1 so that the first supply voltage Vdd-1 is applied to the electronic component 102. At this time, the electronic component 102 is electrically coupled to the first power supply P1 via the common contact point 122, the switch arm 128, and the normally closed contact point 124. Therefore, the first current I1 driven by the potential difference between the first power supply P1 and the electronic component 102 flows from the first power supply P1. After passing through the relay switch SW, the first current I1 is divided into a current I 1a and a current I 1b , current I 1a is flowing to the electronic component 102, the current I 1b In some embodiments, the current I 1a The test for activating the electronic component 102 and the current I 1b Used to charge the power management capacitor CC.

[0145] Please refer to Fig.10 , the control switch 112 of the relay circuit CL is turned on to magnetically change the relay switch SW from the first closed state to a second closed state. During the rotation of the switch arm 128, there is a period of several tens of milliseconds in which the common contact point 122 is not connected to either the normally closed contact point 124 or the normally open contact point 126. At this time, the power management capacitor CC is discharged to provide a current I c to the electronic component 102 .

[0146] Please refer to Figures 8 to 11In step S105, the relay system RS is operated in the second closed state to apply the second power supply P2 to the electronic component 102. In particular, the electronic component 102 is connected to the second power supply P2 so that the second supply voltage Vdd-2 is applied to the electronic component 102. At this time, the electronic component 102 is electrically coupled to the second power supply P2 via the common contact point 122, the switch arm 128, and the normally open contact point 126. Therefore, a second current I2 driven by the potential difference between the second power supply P2 and the electronic component 102 flows from the second power supply P2. After passing through the relay switch SW, the second current I2 is divided into a current I 2a and a current I 2b , current I 2a is flowing to the electronic component 102, the current I 2b is flowing to the power management capacitor CC. In some embodiments, the power supply I 2a For starting the test of the electronic component 102, and the power supply I 2b Used to charge the power management capacitor CC.

[0147] Please refer to Fig.12 , the control switch 112 of the relay circuit CL is turned off, causing the relay switch SW to magnetically change from the second closed state to the first closed state. At this time, there is also a time in which the common contact point 122 is not connected to either the normally closed contact point 124 or the normally open contact point 126. Therefore, during the rotation of the switch arm 128, the power management capacitor CC is discharged again to provide the current I c to the electronic component 102. Figure 8 After step S105, a first cycle including step S101 to step S105 has been completed. In some embodiments, the complete test method 200 may include multiple cycles of repeating step S103 to step S105.

[0148] Figure 13 to Figure 15 In some embodiments of the present disclosure, Figure 8 Schematic diagram of different operating states of the test method 200 in FIG. Figure 13 to Figure 15 , the y-axis shows a supply voltage (V) applied to the electronic component 102 and a state of the control switch 112, and the x-axis shows time (milliseconds).

[0149] Please refer to Fig.13In some embodiments, when the electronic component 102 is tested, the first supply voltage Vdd-1 is set to 102V, and the second supply voltage Vdd-2 is set to 1.0V. The second supply voltage Vdd-2 can be set to any voltage lower than 1.2V to check the degree of power supply drop that the electronic component 102 can withstand. In some embodiments, Figure 7 As shown, the microcontroller MC is electrically coupled to the control switch 112 to control the time interval of an on state or an off state of the control switch 112. First, the control switch 112 is closed at time t0. During the first high power time interval t0 to t1, the relay switch SW is maintained in the first off state, and a 1.2V voltage is applied to the electronic component 102. At time t1, the control switch 112 is turned on to pull the relay switch SW from the first off state to the second off state. The magnetization of the magnetizing coil 120 and the rotation of the switch arm 128 require many milliseconds. The change of the electronic component 102 from connecting to the first power supply P1 to connecting to the second power supply P2 takes a corresponding time interval. Therefore, after time t1, the voltage applied to the electronic component 102 is reduced from 1.2V to 1.0V in a very short time t2. In some embodiments, a power drop slope S1 is defined as: It can be adjusted according to the test requirements. In addition, the power drop slope S1 can be designed to be large enough, and thus a sudden drop in the power supplied to the electronic component 102 is applied to verify the robustness of the electronic component 102. During a first low power time interval t2 to t3, the control switch 112 is maintained on, and the relay switch SW is in the second off state. At time t3, the control switch 112 is closed. At time t4, i.e., shortly after time t3, the voltage applied to the electronic component 102 is increased from 1.0V back to 1.2V. In some embodiments, a power increase slope S2 is defined as: It can be adjusted according to the test requirements. In addition, the power supply rising slope S2 can be designed to be large enough, and thus a sudden rise in the power supplied to the electronic component 102 is applied to verify the robustness of the electronic component 102. During a second high power time interval t4 to t5, the control switch 112 remains off, and the relay switch SW is in the first closed state. At time t5, the control switch 112 is turned on again. At time t6, i.e., shortly after time t5, the voltage applied to the electronic component 102 is reduced from 1.2V back to 1.0V. During a second low power time interval t6 to t7, the control switch 112 is maintained on, and the relay switch SW is in the second closed state. Usually, the aforementioned steps are repeated until the test is completed. Therefore, each sudden drop of the power supply can be repeatedly applied to test the endurance of the electronic component 102.

[0150] Please still refer to Fig.13 In some embodiments, the first high power time interval t0 to t1, the second high power time interval t4 to t5, and similar time intervals thereof have the same first duration t a In some embodiments, the first low power time interval t2 to t3, the second low power time interval t6 to t7, and similar time intervals have the same second duration t b In some embodiments, the first duration t a With the second duration t b is through the microcontroller MC (such as Figure 7 In some embodiments, the first duration t a is much longer than the second duration t b , because the high power time interval represents a period of normal power supply simulated by the first supply voltage Vdd-1, and the low power time interval represents a short period of abnormal power supply simulated by the second supply voltage Vdd-2. In some embodiments, a period between the first high power time interval t0 to t1 and the first low power time interval t2 to t3 has a third duration t c , so that the relay switch SW operates in the open state. In addition, the third duration t c Less than the first duration t a and the second duration t b According to the present disclosure, the voltage input to the electronic component 102 is alternated between 1.2V and 1.0V to simulate a variation in supply voltages experienced by a memory chip in actual use.

[0151] Although a memory chip rarely encounters a power spike, the method 200 can be used to simulate multiple spikes in the power supplied to the electronic component 102. Fig.14 In some embodiments, when the electronic component 105 is tested, the first supply voltage Vdd-1 is set to 1.2V, and the second supply voltage Vdd-2 is set to 1.4V. In some embodiments, the second supply voltage Vdd-2 can be set to any voltage above 1.2V to test the degree of power supply increase that the electronic component 102 can withstand. First, the control switch 112 is closed at time t0'. During a first low power time interval t0' to t1', the relay switch SW is maintained in the first closed state, and a 1.2V voltage is applied to the electronic component 102. At time t1', the control switch 112 is turned on to pull the relay switch SW from the first closed state to the second closed state. Therefore, at time t2' shortly after time t1', the voltage applied to the electronic component 102 rises from 1.2V to 1.4V. During a first high power time interval t2' to t3', the control switch 112 is maintained in conduction (on), and the relay switch SW is in the second closed state. At time t3', the control switch 112 is closed. At a time t4', i.e., shortly after time t3', the voltage applied to the electronic component 102 is reduced from 1.4V back to 1.2V. During a second low power time interval t4' to t5', the control switch 112 is maintained off, and the relay switch SW is in the first closed state. At time t5', the control switch 112 is turned on again. At time t6', i.e., shortly after time t5', the voltage applied to the electronic component 102 is increased from 1.2V back to 1.4V. During a second low power time interval t6' to t7', the control switch 112 is maintained on, and the relay switch SW is in the second closed state. Typically, the aforementioned steps are repeated until the test is completed. Therefore, each sudden rise of the power supply can be repeatedly applied to test the endurance of the electronic component 102.

[0152] Please still refer to Fig.14 In some embodiments, the first low power time interval t0' to t1', the second low power time interval t4' to t5' and similar time intervals have the same first duration t a In some embodiments, the first high power time interval t2' to t3', the second high power time interval t6' to t7' and similar time intervals have the same second duration t b '. In some embodiments, the first duration t a ' and the second duration t b' is through the microcontroller MC (such as Figure 7 In some embodiments, the first duration t a ' is much longer than the second duration t b '.

[0153] In some embodiments, Figure 7 As shown, multiple instructions can be given to the microcontroller MC to control the duration of each of the high power time intervals and the low power time intervals. Fig.15 The embodiment shown is similar to Fig.13 In the illustrated embodiment, the high power time intervals (i.e., the time intervals during which the 1.2V voltage is applied to the electronic component 102) have different durations, such as t a1 ,t a2 ,t a3 or similar durations, and the low power time intervals (ie, the time intervals during which 1.0 V voltage is applied to the electronic component 102) have different durations, such as t b1 ,t b2 ,t b3 Or a similar duration. In some embodiments, the duration t a1 ,t a2 ,t a3 or similar time intervals may be the same as or different from each other, and the duration t b1 ,t b2 ,t b3 or similar durations may be the same as or different from each other. Therefore, when the electronic component 102 is under test, the first duration t a1 ,t a2 ,t a3 , the second duration t b1 ,t b2 ,t b3 And similar durations form a more realistic simulation. In addition, according to the microcontroller MC, when a memory chip provides multiple functions simultaneously, the electronic component 102 can test the memory chip according to a simulation of an unstable power supply.

[0154] Existing automatic test equipment (ATE) cannot accurately reflect the change of the power supply input to the electronic component, so it is impossible to screen out the problematic electronic components in the verification stage. The present disclosure provides a functional test device. The functional test device mainly has a relay system and a pair of power supplies. The pair of power supplies provides a pair of different supply voltages to an electronic component (DUT), and the electronic component is placed in the functional test device. The combination of the relay system and the pair of power supplies is to perform a test on the electronic component to simulate multiple conditions, which are various conditions that a memory chip may encounter in actual use. For example, the pair of different supply voltages input to the electronic component simulates a change of each supply voltage encountered by the memory chip. In this test, the power supplied to the electronic component suddenly drops in order to verify the robustness or endurance of the electronic component. Therefore, according to the present disclosure, a more realistic simulation can be achieved when testing the DUT. Therefore, according to the present disclosure, a more realistic simulation can be achieved when testing the electronic component. Additionally, a microcontroller in a relay system can be used as a timing programmer, which controls the duration of the period during which power is supplied to the electronic components.

[0155] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements can be made without departing from the concept and scope of the present disclosure defined by the claims. For example, many of the above processes can be implemented in different ways, and other processes or combinations thereof can be used to replace many of the above processes.

[0156] Furthermore, the scope of the present disclosure is not limited to the specific embodiments of the processes, machines, manufactures, material compositions, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, material compositions, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, material compositions, means, methods, or steps are included in the claims of the present disclosure.

Claims

1. A functional testing device for electronic components, comprising: a first power supply configured to generate a first supply voltage; a second power supply configured to generate a second supply voltage different from the first supply voltage; as well as a relay system configured to electrically couple the first power supply or the second power supply to the electronic component, wherein the first supply voltage is applied to the electronic component for a first duration, the second supply voltage is applied to the electronic component for a second duration, and the second duration is less than the first duration, The relay system includes a relay and a microcontroller, wherein the relay is composed of a relay switch and a magnetizing coil, the magnetizing coil is magnetically coupled to the relay switch, and the microcontroller is configured to control multiple operations of the relay switch; The relay system further comprises a power source and a control switch, the control switch being inserted between the power source and the magnetizing coil, wherein the microcontroller is configured to close or open the control switch to control the operation of the relay switch; The functional test device further comprises a power management capacitor, wherein one terminal of the power management capacitor is electrically coupled to the relay switch and the electronic component, and another terminal of the power management capacitor is grounded, wherein when the relay system couples the first power supply to the electronic component, the power management capacitor is charged by the first supply voltage; when the relay system couples the second power supply to the electronic component, the power management capacitor is charged by the second supply voltage; And when the relay system does not couple the first power supply or the second power supply to the electronic component, the power management capacitor is discharged to power the electronic component.

2. The functional testing device as claimed in claim 1, wherein the functional testing device is provided with a plurality of data lines, a plurality of address lines and a plurality of control lines, and the plurality of data lines, the plurality of address lines and the plurality of control lines are electrically coupled to the electronic component. 3 . The functional testing device as claimed in claim 1 , wherein the microcontroller is configured to control a first time interval of an off state of the control switch and a second time interval of an on state of the control switch.

4. A functional testing device as described in claim 1, wherein the relay switch includes a common contact point, a normally closed contact point, a normally open contact point and a switch arm, the common contact point is electrically coupled to the electronic component, the normally closed contact point is electrically coupled to the first power supply, and the normally open contact point is electrically coupled to the second power supply, wherein the switch arm is spring-loaded by the common contact point and connects the common contact point to the normally closed contact point. 5 . The functional testing apparatus of claim 4 , wherein when the switch arm connects the common contact point to the normally closed contact point, the first supply voltage is applied to the electronic component. 6 . The functional testing apparatus of claim 4 , wherein when the switch arm connects the common contact point to the normally open contact point, the second supply voltage is applied to the electronic component.

7. A functional testing device as described in claim 4, wherein when the switch arm connects the common contact point to the normally closed contact point, the power management capacitor is charged through the first power supply; and when the switch arm connects the common contact point to the normally open contact point, the power management capacitor is charged through the second power supply. 8 . The functional testing device of claim 4 , wherein when the switch arm does not connect the common contact point to any one of the normally closed contact point and the normally open contact point, the power management capacitor is discharged to power the electronic component.

9. The functional testing device of claim 4, wherein the power management capacitor has a capacitance value between 20 microfarads and 220 microfarads.

10. A method for testing an electronic component, comprising: Coupling an electronic component to a functional test device, the functional test device comprising a first power supply, a second power supply, a power management capacitor and a relay switch, the relay switch coupled to the electronic component, wherein the first power supply is used to provide a first supply voltage, and the second power supply is used to provide a second supply voltage, and the second supply voltage is different from the first supply voltage; operating the relay switch in a first closed state to apply the first supply voltage to the electronic component; as well as operating the relay switch in a second closed state to apply the second supply voltage to the electronic component; wherein the first supply voltage is applied to the electronic component for a first duration, and the second supply voltage is applied to the electronic component for a second duration, and the second duration is shorter than the first duration, The test method also includes: When the relay switch is operated in the first closed state, charging the power management capacitor with the first supply voltage; When the relay switch is operated in the second closed state, charging the power management capacitor with the second supply voltage; and When the relay switch is operated in an open state, the power management capacitor is discharged to power the electronic component. 11 . The testing method as claimed in claim 10 , wherein a third duration of the relay switch operation in the open state is shorter than the first duration. The testing method as claimed in claim 11 , wherein the third duration is shorter than the second duration. 13 . The testing method of claim 12 , wherein when the relay switch is operated in the open state, the electronic component is not powered by the first supply voltage or the second supply voltage. 14 . The testing method as claimed in claim 13 , wherein the relay switch changes from the first closed state via the open state to the second closed state, and the relay switch changes from the second closed state via the open state to the first closed state. 15 . The testing method of claim 14 , wherein the first duration and the second duration are controlled by a microcontroller, the microcontroller is coupled to the relay switch and a magnetizing coil, the magnetizing coil is magnetically coupled to the relay switch.

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