Method of forming fin structure and method of forming finfet device

Abstract

The application provides a fin structure forming method and a FinFET device forming method, the fin structure forming method comprises the following steps: providing a substrate; forming a first dielectric layer to fill the space between fins in a fin group and the surface of the substrate; forming a second dielectric layer to fill the fin group and cover the first dielectric layer; etching the second dielectric layer between the fin group to form a groove; forming a third dielectric layer to fill the groove, the first dielectric layer and the second dielectric layer have opposite types of stress; performing a heat treatment process to form an isolation dielectric layer and remove part of the thickness of the isolation dielectric layer to expose part of the fins as a fin structure. In the application, the first dielectric layer, the second dielectric layer and the third dielectric layer fill the space between the fin group, the first dielectric layer and the second dielectric layer have opposite types of stress and the stress of the third dielectric layer is smaller than that of the first dielectric layer and the second dielectric layer, so as to balance the stress between the fin group, reduce the stress difference on both sides of the fin and prevent the deformation of the fin.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit manufacturing technology, and particularly relates to a fin structure forming method and a FinFET device forming method. BACKGROUND

[0002] With the continuous development of semiconductor technology, the traditional planar device has been difficult to meet the demand of people for high performance device. Fin-Field-Effect-Transistor (FinFET) is a three-dimensional device, including a fin vertically formed on a substrate and a gate structure covering both sides of the fin, which can greatly improve the circuit control and reduce the leakage current, and also can greatly shorten the gate length of the transistor.

[0003] However, in the process of forming the fin structure (fin) of the FinFET device, the fin is prone to deformation (bending or tilting), which is not conducive to the subsequent process (such as the formation of the source-drain structure in the fin and the formation of the gate structure on the fin), and also leads to the leakage between the gate and the source-drain, which seriously affects the performance and reliability of the FinFET device. SUMMARY

[0004] The purpose of the present application is to provide a fin structure forming method and a FinFET device forming method to solve the problem of fin structure tilting or bending.

[0005] To solve the above technical problems, the fin structure forming method provided by the present application comprises: providing a substrate, the substrate has at least two spaced fin groups, each of the fin groups comprises at least two spaced fins, the spacing between the fin groups is greater than the spacing between the fins in the fin group; forming a first dielectric layer, the first dielectric layer fills between the fins in the fin group and covers the surface of the fin and the substrate; forming a second dielectric layer, the second dielectric layer fills between the fin groups and covers the surface of the first dielectric layer; performing etching process to form a trench in the second dielectric layer between the fin groups; forming a third dielectric layer, the third dielectric layer fills the trench, the first dielectric layer and the second dielectric layer have opposite types of stress, the stress of the third dielectric layer is less than the stress of the first dielectric layer and the stress of the second dielectric layer; performing heat treatment process to form the third dielectric layer, the second dielectric layer and the first dielectric layer into an isolation dielectric layer, and removing part of the thickness of the isolation dielectric layer to expose part of the fin as a fin structure.

[0006] Optionally, the material of the first dielectric layer, the second dielectric layer and the third dielectric layer includes one or more of silicon oxide, silicon oxynitride and silicon oxycarbide.

[0007] Optionally, the first, second and third dielectric layers all include silicon oxide and are formed by different processes.

[0008] Optionally, the first dielectric layer is formed by FCVD with ozone treatment, the second dielectric layer is formed by FCVD with ultraviolet treatment, or the first dielectric layer is formed by FCVD with ultraviolet treatment and the second dielectric layer is formed by FCVD with ozone treatment.

[0009] Optionally, after the second dielectric layer is formed on the first dielectric layer and before the third dielectric layer is formed, the method further includes: forming a fourth dielectric layer covering the second dielectric layer, and the third dielectric layer covering the fourth dielectric layer; and performing a planarization process on the fourth dielectric layer.

[0010] Optionally, the step of forming the trench in the second dielectric layer between the fin groups includes: forming a mask layer having an opening at least partially exposing the fourth dielectric layer between the fin groups; etching the fourth dielectric layer and a portion of the second dielectric layer to form the trench using the mask layer; and removing the mask layer.

[0011] Optionally, the fourth dielectric layer and the third dielectric layer are formed by the same process under the same process conditions.

[0012] Optionally, the cross-sectional shape of the trench is an inverted trapezoid.

[0013] Optionally, the process gas used in the thermal treatment process includes one or more of water vapor, hydrogen, oxygen and nitrogen.

[0014] Based on another aspect of the present application, the embodiments of the present application further provide a method for forming a FinFET device, which includes the method for forming a fin structure as described above.

[0015] In summary, the method for forming a fin structure and the method for forming a FinFET device provided by the present application fill the first dielectric layer between the fin pieces in a fin group and partially fill the space between the fin groups, then fill the second and third dielectric layers between the fin groups, balance the stresses of the first, second and third dielectric layers between the fin groups after thermal treatment to achieve stress balance between the fin groups, thereby reducing the stress difference on both sides of the fin pieces and preventing the fin pieces from deforming, and further solving the problem of fin structure tilting or bending. BRIEF DESCRIPTION OF DRAWINGS

[0016] Those skilled in the art will understand that the drawings provided herein are for illustrative purposes and are not limiting of the scope of the application.

[0017] Figure 1 is a flowchart of a method for forming a fin structure provided in the present embodiment;

[0018] Figures 2a to 2h The corresponding structure schematic diagram corresponding to the respective steps of the method for forming a fin structure provided in the present embodiment.

[0019] In the drawings:

[0020] 10 - substrate; 11 - fin group; 111 - fin;

[0021] 21 - first dielectric layer; 22 - second dielectric layer; 23 - third dielectric layer; 24 - fourth dielectric layer; 25 - mask layer; 26 - trench;

[0022] 30 - isolation dielectric layer. DETAILED DESCRIPTION

[0023] In order to make the objects, advantages and features of the present application clearer, the following further describes the present application in conjunction with the drawings and specific embodiments. It should be noted that the drawings are all very simplified and not drawn to scale, and are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the present application. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different scales are sometimes used in the drawings to show different focuses.

[0024] As used in the present application, the singular forms "a", "an" and "the" include plural referents, the term "or" is generally used in the sense of "and / or", the term "several" is generally used in the sense of "at least one", the term "at least two" is generally used in the sense of "two or more", and in addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second", "third" can explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0025] Figure 1 is a flowchart of a method for forming a fin structure provided in the present embodiment.

[0026] As Figure 1 shown, the method for forming a fin structure provided in the present embodiment includes the following steps:

[0027] S01: A substrate is provided, the substrate having at least two spaced-apart fin groups, each fin group including at least two spaced-apart fins, the spacing between the fin groups being greater than the spacing between the fins within the fin group;

[0028] S02: Forming a first dielectric layer, the first dielectric layer filling between the fins in the fin group and covering the surfaces of the fins and the substrate;

[0029] S03: Form a second dielectric layer, which fills the spaces between the fins and covers the surface of the first dielectric layer;

[0030] S04: Perform an etching process to form trenches in the second dielectric layer between the fins;

[0031] S05: Form a third dielectric layer, the third dielectric layer filling the trench, the first dielectric layer and the second dielectric layer having opposite types of stress, the stress of the third dielectric layer being less than the stress of the first dielectric layer and the stress of the second dielectric layer;

[0032] S06: Perform a heat treatment process to form the third dielectric layer, the second dielectric layer, and the first dielectric layer into an isolation dielectric layer, and remove a portion of the thickness of the isolation dielectric layer to expose a portion of the fins as a fin structure.

[0033] Figures 2a to 2h The structural diagrams corresponding to the steps of the fin structure formation method provided in this embodiment are shown below. Next, we will combine... Figures 2a to 2h The method for forming the fin structure is described in detail.

[0034] First, please refer to Figure 2a In step S01, a substrate 10 is provided, on which at least two spaced-apart fin groups 11 are provided, each fin group 11 including at least two spaced-apart fins 111, the spacing between the fin groups 11 being greater than the spacing between the fins 111 within the fin group 11.

[0035] The substrate 10 can be any suitable substrate material well known to those skilled in the art, such as at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). In this embodiment, silicon is used as an example to illustrate the material of the substrate 10.

[0036] Specifically, a plurality of fins 111 can be formed on the surface of the substrate 10 by using a self-aligned multiple patterning technique, and a hard mask layer (not shown in the figure) is reserved on the top wall of the fins 111. The distance between the fins 111 in the fin group 11 and the specific distance between the fin groups 11 can be determined according to actual needs, and is not limited by the distance between the fins 111. In the embodiment, two fin groups 11 are located on the substrate 10, each of which includes four fins 111, and the distance between the fin groups 11 is greater than the distance between the fins 111 in the fin group 11. Of course, the number of fins 111 in different fin groups 11 can also be different in practice.

[0037] Next, referring to Figure 2b , step S02 is performed to form a first dielectric layer 21, which fills between the fins 111 in the fin group 11 and covers the surface of the fins 111 and the substrate 10.

[0038] Specifically, the first dielectric layer 21 has a good step coverage and can conformally cover the outer wall of the fins 111 and the surface of the substrate 10, and fill in the fin group 11 and between the fin groups 11. In a specific implementation, since the distance between the fins 111 in the fin group 11 is relatively small compared to the distance between the fin groups 11, the filling amount and filling rate of the first dielectric layer 21 can be controlled to fill the first dielectric layer 21 between the fins 111 in the fin group 11 and partially fill between the fin groups 11 (cover the surface of the substrate 10). The depth of the first dielectric layer 21 partially filling between the fin groups 11 can be specifically set in combination with the height at which the fins 111 begin to deform (bend or tilt) in the actual process, so that the filling depth is lower than or equal to the height at which the fins 111 begin to deform in the actual process, so as to improve the morphology of the fins 111 by the stress on both sides of the fins 111.

[0039] Among them, the first dielectric layer 21 can be formed by using an ozone solidification FCVD (Ozone FCVD) process or an ultraviolet solidification FCVD (UV cure FCVD) process to improve its filling effect, and the material of the first dielectric layer 21 includes silicon oxide, silicon oxynitride or silicon oxycarbide.

[0040] Next, referring to Figure 2c , step S03 is performed to form a second dielectric layer 22, which fills between the fin groups 11 and covers the surface of the first dielectric layer 21.

[0041] Among them, the material and forming process of the second dielectric layer 22 can be selected to make the second dielectric layer 22 (after solidification) have a stress of the opposite type to that of the first dielectric layer 21 (after solidification), so as to balance the stress of the first dielectric layer 21 and the second dielectric layer 22 between the fin groups 11.

[0042] Preferably, the second dielectric layer 22 is formed of the same material as the first dielectric layer 21 but by a different process so as to have different stress and can be etched simultaneously with the first dielectric layer 21 by an etching process to simplify the subsequent process steps. In the present embodiment, if the first dielectric layer 21 is formed of silicon oxide by an ozone curing FCVD process, the second dielectric layer 22 can be formed of silicon oxide by an ultraviolet curing FCVD process; if the first dielectric layer 21 is formed of silicon oxide by an ultraviolet curing FCVD process, the second dielectric layer 22 can be formed of silicon oxide by an ozone curing FCVD process. It should be understood that the first dielectric layer 21 formed by the ozone curing FCVD process (after curing) has tensile stress and the second dielectric layer 22 formed by the ultraviolet curing FCVD process (after curing) has compressive stress.

[0043] Next, referring to Figure 2d , a fourth dielectric layer 24 is formed covering the second dielectric layer 22 and a planarization process is performed on the fourth dielectric layer 24.

[0044] The fourth dielectric layer 24 is planar and serves as a platform for subsequent processes so as to facilitate the performance of corresponding photolithography and etching processes. Preferably, the fourth dielectric layer 24 can be formed of silicon oxide by a PECVD process to facilitate subsequent etching. It should be understood that the second dielectric layer 22 fills the spaces between the fin groups 11 and the top surface thereof is not planar, which is not conducive to the performance of subsequent photolithography and etching processes. Of course, in other embodiments, the fourth dielectric layer 24 can not be formed and the second dielectric layer 22 is preliminarily cured and a planarization process is performed on the preliminarily cured second dielectric layer 22 to facilitate subsequent photolithography and etching processes.

[0045] Next, step S04 is performed, referring to Figure 2e , an etching process is performed to form trenches 26 in the second dielectric layer 22 between the fin groups 11.

[0046] The specific steps can include, for example, forming a mask layer 25 on the fourth dielectric layer 24, the openings of the mask layer 25 exposing the fourth dielectric layer 24 between the fin groups 11, etching the fourth dielectric layer 24 and the second dielectric layer 22 by using the mask layer 25 to form the trenches 26 in the second dielectric layer 22 between the fin groups 11. The depth of the trenches 26 and the width of the trenches 26 can be adjusted according to the deformation degree of the actual fin to adjust the volume ratio of the first dielectric layer 21 between the fin groups 11, the second dielectric layer 22 remaining between the fin groups 11 after the formation of the trenches 26, and the third dielectric layer to be filled in the trenches 26 so as to achieve stress balance between the fin groups 11.

[0047] Preferably, the cross-sectional shape of the trenches 26 is inverted trapezoidal (wide at the top and narrow at the bottom) to facilitate the subsequent filling of the third dielectric layer.

[0048] Next, step S05 is performed, please refer to Figure 2f , the third dielectric layer 23 is formed to fill the trench 26, the first dielectric layer 21 and the second dielectric layer 22 have opposite types of stress, and the stress of the third dielectric layer 23 is smaller than the stress of the first dielectric layer 21 and the second dielectric layer 22.

[0049] Specifically, the mask layer 25 on the fourth dielectric layer 24 can be removed first, and then the third dielectric layer 23 is formed to fill the trench 26, cover the second dielectric layer 22, and extend to cover the fourth dielectric layer 24.

[0050] The third dielectric layer 23 fills the trench 26 between the fin groups 11, and the stress of the third dielectric layer 23 is smaller than the stress of the first dielectric layer 21 and the stress of the second dielectric layer 22, which is used to adjust the volume ratio of the first dielectric layer 21 and the second dielectric layer 22 between the fin groups 11, so as to achieve stress balance between the fin groups 11 by using the different stress types of the first dielectric layer 21 and the second dielectric layer 22 and the smaller stress of the third dielectric layer 23, and further prevent the fins 111 in the fin group 11 from being deformed (bent or tilted) due to the stress imbalance between the fin groups 11.

[0051] Further, the material and forming process (process conditions) of the third dielectric layer 23 can be the same as those of the fourth dielectric layer 24, so as to facilitate subsequent etching.

[0052] Further, the material of the third dielectric layer 23 can be the same as that of the first dielectric layer 21 and the second dielectric layer 22, but the forming process is different, so as to facilitate subsequent etching. In this embodiment, the material of the third dielectric layer 23 is silicon oxide, which can be formed by PECVD process or HARP (High Aspect Ratio Process) process. It should be understood that the silicon oxide formed by PECVD process or HARP process has a smaller expansion rate after heat treatment, that is, has a smaller stress.

[0053] Next, step S06 is performed, please refer to Figure 2g and Figure 2h , a heat treatment process is performed to form the third dielectric layer 23, the second dielectric layer 22, the first dielectric layer 21 and the fourth dielectric layer 24 into an isolation dielectric layer 30, and part of the thickness of the isolation dielectric layer 30 is removed to expose part of the fins 111 as a fin structure.

[0054] Specifically, the process gas used in the heat treatment process (annealing process) includes one or more of water vapor, hydrogen, oxygen, and nitrogen, so that the first dielectric layer 21 and the second dielectric layer 22 formed by different FCVD can be solidified in the heat treatment process, and thus the stress balance between the fin groups 11 is achieved. Moreover, after the heat treatment process, the material of the first dielectric layer 21 and the second dielectric layer 22 (for example, silicon oxide mixture) is converted into silicon dioxide which is the same as (or similar to) the material of the fourth dielectric layer 24 and the third dielectric layer 23, so as to form the isolation dielectric layer 30. Thus, the isolation dielectric layer 30 can be removed by dry etching to expose part of the fin 111, and the exposed part of the fin 111 is used as the fin structure.

[0055] The embodiment of the present application also provides a method for forming a FinFET device including a fin structure, and the method for forming the FinFET device includes the method for forming the fin structure as described above, i.e., the method for forming the FinFET device includes the method for forming the fin structure as described above.

[0056] In summary, the method for forming a fin structure and the method for forming a FinFET device provided by the present application fill the first dielectric layer between the fins in the fin group and partially fill the space between the fin groups, and then fill the second dielectric layer and the third dielectric layer between the fin groups. The first dielectric layer and the second dielectric layer have opposite types of stress, and the stress of the third dielectric layer is smaller than that of the first dielectric layer and the second dielectric layer. After heat treatment, the stress of the first dielectric layer, the second dielectric layer, and the third dielectric layer between the fin groups is balanced to achieve stress balance between the fin groups, thereby reducing the stress difference on both sides of the fin and preventing the fin from deforming, and further solving the problem of tilting or bending of the fin structure.

[0057] The above description is only a description of the preferred embodiments of the present application, and does not limit the scope of the present application in any way. Any modification or change made by a person of ordinary skill in the art based on the above disclosure is within the scope of protection of the claims.

Claims

1. A method of forming a fin structure, the method comprising: The method comprises: providing a substrate having at least two spaced-apart fin groups on the substrate, each of the fin groups comprising at least two spaced-apart fins, the spacing between the fin groups being greater than the spacing between the fins within the fin groups; forming a first dielectric layer filling the space between the fins within the fin groups and covering the surfaces of the fins and the substrate; forming a second dielectric layer filling the space between the fin groups and covering the surfaces of the first dielectric layer; performing an etching process to form a trench in the second dielectric layer between the fin groups; forming a third dielectric layer filling the trench, the first dielectric layer and the second dielectric layer having opposite types of stress, the third dielectric layer having a stress smaller than the stress of the first dielectric layer and the stress of the second dielectric layer; performing a thermal treatment process to form the third dielectric layer, the second dielectric layer and the first dielectric layer into an isolation dielectric layer and removing a portion of the thickness of the isolation dielectric layer to expose a portion of the fins as a fin structure.

2. The method of claim 1, wherein The materials of the first dielectric layer, the second dielectric layer and the third dielectric layer comprise one or more of silicon oxide, silicon oxynitride and silicon oxy-carbide.

3. The method of claim 2, wherein The materials of the first dielectric layer, the second dielectric layer and the third dielectric layer all comprise silicon oxide and are formed using different processes.

4. The method of claim 3, wherein The first dielectric layer is formed using an FCVD process with ozone treatment, the second dielectric layer is formed using an FCVD process with ultraviolet treatment, or the first dielectric layer is formed using an FCVD process with ultraviolet treatment and the second dielectric layer is formed using an FCVD process with ozone treatment.

5. The method of claim 1, wherein After forming the second dielectric layer on the first dielectric layer and before forming the third dielectric layer, the method further comprises: forming a fourth dielectric layer covering the second dielectric layer, the third dielectric layer covering the fourth dielectric layer; and performing a planarization process on the fourth dielectric layer.

6. The method of claim 5, wherein The step of forming a trench in the second dielectric layer between the fin groups comprises: forming a mask layer having openings at least partially exposing the fourth dielectric layer between the fin groups; using the mask layer, etching the fourth dielectric layer and a portion of the thickness of the second dielectric layer to form the trench; and removing the mask layer.

7. The method of claim 6, wherein The fourth dielectric layer and the third dielectric layer have the same material and are formed using the same process conditions.

8. The method of claim 1-7, wherein The cross-sectional shape of the trench is an inverted trapezoid.

9. The method of claim 1-7, wherein The process gas used in the thermal treatment process comprises one or more of water vapor, hydrogen, oxygen and nitrogen.

10. A method of forming a FinFET device, comprising: The method of forming the FinFET device comprises the method of forming the fin structure as claimed in any one of claims 1 to 9.

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