Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same are disclosed. The method includes: providing a substrate and a channel structure discretely disposed on the substrate, and a capping layer on the substrate located on a side portion of the channel structure; forming an opening through the capping layer between adjacent channel structures, the bottom of the opening exposing the substrate; and forming a conductive layer on the top surface of the substrate at the bottom of the opening for use as a resistive structure. This embodiment of the invention fabricates the resistive structure on the top surface of the substrate between adjacent channel structures. This not only liberates the resistive structure from the interlayer dielectric layer in the middle or later stages of the semiconductor structure, thereby reducing the height of metal interconnects and conductive plugs and achieving optimized middle-stage RC (resistance-capacitance) and thus optimizing the performance of the semiconductor structure, but also reduces the area of ​​the HiR circuit by forming the resistive structure on the top surface of the substrate between adjacent channel structures, thus meeting the requirements for device miniaturization.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] In semiconductor manufacturing processes, the resistive structure formed by the HiR (High-Resistor) layer can divide voltage and limit current, and is therefore widely used in analog circuits.

[0003] In traditional planar transistor manufacturing processes, the HiR layer is mainly formed using high-resistance polysilicon (HRP), which involves ion doping of the polysilicon (Poly) (e.g., through ion implantation) to adjust the required resistance value. The doped polysilicon is then connected through contact plugs (CT) to form a resistive structure.

[0004] As the feature size of integrated circuits continues to shrink, semiconductor processes are gradually transitioning from planar transistors to three-dimensional transistors with higher efficiency, such as FinFETs, to accommodate these smaller feature sizes. In FinFET processes, because polysilicon gates are replaced by high-k metal gates (HKMG), traditional HRPs cannot be used to fabricate HiR resistors. Therefore, TIN (titanium nitride) thin films are used to fabricate HiR resistors.

[0005] For example, a TIN resistive film is typically formed in the inter-layer dielectric (ILD) layer where M0 (Metal 0) is located. Then, when forming the interconnect (MOG) that contacts the gate, an interconnect electrically connected to the TIN resistive film is also formed, thus connecting the TIN resistive film through the interconnect to form a resistive structure. Here, M0 refers to the metal line closest to the gate or source / drain doped layer.

[0006] However, fabricating HiR in the intermetallic dielectric layer can easily lead to poor device performance. Summary of the Invention

[0007] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and its formation method, which is beneficial for optimizing the mid-section RC and reducing the area of ​​the HiR circuit.

[0008] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate and a channel structure discretely disposed on the substrate, and a capping layer on the substrate located on the side of the channel structure; forming an opening through the capping layer between adjacent channel structures, the bottom of the opening exposing the substrate; and forming a conductive layer on the top surface of the substrate at the bottom of the opening for use as a resistive structure.

[0009] Accordingly, embodiments of the present invention also provide a semiconductor structure, including: a substrate; a channel structure disposed on the substrate; and a conductive layer located on the top surface of the substrate between adjacent channel structures, wherein the conductive layer is used as a resistive structure.

[0010] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0011] In the semiconductor structure formation method provided by the embodiments of the present invention, after forming a capping layer, an opening is formed in the capping layer between adjacent channel structures, the bottom of the opening exposes the substrate, and then a conductive layer is formed on the top surface of the substrate at the bottom of the opening to serve as a resistive structure. Compared with fabricating the resistive structure in the interlayer dielectric (IMD) layer where the metal interconnects or conductive plugs are located, the embodiments of the present invention fabricate the resistive structure on the top surface of the substrate between adjacent channel structures. This not only liberates the resistive structure from the interlayer dielectric layer in the middle or later stages, but also reduces the height of the metal interconnects and conductive plugs, thereby obtaining optimized middle-stage RC (resistance-capacitance), and thus optimizing the performance of the semiconductor structure. Moreover, by forming the resistive structure on the top surface of the substrate between adjacent channel structures, the area of ​​the HiR (High-Resistor) circuit can also be reduced, thereby meeting the requirements for device miniaturization. Attached Figure Description

[0012] Figures 1 to 11 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0013] As can be seen from the background technology, current HiR processes tend to lead to poor device performance.

[0014] Specifically, as device dimensions are further miniaturized, and to achieve smaller parasitic capacitance and contact resistance, the height of M0 (Metal 0, the zeroth metal line) gradually decreases, and the thickness of the interlayer dielectric layer containing M0 also gradually decreases. Since the interlayer dielectric layer containing M0 cannot accommodate the HiR layer, a HiR layer is formed in the interlayer dielectric layer containing V0 (Via 0, the first conductive plug). Here, M0 refers to the metal line closest to the gate or source / drain doped region, V0 refers to the conductive plug used to electrically connect M0 and M1 (Metal 1, the first metal line), and M1 refers to the metal line closest to M0.

[0015] After moving the HiR layer from the interlayer dielectric layer where M0 is located to the interlayer dielectric layer where V0 is located, the height of M0 can be reduced. Correspondingly, the RC (resistance-capacitance) of M0 decreases as the height of M0 decreases.

[0016] However, since the interlayer dielectric layer where V0 is located needs to accommodate the HiR layer, the thickness of the interlayer dielectric layer where V0 is located is difficult to reduce. This makes it difficult to reduce the height of V0 as well. Consequently, the current flow path from M1 to M0 is easily increased, which in turn easily increases the RC (resistance-capacitance) delay of V0. As a result, the mid-section RC is not improved, and the device performance is poor. Moreover, the CD of the HiR layer is usually large. Fabricating the HiR layer in the metal interlayer dielectric layer also occupies a lot of chip area, which leads to a waste of circuit area.

[0017] To address the aforementioned technical problems, the semiconductor structure formation method provided in this embodiment of the invention forms a conductive layer on the top surface of the substrate at the bottom of the opening, which serves as a resistive structure. Compared to fabricating the resistive structure in the interlayer dielectric (IMD) layer where the metal interconnects or conductive plugs are located, this embodiment of the invention fabricates the resistive structure on the top surface of the substrate between adjacent channel structures. This not only liberates the resistive structure from the middle or rear section of the interlayer dielectric layer, thereby reducing the height of the metal interconnects and conductive plugs and achieving optimized middle section RC (resistance-capacitance), thus optimizing the performance of the semiconductor structure, but also reduces the area of ​​the HiR (High-Resistor) circuit by forming the resistive structure on the top surface of the substrate between adjacent channel structures, thereby meeting the requirements for device miniaturization.

[0018] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0019] Figures 1 to 11 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0020] refer to Figure 1 and Figure 2 , Figure 1 This is a cross-sectional view. Figure 2 for Figure 1 The corresponding partial top view shows a substrate 100 and a channel structure 110 discretely disposed on the substrate 100, and a capping layer 140 located on the substrate 100 at the side of the channel structure 110. The substrate 100 is used to provide a process platform for subsequent processes.

[0021] In this embodiment, the substrate 100 is a silicon substrate, and the material of the substrate 100 includes silicon. Because the substrate 100 is made of silicon, a conductive layer can be subsequently formed on the top surface of the substrate 100 between adjacent channel structures 110 using a self-aligned metal silicide process, which serves as a resistive structure.

[0022] When the device is operating, the channel structure 110 is used to provide a conductive channel for the transistor. In this embodiment, there are multiple channel structures 110, which are arranged in parallel and spaced apart.

[0023] As an example, the channel structure 110 is a fin. Accordingly, the fin is used to form a fin field-effect transistor (FinFET). In this embodiment, the material of the fin is the same as the material of the substrate 100, which is silicon. In other embodiments, the material of the fin can be other semiconductor materials suitable for forming fins, and the material of the fin can also be different from the material of the substrate.

[0024] In other embodiments, the channel structure is spaced apart from the substrate, and the channel structure includes one or more spaced-apart channel layers. A subsequently formed gate structure covers a portion of the top of the channel structure and surrounds the channel layers. Accordingly, the channel layers are used to form a gate-all-around (GAA) transistor or a forksheet transistor. In the embodiments described, during the steps of providing the substrate and the channel structure discrete on the substrate, one or more spaced-apart sacrificial layers are also formed on the substrate. The sacrificial layers are spaced apart from the channel layers and are located between the channel layers and the substrate or between adjacent channel layers. The sacrificial layers support the channel layers, allowing the channel layers to be suspended after subsequent removal. The sacrificial layers also occupy space for forming the gate structure.

[0025] In this embodiment, during the step of providing the substrate 100, a power track line 120 is further formed in the substrate 100. The power track line 120 has an elongated structure, and the extension directions of the power track line 120 and the channel structure 110 are (e.g., Figure 2 The power track line 120 and the channel structure 110 are parallel to each other (as shown in the X direction), and there is a gap between them.

[0026] Power rails 120 are used to provide power to different components of the chip. In this embodiment, the power rails 120 are located in the substrate 100 and are buried power rails (BPR). This facilitates the freeing up of wiring resources for back-end interconnects and reduces the height of standard cells to meet the needs of continuous logic chip miniaturization. In addition, the buried power rails employ a technique of increasing back-end (BEOL) resistance through pitch miniaturization, which also helps to provide a lower resistance local current distribution.

[0027] In the semiconductor field, it is usually necessary to form a power rail contact plug that contacts the top surface of the power rail line 120. By forming a power rail line 120 in the substrate 100, after the resistor structure located on the top surface of the substrate 100 is formed, the power rail contact plug and the resistor contact plug that contacts the resistor structure can be formed in the same process. That is, the resistor contact plug can be formed using the process of forming the power rail contact plug, so as to electrically connect the resistor structure. Accordingly, there is no need to perform an additional process to form the resistor contact plug. This not only requires less modification to the existing process and helps to reduce process risk, but also helps to improve process integration, simplify the process flow, and thus save costs and improve manufacturing efficiency.

[0028] In this embodiment, the top surface of the power track line 120 is flush with the top surface of the substrate 100, thereby exposing the top surface of the power track line 120 on the substrate 100, so as to facilitate the subsequent formation of a power contact plug that contacts the top surface of the power track line 120.

[0029] The power track 120 is made of a conductive material. In this embodiment, the power track 120 is made of a metallic material, including one or more of Co, W, Ni, and Ru. The low resistivity of the power track 120 material is beneficial for improving RC delay and increasing the chip's processing speed.

[0030] In this embodiment, an insulating layer (not shown) is also formed between the sidewall of the power track line 120 and the substrate 100. The insulating layer is used to achieve insulation between the power track line 120 and the substrate 100. The insulating layer is made of an insulating material, such as silicon oxide, silicon oxynitride, or silicon nitride.

[0031] In this embodiment, a hard mask layer 130 is also formed on the top of the channel structure 110. The hard mask layer 130 serves as an etching mask for forming the channel structure 110. The hard mask layer 130 remains on the top of the channel structure 110 and also protects the top of the channel structure 110 from damage caused by subsequent processes. In this embodiment, the material of the hard mask layer 130 is silicon nitride.

[0032] The capping layer 140 is used to protect the channel structure 110 during the subsequent formation of the opening and the formation of a conductive layer on the top surface of the substrate 100 below the opening.

[0033] In this embodiment, the capping layer 140 is formed on the substrate 100 on the sides of the channel structure 110 and the hard mask layer 130, thereby covering the top and sidewalls of the channel structure 110 to prevent damage to the top and sidewalls of the channel structure 110 in subsequent processes. In this embodiment, the capping layer 140 also covers the power track line 120.

[0034] In this embodiment, the material of the cover layer 140 is a dielectric material. The dielectric material has a certain hardness, which facilitates precise control over the opening size, shape, and cross-sectional morphology quality of the opening 150 in the subsequent step of forming the opening 150 that penetrates the adjacent channel structures 110. Correspondingly, it facilitates precise control over the size and morphology of the subsequent resistor structure. Furthermore, compared to using an organic material for the cover layer, the subsequent process of forming a conductive layer includes a metal layer step. By selecting a dielectric material, it is beneficial to prevent organic contamination in subsequent processes. In addition, by using a dielectric material for the cover layer 140, after the resistor structure is formed, an isolation structure exposing part of the sidewalls of the channel structure 110 can be formed by forming a filling dielectric layer in the opening and then etching back a portion of the filling dielectric layer and the cover layer. This allows the process of forming the resistor structure to be integrated with the process of forming the isolation structure, simplifying the process and improving manufacturing efficiency.

[0035] The material of the capping layer 140 includes one or more of silicon oxide, silicon oxynitride, silicon nitride, amorphous silicon, silicon carbide, silicon oxycarbonate, and silicon carbonitride. In this embodiment, the material of the capping layer 140 is silicon oxide.

[0036] As an example, the steps of providing a substrate 100, a channel structure 110, a cover layer 140, and the power track line 120 include: forming a substrate 100 and a channel structure 110 discrete on the substrate 100; forming a first cover material layer (not shown) on the substrate 100 on the side of the channel structure 110; forming a groove (not shown) penetrating the first cover material layer and a portion of the thickness of the substrate 100, the groove including a bottom groove (not shown) located in the substrate 100 and a top groove (not shown) located on the bottom groove; forming the power track line 120 in the bottom groove; forming a second cover material layer (not shown) on the power track line 120 to fill the top groove, the second cover material layer being used to form the cover layer 140 together with the first cover material layer.

[0037] refer to Figure 3 and Figure 4 , Figure 3 This is a cross-sectional view. Figure 4 for Figure 3 The corresponding partial top view shows an opening 150 through the cover layer 140 between adjacent channel structures 110, with the bottom of the opening 150 exposing the substrate 100.

[0038] The opening 150 is used to define the size, location, and shape of the subsequent resistor structure. The bottom of the opening 150 exposes the substrate 100, allowing a conductive layer to be formed on the substrate 100 at the bottom of the opening 150 as a resistor structure.

[0039] In this embodiment, the opening 150 is an elongated structure, and the extending direction of the opening 150 (e.g., Figure 4 (As shown in the X direction) is parallel to the extension direction of the channel structure 110. The opening 150 is spaced from the channel structure 110, thereby preventing the subsequently formed conductive layer from contacting the channel structure 110, and also helping to prevent damage to the channel structure 110 during the steps of forming the channel structure 110 and the conductive layer.

[0040] In this embodiment, the opening 150 is located in the cover layer 140 between adjacent channel structures 110, and the subsequent conductive layer (i.e., the resistive structure) is also located between adjacent channel structures 110, so that the resistive structure can be formed in the area between adjacent channel structures 110, which is beneficial to saving chip area.

[0041] It should be noted that the size W of the opening 150 is used to define the width of the subsequent resistor structure along the extension direction perpendicular to the channel structure 110. Therefore, the size W of the opening 150 should not be too small or too large. If the size W of the opening 150 is too small, the process precision requirements for forming the opening 150 will be too high, and the difficulty of forming the opening 150 will be too great. Moreover, if the size W of the opening 150 is too small, it is easy to cause the aspect ratio of the opening 150 to be too large, which will make it too difficult to form a conductive layer in the substrate 100 at the bottom of the opening 150. In addition, if the size W of the opening 150 is too small, it is easy to cause the width of the subsequent conductive layer (i.e., the resistor structure) to be too small, which will easily lead to the resistance value of the resistor structure being too large. If the size W of the opening 150 is too large, it is easy to increase the risk of the opening 150 exposing the channel structure 110 or causing damage to the channel structure 110. It is also easy to cause the distance between the subsequent resistor structure and the channel structure 110 to be too close, which will easily increase the probability of short circuit between the resistor structure and the channel structure 110. At the same time, if the size W of the opening 150 is too large, it is easy to cause the resistor structure to occupy too much area. In addition, if the size W of the opening 150 is too large, it is easy to cause the width of the resistor structure to be too large, which will lead to the resistance value of the resistor structure being too small. Therefore, in this embodiment, the size W of the opening 150 is 50 nanometers to 1000 nanometers along the extension direction perpendicular to the channel structure 110.

[0042] In this embodiment, the step of forming the opening 150 includes: forming a patterned layer (not shown) on the cover layer 140 and the hard mask layer 130, wherein a patterned opening (not shown) is formed in the patterned layer above the region between adjacent channel structures 110; using the patterned layer as a mask, etching the cover layer 140 along the patterned opening; and removing the patterned layer.

[0043] In this embodiment, the material of the pattern layer includes photoresist, and the process of forming the pattern layer includes photolithography processes such as exposure and development.

[0044] In this embodiment, an anisotropic dry etching process is used to etch the capping layer 140 between adjacent channel structures 110 to form the opening 150. The anisotropic dry etching process has the characteristics of anisotropic etching, with high etching accuracy and high control over the etching profile, which is beneficial to improving the accuracy of pattern transfer and correspondingly helps to ensure that the size and morphology of the opening 150 meet the process requirements.

[0045] In this embodiment, one or both of the ashing process and the wet desmearing process are used to remove the graphic layer.

[0046] refer to Figure 5 and Figure 6 , Figure 5 This is a cross-sectional view. Figure 6 for Figure 5In the corresponding partial top view, a conductive layer is formed on the top surface of the substrate 100 at the bottom of the opening 150, which serves as a resistive structure 200.

[0047] By forming a conductive layer on the top surface of the substrate 100 at the bottom of the opening 150 to serve as a resistor structure 200, compared to fabricating the resistor structure in the interlayer dielectric (IMD) layer where the metal interconnects or conductive plugs are located, this embodiment fabricates the resistor structure 200 on the top surface of the substrate 100 between adjacent channel structures 110. This not only liberates the resistor structure 200 from the middle or rear section of the interlayer dielectric layer, but also reduces the height of the metal interconnects and conductive plugs, thereby obtaining an optimized middle section RC (resistance-capacitance), and thus optimizing the performance of the semiconductor structure, but also utilizes the area between adjacent channel structures 110 by forming the resistor structure 200 on the top surface of the substrate 100 between adjacent channel structures 110. This helps to reduce the area of ​​HiR (High-Resistor) circuits and meets the requirements for device miniaturization.

[0048] In this embodiment, the resistor structure 200 is a HiR, which can play the role of voltage division and current limiting.

[0049] In this embodiment, the substrate 100 is made of silicon; the process for forming the conductive layer includes a self-aligned metal silicide process. By utilizing a self-aligned metal silicide process to form the conductive layer, since the metal layer in the self-aligned silicide process only reacts with silicon to form metal silicide, the metal layer only reacts with a portion of the substrate 100 to form metal silicide as the conductive layer. Consequently, the conductive layer can be self-aligned and formed on the top surface of the substrate 100 below the opening 150, avoiding alignment errors. This improves the positional accuracy of the conductive layer and reduces the difficulty of forming the conductive layer. Moreover, after the metal layer reacts with a portion of the substrate 100, the unreacted metal layer can be selectively removed, which also helps to reduce the difficulty of forming the conductive layer. Furthermore, the process of forming the conductive layer using the metal silicide process does not require the use of a mask, which helps to save costs. In addition, when the conductive layer is formed using the metal silicide process, the material of the conductive layer is a metal silicide material. Compared with metal materials, metal silicide materials have higher resistance, which makes it easier to make the resistor structure 200 have a higher resistance value, and thus it can be used as a HiR.

[0050] Therefore, in this embodiment, the material of the conductive layer is a metal silicide material, including TiSi, NiSi, CoSi, or NiPtSi.

[0051] In this embodiment, the conductive layer (i.e., the resistive structure 200) is an elongated strip structure, and the extension direction of the conductive layer is parallel to the extension direction of the channel structure 110. In this embodiment, the conductive layer is located on the top surface of the substrate 100 below the opening 150. Therefore, along the extension direction perpendicular to the channel structure 110, the size of the conductive layer (i.e., the resistive structure 200) is 50 nanometers to 1000 nanometers.

[0052] The greater the thickness of the conductive layer, the lower the resistance of the resistor structure 200. Therefore, the thickness of the conductive layer should not be too small or too large. In this embodiment, based on the required resistance value and width of the resistor structure 200, the thickness of the conductive layer is... to

[0053] In actual processes, the resistance value of the resistor structure 200 can be adjusted by selecting different conductive layer materials, adjusting the width and thickness of the conductive layer, etc., so that the resistance value of the resistor structure 200 meets the design requirements.

[0054] As an example, the steps of forming the conductive layer include: forming a metal layer (not shown) on the bottom and sidewalls of the cover layer 140 and the opening 150; performing a first heat treatment to convert a portion of the substrate 100 and the metal layer in contact with the metal layer into an initial metal silicide (not shown); and removing the remaining metal layer.

[0055] In this embodiment, the material of the metal layer includes Ti, Ni, Co, or NiPt. In this embodiment, the process for forming the metal layer includes physical vapor deposition, electroplating (ECP), or chemical vapor deposition.

[0056] In this embodiment, except for the top surface of the substrate 100 exposed at the bottom of the opening 150, the surfaces exposed by the semiconductor structure (e.g., the capping layer 140 and the hard mask layer 130) are all dielectric materials. Therefore, the silicon material surface in contact with the metal layer is only the top surface of the substrate 100 at the bottom of the opening 150. Accordingly, during the first heat treatment, metal silicide can be formed only on the substrate 100 at the bottom of the opening 150.

[0057] In this embodiment, the first heat treatment is used to form a metal silicide on the substrate 100 below the opening 150, thereby fixing the metal silicide at the location required by the process and defining the formation location of the conductive layer accordingly. In this embodiment, the first heat treatment forms a metal silicide with high resistivity.

[0058] In this embodiment, the first heat treatment includes annealing. The annealing process includes Dynamic Surface Annealing (DSA), Rapid Thermal Annealing (RTA), or Laser Annealing. As an example, RTA is used for the first heat treatment. RTA is a relatively mature annealing process, which is beneficial for improving process compatibility.

[0059] The process temperature of the first heat treatment should not be too low or too high. If the process temperature of the first heat treatment is too low, the metal layer and silicon may not react or the reaction may be insufficient, which will also reduce the formation quality and efficiency of the initial metal silicide. If the process temperature of the first heat treatment is too high, it may have an adverse effect on the semiconductor structure, for example, the metal silicide is prone to diffusion at high temperatures. Therefore, in this embodiment, the process temperature of the first heat treatment is 300°C to 500°C.

[0060] In this embodiment, since the metal layer does not react with the capping layer 140 or the hard mask layer 130, the metal layer located on the capping layer 140 and the hard mask layer 130 can be selectively removed after annealing. In this embodiment, the process for removing the remaining metal layer includes a wet etching process.

[0061] In this embodiment, the step of forming the conductive layer further includes: after removing the remaining metal layer, performing a second heat treatment on the metal silicide, wherein the process temperature of the second heat treatment is higher than the process temperature of the first heat treatment, and the metal silicide after the second heat treatment is used as the conductive layer.

[0062] The second heat treatment is used to further adjust the resistivity of the metal silicide, thereby adjusting the resistance value of the resistor structure 200. In this embodiment, the second heat treatment is used to reduce the resistivity of the metal silicide.

[0063] The second heat treatment includes annealing. Annealing processes include dynamic surface annealing, rapid thermal annealing, or laser annealing. As an example, the RTA process is used for the second heat treatment.

[0064] In order to ensure that the resistivity of the metal silicide meets the process requirements and that the resistance value of the resistor structure meets the design requirements, and in order to prevent adverse effects on the semiconductor structure, in this embodiment, the process temperature of the second heat treatment is 700°C to 900°C.

[0065] Reference Figures 7 to 9 , Figure 7 For based on Figure 5 Cross-sectional view, Figure 8 For based on Figure 7 Cross-sectional view, Figure 9 for Figure 8 According to the corresponding partial top view, after forming the resistor structure 200, the method of forming the semiconductor structure further includes: forming an isolation structure 160 on the substrate 100 and the resistor structure 200 on the side of the channel structure 110, wherein the isolation structure 160 exposes a portion of the sidewall of the channel structure 110.

[0066] In this embodiment, the isolation structure 160 also covers the power rail line 120.

[0067] The isolation structure 160 is used to isolate adjacent channel structures 110, and the isolation structure 160 is also used to isolate the substrate 100 or resistor structure 200 from the subsequent gate structure. In this embodiment, the channel structure 110 is a fin, and the portion of the fin exposed in the isolation structure 160 is used as an active fin, which provides a conductive channel when the device is in operation.

[0068] In this embodiment, the isolation structure 160 is a shallow trench isolation structure (STI).

[0069] In this embodiment, the step of forming the isolation structure 160 includes: after forming the resistor structure 200, forming a filling dielectric layer 170 in the opening 150; removing a portion of the thickness of the filling dielectric layer 170 and the cover layer 140 to expose a portion of the sidewall of the channel structure 110, and using the remaining filling dielectric layer 170 and cover layer 140 as the isolation structure 160.

[0070] By forming a filling dielectric layer 170 in the opening 150 and forming an isolation structure 160 by removing a portion of the thickness of the filling dielectric layer 170 and the cover layer 140, the process of forming the isolation structure 160 is integrated with the process of forming the resistor structure 200, thereby improving the process integration and process compatibility.

[0071] The material of the filling dielectric layer 170 is also an insulating material, such as one or more of silicon oxide, silicon oxynitride, and silicon nitride. In this embodiment, to improve process compatibility, the material of the filling dielectric layer 170 is the same as that of the capping layer 140, and the material of the filling dielectric layer 170 is silicon oxide.

[0072] In this embodiment, the step of forming the filling dielectric layer 170 includes: as follows Figure 7 As shown, a dielectric material layer (not shown) is filled in the opening 150, and the dielectric material layer is also formed on the cover layer 140; as Figure 8 and Figure 9 As shown, the dielectric material layer above the top surface of the cover layer 140 is removed to form the filling dielectric layer 170.

[0073] In this embodiment, the process for forming the dielectric material layer includes a flow-through chemical vapor deposition (FCVD) process. The FCVD process has a high gap-filling capability, which is beneficial for improving the filling capability and quality of the dielectric material layer in the opening 150, and correspondingly improving the film quality of the filled dielectric layer 170.

[0074] In this embodiment, the process of removing the dielectric material layer above the top surface of the capping layer 140 includes a chemical mechanical planarization (CMP) process. CMP is a global planarization process that helps improve the flatness and height consistency of the top surfaces of the filling dielectric layer 170 and the capping layer 140.

[0075] Continue to refer to Figure 8 and Figure 9 In this embodiment, the method for forming the semiconductor structure further includes: forming a gate structure 190 that spans the channel structure 110, source / drain doped regions 180 located in the channel structures 110 on both sides of the gate structure 190, and an interlayer dielectric layer 210 located on the isolation structure 160 on the side of the gate structure 190 and covering the source / drain doped regions 180.

[0076] In this embodiment, when the device is in operation, the gate structure 190 is used to control the opening or closing of the conductive channel.

[0077] In this embodiment, the gate structure 190 is a metal gate structure. In this embodiment, the gate structure 190 includes a high-k gate dielectric layer (not shown), a work function layer (not shown) located on the high-k gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer.

[0078] In this embodiment, the channel structure 110 is a fin, and the gate structure 190 correspondingly spans the fin and covers a portion of the top and sidewalls of the fin. In other embodiments, when the channel structure includes one or more spaced-apart channel layers, the gate structure correspondingly covers a portion of the top of the channel structure and surrounds the channel layers.

[0079] In this embodiment, the gate structure 190 also spans the isolation structure 160 above the resistor structure 200.

[0080] In this embodiment, the gate structure 190 is located on the isolation structure 160. The extension direction of the gate structure 190 (e.g., Figure 9 (As shown in the Y direction) perpendicular to the extension direction of the channel structure 110, resistor structure 200, and power track line 120 (e.g.) Figure 9 (As shown in the X direction).

[0081] The source / drain doped regions 180 are used to provide a carrier source during device operation. When forming an NMOS device, the source / drain doped regions 180 are doped with N-type ions; when forming a PMOS device, the source / drain doped regions 180 are doped with P-type ions. In this embodiment, as... Figure 8 As shown, the source and drain doped regions 180 located in the plurality of channel structures 110 are in contact along the extension direction of the gate structure 190.

[0082] The interlayer dielectric layer 210 is used to isolate adjacent devices. The material of the interlayer dielectric layer 210 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the interlayer dielectric layer 210 is silicon oxide.

[0083] In this embodiment, a contact etch stop layer (CESL) (not shown) is also formed between the source / drain doped region 180 and the interlayer dielectric layer 210, and between the isolation structure 160 and the interlayer dielectric layer 210. In the subsequent step of forming the source / drain interconnect layer through the top of the interlayer dielectric layer 210 of the source / drain doped region 180, the contact etch stop layer is used to temporarily define the etch stop position, thereby improving etch uniformity and reducing the probability of damage to the source / drain doped region 180. In this embodiment, the material of the contact etch stop layer is silicon nitride.

[0084] Reference Figures 10 to 11 , Figure 10 This is a cross-sectional view. Figure 11 for Figure 10 The corresponding partial top view shows a resistor contact plug (VHR) 220 forming through the interlayer dielectric layer 210 and the isolation structure 160 at the top of the resistor structure 200, and the resistor contact plug 220 is in contact with the resistor structure 200.

[0085] The resistor contact plug 220 is used to realize the electrical connection between the resistor structure 200 and external circuits or other interconnection structures.

[0086] In this embodiment, the resistor structure 200 is an elongated structure, including a first connecting end (not shown) and a second connecting end (not shown) extending along the direction of the resistor structure 200 opposite to the first connecting end. The first and second connecting ends serve as contact ends for connecting the resistor structure 200 to the resistor contact plug 220. Therefore, in this embodiment, the resistor contact plug 220 includes a first resistor contact plug 220(a) in contact with the first connecting end and a second resistor contact plug 220(b) in contact with the second connecting end.

[0087] In this embodiment, the resistor contact plug 220 (first resistor contact plug 220(a) and second resistor contact plug 220(b)) is located in the region between adjacent gate structures 190, which helps to save the area occupied by the semiconductor structure.

[0088] In this embodiment, the step of forming the resistive contact plug 220 further includes forming a power rail contact plug (Via-Buried Power Rail, VBPR) 230 that penetrates the interlayer dielectric layer 210 and the isolation structure 160 at the top of the power rail line 120, wherein the power rail contact plug 230 is in contact with the power rail line 120.

[0089] In the semiconductor field, it is typically necessary to form a power rail contact plug 230 that contacts the top surface of the power rail line 120. By forming the resistor structure 200 on the top surface of the substrate 100 between adjacent channel structures 110, the power rail contact plug 230 and the resistor contact plug 220 can be formed in the same process. That is, the resistor contact plug 220 can be formed using the same process as forming the power rail contact plug 230, so as to electrically connect the resistor structure 200. Accordingly, there is no need to perform an additional process to form the resistor contact plug 220. Only the design of the mask pattern for forming the power rail contact plug 230 needs to be adjusted. This not only minimizes the modification to the existing process and helps reduce process risks, but also helps to improve process integration, simplify the process flow, and thus save costs and improve manufacturing efficiency.

[0090] In this embodiment, the method for forming the semiconductor structure further includes: forming a source-drain interconnect layer 240 (e.g., through the interlayer dielectric layer 210 penetrating the top of the source-drain doped region 180) that extends through the top of the source-drain doped region 180. Figure 10 As shown, the source-drain interconnect layer 240 is in contact with the source-drain doped region 180, and along the extension direction of the gate structure 190, the source-drain interconnect layer 240 is in contact with the power rail contact plug 230.

[0091] The source-drain interconnect layer 240 contacts the source-drain doped region 180, thereby enabling electrical connection between the source-drain doped region 180 and external circuits or other interconnect structures. In this embodiment, the source-drain interconnect layer 240 contacts the power rail contact plug 230, thereby enabling electrical connection between the source-drain doped region 180 and the power rail line 120, so that power can be supplied to the source-drain doped region 180 through the power rail line 120 when the device is operating.

[0092] As an example, the source-drain interconnect layer 240 and the power rail contact plug 230 are integrally formed, thereby improving the contact performance between the power rail contact plug 230 and the source-drain interconnect layer 240.

[0093] In this embodiment, the source-drain interconnect layer 240, the power rail contact plug 230, and the resistor contact plug 220 are made of the same material, including one or more of W, Co, Ru, and Ni.

[0094] It should be noted that this embodiment uses the example of no contact between the resistive contact 220 and the source-drain interconnect layer 240. In other embodiments, the resistive contact and the source-drain interconnect layer may be in contact, depending on the actual design requirements. In other embodiments, when the resistive contact and the source-drain interconnect layer are in contact, the gate structures located on both sides of the resistive contact serve as dummy gates.

[0095] Continue to refer to Figure 11 In this embodiment, the method for forming the semiconductor structure further includes: forming a resistor interconnect 250 electrically connected to the resistor contact plug 220 (first resistor contact plug 220 ((a)) and second resistor contact plug 220 (b)).

[0096] The resistor interconnect 250 is used to electrically connect the resistor structure 200 to the subsequent interconnect structure.

[0097] In this embodiment, the extension direction of the resistor interconnect 250 is the same as the extension direction of the gate structure 190. The resistor interconnect 250 is located in the region between adjacent gate structures 190, which helps to save the area occupied by the semiconductor structure.

[0098] The material of the resistor interconnect 250 is a conductive material, such as W, Co, Ni or Cu.

[0099] Accordingly, the present invention also provides a semiconductor structure. (See reference) Figure 10 and Figure 11 , Figure 10 This is a cross-sectional view. Figure 11 for Figure 10 The corresponding partial top view shows a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0100] The semiconductor structure includes: a substrate 100; a channel structure 110 disposed on the substrate 100; and a conductive layer located on the top surface of the substrate 100 between adjacent channel structures 110, the conductive layer serving as a resistive structure 200.

[0101] Compared to fabricating the resistor structure in the interlayer dielectric (IMD) layer where the metal interconnects or conductive plugs are located, this embodiment fabricates the resistor structure 200 on the top surface of the substrate 100 between adjacent channel structures 110. This not only frees the resistor structure 200 from the middle or rear section of the interlayer dielectric layer, thus reducing the height of the metal interconnects and conductive plugs and achieving optimized middle section RC (resistance-capacitance), thereby optimizing the performance of the semiconductor structure, but also utilizes the area between adjacent channel structures 110 by forming the resistor structure 200 on the top surface of the substrate 100 between adjacent channel structures 110. This also reduces the area of ​​HiR (High-Resistor) circuits, thereby meeting the requirements for device miniaturization.

[0102] Substrate 100 is used to provide a platform for process technology. In this embodiment, substrate 100 is a silicon substrate, and the material of substrate 100 includes silicon. The material of substrate 100 includes silicon, thereby enabling the formation of a conductive layer on the top surface of substrate 100 between adjacent channel structures 110 using a self-aligned metal silicide process, for use as a resistive structure 200.

[0103] When the device is operating, the channel structure 110 is used to provide a conductive channel for the transistor. In this embodiment, there are multiple channel structures 110, which are arranged in parallel and spaced apart.

[0104] As an example, the channel structure 110 is a fin. Accordingly, the fin is used to form a fin field-effect transistor (FinFET). In this embodiment, the material of the fin is the same as the material of the substrate 100, which is silicon. In other embodiments, the material of the fin can be other semiconductor materials suitable for forming fins, and the material of the fin can also be different from the material of the substrate.

[0105] In other embodiments, the channel structure is spaced apart from the substrate, and the channel structure includes one or more spaced-apart channel layers. Accordingly, the channel layers are used to form a gate-all-around (GAA) transistor or a forksheet transistor.

[0106] In this embodiment, the semiconductor structure further includes: a power track line 120 located in the substrate 100, wherein the extension directions of the power track line 120 and the channel structure 110 are (e.g., Figure 11 The power track line 120 and the channel structure 110 are parallel to each other (as shown in the X direction), and there is a gap between them.

[0107] Power rails 120 are used to provide power to different components of the chip. In this embodiment, the power rails 120 are located in the substrate 100 and are buried power rails (BPR). This facilitates the freeing up of wiring resources for subsequent interconnects and reduces the height of standard cells to meet the needs of continuous logic chip miniaturization. In addition, the buried power rails utilize pitch reduction technology to increase subsequent resistance, which also helps to provide a lower resistance local current distribution.

[0108] In the semiconductor field, semiconductor structures typically include power rail contact plugs that contact the top surface of the power rail line 120. By including the power rail line 120 located in the substrate 100 in the semiconductor structure, the power rail contact plug and the resistor contact plug that contacts the resistor structure 200 can be formed in the same process. That is, the resistor contact plug can be formed using the process for forming the power rail contact plug to electrically connect the resistor structure 200. Accordingly, there is no need to perform an additional process to form the resistor contact plug. This not only minimizes the modification to the existing process and helps reduce process risks, but also helps improve process integration, simplify processes, and thus save costs and improve production efficiency.

[0109] In this embodiment, the top surface of the power track line 120 is flush with the top surface of the substrate 100, thereby exposing the top surface of the power track line 120 on the substrate 100, so as to form a power contact plug that contacts the top surface of the power track line 120.

[0110] The power track 120 is made of a conductive material. In this embodiment, the power track 120 is made of a metallic material, including one or more of Co, W, Ni, and Ru. The low resistivity of the power track 120 material is beneficial for improving RC delay and increasing the chip's processing speed.

[0111] In this embodiment, the semiconductor structure further includes an insulating layer (not shown) located between the sidewall of the power track line 120 and the substrate 100, the insulating layer being used to achieve insulation between the power track line 120 and the substrate 100.

[0112] In this embodiment, the resistor structure 200 is a HiR (High-Resistor), which can play the role of voltage division and current limiting.

[0113] In this embodiment, the substrate 100 is made of silicon, the conductive layer is made of metal silicide, and the conductive layer is formed by a self-aligned metal silicide (Salicide) process. By utilizing a self-aligned metal silicide process to form a conductive layer, the metal layer in the self-aligned silicide process only reacts with silicon to form a metal silicide. Thus, the metal layer only reacts with a portion of the substrate 100 to form a metal silicide as a conductive layer. Consequently, the conductive layer can be self-aligned and formed on the top surface of a portion of the substrate 100 between adjacent channel structures 100, avoiding alignment errors. This improves the positional accuracy of the conductive layer and reduces the difficulty of forming the conductive layer. Furthermore, after the metal layer reacts with a portion of the substrate 100, the unreacted remaining metal layer can be selectively removed, further reducing the difficulty of forming the conductive layer. The process of forming the conductive layer using the metal silicide process does not require a photomask, saving costs. In addition, the conductive layer is made of metal silicide material, which has a higher resistance than metal material, thus enabling the resistor structure 200 to have a higher resistance value and thus serve as a HiR (High Resistance Resistor).

[0114] In this embodiment, the conductive layer is made of a metal silicide material, including TiSi, NiSi, CoSi, or NiPtSi.

[0115] The conductive layer has an elongated strip structure, and the extension direction of the conductive layer (i.e., the resistive structure 200) is parallel to the extension direction of the channel structure 110.

[0116] The size of the conductive layer along the extension direction perpendicular to the channel structure 110 should not be too small or too large. If the size of the conductive layer is too small, the precision requirements for the conductive layer formation process will be too high, the formation of the conductive layer will be too difficult, and the size of the conductive layer is also prone to causing the resistance value of the resistor structure 200 to be too large. If the size of the conductive layer is too large, the risk of damage to the channel structure 110 during the formation of the conductive layer will be increased, and the distance between the conductive layer and the channel structure 110 will be too close, which will increase the probability of short circuit between the resistor structure 200 and the channel structure 110. At the same time, the size of the conductive layer is also prone to causing the resistor structure 200 to occupy too much area, and the resistance value of the resistor structure 200 is also prone to being too small. Therefore, in this embodiment, the size of the conductive layer along the extension direction perpendicular to the channel structure 110 is 50 nanometers to 1000 nanometers.

[0117] The greater the thickness of the conductive layer, the lower the resistance of the resistor structure 200. Therefore, the thickness of the conductive layer should not be too small or too large. In this embodiment, based on the required resistance value and width of the resistor structure 200, the thickness of the conductive layer is... to

[0118] In actual processes, the resistance value of the resistor structure 200 can be adjusted by selecting different conductive layer materials, adjusting the width and thickness of the conductive layer, etc., so that the resistance value of the resistor structure 200 meets the design requirements.

[0119] In this embodiment, the semiconductor structure further includes an isolation structure 160 located on the substrate 100 and resistor structure 200 on the side of the channel structure 110, wherein the top surface of the isolation structure 160 is lower than the top surface of the channel structure 110. In this embodiment, the isolation structure 160 also covers the power track line 120.

[0120] The isolation structure 160 is used to isolate adjacent channel structures 110, and the isolation structure 160 is also used to isolate the substrate 100 or resistor structure 200 from the gate structure. In this embodiment, the channel structure 110 is a fin, and the portion of the fin exposed in the isolation structure 160 is used as an active fin, which provides a conductive channel when the device is in operation.

[0121] In this embodiment, the isolation structure 160 is a shallow trench isolation structure (STI). The material of the isolation structure 160 is an insulating material, such as one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0122] In this embodiment, the isolation structure 160 includes: a filling dielectric layer 170 located on the resistor structure 200; and a capping layer 140 located on the substrate 100 on the side of the channel structure 110 and the filling dielectric layer 170.

[0123] The step of forming the conductive layer includes: forming a capping layer 140 on the substrate 100 exposed by the channel structure 110; forming an opening through the capping layer between adjacent channel structures 110; and forming a conductive layer on the top surface of the substrate 100 below the opening. In this embodiment, the material of the capping layer 140 is a dielectric material. The capping layer 140 is retained in the semiconductor structure to form an isolation structure 160, thereby integrating the processes of forming the resistor structure 200 and forming the isolation structure 160, improving process integration and process compatibility.

[0124] The filling dielectric layer 170 is used to fill the opening, thereby enabling the isolation structure 160 to be formed by etching back a portion of the thickness of the filling dielectric layer 170 and the capping layer 140. In this embodiment, the material of the filling dielectric layer 170 is the same as that of the capping layer 140, and the material of the filling dielectric layer 170 is silicon oxide.

[0125] In this embodiment, the gate structure 190 is located on the isolation structure 160 and spans the channel structure 110; the source / drain doped regions 180 are located in the channel structures 110 on both sides of the gate structure 190; the interlayer dielectric layer 210 is located on the isolation structure 160 on the side of the gate structure 190 and covers the source / drain doped regions 180; the resistor contact plug 220 penetrates the interlayer dielectric layer 210 and the isolation structure 160 at the top of the resistor structure 200, and the resistor contact plug 220 is in contact with the resistor structure 200.

[0126] In this embodiment, when the device is in operation, the gate structure 190 is used to control the opening or closing of the conductive channel.

[0127] In this embodiment, the gate structure 190 is a metal gate structure. In this embodiment, the gate structure 190 includes a high-k gate dielectric layer (not shown), a work function layer (not shown) located on the high-k gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer.

[0128] In this embodiment, the channel structure 110 is a fin, and the gate structure 190 correspondingly spans the fin and covers a portion of the top and sidewalls of the fin. In other embodiments, when the channel structure includes one or more spaced-apart channel layers, the gate structure correspondingly covers a portion of the top of the channel structure and surrounds the channel layers.

[0129] In this embodiment, the gate structure 190 also spans the isolation structure 160 above the resistor structure 200.

[0130] In this embodiment, the gate structure 190 is located on the isolation structure 160. The extension direction of the gate structure 190 (e.g., Figure 11 (As shown in the Y direction) perpendicular to the extension direction of the channel structure 110, resistor structure 200, and power track line 120 (e.g.) Figure 11 (As shown in the X direction).

[0131] The source / drain doped regions 180 are used to provide a carrier source when the device is in operation. When forming an NMOS device, the source / drain doped regions 180 are doped with N-type ions; when forming a PMOS device, the source / drain doped regions 180 are doped with P-type ions.

[0132] In this embodiment, along the extending direction of the gate structure 190, the source and drain doped regions 180 located in the plurality of channel structures 110 are in contact (e.g., Figure 10 (As shown).

[0133] The interlayer dielectric layer 210 is used to isolate adjacent devices. The material of the interlayer dielectric layer 210 is an insulating material. In this embodiment, the material of the interlayer dielectric layer 210 is silicon oxide.

[0134] In this embodiment, the semiconductor structure further includes a contact etch stop layer (CESL) (not shown), located between the source / drain doped region 180 and the interlayer dielectric layer 210, and between the isolation structure 160 and the interlayer dielectric layer 210. During the step of forming the source / drain interconnect layer through the interlayer dielectric layer 210 extending above the source / drain doped region 180, the contact etch stop layer is used to temporarily define the etch stop position, thereby improving etch uniformity and reducing the probability of damage to the source / drain doped region 180. In this embodiment, the material of the contact etch stop layer is silicon nitride.

[0135] The Via-High Resistor (VHR) 220 is used to achieve electrical connection between the resistor structure 200 and external circuits or other interconnection structures.

[0136] In this embodiment, the resistor structure 200 is an elongated structure, including a first connection terminal (not shown) and a second connection terminal (not shown) extending along the direction of the resistor structure 200 opposite to the first connection terminal. The first and second connection terminals are used as contact terminals for connecting the resistor structure 200 to the resistor contact plug 220, thereby electrically connecting the resistor structure 200 to external circuits or other interconnection structures through the resistor contact plug 220.

[0137] Therefore, in this embodiment, the resistive contact plug 220 includes a first resistive contact plug 220(a) that contacts the first connection end, and a second resistive contact plug 220(b) that contacts the second connection end.

[0138] In this embodiment, the resistor contact plug 220 (first resistor contact plug 220(a) and second resistor contact plug 220(b)) is located in the region between adjacent gate structures 190, which helps to save the area occupied by the semiconductor structure.

[0139] It should be noted that, in this embodiment, the semiconductor structure further includes: a Via-Buried Power Rail (VBPR) 230, which penetrates the interlayer dielectric layer 210 and the isolation structure 160 at the top of the power rail line 120 and is in contact with the power rail line 120.

[0140] In the semiconductor field, it is typically necessary to form a power rail contact plug 230 that contacts the top surface of the power rail line 120. In this embodiment, the resistor structure 200 is located on the top surface of the substrate 100 between adjacent channel structures 110, thereby enabling the power rail contact plug 230 and the resistor contact plug 220 to be formed in the same process. That is, the resistor contact plug 220 can be formed using the same process as the power rail contact plug 230, so as to electrically connect the resistor structure 200. Accordingly, there is no need to perform an additional process to form the resistor contact plug 220. Only the design of the mask pattern for forming the power rail contact plug 230 needs to be adjusted. This not only minimizes the modification to the existing process and helps reduce process risks, but also helps to improve process integration, simplify the process flow, and thus save costs and improve manufacturing efficiency.

[0141] In this embodiment, the semiconductor structure further includes: a source-drain interconnect layer 240, an interlayer dielectric layer 210 that penetrates the top of the source-drain doped region 180 and is in contact with the source-drain doped region 180, and the source-drain interconnect layer 240 is in contact with the power rail contact plug 220 along the extension direction of the gate structure 190.

[0142] The source-drain interconnect layer 240 is in contact with the source-drain doped region 180, thereby enabling electrical connection between the source-drain doped region 180 and external circuits or other interconnect structures.

[0143] The source-drain interconnect layer 240 contacts the power rail contact plug 230, thereby achieving an electrical connection between the source-drain doped region 180 and the power rail line 120. Thus, when the device is working, the source-drain doped region 180 can be powered through the power rail line 120.

[0144] As an example, the source-drain interconnect layer 240 and the power rail contact plug 230 are integrally formed, which helps to improve the contact performance between the power rail contact plug 230 and the source-drain interconnect layer 240.

[0145] In this embodiment, the source-drain interconnect layer 240, the power rail contact plug 230, and the resistor contact plug 220 are made of the same material, including one or more of W, Co, Ru, and Ni.

[0146] It should be noted that this embodiment uses the example of no contact between the resistive contact 220 and the source-drain interconnect layer 240. In other embodiments, the resistive contact and the source-drain interconnect layer may be in contact, depending on the actual design requirements. In other embodiments, when the resistive contact and the source-drain interconnect layer are in contact, the gate structures located on both sides of the resistive contact serve as dummy gates.

[0147] In this embodiment, the semiconductor structure further includes a resistor interconnect 250, which is electrically connected to the resistor contact plug 220 (first resistor contact plug 220(a) and second resistor contact plug 220(b)).

[0148] The resistor interconnect 250 is used to electrically connect the resistor structure 200 to the subsequent interconnect structure.

[0149] In this embodiment, the extension direction of the resistor interconnect 250 is the same as the extension direction of the gate structure 190. The resistor interconnect 250 is located in the region between adjacent gate structures 190, which helps to save the area occupied by the semiconductor structure.

[0150] The material of the resistor interconnect 250 is a conductive material, such as W, Co, Ni or Cu.

[0151] The semiconductor structure can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0152] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate and a channel structure discrete on the substrate are provided, and a cover layer on the substrate located on the side of the channel structure is provided; An opening is formed in the cover layer between adjacent channel structures, the bottom of which exposes the substrate; A conductive layer is formed on the top surface of the substrate at the bottom of the opening to serve as a resistive structure; wherein the conductive layer is formed using a self-aligned metal silicide process, and the material of the conductive layer is a metal silicide material.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The substrate is made of silicon.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The steps of forming the conductive layer include: forming a metal layer on the cover layer, the bottom of the opening, and the sidewalls; performing a first heat treatment to convert a portion of the substrate and the metal layer in contact with the metal layer into metal silicide; and removing the remaining metal layer.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The step of forming the conductive layer further includes: after removing the remaining metal layer, subjecting the metal silicide to a second heat treatment, wherein the process temperature of the second heat treatment is higher than that of the first heat treatment, and the metal silicide after the second heat treatment serves as the conductive layer.

5. The method for forming a semiconductor structure as described in claim 3, characterized in that, The process temperature for the first heat treatment is 300°C to 500°C.

6. The method for forming a semiconductor structure as described in claim 4, characterized in that, The process temperature for the second heat treatment is 700°C to 900°C.

7. The method for forming a semiconductor structure as described in claim 1 or 2, characterized in that, After forming the resistor structure, the method for forming the semiconductor structure further includes: forming an isolation structure on the substrate and the resistor structure on the side of the channel structure, wherein the isolation structure exposes a portion of the sidewall of the channel structure; A gate structure spanning the channel structure, source / drain doped regions located in the channel structures on both sides of the gate structure, and an interlayer dielectric layer located on the side of the gate structure and covering the source / drain doped regions are formed on the isolation structure. A resistive contact plug is formed that extends through the top of the resistive structure, forming an interlayer dielectric layer and an isolation structure, and the resistive contact plug is in contact with the resistive structure.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, In the step of providing a substrate, power track lines are further formed in the substrate, the power track lines are parallel to the extension direction of the channel structure, and there is a gap between the power track lines and the channel structure; the capping layer covers the power track lines. In the step of forming the resistive contact plug, the method of forming the semiconductor structure further includes: forming a power rail contact plug that penetrates the top of the power rail line and an interlayer dielectric layer and an isolation structure, wherein the power rail contact plug is in contact with the power rail line.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The steps of providing a substrate, a channel structure, a capping layer, and the power track include: forming a substrate and a channel structure discrete on the substrate; forming a first capping material layer on the substrate at a side of the channel structure; forming a groove penetrating the first capping material layer and a portion of the substrate thickness, the groove including a bottom groove in the substrate and a top groove on the bottom groove; forming the power track in the bottom groove; and forming a second capping material layer on the power track that fills the top groove, the second capping material layer serving to form the capping layer together with the first capping material layer.

10. The method for forming a semiconductor structure as described in claim 7, characterized in that, The material of the covering layer is a dielectric material; The steps of forming the isolation structure include: after forming the resistive structure, forming a filling dielectric layer in the opening; A portion of the filler medium layer and cover layer is removed to expose part of the sidewalls of the channel structure, and the remaining filler medium layer and cover layer are used as an isolation structure.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The opening is an elongated structure, and the extension direction of the opening is parallel to the extension direction of the channel structure; along the extension direction perpendicular to the channel structure, the size of the opening is 50 nanometers to 1000 nanometers.

12. A semiconductor structure, characterized in that, include: Substrate; The channel structure is discretely disposed on the substrate; A conductive layer is located on the top surface of the substrate between adjacent channel structures, and the conductive layer is used as a resistive structure; wherein the conductive layer is formed using a self-aligned metal silicide process, and the material of the conductive layer is a metal silicide material.

13. The semiconductor structure as described in claim 12, characterized in that, The substrate is made of silicon.

14. The semiconductor structure as described in claim 13, characterized in that, The conductive layer is made of materials including TiSi, NiSi, CoSi, or NiPtSi.

15. The semiconductor structure as described in claim 12, characterized in that, The semiconductor structure further includes: an isolation structure located on a substrate and a resistor structure on the side of the channel structure, wherein the top surface of the isolation structure is lower than the top surface of the channel structure; A gate structure is located on the isolation structure and spans the channel structure; The source and drain doped regions are located in the channel structures on both sides of the gate structure; An interlayer dielectric layer is located on the isolation structure on the side of the gate structure and covers the source / drain doped region; A resistor contact plug extends through the interlayer dielectric layer and the isolation structure at the top of the resistor structure, and the resistor contact plug is in contact with the resistor structure.

16. The semiconductor structure as claimed in claim 15, characterized in that, The semiconductor structure further includes: a power track line located in the substrate, wherein the power track line extends parallel to the extension direction of the channel structure and there is a gap between the power track line and the channel structure; A power rail contact plug penetrates the interlayer dielectric layer and isolation structure at the top of the power rail line and is in contact with the power rail line; The source-drain interconnect layer extends through the interlayer dielectric layer at the top of the source-drain doped region and contacts the source-drain doped region. Along the extension direction of the gate structure, the source-drain interconnect layer contacts the power rail contact plug.

17. The semiconductor structure as claimed in claim 15, characterized in that, The isolation structure includes: a filling dielectric layer located on the resistive structure; and a capping layer located on the substrate on the side of the channel structure and the filling dielectric layer.

18. The semiconductor structure as claimed in claim 12, characterized in that, The conductive layer has an elongated strip structure, and the extension direction of the conductive layer is parallel to the extension direction of the channel structure; along the extension direction perpendicular to the channel structure, the size of the conductive layer is 50 nanometers to 1000 nanometers.

19. The semiconductor structure as claimed in claim 12, characterized in that, The thickness of the conductive layer is 20 Å to 500 Å.

20. The semiconductor structure as claimed in claim 12, characterized in that, The channel structure is a fin; or, the channel structure is spaced apart from the substrate, and the channel structure includes one or more spaced-apart channel layers.

Images