Package with pads having open slots

Abstract

An enclosure (100) includes: an electronic component (102) having a first main surface (104) with a first pad (106) having a conductive first pad (106) having an opening slot (108); and a spacer (110) mounted on the first pad (106) and spanning at least a portion of the opening slot (108).

Description

Technical Field

[0001] The various embodiments generally involve a variety of packages and methods of manufacturing packages. Background Technology

[0002] A package can be represented as a typically encapsulated electronic component having electrical connection structures extending out of the encapsulation material. For example, a package can be connected to peripheral electronic devices, such as being mounted on a printed circuit board or to a heat sink and connected to a larger system via a connector.

[0003] Packaging cost is a significant driver in this industry. Related to this are performance, size, and reliability. A wide variety of packaging solutions exist, each designed to meet the specific needs of an application.

[0004] In particular, packages containing power semiconductor chips can generate a significant amount of heat during operation. This can limit reliability and performance. Summary of the Invention

[0005] A package with appropriate reliability and performance may be required.

[0006] According to an exemplary embodiment of a first aspect of the present disclosure, a package is provided, comprising: an electronic component having a first main surface with a conductive first pad having an opening slot; and a spacer mounted on the first pad and spanning at least a portion of the opening slot.

[0007] According to another exemplary embodiment of the first aspect of this disclosure, a method of manufacturing a package is provided, wherein the method includes: providing an electronic component having a first main surface with a conductive first pad having an opening slot; and mounting a spacer on the first pad such that the spacer spans at least a portion of the opening slot.

[0008] According to an exemplary embodiment of a second aspect of this disclosure, a package is provided comprising: an electronic component having a first main surface with a conductive first pad having an opening slot; and a spacer having another opening slot and mounted on the first pad such that the opening slot of the first pad partially or completely overlaps (particularly aligns) with the opening slot of the spacer.

[0009] According to another exemplary embodiment of the second aspect of this disclosure, a method of manufacturing a package is provided, wherein the method includes: providing an electronic component having a first main surface with a conductive first pad having an opening slot; and mounting a spacer having another opening slot on the first pad such that the opening slot of the first pad at least partially overlaps with the opening slot of the spacer.

[0010] According to an exemplary embodiment of a third aspect of this disclosure, a package is provided comprising: an electronic component having a conductive first pad with an opening notch and a conductive second pad, wherein the second pad is arranged to be substantially equidistant from the first pad along the opening notch (particularly along the entire edge of the first pad defining the opening notch).

[0011] According to another exemplary embodiment of the third aspect of this disclosure, a method of manufacturing a package is provided, wherein the method includes: providing an electronic component having a conductive first pad with an opening notch and a conductive second pad; and arranging the second pad to be substantially equidistant from the first pad along the opening notch.

[0012] According to an exemplary embodiment of the first aspect, a package is provided in which spacers for electrical and / or thermal connections of electronic components within the package are arranged to span a notch across designated pads on which the spacers are mounted. This increases the spatial coverage of the spacers over the pads, thereby enhancing the electrical and / or thermal coupling of the electronic components. Simultaneously, the pads of the electronic components can advantageously be provided with the notch, which effectively prevents assembly and / or stress-related short circuits between different pads of the electronic components caused by interconnecting materials (e.g., solder) used to connect the electronic components within the package, particularly those connected to the spacers. Therefore, the requirement for highly precise assembly processes can be relaxed. Furthermore, the electrical and / or thermal coupling characteristics of the electronic components can be improved because the spanning configuration of the spacers combines a large spacer surface with a simple spacer geometry.

[0013] According to an exemplary embodiment of the second aspect, a package is provided in which pads of electronic components and designated spacers can each be provided with at least partially matching opening-slot geometries. In other words, the opening slots of the spacers and pads can be aligned (specifically, the spacers do not cross pad slots). This opening-slot geometry of the pads and spacers can reliably prevent undesirable electrical short circuits between different pads of the electronic components due to interconnect materials. By configuring the spacers to have adaptable opening-slot geometries that conform to the opening-slot geometry of the pads, the electrical and / or thermal coupling surface between the pads and spacers can be increased while keeping the spacers small, thereby making the package lightweight and compact.

[0014] According to an exemplary embodiment of the third aspect, a package is provided in which the position and shape of the opening notch of the first pad and the second pad are adjusted or balanced to ensure that the distance between the first pad and the second pad is nearly constant along the extension of the opening notch of the first pad. This substantially equidistant design rule can significantly suppress the risk of undesirable electrical short circuits between the first and second pads of electronic components due to the interconnect material connecting the first pad and the spacer, thereby enhancing the electrical and / or thermal reliability of the package.

[0015] Description of further exemplary embodiments

[0016] Further exemplary embodiments of the encapsulation and method will be explained below.

[0017] In the context of this application, the term "package" may specifically refer to an electronic device that may include, for example, one or more electronic components mounted on a carrier, the carrier comprising or consisting of a single component, multiple components joined via an encapsulation or other package member, or sub-assemblies of multiple carriers. The components of the package may optionally be at least partially encapsulated by an encapsulation material.

[0018] In the context of this application, the term "electronic component" may specifically include semiconductor chips (particularly power semiconductor chips), active electronic devices (e.g., transistors), passive electronic devices (e.g., capacitors, inductors, or ohmic resistors), sensors (e.g., microphones, light sensors, or gas sensors), actuators (e.g., loudspeakers), and microelectromechanical systems (MEMS). Specifically, an electronic component may be a semiconductor chip having at least one integrated circuit element (e.g., a diode or transistor) in its surface portion. The electronic component may be a bare die or may have been packaged or encapsulated. The semiconductor chip implemented according to exemplary embodiments may be formed, for example, using silicon technology, gallium nitride technology, silicon carbide technology, etc.

[0019] In the context of this application, the term "spacer" may specifically refer to a conductive and / or thermally conductive material configured to perpendicularly space pads of electronic components relative to the outer main surface of a substrate or package while facilitating electrical and / or thermal coupling of electronic components within the package. In one embodiment, current or electrical signals may flow between the pads of the electronic component connected to the spacer and the spacer. Additionally or alternatively, heat generated by the electronic component during operation of the package may be thermally conducted away from the electronic component and removed from the package by the spacer. The spacer may also provide an electrical clamp function, i.e., serve as an electrical connection element for electrically connecting the electronic component to another conductor within the package, such as a conductive carrier (e.g., a lead frame or a direct copper bond (DCB) substrate).

[0020] In the context of this application, the term "open notch" may specifically refer to a notch or recess that extends into a first pad or spacer and opens or exposes itself to the surrounding environment of the first pad or spacer. Specifically, such an open notch-type recess may be defined by a continuous edge line or edge region of the first pad or spacer and may correspondingly open to the surrounding environment of the first pad or spacer. For example, the first pad may include different sections that partially define the notch from different sides. These different sections may be spaced apart from each other or integrally connected conductively to form an equipotential surface. For example, the notch may be open on the open side and another pad (particularly a gate pad) may be arranged adjacent to the open notch of the aforementioned first pad (particularly a source pad).

[0021] In the context of this application, the phrase "spacer spans at least a portion of the opening slot of the first pad of the electronic component" can specifically mean that the spacer covers or overlaps the opening slot of the first pad of the electronic component, while there is no direct physical contact between the spacer and the bottom surface of the electronic component in the spanned area.

[0022] In the context of this application, the statement "the opening notch of the first pad at least partially overlaps with the opening notch of the spacer" specifically indicates that the opening notch of the spacer may extend partially or completely over the space defined by the opening notch of the first pad. In one embodiment, the spacer material may not be visible in a top view of the entire space defined by the opening notch of the first pad of the electronic component. In another embodiment, the spacer material may not be visible in a top view of a sub-part of the space defined by the opening notch of the first pad of the electronic component, but may be visible in a top view of another sub-part of the space defined by the opening notch of the first pad.

[0023] In the context of this application, the statement "the second pad is arranged to be substantially equidistant from the first pad along the opening notch" can specifically indicate that the shortest distance defining the edges of the first and second pads can be precisely the same or at least substantially the same along the extension of the opening notch of the first pad. For example, the respective distances can differ from the average distance value (i.e., the average over the extension of the opening notch of the first pad) by no more than ±20%, particularly no more than ±10%, and preferably no more than ±5%.

[0024] A key aspect of an exemplary embodiment may be providing a package that uses one or more spacers for a specific chip design to connect chip-type electronic components within the package, particularly to the top substrate of the package. In one embodiment, spacers with a shape (e.g., rectangular) different from the shape of the source pads of the electronic components (e.g., a generally rectangular shape with an opening notch) can be implemented. Thus, the spacers can span one or more dielectric (e.g., polyimide) regions on the electronic components. Collaboratively, such an embodiment can be combined with another embodiment providing electronic components having source pads with opening notches (e.g., V-shaped or trapezoidal notches) adjacent to (e.g., polygonal) gate pads. In such a configuration, the source-to-gate distance can be adjusted to be substantially or exactly the same along the edge of the pad defining the notch. This can advantageously make undesirable short circuits between the source and gate less likely and can thereby improve the electrical reliability of the package. Attached to or alternative to the spacer-to-source pad spanning configuration, the spacers may also be provided with opening notches to increase the compactness of the package.

[0025] In one embodiment, the spacer is attached to or replaces the spacer by laterally projecting above the opening of the first pad, and the spacer may extend or protrude beyond one or more edges of the first pad. This oversized spacer can further improve the thermal performance of the package.

[0026] In one embodiment, the first main surface has an electrically insulating region at or in the opening slot. The electrically insulating region may also surround the first pad (and the second pad, if the second pad exists on the same main surface of the electronic component). This can improve the reliability of dielectric decoupling between the first and second pads of the electronic component.

[0027] In one embodiment, the spacer spans the opening slot without physically contacting the electrically insulating region. Furthermore, by avoiding direct contact between the spacer and the electrically insulating region, the formation of undesirable conductive paths within the package can be prevented.

[0028] In one embodiment, the spacer is thermally and / or electrically conductive. For example, the spacer may have a thermal conductivity of at least 50 W / mK. When made of a thermally conductive material, the spacer can significantly help remove heat generated by the electronic components from the package. When made of a conductive material, current and / or electrical signals can be conducted between the electronic components and the spacer. Preferably, the spacer has both heat dissipation and electrical functions within the overall function of the package.

[0029] In one embodiment, the spacer is mounted on a first pad of the electronic component in a thermally and / or electrically conductive manner. In particular, heat and / or current can be conducted between the spacer and the active semiconductor region of the electronic component via the first pad.

[0030] In one embodiment, the spacer is mounted on the first pad by one of the group consisting of soldering (especially diffusion soldering), sintering, welding, and adhesion (especially using conductive adhesive). Other connection techniques may also be implemented.

[0031] In one embodiment, the first pad and the mounting surface of the spacer have different geometries. This increases the design freedom when configuring the package for a specific application.

[0032] In another embodiment, the mounting surfaces of the first pad and the spacer have the same geometry, particularly the same profile. By forming the first pad and mounting surface with corresponding shapes and profiles, thermal and electrical conduction between the spacer and the first pad can be precisely matched or adjusted. By keeping the spacer small enough, the weight and size of the package can be kept small.

[0033] In one embodiment, the first pad has (particularly integrally) a rectangular segment connected to a first extension segment (e.g., a narrowing segment) and a second extension segment (e.g., another narrowing segment), the first and second extension segments being spaced apart from each other by an opening. The rectangular segment can be a single integral structure or can be composed of multiple connected or unconnected individual substructures. Providing two opposing extension segments can help define the opening and can thereby support an advantageous arrangement of different pads having substantially equal distances along the extension edge of the opening.

[0034] In one embodiment, the mounting surface of the spacer is rectangular. This allows the spacer to be easily manufactured, for example, as a rectangular metal block.

[0035] In one embodiment, the spacer is mounted on at least a portion (particularly substantially the entirety) of the rectangular segment, at least a portion (particularly substantially the entirety) of the first extension segment, and at least a portion (particularly substantially the entirety) of the second extension segment. Therefore, a high degree of thermal and / or electrical coupling can be established between the spacer and the electronic components. This strongly suppresses the formation of hot spots, thereby improving the reliability and performance of the package.

[0036] In one embodiment, the opening slot is shaped according to at least one of the group consisting of rounded (e.g., semi-circular), trapezoidal (particularly based on an inwardly narrowing trapezoid and preferably formed as a symmetrical or regular trapezoid), generally V-shaped, generally U-shaped, and rectangular. Other shapes of the opening slot for the first pad are also possible.

[0037] In one embodiment, the electronic component has a conductive second pad on a first main surface. The first and second pads may be coplanar and electrically decoupled from each other.

[0038] In one embodiment, the second pad is arranged adjacent to the opening slot. Specifically, the second pad may be located outside the opening slot but facing it. This geometric configuration allows for a compact arrangement with reliable dielectric decoupling between the first and second pads. In particular, the minimum distance between the first and second pads can be less than 3 mm, especially less than 1.5 mm. For example, the minimum distance between the first and second pads can be at least 300 μm, especially at least 600 μm.

[0039] In one embodiment, the second pad is arranged to be substantially equidistant from the first pad along the entire opening. This is highly advantageous in preventing the distance between the first and second pads from being too small. By equidistantly spacing the first and second pads at a substantially constant distance between their opposite edges, it is ensured that the bonding medium (e.g., solder or adhesive) connecting the spacer to the first pad will not unintentionally flow onto the second pad. Therefore, undesirable short circuits between the pads can be suppressed.

[0040] In one embodiment, the second pad is shaped according to at least one of the groups consisting of circles and polygons, particularly rectangles, hexagons, and octagons. However, other shapes are also possible.

[0041] In one embodiment, the spacer does not extend across the second pad. This ensures that reliable electrical isolation between the first and second pads is not affected by the spacer.

[0042] In one embodiment, the electronic component has a conductive third pad on a second main surface opposite to the first main surface. Furthermore, the third pad can contribute to heat dissipation and / or the transmission of electrical signals or power within the package. Preferably, the third pad substantially covers the entire second main surface.

[0043] In one embodiment, the electronic component is a semiconductor power chip. Especially for semiconductor power applications, efficient heat dissipation, high current carrying capacity, high performance, and high reliability are the greatest advantages. The aforementioned configuration of the first and second pads and the spacer thus provides a significant improvement to the semiconductor power package.

[0044] In one embodiment, the electronic component is configured to be subjected to a vertical current during operation. Specifically, the current can flow from a pad on the lower main surface of the electronic component through the semiconductor material of the electronic component to another pad on the upper main surface of the electronic component.

[0045] In one embodiment, the electronic component is a transistor chip. Therefore, the electronic component can provide transistor functionality, specifically operating as a field-effect transistor or a bipolar transistor. However, the electronic component can also provide another electronic function, such as diode functionality.

[0046] In one embodiment, the first main surface of the electronic component may have a first pad configured as a source pad and a second pad configured as a gate pad. The opposite main surface of the electronic component may have a third pad configured as a drain pad.

[0047] In one embodiment, the package includes a bottom substrate on which electronic components are mounted. In the context of this application, the terms "bottom substrate" or "carrier" may specifically refer to a support structure (preferably, but not necessarily conductive) that serves as mechanical support for one or more electronic components, and may also facilitate electrical interconnection between the electronic components and the periphery of the package. In other words, the bottom substrate or carrier provides both mechanical support and electrical connectivity. The bottom substrate or carrier may include or consist of a single portion, multiple portions connected via an encapsulation or other package components, or sub-assemblies of multiple carriers.

[0048] In one embodiment, the package includes a top substrate mounted on a spacer. During operation of the package, the top substrate can aid in cooling the electronic components.

[0049] In one embodiment, at least one of the bottom and top substrates includes a thermally conductive insulating sheet covered with respective conductive layers on its two opposite main surfaces. Therefore, either substrate can comprise a stack consisting of a central electrically insulating and thermally conductive layer (e.g., a ceramic layer) and respective conductive layers (e.g., copper or aluminum layers, wherein the respective conductive layers may be continuous or patterned layers) covering the two opposite main surfaces of the central electrically insulating and thermally conductive layer. For example, such a stacked substrate can be a direct copper bond (DCB) substrate and a direct aluminum bond (DAB) substrate. However, each substrate can also be configured as an active metal brazing (AMB) substrate or a patterned metal plate (e.g., a lead frame).

[0050] Providing a bottom substrate with high thermal conductivity and a top substrate with high thermal conductivity allows for the creation of a dual-sided cooling architecture.

[0051] In one embodiment, the package includes conductive connectors (e.g., leads of a lead frame) electrically coupled to a first pad via spacers configured as conductive clips. Thus, the spacers can also cooperate to function as clips. Such clip-type spacers can be specifically configured to electrically couple pads of electronic components to conductive connectors located at a different vertical height from the pads.

[0052] In one embodiment, the package includes an encapsulating material that encapsulates at least a portion of the electronic component and at least a portion of the spacer. For example, such encapsulating material may be a molding compound or a soft encapsulating material. In the context of this application, the term "encapsulating material" may specifically refer to a substantially electrically insulating and preferably thermally conductive material that surrounds at least a portion of the electronic component and at least a portion of the spacer to provide mechanical protection, electrical insulation, and optionally contributes to heat dissipation during operation.

[0053] In one embodiment, the mounting surface of the spacer is larger than the area of ​​the first pad. This oversized spacer enhances its ability to carry heat (and electricity) and can advantageously help suppress hot spots.

[0054] In one embodiment, the second pad is shaped according to at least one of the group consisting of rounded, particularly circular, and angular, particularly hexagonal or octagonal shapes. While other geometries of the second pad are possible, it may be advantageous to adjust the contours of the first and second pads to achieve a constant spacing between them to reliably maintain dielectric decoupling between the pads.

[0055] In one embodiment, the first pad is formed as a rectangular metal layer, wherein the opening slot extends to one side of the rectangular metal layer, particularly the short side. This pad geometry is particularly advantageous for achieving proper electrical reliability.

[0056] In one embodiment, the outer surfaces of the first and second pads are made of the same material. This allows for different possibilities for pad interconnection, such as by soldering or wire connection. In particular, the second pad can make an electrical contact via a solder structure, connecting wire, or clamp.

[0057] In one embodiment, the package includes multiple electronic components. Therefore, the package may include one or more electronic components (e.g., at least one passive component, such as a capacitor, and at least one active component, such as a semiconductor chip).

[0058] In one embodiment, the at least one electronic component includes at least one of the group consisting of controller circuitry, driver circuitry, and power semiconductor circuitry. All these circuits can be integrated into a single semiconductor chip or integrated into different chips. For example, the corresponding power semiconductor application can be implemented by a chip, wherein the integrated circuit elements of such a power semiconductor chip can include at least one transistor (particularly a MOSFET, metal-oxide-semiconductor field-effect transistor), at least one diode, etc. In particular, circuits implementing half-bridge functions, full-bridge functions, etc., can be fabricated.

[0059] In one embodiment, the package is configured as a power converter, particularly one of an AC / DC power converter and a DC / DC power converter. However, other electronic applications, such as inverters, are also possible.

[0060] As a substrate or wafer for a semiconductor chip, a semiconductor substrate, namely a silicon substrate, can be used. Alternatively, silicon oxide or another insulating substrate can be provided. Germanium substrates or III-V semiconductor materials can also be implemented. For example, exemplary embodiments can be implemented using GaN or SiC technology.

[0061] Furthermore, exemplary embodiments may utilize standard semiconductor processing techniques, such as appropriate etching techniques (including isotropic and anisotropic etching techniques, particularly plasma etching, dry etching, and wet etching), patterning techniques (which may involve photolithographic masks), and deposition techniques (e.g., chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), sputtering, etc.).

[0062] The above and other objects, features and advantages will become apparent from the following description and the appended claims, taken in conjunction with the accompanying drawings, wherein like parts or elements are indicated by like reference numerals. Attached Figure Description

[0063] The accompanying drawings, which are included to provide a further understanding of exemplary embodiments and form part of the specification, illustrate exemplary embodiments.

[0064] In the diagram:

[0065] Figure 1 A top view of a preform of an encapsulation body according to an exemplary embodiment is shown.

[0066] Figure 2 It shows that according to Figure 1 Top view of the package after the spacer is installed.

[0067] Figure 3 A top view of the package after the spacer is installed, according to another exemplary embodiment, is shown.

[0068] Figure 4 It shows that according to Figures 1 to 3 A top view of a preform of any of the packages shows the active area of ​​the electronic components within the package.

[0069] Figure 5 A three-dimensional view of a package having electronic components and spacers between a bottom substrate and a top substrate, according to another exemplary embodiment, is shown.

[0070] Figure 6A cross-sectional view of a package having a clip-type spacer is shown according to another exemplary embodiment.

[0071] Figure 7 A top view of a package according to another exemplary embodiment is shown.

[0072] Figure 8 A cross-sectional view of the package according to yet another exemplary embodiment is shown.

[0073] Figure 9 A cross-sectional view of the package according to yet another exemplary embodiment is shown.

[0074] Figures 10 to 12 Different configurations of source pads and gate pads that are substantially equidistant from each other are shown according to an exemplary embodiment. Detailed Implementation

[0075] The illustrations in the attached figures are schematic and not drawn to scale.

[0076] Before describing exemplary embodiments in more detail with reference to the accompanying drawings, some general considerations will be summarized based on exemplary embodiments that have been developed.

[0077] Typically, spacers are mounted on the top front side of a semiconductor chip. In such a conventional design, the semiconductor chip may have rectangular source pads. In this conventional design, the spacer geometry can match the rectangular shape. The spacer can be soldered onto the source pads of the semiconductor chip, allowing the rectangular spacer to match the shape of the pads.

[0078] However, this conventional design can pose a risk of assembly- or stress-related short circuits between the gate and source pads if interconnect materials, such as solder paste, inadvertently contact the gate pads. Therefore, very precise assembly processes are traditionally required to ensure tight spacing between the gate and source. To relax assembly design rules, the spacing between adjacent pads must be increased. This typically limits the compactness of the package.

[0079] According to an exemplary embodiment, a spacer (which in one embodiment may be configured as a clip) may span one or more electrically insulating (e.g., imide) regions on the front side of an electronic component. Therefore, providing a spacer whose shape must be identical to that of the source pads may be unnecessary, and vice versa. This provides front-end designers with greater freedom in chip layout. In particular, a spacer may be provided that spans electrically insulating regions on the chip and connects only to metallized pad regions. Specifically, such a configuration ensures that heat can be efficiently transferred from the chip-type electronic component to the top portion of the package or module. Advantageously, localized hot spots can be reduced or even avoided. Therefore, with better heat dissipation, the package or module can operate under higher current conditions, thereby achieving improved performance. Production yield losses due to unconnected front-side segments or misaligned spacers can be reduced.

[0080] Advantageously, chip designs for electronic components, including source pads with open notches and gate pads spaced substantially equidistant from the source pads in the region of the open notches, allow for clamp bonding without requiring the highest precision pick-and-place tools. Such chip designs can also increase or even maximize the ratio of active area to total area. Furthermore, chip-type electronic components can be designed to allow for different methods of gate bonding. In particular, fine-line gate bonding may be a viable option.

[0081] More specifically, in applications with, for example, double-sided cooled packages or modules, exemplary embodiments may connect the front side of chip-type electronic components to spacers. Such a package with double-sided cooling may include a stack of electronic components and spacers located between a bottom-side first carrier (particularly a direct copper bond (DCB) substrate) and a top-side second carrier (particularly another direct copper bond (DCB) substrate). This ensures improved heat transfer from active regions on the semiconductor chip-type electronic components, particularly through the spacers, to the top side of the package.

[0082] According to an exemplary embodiment, the shape of the front-side metallization structure of the semiconductor chip does not need to match the shape of the spacer, thereby enabling a high degree of freedom in chip design. Furthermore, stable production yields can be established through soft soldering of the spacers.

[0083] Significant benefits can be obtained, particularly when using silicon carbide (SiC) chips, as illustrated in the exemplary embodiments. Silicon carbide chips can be relatively small (e.g., they can have a size of less than 30 mm). 2It is highly advantageous to cover as much of the active area as possible in such a semiconductor chip (surface area). In particular, SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) can be advantageously fabricated according to exemplary embodiments. More advantageously, additional space can be provided for the gate contacts of the electronic components. In contrast to conventional spacer designs, exemplary embodiments can avoid localized hot spots, which can advantageously result in increased power output and / or reduced losses. Meanwhile, exemplary embodiments do not compromise manufacturability concepts and related parameters (e.g., number of units manufactured per hour and yield). Furthermore, exemplary embodiments are compatible with connecting electronic components via one or more clips. Additionally, packages with improved reliability and / or power output can be obtained. Moreover, reduced research and development effort can be achieved due to the greater freedom in chip layout. More advantageously, the described configuration can achieve a favorable ratio of active area to total area, enabling the fabrication of packages using semiconductor chips smaller than conventional designs.

[0084] In one embodiment, the opening notch of the source pad can be formed in the short side of a generally rectangular pad. Advantageously, such a design is symmetrical along the long side of the generally, but not exactly, rectangular pad design. This ensures proper thermal and electrical reliability as well as high package performance.

[0085] Figure 1 A top view of a preform of a package 100 according to an exemplary embodiment is shown. Figure 2 The following is shown after the installation of the spacer 110. Figure 1 Top view of the package 100.

[0086] Figure 2 The package 100 includes an electronic component 102, which can advantageously be implemented as a semiconductor chip, for example, manufactured using silicon or silicon carbide technology. The electronic component 102 can be a transistor chip, more particularly a MOSFET chip. Additionally or alternatively, the electronic component 102 can have different electronic functions, for example, it can be implemented as an insulated-gate bipolar transistor (IGBT), a diode, etc.

[0087] Figure 1 and Figure 2 The upper first main surface 104 of an electronic component 102 is shown, having a conductive first pad 106 with an opening slot 108. The first pad 106 is implemented here as a source pad. Furthermore, the first main surface 104 has an electrically insulating region 112 at the opening slot 108 and surrounding the first pad 106. More specifically, as shown... Figure 1As shown, the first pad 106 may be composed of multiple (three in the illustrated embodiment) pad segments 106a, 106b, and 106c. Adjacent pad segments 106a / 106b, 106b / 106c may optionally be separated by corresponding dielectric strips 152 (e.g., made of polyimide) on the electrically insulating surface 150 of the electrically insulating region 112. The dielectric strips 152 may protrude vertically beyond the pad segments 106a, 106b, and 106c, may be vertically flush with the pad segments 106a, 106b, and 106c, or may even be vertically recessed relative to the pad segments 106a, 106b, and 106c. As shown in the figure, pad segments 106a and 106b can be rectangular, while pad segment 106c of the first pad 106 can have an opening slot 108 on the side opposite to pad segments 106a and 106b. The opening slot 108 is implemented here as a trapezoidal recess in pad segment 106c facing a second pad 120 formed on the same first main surface 104 of the electronic component 102. Preferably, the outer surfaces of the first pad 106 and the second pad 120 are made of the same material. The second pad 120 is configured here as a gate pad of the electronic component 102. More specifically, the opening slot 108 is defined by a continuous edge line of the first pad 106 and opens toward the peripheral portion of the first pad 106 and toward the second pad 120.

[0088] like Figure 2 As shown, spacer 110 is mounted on first pad 106. Preferably, spacer 110 is electrically and thermally conductive and should be made of a material that can be connected to first pad 106. For example, spacer 110 can be made of copper, aluminum, AlSiC, or any electrically and thermally conductive composite material. Advantageously, the material of spacer 110 is solderable. Preferably, spacer 110 is soldered to first pad 106 (e.g., by diffusion soldering). Alternatively, the connection between spacer 110 and first pad 106 of electronic component 102 can be achieved by sintering, fusion welding, or gluing (preferably using conductive adhesive). During operation of package 100, current can be conducted between first pad 106 and spacer 110. Furthermore, heat generated by electronic component 102 during operation can be removed from package 100 through spacer 110.

[0089] exist Figure 2 In this configuration, the spacer 110 can be implemented as a rectangular block having a rectangular ground surface connected to a first pad 106 of the electronic component 102. Similarly, as... Figure 2As shown, the rectangular grounding surface of the spacer 110 is mounted on the first pad 106 to span a portion of the opening slot 108. More specifically, the grounding surface of the spacer 110 is directly soldered onto the main portion of the first pad 106 and also covers or spans the main portion of the opening slot 108 of the first pad 106. Thus, a portion of the grounding surface of the spacer 110 (more specifically, according to...) Figure 2 The lower portion of the spacer 110 is electrically and thermally coupled to the extended sections 116 and 118 formed between the opening slot 108 of the first pad 106. The bottom of the opening slot 108 is defined by the dielectric material of the electrically insulating surface 150 of the electronic component 102. In the region of the opening slot 108, no direct physical contact is established between the ground surface of the spacer 110 and the electrically insulating surface 150. Therefore, the spacer 110 spans the opening slot 108 without physical contacting the electrically insulating region 112. In addition to spanning the opening slot 108, the spacer 110 is mounted on substantially the entire rectangular section 114, almost the entire first extended section 116 of the first pad 106, and almost the entire second extended section 118, thereby ensuring efficient electrical and thermal coupling between the electronic component 102 and the spacer 110. Therefore, the rectangular mounting surface of the spacer 110 is larger than the region of the first pad 106. By indirectly ensuring a sufficiently large contact area across the spacer 110 and the first pad 106, the notch design of the first pad 106 can be achieved without creating significant hot spots. Figure 2 As shown by reference numeral 154 in the accompanying drawings, a moderately formed hot spot may appear below the extension sections 116, 118 of the first pad 106. However, this hot spot 154 may not be very noticeable because the thermally conductive spacer 110, with its rectangular grounded surface, also contacts the main portion of the extension sections 116, 118. Therefore, the formation of intensely heated portions can be avoided, without even needing to deviate from the simple rectangular geometry of the spacer 110. Figure 2 The spacer 110 can be manufactured in a simple manner and still ensures proper heat dissipation from the electronic components 102 during operation of the package 100. This can be facilitated by manufacturing the first pad 106 and the mounting surface of the spacer 110 with different geometries.

[0090] like Figure 1 Ideally, the first pad 106 has a rectangular segment 114 (composed of the entire pad segments 106a, 106b and a portion of pad segment 106c) connecting to the first extension segment 116 and the second extension segment 118 (both of which are formed by another portion of pad segment 106c). As shown, the extension segments 116 and 118 are spaced apart from each other by an opening slot 108. The opening slot 108 of the first pad 106 is defined by the opposing edges of the extension segments 116 and 118 and the horizontal edge of pad segment 106c. Figure 1 and Figure 2 The opposing edges of the extension sections 116 and 118 are straight and sloping, while the additional slot defining edge of the pad section 106c is arranged horizontally. Given this configuration, in the illustrated embodiment, the opening slot 108 is trapezoidal in shape.

[0091] As described above, the electronic component 102 has a second conductive pad 120 on the first main surface 104. As shown, the second pad 120 is arranged beside the opening slot 108. More specifically and very advantageously, the second pad 120 is arranged to be substantially equidistant from the first pad 106 along the entire extension of the opening slot 108. In other words, the distance d between the first pad 106 and the second pad 120 is exactly or nearly the same along the slot-related facing portions of the first pad 106 and the second pad 120. In other words, the source-to-gate distance is the same at any location. For example, the distance d can be in the range of 100 μm to 3 mm, particularly in the range of 500 μm to 2 mm, for example, 900 μm. This distance d reliably prevents solder material (which can temporarily become flowable to contact the first gate pad 106 with the spacer 110) from continuing to flow to the second pad 120. Therefore, the formation of undesirable conductive paths can be reliably prevented. The resulting reliable electrical isolation between the source pad 106 and the gate pad 120 offers the greatest advantage for high-current applications.

[0092] To ensure the substantially equidistant spacing between the first pad 106 and the second pad 120 in the region of the notch 108, the second pad 120 has an octagonal shape. In the region of the notch 108, both the notch 108 and the second pad 120 are defined by three straight and angled segments (108a, 108b, 108c and 120a, 120b, 120c), wherein corresponding pairs of segments (108a and 120a, 108b and 120b, and 108c and 120c) of the notch 108 and the second pad 120 are parallel to each other. By connecting the first pad 106 to the spacer 110 with a soldering material, this substantially equidistant design rule can significantly suppress the risk of undesirable electrical short circuits between the first pad 106 and the second pad 120 of the electronic component 102. This can improve the electrical reliability of the package 100. Figure 2 The spanning arrangement of spacers 110, as indicated by reference numeral 156 in the figure, can synergistically suppress the formation of hot spots 154 caused by the illustrated chip design, thereby also achieving appropriate thermal reliability and performance.

[0093] like Figure 2As shown, the spacer 110 does not extend to and cross the second pad 120, thereby keeping the second pad 120 free for electrical connection, such as using connecting wires (not shown).

[0094] Although only Figure 1 and Figure 2 The diagram illustrates the point, but electronic component 102 may be located on a second main surface of electronic component 102 opposite to the first main surface 104 (see [reference]). Figure 6 The figure shows a conductive third pad on reference numeral 124 (see figure). Figure 6 (Ref. 122 in the accompanying drawings). The third pad can be configured as the drain pad of a transistor chip-type electronic component 102. The electronic component 102 can therefore be configured as a semiconductor power chip with MOSFET functionality. Advantageously, the MOSFET-type electronic component 102 is configured to experience a vertical current during operation, i.e., a current perpendicular to... Figure 1 and Figure 2 The semiconductor material of electronic component 102 passes through the paper surface.

[0095] Therefore, as Figure 1 and Figure 2 The illustrated embodiment provides an oversized spacer 110 for improved thermal performance through a simple spacer design. This allows for the connection of nearly the entire source pad 106 and its trapezoidal (or V-shaped) opening slot 108 to the spacer 110 while maintaining a simple rectangular shape for the spacer 110. The opening slot design of the first pad 106 of the electronic component 102 is well compatible with the rectangular design of the spacer 110. The imide region of the electrically insulating region 112 in the opening slot 108 can be traversed by the spacer 110 (and is therefore unaffected). This oversized design of the spacer 110 can efficiently reduce the hotspot area, i.e., the area according to reference numeral 154, without requiring direct connection to the spacer 110. This reduction in hotspot area can be, for example, approximately 50%. Due to the aforementioned design of the first pad 106 and the spacer 110, heat can be generated perpendicular to the... Figure 2The paper efficiently transfers the material upwards to the top of the module or package 100. Further advantageously, the technology of the described embodiments does not involve significant complexity in the manufacturing architecture. While the oversized spacer 110 can also be soldered to the extension segments 116, 118, the spacer 110 can partially span the imide material of the electrically insulating region 112 (i.e., soldering may not be performed here). The increased contact area between the spacer 110 and the first pad 106 dissipates more heat and thus allows for higher output current. A proper match is achieved between the illustrated chip design with a substantially constant gate-source distance (d) and the oversized and spanning spacer design. As a further advantage, the implementation of the oversized spacer 110 can even exhibit improved positioning during soldering. When manufacturing according to... Figure 2 When the package size is 100, production volume can be increased.

[0096] For example, the rectangular spacer 110 can have spatial dimensions of 5.1 mm × 3.0 mm × 1.0 mm. Such a spacer 110 can substantially completely cover the three segments or sections 106a, 106b, and 106c of the source-type first pad 106. The spacer 110 can be symmetrically positioned on the chip-type electronic component 102. The trapezoidal or V-shaped imide notch 108 near the second pad 120 (configured as a gate pad) can be partially or completely spanned by the spacer 110. In a top view of the package 100, the oversized spacer 110 can protrude laterally into the opening notch 108. This package design achieves good yield.

[0097] Figure 3 A top view of the package 100 after the mounting spacer 110 is shown according to another exemplary embodiment.

[0098] Figure 3 Implementation examples and Figure 2 The difference in the embodiment is that the spacer 110 has a smaller size. The spacer 110, having a rectangular bottom surface, is not covered according to... Figure 3 The extension sections 116 and 118 of the first pad 106. Therefore, according to Figure 3 Hot Topics 154 and Figure 2 This is more obvious in comparison. However, due to the smaller spacer 110, according to Figure 3 The package 100 can be more than according to Figure 2 The package is manufactured to be more compact. In applications where medium power or sufficient current is required for operation, depending on... Figure 3 The package 100 can be a compact and lightweight option.

[0099] You can also from Figure 3As can be seen, the embodiment can also implement a silicon carbide chip as an electronic component 102, the silicon carbide chip having a generally rectangular source pad 106 with an opening notch 108 to provide a constant distance d between the source pad 106 and the gate pad 120 along the opening notch 108. This chip design ensures that the spacing between the source pad 106 and the gate pad 120 is constant along the periphery of the serrated, notched, or recessed portion of the source pad 106. This can be achieved by introducing a cornered gate pad 120 (e.g., having a hexagonal or octagonal profile) or alternatively by rounding the gate pad (…). Figure 3 (Not shown in the diagram) is used to achieve this. The notch within the source pad 106 allows for the same geometry, thus maintaining a constant distance d.

[0100] Figure 4 It shows that according to Figure 3 The diagram shows a top view of a preform of the package 100, with particular emphasis on the active region 158 of the electronic component 102 within the package 100. Since the area beneath the gate pad 120 can be an active region, i.e., it can be disposed outside the active region 158, configuring the gate pad 120 with the shape shown can reduce losses in the active region 158 of the electronic component 102. In contrast, the source pad 106 can be formed on the active region 158. The active region 158 of the electronic component 102 may correspond to the region of the semiconductor body that is processed to form one or more integrated circuit elements of the electronic component 102. Descriptively, the active region 158 represents the region of the electronic component 102 that becomes hot during operation of the package 100.

[0101] More generally, the metallization structure of the gate pad 120 can have the same finishing characteristics as the source pad 106. This allows for different possibilities in gate interconnection: the gate pad 120 can be soldered as well as joined by ball joints. By making the gate pad 120 rounded or nearly rounded (e.g., octagonal) in shape, solder balls can even be placed on the gate pad 120 at the wafer level. In this case, the gate pad 120 can also be connected to a clip (not shown).

[0102] Refer again Figure 3 The spacer 110 does not cover the opening 108 of the source pad 106. Therefore, a large portion of the active region 158 of the chip-type electronic component 102 is not directly coupled to the spacer 110 (comparatively). Figure 3 and Figure 4 Therefore, with Figure 2 Compared to the previous embodiment, according to Figure 3 Hotspot 154 can be more prominent. However, this can be achieved through implementation. Figure 2 The configuration of the extra-large spacer and / or by reducing Figure 3The power output of the module or package 100 is used to avoid localized overheating, which may be sufficient for the requirements of some applications.

[0103] Finally, when high thermal performance and high power output are required, Figure 2 This embodiment may be preferred. When a compact and lightweight configuration is required, Figure 3 The embodiments described are likely preferred. When the source pad 106 is connected to the spacer 110, both embodiments provide reliable protection against unwanted solder flowing to the gate pad 120.

[0104] Figure 5 A three-dimensional view of a package 100 having electronic components 102 and spacers 110 between a bottom substrate 126 and a top substrate 128, according to another exemplary embodiment, is shown. Figure 5 It can be seen that the configuration of spacer 110, first pad 106 and second pad 120 can be consistent with... Figure 2 Similarities. However, alternatively, according to Figure 3 The relationship between the spacer 110 and the first pad 106 can also be found in Figure 5 The implementation is carried out in the example.

[0105] like Figure 5 As shown, package 100 includes a bottom substrate 126 on which electronic components 102 are mounted. Furthermore, package 100 includes a top substrate 128 mounted on a spacer 110. Each of the bottom substrate 126 and the top substrate 128 may include a central thermally conductive insulating sheet 130 (particularly a ceramic plate) covered with corresponding conductive layers 132, 134 (e.g., patterned or continuous copper layers) on its two opposite main surfaces. Therefore, each of substrates 126, 128 may be a direct copper bond (DCB) substrate. Alternatively, either substrate 126, 128 may be implemented as a direct aluminum bond (DAB) substrate, an active metal brazing (AMB) substrate, or a patterned metal plate (e.g., a lead frame).

[0106] like Figure 5 As indicated by reference numeral 160 in the figure, any connection between the bottom substrate 126 and the electronic component 102, between the electronic component 102 and the spacer 110, and between the spacer 110 and the top substrate 128 may be a solder joint.

[0107] like Figure 5As schematically shown, package 100 may include encapsulating material 138 encapsulating at least a portion of electronic component 102 and at least a portion of spacer 110. One or both of substrates 126 and 128 may also be encapsulated by encapsulating material 138. Preferably, encapsulating material 138 is a molding compound. Alternatively, encapsulating material 138 may be a soft potting compound. Optionally, the molding compound may be provided with functional particles, such as ceramic particles (e.g., made of alumina, aluminum nitride, silicon oxide, etc.), to enhance the thermal conductivity of encapsulating material 138.

[0108] Figure 5 The architecture shown provides a dual-sided cooling (DSC) module or package 100. Therefore, heat generated by the electronic components 102 during operation of the package 100 can be removed from the package 100 via the top substrate 128 in an upward direction and via the bottom substrate 126 in a downward direction. Specifically, the top side of the spacer 110 is connected to the bottom side of the top substrate 128. This allows heat to be transferred from the chip-type electronic components 102 to the top side as well. By taking this measure, the thermal performance of the package 100 can be significantly improved compared to the conventional concept of heat dissipation only through the bottom side of the module. Figure 5 The spacer 110 thermally and electrically connects the electronic component 102 to the top substrate 128. This allows current and heat to flow along the path of electronic component 102-spacer 110-top substrate 128.

[0109] In order to manufacture a device configured for double-sided cooling Figure 5 The solder paste can be printed onto the electronic component 102, for example, using a stencil. Then, a pick-and-place process can manipulate the spacer 110 onto the stored solder. Different pick-and-place tools can be implemented for different spacer sizes. The stack consisting of the bottom substrate 126, the electronic component 102, the spacer 110, and the top substrate 128 can then be interconnected by soldering.

[0110] Figure 6 A cross-sectional view of a package 100 having a clip-type spacer 110 according to another exemplary embodiment is shown.

[0111] according to Figure 6 The drain pad 122 on the bottom side of the electronic component 102 is mounted on a leadframe-type bottom substrate 126, i.e., a patterned metal plate. More specifically, the electronic component 102 can be mounted on a die pad of the leadframe-type bottom substrate 126. The gate pad 120 on the opposite side of the electronic component 102 is electrically connected to the leads of the bottom substrate 126 via connecting wires 162. The source pad 106 on the same side of the electronic component 102 is coupled to the spacer 110. The source pad 106 can be configured with an opening notch 108, for example, as shown in the image. Figure 2As shown. The described configuration is encapsulated in an encapsulating material 138, particularly a molding compound. However, the upper surface of the spacer 110 is exposed relative to the encapsulating material 138 to allow for more efficient cooling.

[0112] Furthermore, the conductive connector 136 is electrically coupled to the first pad 106 via the spacer 110. Descriptively, the spacer 110 thus also functions as a conductive clip. In the illustrated embodiment, the conductive connector 136 is a lead of the leadframe-type bottom substrate 126.

[0113] Figure 7 A top view of a package 100 according to another exemplary embodiment is shown.

[0114] Figure 7 The embodiments differ from Figure 2 The embodiments, particularly regarding the configuration of the spacer 110. Although the spacer 110 has according to Figure 2 A rectangular mounting surface, but Figure 7 The spacer 110 has an opening 109 that aligns with the opening 108 of the first pad 106. For example... Figure 7 As shown, the spacer 110 is mounted on the first pad 106 such that the opening slot 108 of the first pad 106 overlaps and aligns with the opening slot 109 of the spacer 110. In other words, the outline of the first pad 106 substantially corresponds to the outline of the spacer 110. Figure 7 The spacer 110 does not extend across the opening slot 108, but rather substantially covers the entire first pad 106 and does not extend over the electrically insulating area 112. In other words, the mounting surfaces of the first pad 106 and the spacer 110 have the same geometry. Specifically, the extensions 166 and 168 of the spacer 110 forming the opening slot 109 cover the extensions 116 and 118 of the first pad 106.

[0115] Descriptively, the generally rectangular geometry of the spacer 110 with the notch 109 mimics the generally rectangular geometry of the source pad 106 with the notch 108. Thus, the spacer configuration is fully compatible with the configuration of the first pad 106 with the notch 108, together with the second pad 120 equidistantly spaced from the first pad 106 along the notch 108. As with the notch 108, the notch 109 is also based on... Figure 7 It has a trapezoidal shape.

[0116] like Figure 2 and Figure 3 As shown, Figure 7 The first pad 106 is formed as a rectangular metal layer with an opening slot 108, the opening slot 108 extending into the short side of the rectangular metal layer. Accordingly, Figure 7The spacer 110 is formed as a rectangular metal block with an opening slot 109 extending into the short side of the rectangular metal block. In the top view, the opening slots 108 and 109 are aligned with each other.

[0117] Figure 8 A cross-sectional view of a package 100 according to yet another exemplary embodiment is shown.

[0118] and Figure 5 similar, Figure 8 The package 100 includes a bottom-side ceramic substrate 126 (e.g., DCB or AMB), on which electronic components 102 (e.g., silicon, silicon carbide, or gallium nitride semiconductor chips) are mounted. Accordingly, Figure 8 The package 100 includes a top-side ceramic substrate 128 (e.g., DCB or AMB) mounted on a spacer 110.

[0119] As shown by reference numeral 160 in the figure, interconnect layers (e.g., including diffused solder, Ag / Cu sinter, adhesive) are arranged between substrate 126 and electronic component 102, between electronic component 102 and spacer 110, and between spacer 110 and substrate 128.

[0120] Figure 9 A cross-sectional view of a package 100 according to yet another exemplary embodiment is shown.

[0121] Figure 9 The package 100 includes a conductive connector 136 electrically coupled to a first pad 106 via a spacer 110, the spacer 110 thus configured as a conductive clip in addition to its spacer function. For example, the spacer 110 may be made of copper. Regarding the configuration of the substrate 126, electronic components 102, and interconnect layer 160, refer to... Figure 8 The description.

[0122] Figures 10 to 12 Different configurations of source pad 106 and gate pad 120 on the same main surface 104 of electronic component 102 according to several exemplary embodiments are shown, wherein there is a substantially constant distance d between source pad 106 and gate pad 120 along the extension of the opening slot 108 of source pad 106.

[0123] refer to Figure 10 The generally rectangular source pad 106 has a rectangular (particularly square) slot 108, wherein a rectangular (particularly square) gate pad 120 is arranged along the slot 108 in such a way that there is a constant distance d between the edge of the source pad 106 and the edge of the gate pad 120.

[0124] refer to Figure 11The generally rectangular source pad 106 has a triangular notch 108, wherein a rectangular (particularly square) gate pad 120 is arranged along the notch 108 in such a way that there is a constant distance d between the edge of the source pad 106 and the edge of the gate pad 120.

[0125] refer to Figure 12 The generally rectangular source pad 106 has a semi-circular slot 108, wherein a circular gate pad 120 is arranged along the slot 108 in such a way that there is a constant distance d between the edge of the source pad 106 and the edge of the gate pad 120.

[0126] It should be noted that the term "comprising" does not exclude other elements or features, and "an" or "a" does not exclude a plurality. Furthermore, elements described in association with different embodiments may be combined. It should also be noted that reference numerals should not be construed as limiting the scope of the claims. Moreover, the scope of this application is not intended to be limited to specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Therefore, the appended claims are intended to include such processes, machines, manufactures, compositions of matter, means, methods, or steps within their scope.

Claims

1. A package (100), comprising: • An electronic component (102) having a first main surface (104) with a conductive first pad (106), the first pad (106) having an opening slot (108); and • A spacer (110) mounted on the first pad (106) and spanning at least a portion of the opening slot (108); • The electronic component (102) has a conductive second pad (120) on the first main surface (104); • The second pad (120) is arranged as an opening slot (108) adjacent to the first pad (106); • The spacer (110) does not extend over the second pad (120); • The second pad (120) is arranged to be substantially equidistant from the first pad (106) along the opening slot (108) of the first pad (106); • The second pad (120) is shaped according to at least one of the group consisting of circles, hexagons and octagons.

2. A package (100), comprising: • An electronic component (102) having a first main surface (104) with a conductive first pad (106), the first pad (106) having an opening slot (108); and • A spacer (110) having an opening slot (109) and mounted on a first pad (106) such that the opening slot (108) of the first pad (106) at least partially overlaps with the opening slot (109) of the spacer (110). • The electronic component (102) has a conductive second pad (120) on the first main surface (104); • The second pad (120) is arranged as an opening slot (108) adjacent to the first pad (106); • The spacer (110) does not extend over the second pad (120); • The second pad (120) is arranged to be substantially equidistant from the first pad (106) along the opening slot (108) of the first pad (106); • The second pad (120) is shaped according to at least one of the group consisting of circles, hexagons and octagons.

3. The package (100) according to claim 1 or 2, wherein, The first primary surface (104) has an electrically insulating region (112) at the opening slot (108) of the first pad (106).

4. The package (100) according to claim 3, wherein, The spacer (110) spans the opening slot (108) of the first pad (106) without directly physical contacting the electrically insulating region (112).

5. The package (100) according to any one of claims 1-2 and 4, wherein, The package (100) includes at least one of the following features: The spacer (110) is thermally and / or electrically conductive; The spacer (110) is mounted on the first pad (106) of the electronic component (102) in a thermally and / or electrically conductive manner; The spacer (110) is mounted on the first pad (106) by one of the group consisting of soldering, sintering, fusion and adhesion.

6. The package (100) according to any one of claims 1-2 and 4, wherein, The mounting surfaces of the first pad (106) and the spacer (110) have different geometries.

7. The package (100) according to any one of claims 1-2 and 4, wherein, The mounting surfaces of the first pad (106) and the spacer (110) have the same geometry.

8. The package (100) according to any one of claims 1-2 and 4, wherein, The first pad (106) has a rectangular section (114) connected to a first extension section (116) and a second extension section (118), the first and second extension sections (116, 118) being spaced apart from each other by an opening slot (108) of the first pad (106).

9. The package (100) according to claim 1 or 4, wherein, The mounting surface of the spacer (110) is rectangular.

10. The package (100) according to claim 8, wherein, The spacer (110) is mounted on at least a portion of the rectangular section (114); at least a portion of the first extension section (116); and at least a portion of the second extension section (118).

11. The package (100) according to any one of claims 1-2, 4, and 10, wherein, The opening slot (108) of the first pad (106) is shaped according to at least one of the group consisting of round, trapezoidal, generally V-shaped, generally U-shaped and rectangular.

12. The package (100) according to any one of claims 1-2, 4, and 10, wherein, The electronic component (102) has a conductive third pad (122) on a second main surface (124) opposite to the first main surface (104).

13. The package (100) according to any one of claims 1-2, 4, and 10, wherein, The package (100) includes at least one of the following features: The electronic component (102) is a semiconductor power chip; The electronic component (102) is configured to be subjected to vertical current flow during operation; The electronic component (102) is a transistor chip; The first pad (106) is the source pad; The second pad (120) is the gate pad; The third pad (122) is the drain pad; The package (100) includes a bottom substrate (126) on which electronic components (102) are mounted; The package (100) includes a top substrate (128) mounted on a spacer (110); The package (100) includes a conductive connector (136) electrically coupled to a first pad (106) via a spacer (110) configured as a conductive clip; The package (100) includes encapsulating material (138) for at least a portion of the electronic component (102) and at least a portion of the spacer (110); The area of ​​the mounting surface of the spacer (110) is larger than the area of ​​the first pad (106).

14. The package (100) according to claim 8, wherein, The spacer (110) is installed on each of the entire rectangular section (114); the entire first extension section (116); and the entire second extension section (118).

15. A method for manufacturing a package (100), wherein, The method includes: • Provides an electronic component (102) having a first main surface (104) with a first conductive pad (106), the first pad (106) having an opening slot (108); and • The spacer (110) is mounted on the first pad (106) such that the spacer (110) spans at least a portion of the opening slot (108); • The second pad (120) is arranged as an opening slot (108) adjacent to the first pad (106); • The spacer (110) does not extend over the second pad (120); • The electronic component (102) has a conductive second pad (120) on the first main surface (104); • The second pad (120) is arranged to be substantially equidistant from the first pad (106) along the opening slot (108) of the first pad (106); • The second pad (120) is shaped according to at least one of the group consisting of circles, hexagons and octagons.

16. A method for manufacturing a package (100), wherein, The method includes: • Provides an electronic component (102) having a first main surface (104) with a first conductive pad (106), the first pad (106) having an opening slot (108); and • A spacer (110) with an opening slot (109) is mounted on a first pad (106) such that the opening slot (108) of the first pad (106) at least partially overlaps with the opening slot (109) of the spacer (110). • The electronic component (102) has a conductive second pad (120) on the first main surface (104); • The second pad (120) is arranged as an opening slot (108) adjacent to the first pad (106); • The spacer (110) does not extend over the second pad (120); • The second pad (120) is arranged to be substantially equidistant from the first pad (106) along the opening slot (108) of the first pad (106); • The second pad (120) is shaped according to at least one of the group consisting of circles, hexagons and octagons.

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