An encapsulation structure and a preparation method thereof

Abstract

The present invention provides a packaging structure and preparation method, comprising: a lower package body, an upper package body, and a first redistribution stack layer disposed between the lower and upper package bodies, the first redistribution stack layer electrically connecting the lower and upper package bodies; the lower package body comprising a prefabricated substrate and a first plastic encapsulation layer surrounding the prefabricated substrate; wherein the minimum line width / line spacing of the first redistribution stack layer is smaller than the minimum line width / line spacing of the prefabricated substrate; the lower package body comprising a prefabricated substrate and the first redistribution stack layer disposed above the prefabricated substrate and having a smaller minimum line width / line spacing than the prefabricated substrate. Utilizing the first redistribution stack layer with a smaller line width / line spacing enables the integration of more chips and / or device packages into the packaging structure.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and in particular relates to a packaging structure and a preparation method thereof. Background Art

[0002] The rapid development of high-speed computing and artificial intelligence has placed higher demands on the packaging of semiconductor chips and packages. This is particularly true for packaging substrates, which typically require laminates with narrower line widths and spacings and better voltage drop control. Traditional laminate substrate wiring typically has a line width and spacing of around 15µm / 15µm, which is increasingly unable to meet the high-density packaging requirements of electronic components used in high-speed computing and artificial intelligence.

[0003] In addition, traditional laminate substrate technology has great difficulties in 1) the supply of stacked dielectric materials; 2) manufacturing cycle; 3) wiring with a line width of less than 10um and yield control of embedded chips.

[0004] Therefore, it is necessary to propose a new packaging structure and preparation method to overcome the problem that traditional laminated substrates cannot meet the requirements of high-density packaging due to the wide line width / line spacing of the wiring. Summary of the Invention

[0005] The present invention provides a packaging structure and a preparation method, so that a prefabricated substrate with a large line width / line spacing can meet the requirements of high-density integration.

[0006] To solve the above problems, the technical solution of the present invention provides a packaging structure, which includes: a lower packaging body, an upper packaging body arranged above the lower packaging body, and a first redistribution stacking layer arranged between the lower packaging body and the upper packaging body, the first redistribution stacking layer electrically connecting the lower packaging body and the upper packaging body; the lower packaging body includes a prefabricated substrate and a first plastic packaging layer surrounding the periphery of the prefabricated substrate; the upper packaging body includes an interconnection chip packaging layer arranged above the first redistribution stacking layer, a second redistribution stacking layer arranged above the interconnection chip packaging layer and a packaging layer with a chip and / or device packaging body arranged above the second redistribution stacking layer; the interconnection chip packaging layer includes a plurality of metal conductive pillars and a second plastic packaging layer, the second plastic packaging layer plastic-seales the plurality of metal conductive pillars above the first redistribution stacking layer, and the first redistribution stacking layer and the second redistribution stacking layer are electrically connected through the plurality of metal conductive pillars; wherein the minimum line width / line spacing of the first redistribution stacking layer is smaller than the minimum line width / line spacing of the prefabricated substrate.

[0007] As an optional technical solution, the minimum line width / line spacing of the first redistribution stack layer and the minimum line width / line spacing of the second redistribution stack layer are respectively less than 10 μm.

[0008] As an optional technical solution, the interconnect chip packaging layer also includes an interconnect chip buried in the second plastic packaging layer, and the interconnect chip is bonded directly above the first redistribution stacking layer; and an interconnect redistribution stacking layer is arranged on the surface of the interconnect chip facing the second redistribution stacking layer, the minimum line width / line spacing of the interconnect redistribution stacking layer is less than 2μm, and the interconnect redistribution stacking layer includes at least one capacitor.

[0009] As an optional technical solution, in a packaging layer having a chip and / or device package, the chip and / or the device package are flip-chip bonded above the second redistribution stacking layer and electrically connected to the second redistribution stacking layer; wherein, the packaging layer having the chip and / or device package also includes a third plastic packaging layer, and the third plastic packaging layer plastic-packages the chip and / or device package above the second redistribution stacking layer, and the back side of the chip and / or the back side of the device package are respectively exposed from the third plastic packaging layer.

[0010] As an optional technical solution, the back side of the prefabricated substrate away from the first redistribution stack layer further includes a plurality of metal bumps or solder balls, and the plurality of metal bumps or solder balls are electrically connected to the conductive layer in the prefabricated substrate.

[0011] As an optional technical solution, it also includes: at least one first silicon capacitor chip and / or at least one second silicon capacitor chip; wherein, the at least one first silicon capacitor chip is buried in the first base material layer of the prefabricated substrate, and the at least one first silicon capacitor chip is directly electrically connected to the first redistribution stacking layer; the at least one second silicon capacitor chip is buried in the second plastic encapsulation layer, and the at least one second silicon capacitor chip is directly electrically connected to the first redistribution stacking layer or the second redistribution stacking layer.

[0012] As an optional technical solution, the lower package body also includes: a first prefabricated redistribution stacking layer and / or a second prefabricated redistribution stacking layer, the prefabricated substrate includes a first surface and a second surface relative to each other, the first prefabricated redistribution stacking layer is arranged on one side of the first surface, and the second prefabricated redistribution stacking layer is arranged on one side of the second surface; wherein, the first plastic encapsulation layer is arranged around the first prefabricated redistribution stacking layer and / or the second prefabricated redistribution stacking layer and the prefabricated substrate to form a substrate unit; the minimum line width / line spacing of the first prefabricated redistribution stacking layer and the minimum line width / line spacing of the second prefabricated redistribution stacking layer are respectively less than 10μm.

[0013] As an optional technical solution, a passive component is further included. The passive component is embedded in the first plastic packaging layer and is electrically connected to the first redistribution stack layer.

[0014] As an optional technical solution, a heat dissipation device is further included, and the heat dissipation device is arranged at the edge and / or corner of the first redistribution stack layer.

[0015] As an optional technical solution, the lower packaging body also includes: a third prefabricated redistribution stacking layer and a prefabricated interconnection chip packaging layer arranged between the prefabricated substrate and the first redistribution stacking layer, the third prefabricated redistribution stacking layer is arranged above the prefabricated substrate, and the prefabricated interconnection chip packaging layer is arranged above the third prefabricated redistribution stacking layer; the prefabricated interconnection chip packaging layer includes a plurality of prefabricated metal conductive columns, a prefabricated interconnection chip and a fourth plastic packaging layer, the fourth plastic packaging layer plastic-encapsulates the plurality of prefabricated metal conductive columns and the prefabricated interconnection chip above the third prefabricated redistribution stacking layer; the first redistribution stacking layer and the third prefabricated redistribution stacking layer are electrically connected through the plurality of prefabricated metal conductive columns; wherein, the prefabricated substrate, the first plastic packaging layer, the third prefabricated redistribution stacking layer, the prefabricated interconnection chip packaging layer and the first redistribution stacking layer together constitute a prefabricated packaging substrate.

[0016] The present invention also provides a method for preparing a packaging structure, the preparation method comprising: providing a prefabricated substrate, plastic-sealing the prefabricated substrate to form a first plastic-sealing layer to constitute a lower packaging body; forming a first redistribution stacking layer on one side of the lower packaging body, the first redistribution stacking layer and the prefabricated substrate being electrically connected; and packaging an upper packaging body above the first redistribution stacking layer to obtain a packaging structure; wherein the minimum line width / line spacing of the first redistribution stacking layer is smaller than the minimum line width / line spacing of the prefabricated substrate.

[0017] As an optional technical solution, a prefabricated substrate is provided, and the prefabricated substrate is molded to form a first molding layer. The steps of forming a lower packaging body include: providing a carrier board, temporarily bonding a number of prefabricated substrates pre-cut into single particles to the carrier board; applying molding material to the carrier board, molding the prefabricated substrate to form the first molding layer; separating the first molding layer and the prefabricated substrate from the carrier board to obtain the lower packaging body.

[0018] As an optional technical solution, the upper package body is packaged above the first redistribution stacking layer, and the steps of obtaining the package structure include: forming a plurality of metal conductive pillars above the first redistribution stacking layer; bonding an interconnection chip above the first redistribution stacking layer, and the interconnection chip includes an interconnection redistribution stacking layer and a plurality of conductive bumps above the first redistribution stacking layer; plastic encapsulating the plurality of metal conductive pillars and the interconnection chip to form a second plastic encapsulation layer; thinning the second plastic encapsulation layer to expose the plurality of metal conductive pillars and the plurality of conductive bumps; forming a second redistribution stacking layer above the second plastic encapsulation layer, and the second redistribution stacking layer and the plurality of metal conductive pillars and the conductive bumps are electrically connected; flip-chip bonding the chip and / or device package body above the second redistribution stacking layer; and plastic encapsulating the chip and / or device package body to form a third plastic encapsulation layer.

[0019] As an optional technical solution, it also includes: thinning the side of the first plastic encapsulation layer away from the first redistribution stacking layer to expose the conductive layer on the back side of the prefabricated substrate; implanting solder balls or metal bumps on the conductive layer, and the solder balls or metal bumps are electrically connected to the conductive layer; and thinning the third plastic encapsulation layer to expose the back side of the chip and / or the back side of the device package.

[0020] Compared with the prior art, the present invention provides a packaging structure and a preparation method, wherein the lower packaging body of the packaging structure includes a prefabricated substrate and a first redistribution stacking layer arranged above the prefabricated substrate, and having a minimum line width / line spacing smaller than that of the prefabricated substrate. The first redistribution stacking layer with a smaller line width / line spacing is used to integrate more chips and / or device packages in the packaging structure. In addition, the upper packaging body of the packaging structure includes a metal conductive column for vertical interconnection, a second plastic encapsulation layer, and a second redistribution stacking layer, wherein the second plastic encapsulation layer plastic-encapsulates the metal conductive column, the second redistribution stacking layer is arranged above the second plastic encapsulation layer, the first redistribution stacking layer and the second redistribution stacking layer are vertically interconnected through the metal conductive column, and the capacitor and inductor formed between the first redistribution stacking layer and the second redistribution stacking layer arranged at intervals above and below can be used as a filter or an electrostatic protection structure.

[0021] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments, but this does not limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 A schematic cross-sectional view of a packaging structure provided in accordance with a first embodiment of the present invention.

[0024] Figure 2 A schematic cross-sectional view of a packaging structure provided in accordance with a second embodiment of the present invention.

[0025] Figure 3 A schematic cross-sectional view of a packaging structure provided in a third embodiment of the present invention.

[0026] Figure 4 A schematic cross-sectional view of a packaging structure provided by a fourth embodiment of the present invention.

[0027] Figure 5 A schematic cross-sectional view of a packaging structure provided in accordance with a fifth embodiment of the present invention.

[0028] Figure 6 A schematic cross-sectional view of a packaging structure provided by a sixth embodiment of the present invention.

[0029] Figure 7 A schematic cross-sectional view of a packaging structure provided by a seventh embodiment of the present invention.

[0030] Figure 8 A schematic cross-sectional view of a packaging structure provided in accordance with an eighth embodiment of the present invention.

[0031] Figure 9 This is a cross-sectional schematic diagram of the prefabricated substrate and the carrier after temporary bonding.

[0032] Figure 10 It is a cross-sectional schematic diagram of forming a first plastic packaging layer on a carrier board.

[0033] Figure 11 It is a cross-sectional schematic diagram of the prefabricated substrate and the carrier board after being separated after plastic packaging.

[0034] Figure 12 It is a cross-sectional schematic diagram of forming a first redistribution stacking layer.

[0035] Figure 13 Schematic diagram of the cross section of forming a metal conductive column.

[0036] Figure 14 A cross-sectional diagram of a bonded interconnected chip.

[0037] Figure 15 It is a cross-sectional schematic diagram of forming the second plastic sealing layer.

[0038] Figure 16 Schematic diagram of the cross section of the upper side of the second plastic layer being thinned

[0039] Figure 17 It is a cross-sectional schematic diagram of forming the second redistribution layer.

[0040] Figure 18 This is a cross-sectional diagram of a flip-chip bonded chip and / or device package.

[0041] Figure 19 Schematic cross-section of forming an underfill material on a chip and / or device package.

[0042] Figure 20 It is a cross-sectional schematic diagram of forming the third plastic sealing layer.

[0043] Figure 21 A cross-sectional view showing the metal layer in the prefabricated substrate after the back side of the first plastic packaging layer is thinned.

[0044] Figure 22 A schematic cross-sectional view of fabricating metal bumps on a metal layer.

[0045] Figure 23 A cross-sectional schematic diagram showing thinning the third plastic encapsulation layer to expose the back side of the chip and / or device package.

[0046] Figure 24 The present invention provides a flow chart of a method for preparing a packaging structure. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below in conjunction with the embodiments and drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0048] In the description of the present invention, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they cannot be understood as limiting the present invention.

[0049] One of the objects of the present invention is to provide a packaging structure, which includes a lower package body, an upper package body and a first redistribution stacking layer arranged between the lower package body and the upper package body, and the lower package body and the upper package body are electrically connected through the first redistribution stacking layer, wherein the lower package body includes a prefabricated substrate and a first plastic encapsulation layer surrounding the periphery of the prefabricated substrate, and the line width / line spacing of the first redistribution stacking layer is smaller than the line width / line spacing of the prefabricated substrate, so as to realize the integration of more chips or device packages on the first redistribution stacking layer.

[0050] In addition, the upper package body includes metal conductive columns for vertical interconnection, a second plastic encapsulation layer and a second redistribution stacking layer, wherein the second plastic encapsulation layer plastic encapsulates the metal conductive columns, the second redistribution stacking layer is arranged above the second plastic encapsulation layer, the first redistribution stacking layer and the second redistribution stacking layer are vertically interconnected through the metal conductive columns, and the capacitors and inductors formed between the first redistribution stacking layer and the second redistribution stacking layer arranged at intervals can be used as filters or electrostatic protection structures.

[0051] The following will be combined Figures 1 to 6 The packaging structure provided by the present invention is described in detail.

[0052] like Figure 1 As shown, a first embodiment of the present invention provides a packaging structure 100, including a lower packaging body 110, an upper packaging body 120 and a first redistribution stacking layer 130 arranged between the lower packaging body 110 and the upper packaging body 120, wherein the first redistribution stacking layer 130 electrically connects the lower packaging body 110 and the upper packaging body 120; the lower packaging body 110 includes a prefabricated substrate 111 and a first plastic packaging layer 112 surrounding the prefabricated substrate 111; the upper packaging body 120 includes an interconnect chip packaging layer 121 arranged above the first redistribution stacking layer 130, and an interconnect chip packaging layer 121 arranged on the interconnect chip packaging layer 121. 1 and a packaging layer 123 having a chip and / or device package body arranged above the second redistribution stacking layer 122; the interconnected chip packaging layer includes a plurality of metal conductive pillars 1211 and a second plastic packaging layer 1212, the second plastic packaging layer 1212 plastic-seales the plurality of metal conductive pillars 1211 above the first redistribution stacking layer 130, and the first redistribution stacking layer 130 and the second redistribution stacking layer 122 are electrically connected through the plurality of metal conductive pillars 1211; wherein the minimum line width / line spacing of the first redistribution stacking layer 130 is smaller than the minimum line width / line spacing of the prefabricated substrate 111.

[0053] In a preferred embodiment, the minimum line width / line space of the first redistribution stack layer 130 and the minimum line width / line space of the second redistribution stack layer 122 are respectively less than 10 μm.

[0054] like Figure 1 As shown, the interconnect chip packaging layer 121 also includes an interconnect chip 1213 buried in the second plastic packaging layer 1212, which is bonded to the first redistribution stacking layer 130. Preferably, an adhesive layer 1216 is provided between the interconnect chip 1213 and the first redistribution stacking layer 130. The adhesive layer 1216 helps to stably bond the interconnect chip 1213 to the first redistribution stacking layer 130, thereby preventing the interconnect chip 1213 from being affected by harmful operating environments such as moisture and vibration.

[0055] An interconnect redistribution stack 1214 is disposed on the surface of the interconnect chip 1213 facing the second redistribution stack 122. The interconnect redistribution stack 1214 has a minimum line width / line spacing of less than 2 μm and includes at least one capacitor. The interconnect redistribution stack 1214 is fabricated, for example, during a wafer-level or panel-level packaging process for the interconnect chip 1213.

[0056] In addition, a metal bump 1215 is provided above the interconnection redistribution stack layer 1214 , and the metal bump 1215 is electrically connected to the second redistribution stack layer 122 .

[0057] In this embodiment, the interconnected redistribution stacking layer 1214 is buried in the second plastic packaging layer 1212, and the first redistribution stacking layer 130 and the second redistribution stacking layer 122 are respectively located on opposite sides of the second plastic packaging layer 1212. Therefore, the capacitors and inductors formed between any two of the first redistribution stacking layer 130, the interconnected redistribution stacking layer 1214 and the second redistribution stacking layer 122 can be used as filters or electrostatic protection structures.

[0058] Continue to refer to Figure 1 In the packaging layer 123 having a chip and / or device package 1231, the chip and / or device package 1231 is flip-chip bonded to the second redistribution stack 122 and electrically connected to the second redistribution stack 122. The chip and / or device package 1231 is first filled with an underfill material layer 1233, which helps stabilize the chip and / or device package 1231 on the second redistribution stack 122 and protects the chip and / or device package 1231 from harmful operating environments such as moisture and vibration. A third plastic layer 1232 is then formed above the second redistribution stack 122. The third plastic layer 1232 surrounds the chip and / or device package 1231, exposing the back side of the chip and / or device package 1231 to the front side of the third plastic layer 1232. The front side of the third plastic layer 1232 is, for example, the side away from the second wiring layer 122.

[0059] In this embodiment, the upper package body 120 is fabricated, for example, by wafer-level packaging or panel-level packaging on top of the prefabricated substrate 111 after plastic encapsulation, but the present invention is not limited thereto. In the packaging structures provided in the fourth to sixth embodiments of the present invention, the upper package body can be a pre-packaged independent unit. After the prefabricated substrate is plastic encapsulated and the first redistribution stack layer is reconstructed, the two independent units are bonded to each other to achieve electrical connection.

[0060] Continue to refer to Figure 1The prefabricated substrate 111 can be a conventional multi-layer laminate substrate, with a wiring line width / line spacing greater than 10 μm. The prefabricated substrate 111 includes, for example, a first substrate layer 1111, a first dielectric layer 1112, a conductive layer 1113, and vias 1114. The first dielectric layer 1112 and the conductive layer 1113 are alternately arranged on opposite sides of the first substrate layer 1111. The vias 1114 provide electrical connection between the conductive layers 1113.

[0061] First substrate layer 1111 and first dielectric layer 1112 are selected from, for example, at least one of a build-up film, polyimide, bismaleimide triazine (BT) resin, epoxy resin, polyurethane, benzocyclobutene (BCB), high-density polyethylene (HDPE), and reinforced glass fiber, or a combination thereof. Conductive layer 1113 is formed from a conductive material such as copper. First dielectric layer 1112 and conductive layer 1113 are interspersed.

[0062] In this embodiment, the back side of the prefabricated substrate 111 is exposed, and a plurality of metal bumps or solder balls 140 are arranged thereon and electrically connected to the conductive layer 1113 inside the prefabricated substrate 111 .

[0063] like Figure 2 As shown, a second embodiment of the present invention further provides a packaging structure 200, which differs from the packaging structure 100 in that it includes at least one first silicon capacitor chip and at least one second silicon capacitor chip for decoupling control voltage drop or electrostatic protection.

[0064] The same reference numerals in the package structure 200 and the package structure 100 represent the same elements and have similar functions, and thus are not described in detail.

[0065] like Figure 2 As shown, there are two first silicon capacitors 201, which are respectively buried in the first substrate layer 1111 and directly electrically connected to the first redistribution stacking layer 130 through the conductive layer 1113; there are two second silicon capacitors 202, which are respectively buried in the second plastic encapsulation layer 1212, one of the two second silicon capacitors 202 is electrically connected to the first redistribution stacking layer 130, and the other of the two second silicon capacitors 203 is directly electrically connected to the second redistribution stacking layer 122.

[0066] It should be noted that in other embodiments of the present invention, the packaging structure may only include at least one first silicon capacitor embedded in the first substrate layer of the prefabricated circuit, or only include at least one second silicon capacitor embedded in the second plastic layer.

[0067] In other words, the packaging structure provided by the present invention includes at least one first silicon capacitor chip and / or at least one second silicon capacitor chip, at least one first silicon capacitor chip is buried in the first base material layer of the prefabricated substrate, and at least one first silicon capacitor chip is directly electrically connected to the first redistribution stacking layer; at least one second silicon capacitor chip is buried in the second plastic packaging layer, and at least one second silicon capacitor chip is directly electrically connected to the first redistribution stacking layer or the second redistribution stacking layer.

[0068] like Figure 3 As shown, a third embodiment of the present invention further provides a packaging structure 300 , which differs from the packaging structure 100 in that, in the packaging structure 300 , the lower packaging body 310 further includes a first prefabricated redistribution stack layer 313 disposed below the prefabricated substrate 311 .

[0069] The same reference numerals in the package structure 300 and the package structure 100 represent the same elements and have similar functions, and are not described in detail. Figure 1 Detailed description of the prefabricated substrate 111.

[0070] like Figure 3 As shown, the lower package body 310 includes a prefabricated substrate 311 and a first prefabricated redistribution stacking layer 313 arranged below the prefabricated substrate 311. Preferably, a conductive member 314 is provided between the prefabricated substrate 311 and the first prefabricated redistribution stacking layer 313 to facilitate electrical connection between the prefabricated substrate 311 and the first prefabricated redistribution stacking layer 313.

[0071] In this embodiment, the first plastic encapsulation layer 312 is arranged around the periphery of the prefabricated substrate 311 and the first prefabricated redistribution stack layer 313, and part of the first plastic encapsulation layer 312 is filled between the prefabricated substrate 311 and the first prefabricated redistribution stack layer 313. Figure 3 As shown, the size of the prefabricated substrate 311 is the same as the size of the first prefabricated redistribution stack layer 313, but the present invention is not limited thereto. In other embodiments of the present invention, the size of the prefabricated substrate is different from the size of the first prefabricated redistribution stack layer.

[0072] Since the packaging structure 300 uses a stacked prefabricated substrate 311 and a first prefabricated redistribution stack layer 313, the thickness of the first plastic encapsulation layer 312 is appropriately increased. Therefore, the first plastic encapsulation layer 312 is used to place a larger passive component 301, and a covering layer 302 is set on the outside of the passive component 301. The covering layer 302 electrically connects the passive component 301 and the first redistribution stack layer 130 to each other.

[0073] In a preferred embodiment, the minimum line width / line space of the first pre-fabricated redistribution stack layer 313 is less than 10 μm.

[0074] like Figure 3 As shown, the first prefabricated redistribution stack layer 313 includes a second substrate layer 3131 , a second dielectric layer 3132 , a conductive layer 3133 and vias 3134 . The conductive layers 3133 and the second dielectric layers 3132 are alternately arranged, and the vias 3134 realize electrical connection between the conductive layers 3133 .

[0075] In a preferred embodiment, the second dielectric layer 3132 and the conductive layer 3133 are alternately stacked above (or on the inside of) the second substrate layer 3131, wherein the second substrate layer 3131 is located at the outermost layer and has a higher modulus, a higher glass transition temperature, and a lower thermal expansion coefficient difference relative to the second dielectric layer 3132.

[0076] like Figure 4 As shown, the fourth embodiment of the present invention further provides a packaging structure 400, which is different from the packaging structure 300 in that:

[0077] 1) In the package structure 400 , the upper package body 420 is a prefabricated independent package unit. The prefabricated upper package body 420 can be manufactured, for example, in wafer-level packaging or panel-level packaging;

[0078] 2) The internal structure of the prefabricated upper package body 420 and the upper package body 120 (such as Figure 1 or Figure 3 The internal structural differences of the upper package body 420 as shown in FIG1 include: a plurality of metal bumps or solder balls are provided on the side of the prefabricated upper package body 420 facing the first redistribution stack layer 130, and the plurality of metal bumps or solder balls are electrically connected to the metal conductive pillars 4211 in the interconnect chip packaging layer;

[0079] 3) The prefabricated upper package body 420 is flip-chip bonded on top of the first redistribution stack layer 130 and electrically connected to the metal layer of the first redistribution stack layer 130 through a plurality of metal bumps;

[0080] 4) The internal structure of the prefabricated upper package body 420 and the upper package body 120 (such as Figure 1 or Figure 3 The internal structural difference of the upper package body 420 is that in the interconnect chip packaging layer of the prefabricated upper package body 420, a dummy element 4201 is embedded in the sidewall of the second plastic packaging layer 4212. The dummy element 4201 is used to enhance heat dissipation and adjust the warping of the edges and / or corners of the upper package body 420.

[0081] 5) Other passive components or packaging bodies 401 and heat dissipation structures 402 are arranged at the edges and / or corners of the first redistribution stacking layer 130. The heat dissipation structures 402 at the edges and / or corners of the first redistribution stacking layer 130 can be used to dissipate heat and enhance the structural strength of the packaging structure 400, thereby preventing warping at the edges and / or corners of the packaging structure 400.

[0082] like Figure 4 As shown, the solder balls 440 located outside the second substrate layer 3131 of the first pre-fabricated redistribution stack layer 313 in the package structure 400 are electrically connected to the vias 3134 in the second substrate layer 3131 .

[0083] like Figure 5 As shown, the fifth embodiment of the present invention further provides a packaging structure 500, which differs from the packaging structure 400 in that, in the packaging structure 500, the lower packaging body 510 includes a prefabricated substrate 511 and a second prefabricated redistribution stacking layer 513 arranged above the prefabricated substrate 511, wherein the structure of the prefabricated substrate 511 is similar to that of the prefabricated substrate 311, and the structure of the second prefabricated redistribution stacking layer 513 is similar to that of the first prefabricated redistribution stacking layer 313.

[0084] In this embodiment, the third substrate layer 5131 of the second prefabricated redistribution stack layer 513 is arranged close to the prefabricated substrate 511; the third dielectric layer 5132 and the conductive layer 5133 of the second prefabricated redistribution stack layer 513 are alternately stacked on top of the third substrate layer 5131; the conductive layers 5133 of the second prefabricated redistribution stack layer 513 are electrically connected through vias 5134.

[0085] In this embodiment, the first plastic encapsulation layer 512 encapsulates the periphery of the prefabricated substrate 511 and the second prefabricated redistribution stack layer 513 .

[0086] like Figure 6 As shown, a sixth embodiment of the present invention further provides a package structure 600, which differs from package structures 400 and 500 in that, in package structure 600, a lower package body 610 includes a prefabricated substrate 611, a first prefabricated redistribution stack layer 613 disposed above the prefabricated substrate 611, and a second prefabricated redistribution stack layer 614 disposed below the prefabricated substrate 611. A first conductive member 615 and an optional underfill layer are disposed between the first prefabricated redistribution stack layer 613 and the prefabricated substrate 611; and a second conductive member 616 and an optional underfill layer are disposed between the second prefabricated redistribution stack layer 614 and the prefabricated substrate 611.

[0087] The size of the first pre-fabricated redistribution stack layer 613 and the size of the second pre-fabricated redistribution stack layer 614 may be the same or different.

[0088] In addition, the structure of the first prefabricated redistribution stack layer 613 can refer to Figure 3 Regarding the description of the first prefabricated redistribution stack layer 313, the structure of the second prefabricated redistribution stack layer 614 can refer to Figure 5 Detailed description of the second prefabricated redistribution stack layer 513 .

[0089] In this embodiment, the first plastic encapsulation layer 612 encapsulates the peripheries of the prefabricated substrate 611 , the first prefabricated redistribution stack layer 613 , and the second prefabricated redistribution stack layer 614 .

[0090] Depend on Figures 3 to 6 As can be seen from the package structures 300, 400, 500 and 600, the lower package body may further include:

[0091] A first prefabricated redistribution stacking layer and / or a second prefabricated redistribution stacking layer, a prefabricated substrate includes a first surface and a second surface relative to each other, the first prefabricated redistribution stacking layer is arranged on one side of the first surface, and the second prefabricated redistribution stacking layer is arranged on one side of the second surface; wherein, the first plastic encapsulation layer is arranged around the periphery of the substrate unit formed by the first prefabricated redistribution stacking layer and / or the second prefabricated redistribution stacking layer and the prefabricated substrate; the minimum line width / line spacing of the first prefabricated redistribution stacking layer and the minimum line width / line spacing of the second prefabricated redistribution stacking layer are respectively less than 10μm.

[0092] like Figure 7 As shown, the seventh embodiment of the present invention further provides a packaging structure 700, which differs from the packaging structure 100 in that, in the packaging structure 700, the lower packaging body 710 also includes a third prefabricated redistribution stacking layer 731 and a prefabricated interconnect chip packaging layer 721 arranged between the prefabricated substrate 711 and the first redistribution stacking layer 730, the third prefabricated redistribution stacking layer 731 is arranged above the prefabricated substrate 711, and the prefabricated interconnect chip packaging layer 721 is arranged above the third prefabricated redistribution stacking layer 731.

[0093] The prefabricated interconnect chip packaging layer 721 includes multiple prefabricated metal conductive pillars 7211, a prefabricated interconnect chip 7213 and a fourth plastic encapsulation layer 7212. The fourth plastic encapsulation layer 7212 encapsulates multiple prefabricated metal conductive pillars 7211 and the prefabricated interconnect chip 7213 above the third prefabricated redistribution stacking layer 731; wherein, the first redistribution stacking layer 730 and the third prefabricated redistribution stacking layer 731 are electrically connected through multiple prefabricated metal conductive pillars 7211.

[0094] In this embodiment, the prefabricated substrate 711, the first plastic encapsulation layer 712 surrounding the prefabricated substrate 711, the third prefabricated redistribution stack layer 731, the prefabricated interconnect chip packaging layer 721, and the first redistribution stack layer 730 collectively constitute a prefabricated packaging substrate. In other words, the lower package body 710 can serve as an independent prefabricated packaging substrate. This prefabricated packaging substrate, as an independent structure, can be manufactured in a wafer-level or panel-level packaging process.

[0095] like Figure 7 As shown, on an independent lower package body 710, a chip 7231 and / or a device package body 7231 is flip-chip bonded to the top of the first redistribution stacking layer 730; an underfill material layer 7233 is filled between the chip 7231 and / or the device package body 7231 and the first redistribution stacking layer 730; optionally, a reinforcement structure 701 is provided at the edge and / or corner of the first redistribution stacking layer 730. The reinforcement structure 701 is made of, for example, a high thermal conductivity material, which can, on the one hand, reinforce the overall strength of the prefabricated package substrate; on the other hand, it can enhance heat dissipation.

[0096] In addition, the minimum line width / line spacing of the third prefabricated redistribution stack layer 731 is smaller than the minimum line width / line spacing of the prefabricated substrate 711 . For example, the minimum line width / line spacing of the third prefabricated redistribution stack layer 731 is less than 10 μm.

[0097] Figure 7 Zhongyu Figure 1 Other identical reference numerals represent identical components with similar functions and are not described in detail herein.

[0098] like Figure 8 As shown, the eighth embodiment of the present invention further provides a packaging structure 800, which differs from the packaging structure 100 in that, in the packaging structure 800, the prefabricated substrate 111 is plastic-sealed by the first plastic sealing layer 112 to form a lower packaging body 110, and a first redistribution stacking layer 130 is arranged above the lower packaging body 110, wherein the chip 1231 and / or the device packaging body 1231 are flip-chip mounted above the first redistribution stacking layer 130 and are electrically connected to the first redistribution stacking layer 130.

[0099] An underfill material layer 1233 is filled between the chip 1231 and / or the device package 1231 and the first redistribution stack layer 130 .

[0100] Optionally, reinforcement structures 801 are provided at the edges and / or corners of the first redistribution stack 130. Reinforcement structures 801, for example, made of a highly thermally conductive material, can enhance the overall strength of the package structure and improve heat dissipation. Furthermore, a plastic encapsulation material can optionally be provided above the first redistribution stack 130 to encapsulate the chip 1231 and / or device package 1231, along with the reinforcement structures 801.

[0101] Figure 8 Zhongyu Figure 1 Other identical reference numerals represent identical components with similar functions and are not described in detail herein.

[0102] like Figure 24 The present invention further provides a method 2000 for preparing a package structure, which comprises: providing a prefabricated substrate, plastic-sealing the prefabricated substrate to form a first plastic-sealing layer to constitute a lower package body;

[0103] forming a first redistribution stack layer on one side of the lower package body, wherein the first redistribution stack layer is electrically connected to the prefabricated substrate; and

[0104] Encapsulating the upper package body above the first redistribution stack layer to obtain a package structure;

[0105] The minimum line width / line spacing of the first redistribution stack layer is smaller than the minimum line width / line spacing of the prefabricated substrate.

[0106] In a preferred embodiment, the steps of providing a prefabricated substrate, encapsulating the prefabricated substrate, forming a first encapsulation layer, and forming a lower package body include:

[0107] A carrier is provided, and a plurality of prefabricated substrates pre-cut into single particles are temporarily bonded to the carrier; a plastic encapsulation material is coated on the carrier, and the prefabricated substrates are plastic encapsulated to form a first plastic encapsulation layer; the first plastic encapsulation layer and the prefabricated substrates are separated from the carrier to obtain a lower package body.

[0108] In a preferred embodiment, the steps of packaging the upper package body above the first redistribution stack layer to obtain the package structure include:

[0109] A plurality of metal conductive pillars are formed above the first redistribution stacking layer; an interconnection chip is bonded above the first redistribution stacking layer, and the interconnection chip includes an interconnection redistribution stacking layer and a plurality of conductive bumps above the first redistribution stacking layer; the plurality of metal conductive pillars and the interconnection chip are plastic-encapsulated to form a second plastic-encapsulation layer; the second plastic-encapsulation layer is thinned to expose the plurality of metal conductive pillars and the plurality of conductive bumps; a second redistribution stacking layer is formed above the second plastic-encapsulation layer, and the second redistribution stacking layer and the plurality of metal conductive pillars and the conductive bumps are electrically connected; a flip-chip bonding chip and / or device package is performed above the second redistribution stacking layer; and the chip and / or device package is plastic-encapsulated to form a third plastic-encapsulation layer.

[0110] In a preferred embodiment, the preparation method 2000 further includes:

[0111] Thinning the first plastic encapsulation layer away from the side of the first redistribution stack layer to expose the conductive layer on the back side of the prefabricated substrate; implanting solder balls or metal bumps on the conductive layer, the solder balls or metal bumps are electrically connected to the conductive layer; and thinning the third plastic encapsulation layer to expose the back side of the chip and / or the back side of the device package.

[0112] The following will take the package structure 100 as an example to illustrate the specific manufacturing process of each step in the above-mentioned manufacturing method 2000.

[0113] like Figures 9 to 11 As shown, the manufacturing process of forming the lower package body includes:

[0114] A carrier 1000 is provided, and a temporary bonding layer 1001, such as a temporary bonding adhesive, is provided on one side of the carrier 1000; a plurality of prefabricated substrates 111 ( Figure 9 Only one is shown).

[0115] A first molding compound is coated on the surface of one side of the carrier 1000 , and the first molding compound covers the prefabricated substrate 111 and the temporary bonding layer 1001 . After the first molding compound is cured, a first molding layer 112 is formed.

[0116] By utilizing a debonding process, the first plastic encapsulation layer 112 and the prefabricated substrate 111 are separated from the temporary bonding layer 1001 on the carrier 1000 , thereby obtaining the lower package body 110 .

[0117] like Figure 12 As shown, a first redistribution stack layer 130 is formed on a surface of the lower package body 110 that is not covered by the first molding compound. The first redistribution stack layer 130 is electrically connected to the conductive layer 1113 in the prefabricated substrate 111 .

[0118] The upper package body 120 in the package structure 100 is a non-prefabricated independent structure. Figures 13 to 16 First, an interconnect chip packaging layer 121 is formed on the first redistribution stack layer 130. Figure 13 As shown, a metal via 1211 is fabricated above the first redistribution stack layer 130 , and the metal via 1211 is electrically connected to the first redistribution stack layer 130 .

[0119] like Figure 14 As shown, an interconnect chip 1213 is face-bonded onto the first redistribution stack layer 130 using an adhesive layer 1216 . A surface of the interconnect chip 1213 away from the first redistribution stack layer 130 includes an interconnect redistribution stack layer 1214 and a plurality of metal bumps 1215 .

[0120] like Figure 15As shown, a second molding compound is applied on the first redistribution stack layer 130 , and a plurality of metal conductive pillars 1211 and interconnection chips 1213 are molded together to form a second molding layer 1212 . At this time, the interconnection chips 1213 are buried in the second molding layer 1212 .

[0121] like Figure 16 As shown, the upper surface of the second plastic encapsulation layer 1212 (the side away from the first redistribution stack layer 130 ) is thinned to expose a plurality of metal conductive pillars 1211 and a plurality of metal bumps 1215 , thereby completing the production of the interconnect chip packaging layer 121 .

[0122] like Figure 17 As shown, a second redistribution stack layer 122 is fabricated above the interconnect chip packaging layer 121 , and a plurality of metal conducting pillars 1211 and a plurality of metal bumps 1215 are electrically connected to the second redistribution stack layer 122 , respectively.

[0123] like Figure 18 As shown, at least one chip 1231 and / or at least one device package 1231 is flip-chip bonded onto the second redistribution stack layer 122 , and the chip 1231 or the device package 1231 is electrically connected to the second redistribution stack layer 122 , respectively.

[0124] like Figure 19 As shown, the underfill material is filled between the second redistribution stack layer 122 and the chip 1231 or the device package 1231 to form an underfill material layer 1233 .

[0125] like Figure 20 As shown, a third molding compound is applied onto the second redistribution stack layer 122 to mold the chip 1231 or the device package 1231 , and a third molding layer 1232 is formed after curing.

[0126] like Figure 21 As shown, the first plastic encapsulation layer 112 is thinned at a side away from the first redistribution stack layer 130 so that the conductive layer 1113 in the prefabricated substrate 111 is exposed.

[0127] like Figure 22 As shown, a plurality of metal bumps 140 are formed on the conductive layer 1113. The metal bumps 140 are, for example, metal bumps with tin caps. In other embodiments of the present invention, a plurality of solder balls (tin balls) may also be implanted on the conductive layer.

[0128] like Figure 23 As shown, the upper surface of the third plastic encapsulation layer 1232 (the side away from the second redistribution stack layer 122 ) is thinned to expose the back side of the chip 1231 or the device package 1231 .

[0129] During the process of manufacturing the metal bumps 140 , the chip 1231 or the device package 1231 is buried in the third plastic layer 1232 to prevent the chip 1231 or the device package 1231 from being adversely affected by the external environment, thereby improving the yield.

[0130] For other embodiments of the present invention, when the lower packaging body of the packaging structure includes a prefabricated substrate, a first prefabricated redistribution stacking layer and / or a second prefabricated redistribution stacking layer, the first prefabricated redistribution stacking layer and / or the second prefabricated redistribution stacking layer are prefabricated, for example, through wafer-level packaging, and then stacked with the uncut prefabricated substrate to form a substrate unit, the cut substrate unit is made into a single-grain structure, and then plastic-sealed on a carrier board.

[0131] In other embodiments of the present invention, the upper packaging body of the packaging structure is a prefabricated independent packaging unit. After the prefabricated substrate is plastic-sealed and the first redistribution stacking layer is produced, the upper packaging body is directly flip-chip bonded to the first redistribution stacking layer to obtain the corresponding packaging structure.

[0132] The present invention provides a packaging structure and a preparation method, wherein the lower packaging body of the packaging structure includes a prefabricated substrate and a first redistribution stacking layer arranged above the prefabricated substrate, and having a minimum line width / line spacing smaller than that of the prefabricated substrate. The first redistribution stacking layer with a smaller line width / line spacing is used to integrate more chips and / or device packages in the packaging structure. In addition, the upper packaging body of the packaging structure includes a metal conductive column for vertical interconnection, a second plastic encapsulation layer, and a second redistribution stacking layer, wherein the second plastic encapsulation layer plastic-encapsulates the metal conductive column, the second redistribution stacking layer is arranged above the second plastic encapsulation layer, the first redistribution stacking layer and the second redistribution stacking layer are vertically interconnected through the metal conductive column, and the capacitor and inductor formed between the first redistribution stacking layer and the second redistribution stacking layer arranged at intervals above and below can be used as a filter or an electrostatic protection structure.

[0133] The present invention has been described by the above-mentioned embodiments. However, the above-mentioned embodiments are merely examples of the present invention. In addition, the technical features involved in the different embodiments of the present invention described above may be combined with each other as long as they do not conflict with each other. It must be pointed out that the present invention may also have various other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art may make various corresponding changes and modifications based on the present invention. However, such corresponding changes and modifications shall fall within the scope of protection of the claims appended to the present invention.

Claims

1. A packaging structure, characterized in that: The packaging structure includes: A lower package body, an upper package body disposed above the lower package body, and a first redistribution stack layer disposed between the lower package body and the upper package body, wherein the first redistribution stack layer electrically connects the lower package body and the upper package body; The lower packaging body includes a prefabricated substrate and a first plastic packaging layer surrounding the periphery of the prefabricated substrate; Wherein, the minimum line width / line spacing of the first redistribution stack layer is smaller than the minimum line width / line spacing of the prefabricated substrate; The upper package body includes an interconnection chip packaging layer arranged above the first redistribution stacking layer, and a second redistribution stacking layer arranged above the interconnection chip packaging layer. The interconnection chip packaging layer includes an interconnection chip buried in the second plastic packaging layer. The interconnection chip is bonded upright above the first redistribution stacking layer, and an interconnection redistribution stacking layer is arranged on the surface of the interconnection chip facing the second redistribution stacking layer. The interconnection redistribution stacking layer includes at least one capacitor.

2. The packaging structure according to claim 1, wherein: The minimum line width / line space of the first redistribution stack layer and the minimum line width / line space of the second redistribution stack layer are respectively less than 10 μm.

3. The packaging structure according to claim 1, wherein: The upper package further comprises a packaging layer having a chip and / or device package disposed above the second redistribution stack layer; The interconnect chip packaging layer includes a plurality of metal conductive pillars and a second plastic packaging layer, wherein the second plastic packaging layer plastic-packages the plurality of metal conductive pillars above the first redistribution stack layer, and the first redistribution stack layer and the second redistribution stack layer are electrically connected through the plurality of metal conductive pillars; Wherein, the minimum line width / line spacing of the interconnect redistribution stack layer is less than 2 μm.

4. The packaging structure according to claim 3, wherein: In the packaging layer having a chip and / or device package, the chip and / or the device package are flip-chip bonded above the second redistribution stacking layer and electrically connected to the second redistribution stacking layer; wherein, the packaging layer having a chip and / or device package also includes a third plastic packaging layer, the third plastic packaging layer plastic-seales the chip and / or device package above the second redistribution stacking layer, and the back side of the chip and / or the back side of the device package are respectively exposed from the third plastic packaging layer.

5. The packaging structure according to claim 3, wherein: Also includes: at least one first silicon capacitor chip and / or at least one second silicon capacitor chip; The at least one first silicon capacitor chip is embedded in the first base material layer of the prefabricated substrate, and the at least one first silicon capacitor chip is directly electrically connected to the first redistribution stack layer; The at least one second silicon capacitor chip is embedded in the second plastic packaging layer, and the at least one second silicon capacitor chip is directly electrically connected to the first redistribution stack layer or the second redistribution stack layer.

6. The packaging structure according to claim 1, wherein: The back side of the prefabricated substrate away from the first redistribution stack layer further includes a plurality of metal bumps or solder balls, and the plurality of metal bumps or solder balls are electrically connected to the conductive layer in the prefabricated substrate.

7. The packaging structure according to claim 1, wherein: The lower package body further includes: a first prefabricated redistribution stack layer and / or a second prefabricated redistribution stack layer, the prefabricated substrate comprising a first surface and a second surface opposite to each other, the first prefabricated redistribution stack layer being disposed on one side of the first surface, and the second prefabricated redistribution stack layer being disposed on one side of the second surface; In which, the first plastic encapsulation layer is arranged around the periphery of the first prefabricated redistribution stacking layer and / or the second prefabricated redistribution stacking layer and the prefabricated substrate to form a substrate unit; the line width / line spacing of the first prefabricated redistribution stacking layer and the minimum line width / line spacing of the second prefabricated redistribution stacking layer are respectively less than 10μm.

8. The packaging structure according to claim 1, wherein: The device further comprises a passive component, wherein the passive component is embedded in the first plastic packaging layer and is electrically connected to the first redistribution stack layer.

9. The packaging structure according to claim 1, wherein: It also includes a heat dissipation device, which is arranged at the edge and / or corner of the first redistribution stack layer.

10. The packaging structure according to claim 1, wherein: The lower package body further includes: A third prefabricated redistribution stack layer and a prefabricated interconnect chip packaging layer are provided between the prefabricated substrate and the first redistribution stack layer, the third prefabricated redistribution stack layer is provided above the prefabricated substrate, and the prefabricated interconnect chip packaging layer is provided above the third prefabricated redistribution stack layer; The prefabricated interconnect chip packaging layer includes a plurality of prefabricated metal conductive pillars, a prefabricated interconnect chip and a fourth plastic encapsulation layer, wherein the fourth plastic encapsulation layer encapsulates the plurality of prefabricated metal conductive pillars and the prefabricated interconnect chip above the third prefabricated redistribution stack layer; the first redistribution stack layer and the third prefabricated redistribution stack layer are electrically connected via the plurality of prefabricated metal conductive pillars; The prefabricated substrate, the first plastic encapsulation layer, the third prefabricated redistribution stacking layer, the prefabricated interconnect chip packaging layer and the first redistribution stacking layer together constitute a prefabricated packaging substrate.

11. A method for preparing a packaging structure, characterized in that: The preparation method comprises: Providing a prefabricated substrate, and plastic-sealing the prefabricated substrate to form a first plastic-sealing layer to constitute a lower packaging body; forming a first redistribution stack layer on one side of the lower package body, wherein the first redistribution stack layer is electrically connected to the prefabricated substrate; and Encapsulating an upper package body above the first redistribution stack layer to obtain a package structure; Wherein, the minimum line width / line spacing of the first redistribution stack layer is smaller than the minimum line width / line spacing of the prefabricated substrate; The upper package body includes an interconnection chip packaging layer arranged above the first redistribution stacking layer, and a second redistribution stacking layer arranged above the interconnection chip packaging layer. The interconnection chip packaging layer includes an interconnection chip buried in the second plastic packaging layer. The interconnection chip is bonded upright above the first redistribution stacking layer, and an interconnection redistribution stacking layer is arranged on the surface of the interconnection chip facing the second redistribution stacking layer. The interconnection redistribution stacking layer includes at least one capacitor.

12. The preparation method according to claim 11, characterized in that The steps of providing a prefabricated substrate, and plastic-sealing the prefabricated substrate to form a first plastic-sealing layer to form a lower packaging body include: Providing a carrier plate, the carrier plate temporarily bonding a plurality of prefabricated substrates pre-cut into individual pieces; Applying a plastic encapsulation material to the carrier plate, and plastic encapsulating the prefabricated substrate to form the first plastic encapsulation layer; The first plastic packaging layer and the prefabricated substrate are separated from the carrier to obtain the lower packaging body.

13. The preparation method according to claim 12, characterized in that: The steps of packaging the upper package body above the first redistribution stack layer to obtain the package structure include: forming a plurality of metal conductive pillars above the first redistribution stack layer; Bonding an interconnect chip on the first redistribution stack layer, wherein the interconnect chip includes an interconnect redistribution stack layer and a plurality of conductive bumps on an upper portion away from the first redistribution stack layer; Plastic-sealing the plurality of metal conducting pillars and the interconnection chip to form a second plastic-sealing layer; thinning the second plastic packaging layer to expose the plurality of metal conductive pillars and the plurality of conductive bumps; forming a second redistribution stack layer on the second plastic encapsulation layer, wherein the second redistribution stack layer is electrically connected to the plurality of metal conductive pillars and the conductive bumps; flip-chip bonding a chip and / or a device package on the second redistribution stack layer; and The chip and / or device package is plastic-encapsulated to form a third plastic-encapsulation layer.

14. The method for preparing the package structure according to claim 13, wherein: Also includes: Thinning the first plastic encapsulation layer on a side away from the first redistribution stack layer to expose the conductive layer on the back side of the prefabricated substrate; implanting solder balls or metal bumps on the conductive layer, wherein the solder balls or metal bumps are electrically connected to the conductive layer; as well as The third plastic encapsulation layer is thinned to expose the back side of the chip and / or the back side of the device package.

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