Display panel and manufacturing method thereof

Abstract

The present application discloses a display panel and a method for manufacturing the same. The display panel includes: an array substrate; an anode disposed on the array substrate; an auxiliary cathode disposed on the same layer as the anode, with a gap between the auxiliary cathode and the anode; a pixel definition layer disposed on the anode and the auxiliary cathode; wherein the pixel definition layer has a first opening at a position corresponding to the anode to expose the anode; the pixel definition layer has a second opening at a position corresponding to the auxiliary cathode to expose the auxiliary cathode; a light-emitting device disposed in the first opening; and a surface cathode disposed on the light-emitting device and connected to the auxiliary cathode through the second opening. In the present application, the auxiliary cathode is disposed on the same layer as the anode, and the surface cathode is connected to the auxiliary cathode through the second opening. There is no need to open a hole in the flat layer, so as to optimize the position of the auxiliary cathode hole and avoid poor overlap between the surface cathode and the auxiliary cathode, thereby reducing the voltage drop effect.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a method for manufacturing the same. Background Art

[0002] Organic light-emitting diode (OLED) display panels offer advantages such as self-luminescence, high contrast, thinness, wide viewing angle, and fast response time. They represent the next generation of flat-panel display technology and are increasingly recognized by the industry. Due to the inherent resistance voltage divider effect of the metal wiring within OLED display panels, current flowing through the internal power supply wiring generates a power supply voltage drop, resulting in uneven current distribution from the source and tail ends of the signal, leading to uneven panel brightness. This phenomenon is known as static resistance voltage drop (IR drop). To improve this problem, auxiliary cathodes are added to the backplane design to even out the voltage distribution across the entire cathode surface, achieving a uniform display brightness.

[0003] like Figure 1 As shown, the OLED display panel includes a substrate 11, a light shielding layer 12, a buffer layer 13, a semiconductor layer 14, a gate insulating layer 15, a gate layer 16, a dielectric layer 17, a source and drain electrode layer 18, a passivation layer 19, a transfer layer 20 (PAD layer), a flat layer 21, an anode 22, a pixel definition layer 23 and a surface cathode 25. Among them, the surface cathode 25 is prepared in the evaporation process. The surface cathode 25 needs to be connected to the metal of the lower layer in sequence through the auxiliary cathode hole 10, that is, the surface cathode 25 → transfer layer 20 → source and drain electrode layer 18 → light shielding layer 12 to realize the transmission of the cathode 25 signal. Since the surface cathode 25 is electrically connected to the transfer layer 20, the source and drain electrode layer 18, and the light shielding layer 12 in sequence, it is equivalent to a design in which the surface cathode 25, the transfer layer 20, the source and drain electrode layer 18, and the light shielding layer 12 are arranged on the same layer.

[0004] Combine Figure 1 As shown, the light shielding layer 12 is evenly distributed across the entire surface. By uniformly distributing auxiliary cathode apertures 10 throughout the panel, the IR drop (voltage drop) phenomenon of the cathode 25 signal is minimized. However, in current practical manufacturing, because the auxiliary cathode apertures 10 must penetrate the relatively thick planar layer 21 and pixel definition layer 23 (bank), residues of the pixel definition layer 23 often remain within the apertures during the exposure and development process. This can result in a loss of electrical continuity between the transfer layer 20 and the cathode 25, and thus an inability to effectively mitigate the IR drop phenomenon. Summary of the Invention

[0005] The object of the present invention is to provide a display panel and a method for manufacturing the same, so as to solve the technical problem that the position of the auxiliary cathode hole causes the transition layer and the cathode to be unable to be electrically connected and the voltage drop cannot be improved.

[0006] To achieve the above-mentioned objectives, the present invention provides a display panel, comprising: an array substrate; an anode, arranged on the array substrate; an auxiliary cathode, arranged in the same layer as the anode, with a gap between the auxiliary cathode and the anode; a pixel definition layer, arranged on the anode and the auxiliary cathode; wherein the pixel definition layer has a first opening at a position corresponding to the anode, for exposing the anode; the pixel definition layer has a second opening at a position corresponding to the auxiliary cathode, for exposing the auxiliary cathode; a light-emitting device, arranged in the first opening; and a surface cathode, arranged on the light-emitting device and connected to the auxiliary cathode through the second opening.

[0007] Furthermore, the first opening includes a red sub-pixel opening, a green sub-pixel opening and a blue sub-pixel opening, the light-emitting device includes a red light-emitting device, a green light-emitting device and a blue light-emitting device, and the red light-emitting device, the green light-emitting device and the blue light-emitting device are respectively arranged corresponding to the red sub-pixel opening, the green sub-pixel opening and the blue sub-pixel opening.

[0008] Furthermore, the gap width between the auxiliary cathode and the anode is greater than 5 μm.

[0009] Furthermore, the auxiliary cathode is in a circular, elliptical or polygonal shape.

[0010] Furthermore, the auxiliary cathode and the anode are made of at least one of aluminum, molybdenum, copper, hafnium and tantalum.

[0011] Furthermore, the array substrate includes: a substrate; a light-shielding layer, arranged on the substrate; a buffer layer, covering the light-shielding layer and extending to the surface of the substrate; a semiconductor layer, arranged on the buffer layer; a gate insulating layer, arranged on the semiconductor layer; a gate layer, arranged on the gate insulating layer; a dielectric layer, covering the gate layer and the semiconductor layer, and extending to the surface of the buffer layer; a source-drain layer, arranged on the dielectric layer, the source-drain layer including a drain and a source; wherein the drain is connected to one side of the semiconductor layer, and the source is simultaneously connected to the other side of the semiconductor layer and the light-shielding layer; a passivation layer, covering the source-drain layer, and extending to the surface of the dielectric layer; a transfer layer, arranged on the passivation layer, and connected to the source; and a planarization layer, covering the transfer layer, and extending to the surface of the passivation layer.

[0012] Furthermore, the planar layer is provided with a third opening for exposing the switching layer; wherein the anode is provided on the planar layer and connected to the switching layer through the third opening.

[0013] To achieve the above-mentioned objectives, the present invention also provides a method for preparing a display panel, comprising the following steps: forming an array substrate; forming a conductive layer on the array substrate; patterning the conductive layer to form an anode and an auxiliary cathode arranged on the same layer, wherein a gap exists between the auxiliary cathode and the anode; forming a pixel definition layer on the anode and the auxiliary cathode; forming a first opening and a second opening in the pixel definition layer, the first opening being used to expose the anode; the second opening being used to expose the auxiliary cathode; forming a light-emitting device in the pixel definition layer, the light-emitting device being located in the first opening; and forming a surface cathode on the light-emitting device, the surface cathode filling the second opening and being connected to the auxiliary cathode.

[0014] Furthermore, the steps of forming the array substrate include: forming a light shielding layer on a substrate; forming a buffer layer on the light shielding layer and extending to the upper surface of the substrate; forming a semiconductor layer on the buffer layer; forming a gate insulating layer on the semiconductor layer; forming a gate layer on the gate insulating layer; forming a dielectric layer on the gate layer, wherein the dielectric layer is formed with a first via hole and a second via hole, the two first via holes are used to expose the two sides of the semiconductor layer, and the second via hole is used to expose a portion of the light shielding layer; forming a source and drain layer on the dielectric layer and filling the first via hole and the second via hole, The source-drain layer includes a drain and a source, the drain is connected to the semiconductor layer through the first via, the source is connected to the semiconductor layer through the first via, and the source is connected to the light-shielding layer through the second via; a passivation layer is formed on the source-drain layer and extends to the surface of the dielectric layer, and a third via is formed in the passivation layer to expose the source; a transfer layer is formed in the third via and partially extends onto the passivation layer; a flat layer is formed on the transfer layer and extends to the surface of the passivation layer, and a third opening is formed in the flat layer to expose the transfer layer.

[0015] Furthermore, the anode is formed on the planar layer and connected to the switching layer through the third opening.

[0016] The technical effect of the present invention is to provide a display panel and a preparation method thereof, wherein the auxiliary cathode and the anode are arranged on the same layer, and the surface cathode is connected to the auxiliary cathode through a second opening, without the need to open a hole in the flat layer, so as to optimize the position of the auxiliary cathode hole, thereby avoiding the problem of residual pixel definition layer in the hole due to the deep hole in the flat layer, avoiding the phenomenon of poor overlap between the surface cathode and the auxiliary cathode, and thus reducing the voltage drop effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0018] Figure 1 Schematic diagram of the structure of an existing display panel.

[0019] Figure 2 A schematic diagram of the structure of a display panel provided in an embodiment of the present application.

[0020] Figure 3 This is a flow chart of a method for manufacturing a display panel provided in an embodiment of the present application.

[0021] Figure 4 Flowchart of a method for preparing an array substrate provided in an embodiment of the present application.

[0022] Figure 5 A schematic structural diagram of an array substrate provided in an embodiment of the present application.

[0023] Figure 6 This is a structural diagram of the auxiliary cathode and anode provided in the embodiment of the present application being arranged on the same layer.

[0024] The components of the accompanying drawings are identified as follows:

[0025] 11. substrate; 12. light-shielding layer;

[0026] 13. Buffer layer; 14. Semiconductor layer;

[0027] 15. Gate insulating layer; 16. Gate layer;

[0028] 17. Dielectric layer; 18. Source and drain layer;

[0029] 18a, source; 18b, drain;

[0030] 19. Passivation layer; 20. Transfer layer;

[0031] 21. Flat layer; 22. Anode;

[0032] 22a, auxiliary cathode; 23, pixel definition layer;

[0033] 24. Light-emitting device; 25. Cathode;

[0034] 10. Auxiliary cathode hole; 31. First via hole;

[0035] 32. Second via hole; 33. Third via hole;

[0036] 41. First opening; 42. Second opening;

[0037] 43. The third opening. DETAILED DESCRIPTION

[0038] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first" and "second" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0039] like Figure 2 As shown, this embodiment provides a display panel, including an array substrate 11 , an anode 22 , an auxiliary cathode 22 a , a pixel definition layer 23 , a light emitting device 24 and a surface cathode 25 .

[0040] The array substrate 11 includes a substrate 11 , a light shielding layer 12 , a buffer layer 13 , a semiconductor layer 14 , a gate insulating layer 15 , a gate layer 16 , a dielectric layer 17 , a source and drain electrode layer 18 , a passivation layer 19 , a transfer layer 20 and a planarization layer 21 .

[0041] The substrate 11 is glass, functional glass (sensor glass) or a flexible substrate. The functional glass is obtained by sputtering a transparent metal oxide conductive film coating on ultra-thin glass and undergoing high-temperature annealing. The material of the transparent metal oxide can be any one of indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium gallium zinc tin oxide (IGZTO), indium tin oxide (ITO), indium zinc oxide (IZO), indium aluminum zinc oxide (IAZO), indium gallium tin oxide (IGTO) or antimony tin oxide (ATO). The material used for the flexible substrate is a polymer material, specifically, the material used for the flexible substrate can be polyimide (PI), polyethylene (PE), polypropylene (PP), polystyrene (PS), polyethylene glycol terephthalate (PET) or polyethylene naphthalate diformicacid glycol ester (PEN). Polymer materials are flexible, lightweight, and impact-resistant, making them suitable for flexible display panels. Polyimide also offers excellent heat resistance and stability.

[0042] The light-shielding layer 12 is provided on the substrate 11. The material used for the light-shielding layer 12 is a metal material, which includes one or more of copper, molybdenum, aluminum, silver, nickel, etc., which improves the electrical conductivity and bending performance of the light-shielding layer 12 and reduces the risk of dynamic bending breakage.

[0043] The buffer layer 13 covers the light shielding layer 12 and extends to the surface of the substrate 11 . The buffer layer 13 is made of one or more materials selected from silicon oxide, silicon nitride, silicon oxynitride and amorphous silicon. The buffer layer 13 is mainly used to block water and oxygen to prevent water and oxygen from corroding the array substrate 11 .

[0044] The semiconductor layer 14 is disposed on the buffer layer 13 and may be made of indium tin oxide (IGZO). The semiconductor layer 14 may also include a carrier channel made of polysilicon. The carrier channel is mainly used to improve the fill factor, short-circuit current, and open-circuit voltage.

[0045] The gate insulating layer 15 is disposed on the semiconductor layer 14 . The gate insulating layer 15 may be made of one or more materials selected from silicon oxide, silicon nitride, silicon oxynitride, and amorphous silicon.

[0046] The gate layer 16 is provided on the gate insulating layer 15. The material used for the gate layer 16 is a metal material, which includes one or more of copper, molybdenum, aluminum, silver, nickel, etc., which improves the conductivity and bending performance of the gate layer 16 and reduces the risk of dynamic bending breakage.

[0047] Dielectric layer 17 completely covers gate layer 16 and semiconductor layer 14 and extends to the upper surface of buffer layer 13. Materials used for dielectric layer 17 include one or more of silicon oxide, silicon nitride, silicon oxynitride, and amorphous silicon. Dielectric layer 17 is formed with first vias 31 and second vias 32. The first vias 31 expose two sides of semiconductor layer 14, while the second vias 32 partially expose light-shielding layer 12.

[0048] The source-drain electrode layer 18 is provided on the dielectric layer 17. The source-drain electrode layer 18 includes a drain electrode 18b and a source electrode 18a. The drain electrode 18b is located on the left side of the semiconductor layer 14 and is connected to the semiconductor layer 14. The source electrode 18a is located on the right side of the semiconductor layer 14. The source electrode 18a is an integrated structure, which includes two connecting terminals, one connecting terminal is connected to the semiconductor layer 14, and the other connecting terminal is connected to the light shielding layer 12. The material used for the source-drain electrode layer 18 is a metal material, which includes one or more of copper, molybdenum, aluminum, silver, nickel, etc., which improves the conductivity and bending performance of the source-drain electrode layer 18 and reduces the risk of breakage due to dynamic bending.

[0049] The passivation layer 19 covers the source / drain electrode layer 18 and extends to the upper surface of the dielectric layer 17. A third via hole 33 is formed in the passivation layer 19 to expose the source electrode 18a of the source / drain electrode layer 18. The passivation layer 19 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, and amorphous silicon.

[0050] The transfer layer 20 is disposed on the passivation layer 19 and is connected to the source electrode 18a through the third via 33. The transfer layer 20 is made of a metal material, such as copper, molybdenum, aluminum, silver, etc., which improves the conductivity and bending performance of the transfer layer 20 and reduces the risk of breakage during dynamic bending.

[0051] The planarization layer 21 covers the transfer layer 20 and extends to the surface of the passivation layer 19. The planarization layer 21 is made of one or more materials selected from silicon oxide, silicon nitride, silicon oxynitride, and amorphous silicon. The planarization layer 21 defines a third opening 43 to expose the transfer layer 20.

[0052] The anode 22 is disposed on the planar layer 21 and connected to the transition layer 20 through the third opening 43. The anode 22 extends from the sidewalls of the third opening 43 to its bottom wall (i.e., the top surface of the transition layer 20), and then extends from the bottom wall of the third opening 43 to the surface of the planar layer 21.

[0053] The auxiliary cathode 22 a is disposed in the same layer as the anode 22 , with a gap existing between the auxiliary cathode 22 a and the anode 22 .

[0054] The auxiliary cathode 22a and the anode 22 are transparent metal oxides, and a stack of metal layers and transparent metal oxides. The materials used for the transparent metal oxide include any one of indium gallium zinc oxide, indium zinc tin oxide, indium gallium zinc tin oxide, indium tin oxide, indium zinc oxide, indium aluminum zinc oxide, indium gallium tin oxide or antimony tin oxide. The above materials have good conductivity and transparency, and are relatively thin, and will not affect the overall thickness of the display panel. At the same time, they can also reduce electronic radiation and ultraviolet and infrared light that are harmful to the human body. The material used for the metal layer is any one of silver (Ag), aluminum (Al) or copper (Cu). Metals such as silver, aluminum, and copper have good conductivity and low cost, which can reduce production costs while ensuring the conductivity of the auxiliary cathode 22a and the anode 22.

[0055] Furthermore, the gap width between the auxiliary cathode 22a and the anode 22 is greater than 5 μm. Specifically, the gap width between the auxiliary cathode 22a and the anode 22 is 5 μm, 6 μm, or 7 μm. Setting the gap width between the auxiliary cathode 22a and the anode 22 to be greater than 5 μm is mainly to ensure the insulation between the anode 22 and the auxiliary cathode 22a. By setting a gap to ensure the insulation between the anode 22 and the auxiliary cathode 22a, there is no need to set up an additional insulating layer, which can save materials and reduce costs. The specific gap width can be determined according to factors such as the pixel aperture ratio requirements and the size of the display panel. The shape of the top view of the auxiliary cathode 22a is circular, elliptical or polygonal, and the polygon can be a triangle, rectangle, square, pentagon, hexagon, etc.

[0056] The pixel definition layer 23 is disposed on the anode 22 and the auxiliary cathode 22a. A first opening 41 is formed in the pixel definition layer 23 at a position corresponding to the anode 22, exposing the anode 22. A second opening 42 is formed in the pixel definition layer 23 at a position corresponding to the auxiliary cathode 22a, exposing the auxiliary cathode 22a. The material of the pixel definition layer 23 is selected from one or more of polyimide, polyethylene naphthalate, polyethylene terephthalate, polycarbonate (PC), polyetherimide (PEI), and polyether sulfone (PES).

[0057] In this embodiment, a pixel definition layer 23 is used to isolate the auxiliary cathode 22a from the anode 22, which can reduce the gap between the auxiliary cathode 22a and the anode 22 while ensuring the insulation effect, so that the laying area of ​​the anode 22 is larger, and the luminous effect of the auxiliary cathode 22a on the light-emitting device 24 is reduced.

[0058] The light-emitting device 24 is disposed within the first opening 41 and includes layers such as a hole injection layer, a light-emitting layer, an electron transport layer, and an electron injection layer. The first opening 41 includes a red sub-pixel opening, a green sub-pixel opening, and a blue sub-pixel opening. The light-emitting device 24 includes a red light-emitting device 24, a green light-emitting device 24, and a blue light-emitting device 24. The red light-emitting device 24, the green light-emitting device 24, and the blue light-emitting device 24 are disposed corresponding to the red sub-pixel opening, the green sub-pixel opening, and the blue sub-pixel opening, respectively.

[0059] The surface cathode 25 is disposed on the light-emitting device 24 and is connected to the auxiliary cathode 22a through the second opening 42. The surface cathode 25 can be made of any one or more of magnesium (Mg), silver, a magnesium alloy, a silver alloy, and a transparent metal oxide. The specific material used is determined by the requirements of the display panel. It should be noted that the material selected for the surface cathode 25 must be compatible with the material of the auxiliary cathode 22a to ensure that the contact resistance between the surface cathode 25 and the auxiliary cathode 22a is appropriate.

[0060] Compared with the prior art, in this embodiment, the auxiliary cathode 22a is arranged in the same layer as the anode 22, and the surface cathode 25 is connected to the auxiliary cathode 22a through the second opening 42. There is no need to open a hole in the flat layer 21 to optimize the position of the auxiliary cathode 22a hole (i.e., the second opening 42). This can avoid the problem of pixel definition layer 23 remaining in the hole due to the deep hole in the flat layer 21, avoid the phenomenon of poor overlap between the surface cathode 25 and the auxiliary cathode 22a, and thus reduce the voltage drop (IR Drop) effect. In addition, the auxiliary cathode 22a is arranged in the same layer as the anode 22, and the auxiliary cathode 22a and other signal lines are not in the same film layer, which can reduce the risk of short circuits between metal lines. The other signal lines here can be the gate line of the gate layer 16, the data line of the source and drain layer 18, the VDD line, and the sense line. In addition, the gap (Space) between other signal lines can be appropriately reduced, thereby achieving a higher resolution design.

[0061] The display panel provided in this embodiment also includes an encapsulation structure (not shown), which may be an inorganic encapsulation layer, an organic encapsulation layer, or an alternating stack of inorganic and organic encapsulation layers. The inorganic encapsulation layer may be selected from inorganic materials such as aluminum oxide, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, titanium oxide, zirconium oxide, and zinc oxide. The organic encapsulation layer may be selected from organic materials such as epoxy resin, polyimide, polyethylene terephthalate, polycarbonate (PC), polyethylene, and polyacrylate (PEA).

[0062] like Figure 3As shown, this embodiment further provides a method for manufacturing a display panel, including the following steps S1) to S6).

[0063] S1) forming an array substrate 11. The steps of forming the array substrate 11 include S11)-S20), referring to Figure 4 .

[0064] S11) forming a light shielding layer 12 on a substrate 11, referring to Figure 5 .

[0065] Specifically, a metal material is deposited on the substrate 11 to form the light shielding layer 12. The metal material includes one or more of copper, molybdenum, aluminum, silver, nickel, etc., which improves the conductivity and bending performance of the light shielding layer 12 and reduces the risk of dynamic bending breakage.

[0066] S12) forming a buffer layer 13 on the light shielding layer 12 and extending to the upper surface of the substrate 11, referring to Figure 5 .

[0067] S13) forming a semiconductor layer 14 on the buffer layer 13, referring to Figure 5 .

[0068] S14) forming a gate insulating layer 15 on the semiconductor layer 14, referring to Figure 5 .

[0069] S15) forming a gate layer 16 on the gate insulating layer 15, referring to Figure 5 .

[0070] S16) forming a dielectric layer 17 on the gate layer 16, wherein the dielectric layer 17 is formed with a first via hole 31 and a second via hole 32, wherein the two first via holes 31 are used to expose two sides of the semiconductor layer 14, and the second via hole 32 is used to expose a portion of the light shielding layer 12, Figure 5 .

[0071] S17) forming a source-drain electrode layer 18 on the dielectric layer 17 and filling the first via hole 31 and the second via hole 32, the source-drain electrode layer 18 including a drain electrode 18b and a source electrode 18a, the drain electrode 18b being connected to the semiconductor layer 14 through the first via hole 31, the source electrode 18a being connected to the semiconductor layer 14 through the first via hole 31, and the source electrode 18a being connected to the light shielding layer 12 through the second via hole 32, Figure 5 .

[0072] S18) forming a passivation layer 19 on the source-drain electrode layer 18 and extending to the surface of the dielectric layer 17, wherein the passivation layer 19 is formed with a third via hole 33 for exposing the source electrode 18a, Figure 5 .

[0073] S19) forming a transfer layer 20 in the third via hole 33, and partially extending onto the passivation layer 19, referring to Figure 5 .

[0074] S20) forming a flat layer 21 on the transfer layer 20 and extending to the surface of the passivation layer 19, wherein the flat layer 21 is formed with a third opening 43 for exposing the transfer layer 20, referring to Figure 5 .

[0075] S2) forming a conductive layer on the array substrate 11.

[0076] Specifically, a metal material is deposited on the planar layer 21 to form a conductive layer.

[0077] S3) Patterning the conductive layer to form an anode 22 and an auxiliary cathode 22a disposed on the same layer, wherein a gap exists between the auxiliary cathode 22a and the anode 22. The anode 22 is connected to the switching layer 20 through the third opening 43, referring to Figure 6 .

[0078] S4) forming a pixel definition layer 23 on the anode 22 and the auxiliary cathode 22a; forming a first opening 41 and a second opening 42 in the pixel definition layer 23, wherein the first opening 41 is used to expose the anode 22; and the second opening 42 is used to expose the auxiliary cathode 22a. Figure 6 .

[0079] S5) forming a light emitting device 24 in the pixel definition layer 23, wherein the light emitting device 24 is located in the first opening 41, Figure 2 .

[0080] Specifically, the light-emitting device 24 is disposed within the first opening 41 and includes layers such as a hole injection layer, a light-emitting layer, an electron transport layer, and an electron injection layer. The first opening 41 includes a red sub-pixel opening, a green sub-pixel opening, and a blue sub-pixel opening. The light-emitting device 24 includes a red light-emitting device 24, a green light-emitting device 24, and a blue light-emitting device 24. The red light-emitting device 24, the green light-emitting device 24, and the blue light-emitting device 24 are disposed corresponding to the red sub-pixel opening, the green sub-pixel opening, and the blue sub-pixel opening, respectively.

[0081] S6) forming a surface cathode 25 on the light emitting device 24, the surface cathode 25 filling the second opening 42 and connected to the auxiliary cathode 22a, referring to Figure 2 .

[0082] Compared with the prior art, in this embodiment, the auxiliary cathode 22a is arranged in the same layer as the anode 22, and the surface cathode 25 is connected to the auxiliary cathode 22a through the second opening 42. There is no need to open a hole in the flat layer 21 to optimize the position of the auxiliary cathode 22a hole (i.e., the second opening 42). This can avoid the problem of pixel definition layer 23 remaining in the hole due to the deep hole in the flat layer 21, avoid the phenomenon of poor overlap between the surface cathode 25 and the auxiliary cathode 22a, and thus reduce the voltage drop (IR Drop) effect. In addition, the auxiliary cathode 22a is arranged in the same layer as the anode 22, and the auxiliary cathode 22a and other signal lines are not in the same film layer, which can reduce the risk of short circuits between metal lines. The other signal lines here can be the gate line of the gate layer 16, the data line of the source and drain layer 18, the VDD line, and the sense line. In addition, the gap (Space) between other signal lines can be appropriately reduced, thereby achieving a higher resolution design.

[0083] The above is a detailed introduction to a display panel and a preparation method thereof provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: include: array substrate; an anode, provided on the array substrate; an auxiliary cathode disposed in the same layer as the anode, with a gap between the auxiliary cathode and the anode; a pixel definition layer disposed on the anode and the auxiliary cathode; wherein the pixel definition layer has a first opening at a position corresponding to the anode for exposing the anode; and a second opening at a position corresponding to the auxiliary cathode for exposing the auxiliary cathode; a light emitting device disposed in the first opening; and A surface cathode is provided on the light emitting device and connected to the auxiliary cathode through the second opening. The surface cathode covers a side of the auxiliary cathode away from the substrate and a side of the auxiliary cathode close to the inner wall of the second opening.

2. The display panel according to claim 1, wherein: The first opening includes a red sub-pixel opening, a green sub-pixel opening and a blue sub-pixel opening, the light-emitting device includes a red light-emitting device, a green light-emitting device and a blue light-emitting device, and the red light-emitting device, the green light-emitting device and the blue light-emitting device are respectively arranged corresponding to the red sub-pixel opening, the green sub-pixel opening and the blue sub-pixel opening.

3. The display panel according to claim 1, wherein: The gap width between the auxiliary cathode and the anode is greater than 5 μm.

4. The display panel according to claim 1, wherein: The auxiliary cathode is in a circular, elliptical or polygonal shape.

5. The display panel according to claim 1, wherein: The auxiliary cathode and the anode are made of at least one of aluminum, molybdenum, copper, hafnium and tantalum.

6. The display panel according to claim 1, wherein: The array substrate includes: substrate; a light shielding layer, disposed on the substrate; a buffer layer, covering the light shielding layer and extending to the surface of the substrate; a semiconductor layer, disposed on the buffer layer; a gate insulating layer, disposed on the semiconductor layer; a gate layer, disposed on the gate insulating layer; a dielectric layer covering the gate layer and the semiconductor layer and extending to a surface of the buffer layer; a source-drain electrode layer, disposed on the dielectric layer, the source-drain electrode layer comprising a drain electrode and a source electrode; wherein the drain electrode is connected to one side of the semiconductor layer, and the source electrode is simultaneously connected to the other side of the semiconductor layer and the light shielding layer; a passivation layer, covering the source and drain electrode layers and extending to the surface of the dielectric layer; a transfer layer, disposed on the passivation layer and connected to the source electrode; and The planar layer covers the transfer layer and extends to the surface of the passivation layer.

7. The display panel according to claim 6, wherein: The flat layer is provided with a third opening for exposing the transfer layer; The anode is disposed on the planar layer and is connected to the switching layer through the third opening.

8. A method for preparing a display panel, characterized in that: The steps include: forming an array substrate; forming a conductive layer on the array substrate; performing patterning on the conductive layer to form an anode and an auxiliary cathode disposed on the same layer, wherein a gap exists between the auxiliary cathode and the anode; A pixel definition layer is formed on the anode and the auxiliary cathode; a first opening and a second opening are formed in the pixel definition layer, wherein the first opening is used to expose the anode; and the second opening is used to expose the auxiliary cathode; a light emitting device formed in the pixel definition layer, the light emitting device being located within the first opening; and A surface cathode is formed on the light emitting device. The surface cathode fills the second opening and is connected to the auxiliary cathode. The surface cathode covers a side of the auxiliary cathode away from the substrate and a side of the auxiliary cathode close to the inner wall of the second opening.

9. The method for manufacturing a display panel according to claim 8, wherein: The steps of forming the array substrate include: forming a light shielding layer on a substrate; forming a buffer layer on the light shielding layer and extending to the upper surface of the substrate; forming a semiconductor layer on the buffer layer; forming a gate insulating layer on the semiconductor layer; forming a gate layer on the gate insulating layer; forming a dielectric layer on the gate layer, wherein the dielectric layer is formed with a first via hole and a second via hole, wherein the two first via holes are used to expose two sides of the semiconductor layer, and the second via hole is used to expose a portion of the light shielding layer; forming a source-drain electrode layer on the dielectric layer and filling the first via hole and the second via hole, wherein the source-drain electrode layer includes a drain electrode and a source electrode, the drain electrode is connected to the semiconductor layer through the first via hole, the source electrode is connected to the semiconductor layer through the first via hole, and the source electrode is connected to the light shielding layer through the second via hole; forming a passivation layer on the source and drain electrode layer and extending to the surface of the dielectric layer, wherein the passivation layer is formed with a third via hole for exposing the source electrode; forming a transfer layer in the third via hole and partially extending onto the passivation layer; A flat layer is formed on the transfer layer and extends to the surface of the passivation layer. The flat layer is formed with a third opening for exposing the transfer layer.

10. The method for manufacturing a display panel according to claim 9, wherein: The anode is formed on the planar layer and connected to the switching layer through the third opening.

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